mirror of https://github.com/lnis-uofu/SOFA.git
79 lines
3.0 KiB
ReStructuredText
79 lines
3.0 KiB
ReStructuredText
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.. _fpga_arch:
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FPGA Overview
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-------------
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.. _fpga_arch_generality:
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Generality
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~~~~~~~~~~
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:numref:`fig_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric.
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The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric.
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I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RISC-V processors (see details in :ref:`io_resource`).
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.. _fig_fpga_arch:
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.. figure:: ./figures/fpga_arch.png
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:scale: 25%
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:alt: Tile-based FPGA architecture
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Tile-based FPGA architecture
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.. _fpga_arch_tiles:
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Tiles
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~~~~~
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The FPGA architecture follows a tile-based organization, to exploit the fine-grainularity in physical design, where three types of tiles are built:
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.. table:: FPGA tile type and functionalities
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+------+----------+---------------------------------------------+
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| Type | Capacity | Description |
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+======+==========+=============================================+
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| CLB | 144 | Each CLB tile consists of |
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| | | - a Configurable Logic Block (CLB) |
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| | | - a X-direction Connection Block (CBx) |
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| | | - a Y-direction Connection Block (CBy) |
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| | | - a Switch Block (SB). |
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| | | This is the majority tile across the fabric |
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| | | to implement logics and registers. |
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+------+----------+---------------------------------------------+
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| IO-A | 36 | The type-A I/O is a low-density I/O tile |
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| | | which is designed to mainly interface the |
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| | | the GPIOs of the SoC. |
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| | | Each I/O-A tile consists of 1 digitial I/O |
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| | | cell. |
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+------+----------+---------------------------------------------+
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| IO-B | 12 | The type-B I/O is a high-density I/O tile |
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| | | which is designed to mainly interface the |
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| | | the wishbone interface and logic analyzer |
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| | | of the SoC. |
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| | | Each I/O-B tile consists of 9 digitial I/O |
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| | | cells. |
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+------+----------+---------------------------------------------+
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.. _fpga_arch_scan_chain:
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Scan-chain
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~~~~~~~~~~
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There is a built-in scan-chain in the FPGA which connects the the `sc_in` and `sc_out` ports of CLBs in a chain (see details in :ref:`clb_arch_scan_chain`), as illustrated in :numref:`fig_fabric_scan_chain`.
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When `Test_en` signal is active, users can
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- overwrite the contents of all the D-type flip-flops in the FPGA by feeding signals to the `SC_HEAD` port
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- readback the contents of all the D-type flip-flops in the FPGA through the `SC_TAIL` port.
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.. _fig_fabric_scan_chain:
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.. figure:: ./figures/fabric_scan_chain.png
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:scale: 25%
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:alt: Built-in scan-chain across FPGA
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Built-in scan-chain across FPGA
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