mirror of https://github.com/lnis-uofu/SOFA.git
1363 lines
73 KiB
Plaintext
1363 lines
73 KiB
Plaintext
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/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga/openfpga -f top_run.openfpga
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Reading script file top_run.openfpga...
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___ _____ ____ ____ _
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/ _ \ _ __ ___ _ __ | ___| _ \ / ___| / \
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| | | | '_ \ / _ \ '_ \| |_ | |_) | | _ / _ \
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| |_| | |_) | __/ | | | _| | __/| |_| |/ ___ \
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\___/| .__/ \___|_| |_|_| |_| \____/_/ \_\
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OpenFPGA: An Open-source FPGA IP Generator
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Versatile Place and Route (VPR)
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FPGA-Verilog
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FPGA-SPICE
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FPGA-SDC
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FPGA-Bitstream
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This is a free software under the MIT License
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Copyright (c) 2018 LNIS - The University of Utah
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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Command line to execute: vpr /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml top.blif --clock_modeling route --device 12x12 --route_chan_width 40 --absorb_buffer_luts off
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VPR FPGA Placement and Routing.
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Version: 0.0.0+3a80af34
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Revision: 3a80af34
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Compiled: 2020-11-17T13:59:01
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Compiler: GNU 8.4.0 on Linux-3.10.0-1062.9.1.el7.x86_64 x86_64
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Build Info: release VTR_ASSERT_LEVEL=2
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University of Toronto
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verilogtorouting.org
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vtr-users@googlegroups.com
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This is free open source code under MIT license.
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VPR was run with the following command-line:
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vpr /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml top.blif --clock_modeling route --device 12x12 --route_chan_width 40 --absorb_buffer_luts off
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Architecture file: /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml
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Circuit name: top
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# Loading Architecture Description
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Warning 1: Model 'io' input port 'outpad' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
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Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
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Warning 3: Model 'frac_lut4' input port 'in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
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Warning 4: Model 'frac_lut4' output port 'lut4_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
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Warning 5: Model 'frac_lut4' output port 'lut3_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
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# Loading Architecture Description took 0.01 seconds (max_rss 9.0 MiB, delta_rss +0.6 MiB)
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# Building complex block graph
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Warning 6: [LINE 593] false logically-equivalent pin clb[0].I0[1].
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Warning 7: [LINE 593] false logically-equivalent pin clb[0].I0[2].
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Warning 8: [LINE 599] false logically-equivalent pin clb[0].I1[1].
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Warning 9: [LINE 599] false logically-equivalent pin clb[0].I1[2].
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Warning 10: [LINE 605] false logically-equivalent pin clb[0].I2[1].
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Warning 11: [LINE 605] false logically-equivalent pin clb[0].I2[2].
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Warning 12: [LINE 611] false logically-equivalent pin clb[0].I3[1].
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Warning 13: [LINE 611] false logically-equivalent pin clb[0].I3[2].
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Warning 14: [LINE 617] false logically-equivalent pin clb[0].I4[1].
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Warning 15: [LINE 617] false logically-equivalent pin clb[0].I4[2].
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Warning 16: [LINE 623] false logically-equivalent pin clb[0].I5[1].
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Warning 17: [LINE 623] false logically-equivalent pin clb[0].I5[2].
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Warning 18: [LINE 629] false logically-equivalent pin clb[0].I6[1].
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Warning 19: [LINE 629] false logically-equivalent pin clb[0].I6[2].
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Warning 20: [LINE 635] false logically-equivalent pin clb[0].I7[1].
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Warning 21: [LINE 635] false logically-equivalent pin clb[0].I7[2].
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# Building complex block graph took 0.01 seconds (max_rss 9.7 MiB, delta_rss +0.7 MiB)
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# Load circuit
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# Load circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.2 MiB)
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# Clean circuit
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Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs
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Inferred 0 additional primitive pins as constant generators due to constant inputs
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Swept input(s) : 0
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Swept output(s) : 0 (0 dangling, 0 constant)
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Swept net(s) : 0
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Swept block(s) : 0
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Constant Pins Marked: 0
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# Clean circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB)
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# Compress circuit
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# Compress circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB)
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# Verify circuit
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# Verify circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB)
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Circuit Statistics:
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Blocks: 4
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.input : 2
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.output: 1
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4-LUT : 1
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Nets : 3
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Avg Fanout: 1.0
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Max Fanout: 1.0
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Min Fanout: 1.0
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Netlist Clocks: 0
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# Build Timing Graph
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Timing Graph Nodes: 6
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Timing Graph Edges: 5
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Timing Graph Levels: 4
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# Build Timing Graph took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB)
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Netlist contains 0 clocks
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# Load Timing Constraints
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SDC file 'top.sdc' not found
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Setting default timing constraints:
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* constrain all primay inputs and primary outputs on a virtual external clock 'virtual_io_clock'
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* optimize virtual clock to run as fast as possible
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Timing constraints created 1 clocks
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Constrained Clock 'virtual_io_clock' (Virtual Clock)
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# Load Timing Constraints took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB)
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Timing analysis: ON
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Circuit netlist file: top.net
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Circuit placement file: top.place
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Circuit routing file: top.route
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Circuit SDC file: top.sdc
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Packer: ENABLED
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Placer: ENABLED
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Router: ENABLED
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Analysis: ENABLED
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NetlistOpts.abosrb_buffer_luts : false
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NetlistOpts.sweep_dangling_primary_ios : true
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NetlistOpts.sweep_dangling_nets : true
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NetlistOpts.sweep_dangling_blocks : true
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NetlistOpts.sweep_constant_primary_outputs: false
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PackerOpts.allow_unrelated_clustering: auto
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PackerOpts.alpha_clustering: 0.750000
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PackerOpts.beta_clustering: 0.900000
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PackerOpts.cluster_seed_type: BLEND2
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PackerOpts.connection_driven: true
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PackerOpts.global_clocks: true
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PackerOpts.hill_climbing_flag: false
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PackerOpts.inter_cluster_net_delay: 1.000000
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PackerOpts.timing_driven: true
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PackerOpts.target_external_pin_util: auto
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PlacerOpts.place_freq: PLACE_ONCE
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PlacerOpts.place_algorithm: PATH_TIMING_DRIVEN_PLACE
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PlacerOpts.pad_loc_type: FREE
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PlacerOpts.place_cost_exp: 1.000000
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PlacerOpts.place_chan_width: 40
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PlacerOpts.inner_loop_recompute_divider: 0
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PlacerOpts.recompute_crit_iter: 1
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PlacerOpts.timing_tradeoff: 0.500000
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PlacerOpts.td_place_exp_first: 1.000000
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PlacerOpts.td_place_exp_last: 8.000000
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PlaceOpts.seed: 1
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AnnealSched.type: AUTO_SCHED
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AnnealSched.inner_num: 1.000000
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RouterOpts.route_type: DETAILED
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RouterOpts.router_algorithm: TIMING_DRIVEN
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RouterOpts.base_cost_type: DELAY_NORMALIZED_LENGTH
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RouterOpts.fixed_channel_width: 40
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RouterOpts.trim_empty_chan: false
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RouterOpts.trim_obs_chan: false
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RouterOpts.acc_fac: 1.000000
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RouterOpts.bb_factor: 3
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RouterOpts.bend_cost: 0.000000
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RouterOpts.first_iter_pres_fac: 0.000000
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RouterOpts.initial_pres_fac: 0.500000
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RouterOpts.pres_fac_mult: 1.300000
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RouterOpts.max_router_iterations: 50
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RouterOpts.min_incremental_reroute_fanout: 16
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RouterOpts.astar_fac: 1.200000
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RouterOpts.criticality_exp: 1.000000
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RouterOpts.max_criticality: 0.990000
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RouterOpts.routing_failure_predictor = SAFE
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RouterOpts.routing_budgets_algorithm = DISABLE
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AnalysisOpts.gen_post_synthesis_netlist: false
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RoutingArch.directionality: UNI_DIRECTIONAL
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RoutingArch.switch_block_type: WILTON
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RoutingArch.Fs: 3
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# Packing
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Warning 22: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
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Warning 23: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
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Warning 24: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
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Warning 25: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
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Begin packing 'top.blif'.
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After removing unused inputs...
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total blocks: 4, total nets: 3, total inputs: 2, total outputs: 1
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Begin prepacking.
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Finish prepacking.
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Using inter-cluster delay: 1.33777e-09
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Packing with pin utilization targets: io_top:1,1 io_right:1,1 io_bottom:1,1 io_left:1,1 clb:0.8,1
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Packing with high fanout thresholds: io_top:128 io_right:128 io_bottom:128 io_left:128 clb:32
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Warning 26: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
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Warning 27: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
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Warning 28: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
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Warning 29: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
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Not enough resources expand FPGA size to (14 x 14)
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Complex block 0: 'c' (clb) .
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Complex block 1: 'out:c' (io) .
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Complex block 2: 'a' (io) .
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Complex block 3: 'b' (io) .
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Pb types usage...
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inpad : 2
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outpad : 1
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fle : 1
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clb : 1
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lut3inter : 1
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ble3 : 1
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io : 3
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lut3 : 1
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lut : 1
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Logic Element (fle) detailed count:
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Total number of Logic Elements used : 1
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LEs used for logic and registers : 0
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LEs used for logic only : 1
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LEs used for registers only : 0
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EMPTY: # blocks: 0, average # input + clock pins used: 0, average # output pins used: 0
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io: # blocks: 3, average # input + clock pins used: 0.333333, average # output pins used: 0.666667
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clb: # blocks: 1, average # input + clock pins used: 2, average # output pins used: 1
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Absorbed logical nets 0 out of 3 nets, 3 nets not absorbed.
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Warning 30: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
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Warning 31: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
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Warning 32: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
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Warning 33: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
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FPGA sized to 14 x 14 (12x12)
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Device Utilization: 0.02 (target 1.00)
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Block Utilization: 0.02 Type: io
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Block Utilization: 0.01 Type: clb
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Netlist conversion complete.
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# Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.7 MiB)
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# Load Packing
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Begin loading packed FPGA netlist file.
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Netlist generated from file 'top.net'.
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Detected 0 constant generators (to see names run with higher pack verbosity)
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Finished loading packed FPGA netlist file (took 0.02 seconds).
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Warning 34: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity).
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# Load Packing took 0.02 seconds (max_rss 10.7 MiB, delta_rss +0.1 MiB)
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Warning 35: Netlist contains 0 global net to non-global architecture pin connections
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Netlist num_nets: 3
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Netlist num_blocks: 4
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Netlist EMPTY blocks: 0.
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Netlist io blocks: 3.
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Netlist clb blocks: 1.
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Netlist inputs pins: 2
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Netlist output pins: 1
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# Create Device
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## Build Device Grid
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Warning 36: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
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Warning 37: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
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Warning 38: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
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Warning 39: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
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FPGA sized to 14 x 14: 196 grid tiles (12x12)
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Resource usage...
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Netlist
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||
|
|
3 blocks of type: io
|
||
|
|
Architecture
|
||
|
|
12 blocks of type: io_top
|
||
|
|
12 blocks of type: io_right
|
||
|
|
108 blocks of type: io_bottom
|
||
|
|
12 blocks of type: io_left
|
||
|
|
Netlist
|
||
|
|
1 blocks of type: clb
|
||
|
|
Architecture
|
||
|
|
144 blocks of type: clb
|
||
|
|
|
||
|
|
Device Utilization: 0.02 (target 1.00)
|
||
|
|
Physical Tile io_top:
|
||
|
|
Block Utilization: 0.25 Logical Block: io
|
||
|
|
Physical Tile io_right:
|
||
|
|
Block Utilization: 0.25 Logical Block: io
|
||
|
|
Physical Tile io_bottom:
|
||
|
|
Block Utilization: 0.03 Logical Block: io
|
||
|
|
Physical Tile io_left:
|
||
|
|
Block Utilization: 0.25 Logical Block: io
|
||
|
|
Physical Tile clb:
|
||
|
|
Block Utilization: 0.01 Logical Block: clb
|
||
|
|
|
||
|
|
## Build Device Grid took 0.00 seconds (max_rss 10.7 MiB, delta_rss +0.0 MiB)
|
||
|
|
## Build tileable routing resource graph
|
||
|
|
X-direction routing channel width is 40
|
||
|
|
Y-direction routing channel width is 40
|
||
|
|
Warning 40: in check_rr_node: RR node: 489 type: OPIN location: (1,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 41: in check_rr_node: RR node: 490 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 42: in check_rr_node: RR node: 579 type: OPIN location: (2,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 43: in check_rr_node: RR node: 580 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 44: in check_rr_node: RR node: 669 type: OPIN location: (3,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 45: in check_rr_node: RR node: 670 type: OPIN location: (3,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 46: in check_rr_node: RR node: 759 type: OPIN location: (4,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 47: in check_rr_node: RR node: 760 type: OPIN location: (4,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 48: in check_rr_node: RR node: 849 type: OPIN location: (5,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 49: in check_rr_node: RR node: 850 type: OPIN location: (5,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 50: in check_rr_node: RR node: 939 type: OPIN location: (6,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 51: in check_rr_node: RR node: 940 type: OPIN location: (6,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 52: in check_rr_node: RR node: 1029 type: OPIN location: (7,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 53: in check_rr_node: RR node: 1030 type: OPIN location: (7,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 54: in check_rr_node: RR node: 1119 type: OPIN location: (8,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 55: in check_rr_node: RR node: 1120 type: OPIN location: (8,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 56: in check_rr_node: RR node: 1209 type: OPIN location: (9,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 57: in check_rr_node: RR node: 1210 type: OPIN location: (9,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 58: in check_rr_node: RR node: 1299 type: OPIN location: (10,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 59: in check_rr_node: RR node: 1300 type: OPIN location: (10,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 60: in check_rr_node: RR node: 1389 type: OPIN location: (11,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 61: in check_rr_node: RR node: 1390 type: OPIN location: (11,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 62: in check_rr_node: RR node: 1479 type: OPIN location: (12,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 63: in check_rr_node: RR node: 1480 type: OPIN location: (12,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
## Build tileable routing resource graph took 0.16 seconds (max_rss 18.1 MiB, delta_rss +7.3 MiB)
|
||
|
|
RR Graph Nodes: 18580
|
||
|
|
RR Graph Edges: 96524
|
||
|
|
# Create Device took 0.16 seconds (max_rss 18.1 MiB, delta_rss +7.3 MiB)
|
||
|
|
|
||
|
|
# Placement
|
||
|
|
## Computing placement delta delay look-up
|
||
|
|
### Build routing resource graph
|
||
|
|
Warning 64: in check_rr_node: RR node: 171 type: OPIN location: (1,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 65: in check_rr_node: RR node: 172 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 66: in check_rr_node: RR node: 1291 type: OPIN location: (2,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 67: in check_rr_node: RR node: 1292 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 68: in check_rr_node: RR node: 2411 type: OPIN location: (3,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 69: in check_rr_node: RR node: 2412 type: OPIN location: (3,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 70: in check_rr_node: RR node: 3531 type: OPIN location: (4,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 71: in check_rr_node: RR node: 3532 type: OPIN location: (4,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 72: in check_rr_node: RR node: 4651 type: OPIN location: (5,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 73: in check_rr_node: RR node: 4652 type: OPIN location: (5,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 74: in check_rr_node: RR node: 5771 type: OPIN location: (6,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 75: in check_rr_node: RR node: 5772 type: OPIN location: (6,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 76: in check_rr_node: RR node: 6891 type: OPIN location: (7,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 77: in check_rr_node: RR node: 6892 type: OPIN location: (7,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 78: in check_rr_node: RR node: 8011 type: OPIN location: (8,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 79: in check_rr_node: RR node: 8012 type: OPIN location: (8,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 80: in check_rr_node: RR node: 9131 type: OPIN location: (9,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 81: in check_rr_node: RR node: 9132 type: OPIN location: (9,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 82: in check_rr_node: RR node: 10251 type: OPIN location: (10,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 83: in check_rr_node: RR node: 10252 type: OPIN location: (10,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 84: in check_rr_node: RR node: 11371 type: OPIN location: (11,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 85: in check_rr_node: RR node: 11372 type: OPIN location: (11,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 86: in check_rr_node: RR node: 12491 type: OPIN location: (12,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 87: in check_rr_node: RR node: 12492 type: OPIN location: (12,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
### Build routing resource graph took 0.07 seconds (max_rss 18.5 MiB, delta_rss +0.4 MiB)
|
||
|
|
RR Graph Nodes: 18580
|
||
|
|
RR Graph Edges: 77708
|
||
|
|
### Computing delta delays
|
||
|
|
### Computing delta delays took 0.03 seconds (max_rss 18.5 MiB, delta_rss +0.0 MiB)
|
||
|
|
## Computing placement delta delay look-up took 0.10 seconds (max_rss 18.5 MiB, delta_rss +0.4 MiB)
|
||
|
|
|
||
|
|
There are 3 point to point connections in this circuit.
|
||
|
|
|
||
|
|
|
||
|
|
BB estimate of min-dist (placement) wire length: 44
|
||
|
|
|
||
|
|
Completed placement consistency check successfully.
|
||
|
|
Initial placement cost: 1 bb_cost: 1.1 td_cost: 1.11489e-09
|
||
|
|
Initial placement estimated Critical Path Delay (CPD): 1.15731 ns
|
||
|
|
Initial placement estimated setup Total Negative Slack (sTNS): -1.15731 ns
|
||
|
|
Initial placement estimated setup Worst Negative Slack (sWNS): -1.15731 ns
|
||
|
|
|
||
|
|
Initial placement estimated setup slack histogram:
|
||
|
|
[ -1.2e-09: -1.2e-09) 1 (100.0%) |**************************************************
|
||
|
|
[ -1.2e-09: -1.2e-09) 0 ( 0.0%) |
|
||
|
|
[ -1.2e-09: -1.2e-09) 0 ( 0.0%) |
|
||
|
|
[ -1.2e-09: -1.2e-09) 0 ( 0.0%) |
|
||
|
|
[ -1.2e-09: -1.2e-09) 0 ( 0.0%) |
|
||
|
|
[ -1.2e-09: -1.2e-09) 0 ( 0.0%) |
|
||
|
|
[ -1.2e-09: -1.2e-09) 0 ( 0.0%) |
|
||
|
|
[ -1.2e-09: -1.2e-09) 0 ( 0.0%) |
|
||
|
|
[ -1.2e-09: -1.2e-09) 0 ( 0.0%) |
|
||
|
|
[ -1.2e-09: -1.2e-09) 0 ( 0.0%) |
|
||
|
|
Placement contains 0 placement macros involving 0 blocks (average macro size -nan)
|
||
|
|
|
||
|
|
------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------
|
||
|
|
T Av Cost Av BB Cost Av TD Cost CPD sTNS sWNS Ac Rate Std Dev R lim Crit Exp Tot Moves Alpha
|
||
|
|
------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------
|
||
|
|
3.1e+00 0.994 1.06 1.0459e-09 1.099 -1.1 -1.099 1.000 0.0592 13.0 1.00 6 0.500
|
||
|
|
1.6e+00 0.749 0.76 8.0409e-10 1.041 -1.04 -1.041 1.000 0.1146 13.0 1.00 12 0.500
|
||
|
|
7.8e-01 1.014 0.62 7.1098e-10 0.809 -0.809 -0.809 0.833 0.0506 13.0 1.00 18 0.900
|
||
|
|
7.0e-01 1.094 0.76 7.9741e-10 0.809 -0.809 -0.809 0.667 0.0921 13.0 1.00 24 0.950
|
||
|
|
6.7e-01 0.843 0.65 8.2123e-10 0.925 -0.925 -0.925 1.000 0.1474 13.0 1.00 30 0.500
|
||
|
|
3.3e-01 1.083 0.82 9.0289e-10 1.041 -1.04 -1.041 1.000 0.0776 13.0 1.00 36 0.500
|
||
|
|
1.7e-01 1.134 0.95 9.2612e-10 0.983 -0.983 -0.983 0.667 0.0390 13.0 1.00 42 0.950
|
||
|
|
1.6e-01 0.982 0.98 9.1327e-10 1.041 -1.04 -1.041 0.667 0.1202 13.0 1.00 48 0.950
|
||
|
|
1.5e-01 0.993 0.82 8.3053e-10 0.983 -0.983 -0.983 1.000 0.1073 13.0 1.00 54 0.500
|
||
|
|
7.5e-02 1.064 0.75 8.9614e-10 0.925 -0.925 -0.925 0.667 0.0943 13.0 1.00 60 0.950
|
||
|
|
7.1e-02 0.941 0.79 8.8035e-10 1.041 -1.04 -1.041 0.500 0.1518 13.0 1.00 66 0.950
|
||
|
|
6.8e-02 0.985 0.60 7.6841e-10 0.867 -0.867 -0.867 0.333 0.0794 13.0 1.00 72 0.950
|
||
|
|
6.4e-02 1.074 0.60 7.7523e-10 0.867 -0.867 -0.867 0.167 0.0000 11.6 1.81 78 0.950
|
||
|
|
6.1e-02 0.936 0.54 7.2608e-10 0.925 -0.925 -0.925 0.500 0.1512 8.4 3.66 84 0.950
|
||
|
|
5.8e-02 0.909 0.35 5.8168e-10 0.809 -0.809 -0.809 0.167 0.0000 8.9 3.37 90 0.950
|
||
|
|
5.5e-02 1.036 0.38 6.2341e-10 0.751 -0.751 -0.751 0.167 0.0000 6.5 4.79 96 0.950
|
||
|
|
5.2e-02 1.015 0.38 6.5241e-10 0.751 -0.751 -0.751 0.333 0.0676 4.7 5.83 102 0.950
|
||
|
|
5.0e-02 1.045 0.36 6.9591e-10 0.751 -0.751 -0.751 0.667 0.0436 4.2 6.12 108 0.950
|
||
|
|
4.7e-02 0.972 0.34 5.8511e-10 0.809 -0.809 -0.809 0.500 0.0317 5.2 5.56 114 0.950
|
||
|
|
4.5e-02 1.000 0.33 6.2341e-10 0.751 -0.751 -0.751 0.000 0.0000 5.5 5.38 120 0.950
|
||
|
|
4.3e-02 0.913 0.29 5.6541e-10 0.751 -0.751 -0.751 0.333 0.0272 3.1 6.79 126 0.950
|
||
|
|
4.1e-02 0.977 0.26 5.6541e-10 0.693 -0.693 -0.693 0.333 0.0321 2.7 6.98 132 0.950
|
||
|
|
3.9e-02 1.000 0.28 5.6541e-10 0.693 -0.693 -0.693 0.333 0.0000 2.5 7.15 138 0.950
|
||
|
|
3.7e-02 1.000 0.28 5.6541e-10 0.693 -0.693 -0.693 0.000 0.0000 2.2 7.31 144 0.950
|
||
|
|
3.5e-02 1.010 0.28 5.8474e-10 0.693 -0.693 -0.693 0.500 0.0605 1.2 7.87 150 0.950
|
||
|
|
3.3e-02 1.025 0.26 5.6541e-10 0.693 -0.693 -0.693 0.333 0.0354 1.3 7.82 156 0.950
|
||
|
|
3.1e-02 0.979 0.26 5.8474e-10 0.693 -0.693 -0.693 0.500 0.1006 1.2 7.91 162 0.950
|
||
|
|
3.0e-02 1.000 0.20 5.6541e-10 0.693 -0.693 -0.693 0.000 0.0000 1.2 7.87 168 0.950
|
||
|
|
2.8e-02 0.967 0.18 6.2341e-10 0.693 -0.693 -0.693 0.167 0.0000 1.0 8.00 174 0.950
|
||
|
|
2.7e-02 1.021 0.19 5.0505e-10 0.751 -0.751 -0.751 0.333 0.0300 1.0 8.00 180 0.950
|
||
|
|
2.6e-02 1.000 0.18 5.3405e-10 0.751 -0.751 -0.751 0.000 0.0000 1.0 8.00 186 0.800
|
||
|
|
2.0e-02 0.900 0.15 4.7605e-10 0.751 -0.751 -0.751 0.167 0.0000 1.0 8.00 192 0.950
|
||
|
|
1.9e-02 1.000 0.15 5.6541e-10 0.693 -0.693 -0.693 0.000 0.0000 1.0 8.00 198 0.800
|
||
|
|
1.6e-02 1.000 0.15 5.6541e-10 0.693 -0.693 -0.693 0.000 0.0000 1.0 8.00 204 0.800
|
||
|
|
1.2e-02 1.000 0.15 5.6541e-10 0.693 -0.693 -0.693 0.000 0.0000 1.0 8.00 210 0.800
|
||
|
|
1.0e-02 1.000 0.15 5.6541e-10 0.693 -0.693 -0.693 0.000 0.0000 1.0 8.00 216 0.800
|
||
|
|
8.0e-03 1.000 0.15 5.6541e-10 0.693 -0.693 -0.693 0.000 0.0000 1.0 8.00 222 0.800
|
||
|
|
6.4e-03 1.000 0.15 5.6541e-10 0.693 -0.693 -0.693 0.000 0.0000 1.0 8.00 228 0.800
|
||
|
|
5.1e-03 1.000 0.15 5.6541e-10 0.693 -0.693 -0.693 0.000 0.0000 1.0 8.00 234 0.800
|
||
|
|
4.1e-03 1.000 0.15 5.6541e-10 0.693 -0.693 -0.693 0.000 0.0000 1.0 8.00 240 0.800
|
||
|
|
3.3e-03 1.000 0.15 5.6541e-10 0.693 -0.693 -0.693 0.000 0.0000 1.0 8.00 246 0.800
|
||
|
|
2.6e-03 1.000 0.15 5.6541e-10 0.693 -0.693 -0.693 0.000 0.0000 1.0 8.00 252 0.800
|
||
|
|
2.1e-03 1.000 0.15 5.6541e-10 0.693 -0.693 -0.693 0.000 0.0000 1.0 8.00 258 0.800
|
||
|
|
1.7e-03 1.000 0.15 5.6541e-10 0.693 -0.693 -0.693 0.000 0.0000 1.0 8.00 264 0.800
|
||
|
|
1.7e-03 1.000 0.15 5.6541e-10 0.693 -0.693 -0.693 0.000 0.0000 1.0 8.00 270 0.000
|
||
|
|
|
||
|
|
BB estimate of min-dist (placement) wire length: 6
|
||
|
|
|
||
|
|
Completed placement consistency check successfully.
|
||
|
|
|
||
|
|
Swaps called: 274
|
||
|
|
|
||
|
|
Placement estimated critical path delay: 0.69331 ns
|
||
|
|
Placement estimated setup Total Negative Slack (sTNS): -0.69331 ns
|
||
|
|
Placement estimated setup Worst Negative Slack (sWNS): -0.69331 ns
|
||
|
|
|
||
|
|
Placement estimated setup slack histogram:
|
||
|
|
[ -6.9e-10: -6.9e-10) 1 (100.0%) |**************************************************
|
||
|
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
|
|
||
|
|
Placement cost: 1, bb_cost: 0.15, td_cost: 5.6541e-10,
|
||
|
|
|
||
|
|
Placement resource usage:
|
||
|
|
io implemented as io_bottom: 3
|
||
|
|
clb implemented as clb : 1
|
||
|
|
|
||
|
|
Placement number of temperatures: 45
|
||
|
|
Placement total # of swap attempts: 274
|
||
|
|
Swaps accepted: 93 (33.9 %)
|
||
|
|
Swaps rejected: 181 (66.1 %)
|
||
|
|
Swaps aborted : 0 ( 0.0 %)
|
||
|
|
|
||
|
|
Aborted Move Reasons:
|
||
|
|
# Placement took 0.11 seconds (max_rss 18.9 MiB, delta_rss +0.9 MiB)
|
||
|
|
|
||
|
|
# Routing
|
||
|
|
## Build tileable routing resource graph
|
||
|
|
X-direction routing channel width is 40
|
||
|
|
Y-direction routing channel width is 40
|
||
|
|
Warning 88: in check_rr_node: RR node: 489 type: OPIN location: (1,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 89: in check_rr_node: RR node: 490 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 90: in check_rr_node: RR node: 579 type: OPIN location: (2,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 91: in check_rr_node: RR node: 580 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 92: in check_rr_node: RR node: 669 type: OPIN location: (3,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 93: in check_rr_node: RR node: 670 type: OPIN location: (3,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 94: in check_rr_node: RR node: 759 type: OPIN location: (4,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 95: in check_rr_node: RR node: 760 type: OPIN location: (4,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 96: in check_rr_node: RR node: 849 type: OPIN location: (5,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 97: in check_rr_node: RR node: 850 type: OPIN location: (5,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 98: in check_rr_node: RR node: 939 type: OPIN location: (6,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 99: in check_rr_node: RR node: 940 type: OPIN location: (6,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 100: in check_rr_node: RR node: 1029 type: OPIN location: (7,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 101: in check_rr_node: RR node: 1030 type: OPIN location: (7,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 102: in check_rr_node: RR node: 1119 type: OPIN location: (8,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 103: in check_rr_node: RR node: 1120 type: OPIN location: (8,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 104: in check_rr_node: RR node: 1209 type: OPIN location: (9,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 105: in check_rr_node: RR node: 1210 type: OPIN location: (9,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 106: in check_rr_node: RR node: 1299 type: OPIN location: (10,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 107: in check_rr_node: RR node: 1300 type: OPIN location: (10,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 108: in check_rr_node: RR node: 1389 type: OPIN location: (11,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 109: in check_rr_node: RR node: 1390 type: OPIN location: (11,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 110: in check_rr_node: RR node: 1479 type: OPIN location: (12,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||
|
|
Warning 111: in check_rr_node: RR node: 1480 type: OPIN location: (12,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||
|
|
## Build tileable routing resource graph took 0.13 seconds (max_rss 19.2 MiB, delta_rss +0.3 MiB)
|
||
|
|
RR Graph Nodes: 18580
|
||
|
|
RR Graph Edges: 96524
|
||
|
|
Confirming router algorithm: TIMING_DRIVEN.
|
||
|
|
---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- --------
|
||
|
|
Iter Time pres BBs Heap Re-Rtd Re-Rtd Overused RR Nodes Wirelength CPD sTNS sWNS hTNS hWNS Est Succ
|
||
|
|
(sec) fac Updt push Nets Conns (ns) (ns) (ns) (ns) (ns) Iter
|
||
|
|
---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- --------
|
||
|
|
1 0.0 0.0 0 234 3 3 3 ( 0.016%) 16 ( 0.1%) 0.809 -0.8093 -0.809 0.000 0.000 N/A
|
||
|
|
2 0.0 0.5 0 94 2 2 2 ( 0.011%) 16 ( 0.1%) 0.809 -0.8093 -0.809 0.000 0.000 N/A
|
||
|
|
3 0.0 0.6 0 102 2 2 1 ( 0.005%) 17 ( 0.1%) 0.809 -0.8093 -0.809 0.000 0.000 N/A
|
||
|
|
4 0.0 0.8 0 102 2 2 1 ( 0.005%) 17 ( 0.1%) 0.809 -0.8093 -0.809 0.000 0.000 N/A
|
||
|
|
5 0.0 1.1 0 108 2 2 1 ( 0.005%) 17 ( 0.1%) 0.809 -0.8093 -0.809 0.000 0.000 N/A
|
||
|
|
6 0.0 1.4 0 108 2 2 1 ( 0.005%) 17 ( 0.1%) 0.809 -0.8093 -0.809 0.000 0.000 N/A
|
||
|
|
7 0.0 1.9 0 108 2 2 1 ( 0.005%) 17 ( 0.1%) 0.809 -0.8093 -0.809 0.000 0.000 N/A
|
||
|
|
8 0.0 2.4 0 108 2 2 1 ( 0.005%) 17 ( 0.1%) 0.809 -0.8093 -0.809 0.000 0.000 N/A
|
||
|
|
9 0.0 3.1 0 108 2 2 1 ( 0.005%) 17 ( 0.1%) 0.809 -0.8093 -0.809 0.000 0.000 N/A
|
||
|
|
10 0.0 4.1 0 108 2 2 1 ( 0.005%) 17 ( 0.1%) 0.809 -0.8093 -0.809 0.000 0.000 N/A
|
||
|
|
11 0.0 5.3 0 108 2 2 1 ( 0.005%) 17 ( 0.1%) 0.809 -0.8093 -0.809 0.000 0.000 N/A
|
||
|
|
12 0.0 6.9 0 108 2 2 1 ( 0.005%) 17 ( 0.1%) 0.809 -0.8093 -0.809 0.000 0.000 N/A
|
||
|
|
13 0.0 9.0 0 108 2 2 1 ( 0.005%) 17 ( 0.1%) 0.809 -0.8093 -0.809 0.000 0.000 N/A
|
||
|
|
14 0.0 11.6 0 108 2 2 1 ( 0.005%) 17 ( 0.1%) 0.809 -0.8093 -0.809 0.000 0.000 N/A
|
||
|
|
15 0.0 15.1 0 108 2 2 1 ( 0.005%) 17 ( 0.1%) 0.809 -0.8093 -0.809 0.000 0.000 N/A
|
||
|
|
16 0.0 19.7 0 214 2 2 1 ( 0.005%) 17 ( 0.1%) 0.809 -0.8093 -0.809 0.000 0.000 N/A
|
||
|
|
17 0.0 25.6 0 466 2 2 1 ( 0.005%) 17 ( 0.1%) 0.809 -0.8093 -0.809 0.000 0.000 N/A
|
||
|
|
18 0.0 33.3 0 232 1 1 0 ( 0.000%) 22 ( 0.2%) 0.925 -0.9253 -0.925 0.000 0.000 N/A
|
||
|
|
Restoring best routing
|
||
|
|
Critical path: 0.92531 ns
|
||
|
|
Successfully routed after 18 routing iterations.
|
||
|
|
Router Stats: total_nets_routed: 36 total_connections_routed: 36 total_heap_pushes: 2632 total_heap_pops: 994
|
||
|
|
# Routing took 0.15 seconds (max_rss 19.4 MiB, delta_rss +0.5 MiB)
|
||
|
|
|
||
|
|
Checking to ensure routing is legal...
|
||
|
|
Completed routing consistency check successfully.
|
||
|
|
|
||
|
|
Serial number (magic cookie) for the routing is: -13691
|
||
|
|
Circuit successfully routed with a channel width factor of 40.
|
||
|
|
|
||
|
|
Average number of bends per net: 2.33333 Maximum # of bends: 3
|
||
|
|
|
||
|
|
Number of global nets: 0
|
||
|
|
Number of routed nets (nonglobal): 3
|
||
|
|
Wire length results (in units of 1 clb segments)...
|
||
|
|
Total wirelength: 22, average net length: 7.33333
|
||
|
|
Maximum net length: 12
|
||
|
|
|
||
|
|
Wire length results in terms of physical segments...
|
||
|
|
Total wiring segments used: 10, average wire segments per net: 3.33333
|
||
|
|
Maximum segments used by a net: 4
|
||
|
|
Total local nets with reserved CLB opins: 0
|
||
|
|
|
||
|
|
Routing channel utilization histogram:
|
||
|
|
[ 1: inf) 0 ( 0.0%) |
|
||
|
|
[ 0.9: 1) 0 ( 0.0%) |
|
||
|
|
[ 0.8: 0.9) 0 ( 0.0%) |
|
||
|
|
[ 0.7: 0.8) 0 ( 0.0%) |
|
||
|
|
[ 0.5: 0.6) 0 ( 0.0%) |
|
||
|
|
[ 0.4: 0.5) 0 ( 0.0%) |
|
||
|
|
[ 0.3: 0.4) 0 ( 0.0%) |
|
||
|
|
[ 0.2: 0.3) 0 ( 0.0%) |
|
||
|
|
[ 0.1: 0.2) 0 ( 0.0%) |
|
||
|
|
[ 0: 0.1) 338 (100.0%) |***********************************************
|
||
|
|
Maximum routing channel utilization: 0.075 at (9,0)
|
||
|
|
|
||
|
|
X - Directed channels: j max occ ave occ capacity
|
||
|
|
---- ------- ------- --------
|
||
|
|
0 3 0.500 40
|
||
|
|
1 1 0.286 40
|
||
|
|
2 1 0.286 40
|
||
|
|
3 0 0.000 40
|
||
|
|
4 0 0.000 40
|
||
|
|
5 0 0.000 40
|
||
|
|
6 0 0.000 40
|
||
|
|
7 0 0.000 40
|
||
|
|
8 0 0.000 40
|
||
|
|
9 0 0.000 40
|
||
|
|
10 0 0.000 40
|
||
|
|
11 0 0.000 40
|
||
|
|
12 0 0.000 40
|
||
|
|
Y - Directed channels: i max occ ave occ capacity
|
||
|
|
---- ------- ------- --------
|
||
|
|
0 0 0.000 40
|
||
|
|
1 0 0.000 40
|
||
|
|
2 0 0.000 40
|
||
|
|
3 0 0.000 40
|
||
|
|
4 0 0.000 40
|
||
|
|
5 0 0.000 40
|
||
|
|
6 0 0.000 40
|
||
|
|
7 1 0.143 40
|
||
|
|
8 1 0.071 40
|
||
|
|
9 3 0.286 40
|
||
|
|
10 0 0.000 40
|
||
|
|
11 0 0.000 40
|
||
|
|
12 0 0.000 40
|
||
|
|
|
||
|
|
Total tracks in x-direction: 520, in y-direction: 520
|
||
|
|
|
||
|
|
Logic area (in minimum width transistor areas, excludes I/Os and empty grid tiles)...
|
||
|
|
Total logic block area (Warning, need to add pitch of routing to blocks with height > 3): 7.76074e+06
|
||
|
|
Total used logic block area: 53894
|
||
|
|
|
||
|
|
Routing area (in minimum width transistor areas)...
|
||
|
|
Total routing area: 616743., per logic tile: 3146.65
|
||
|
|
|
||
|
|
Segment usage by type (index): type utilization
|
||
|
|
---- -----------
|
||
|
|
0 0.00321
|
||
|
|
1 0.00444
|
||
|
|
2 0.000962
|
||
|
|
|
||
|
|
Segment usage by length: length utilization
|
||
|
|
------ -----------
|
||
|
|
1 0.00321
|
||
|
|
2 0.00444
|
||
|
|
4 0.000962
|
||
|
|
|
||
|
|
|
||
|
|
Hold Worst Negative Slack (hWNS): 0 ns
|
||
|
|
Hold Total Negative Slack (hTNS): 0 ns
|
||
|
|
|
||
|
|
Hold slack histogram:
|
||
|
|
[ 7.3e-10: 7.3e-10) 1 (100.0%) |**************************************************
|
||
|
|
[ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
|
||
|
|
[ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
|
||
|
|
[ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
|
||
|
|
[ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
|
||
|
|
[ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
|
||
|
|
[ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
|
||
|
|
[ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
|
||
|
|
[ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
|
||
|
|
[ 7.3e-10: 7.3e-10) 0 ( 0.0%) |
|
||
|
|
|
||
|
|
Final critical path: 0.92531 ns, Fmax: 1080.72 MHz
|
||
|
|
Setup Worst Negative Slack (sWNS): -0.92531 ns
|
||
|
|
Setup Total Negative Slack (sTNS): -0.92531 ns
|
||
|
|
|
||
|
|
Setup slack histogram:
|
||
|
|
[ -9.3e-10: -9.3e-10) 1 (100.0%) |**************************************************
|
||
|
|
[ -9.3e-10: -9.3e-10) 0 ( 0.0%) |
|
||
|
|
[ -9.3e-10: -9.3e-10) 0 ( 0.0%) |
|
||
|
|
[ -9.3e-10: -9.3e-10) 0 ( 0.0%) |
|
||
|
|
[ -9.3e-10: -9.3e-10) 0 ( 0.0%) |
|
||
|
|
[ -9.3e-10: -9.3e-10) 0 ( 0.0%) |
|
||
|
|
[ -9.3e-10: -9.3e-10) 0 ( 0.0%) |
|
||
|
|
[ -9.3e-10: -9.3e-10) 0 ( 0.0%) |
|
||
|
|
[ -9.3e-10: -9.3e-10) 0 ( 0.0%) |
|
||
|
|
[ -9.3e-10: -9.3e-10) 0 ( 0.0%) |
|
||
|
|
|
||
|
|
Timing analysis took 0.000524223 seconds (0.00046474 STA, 5.9483e-05 slack) (67 full updates: 48 setup, 0 hold, 19 combined).
|
||
|
|
VPR suceeded
|
||
|
|
The entire flow of VPR took 0.50 seconds (max_rss 19.5 MiB)
|
||
|
|
|
||
|
|
Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml
|
||
|
|
|
||
|
|
Confirm selected options when call command 'read_openfpga_arch':
|
||
|
|
--file, -f: /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml
|
||
|
|
Reading XML architecture '/research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml'...
|
||
|
|
Read OpenFPGA architecture
|
||
|
|
Warning 112: Automatically set circuit model 'frac_lut4' to be default in its type.
|
||
|
|
Warning 113: Automatically set circuit model 'sky130_fd_sc_hd__sdfxtp_1' to be default in its type.
|
||
|
|
Warning 114: Automatically set circuit model 'sky130_fd_sc_hd__dfxtp_1' to be default in its type.
|
||
|
|
Use the default configurable memory model 'sky130_fd_sc_hd__dfxtp_1' for circuit model 'mux_tree' port 'sram')
|
||
|
|
Use the default configurable memory model 'sky130_fd_sc_hd__dfxtp_1' for circuit model 'mux_tree_tapbuf' port 'sram')
|
||
|
|
Use the default configurable memory model 'sky130_fd_sc_hd__dfxtp_1' for circuit model 'frac_lut4' port 'sram')
|
||
|
|
Read OpenFPGA architecture took 0.00 seconds (max_rss 19.8 MiB, delta_rss +0.3 MiB)
|
||
|
|
Check circuit library
|
||
|
|
Checking circuit library passed.
|
||
|
|
Check circuit library took 0.00 seconds (max_rss 19.8 MiB, delta_rss +0.0 MiB)
|
||
|
|
Found 0 errors when checking configurable memory circuit models!
|
||
|
|
Found 0 errors when checking tile annotation!
|
||
|
|
|
||
|
|
Command line to execute: read_openfpga_simulation_setting -f /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||
|
|
|
||
|
|
Confirm selected options when call command 'read_openfpga_simulation_setting':
|
||
|
|
--file, -f: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||
|
|
Reading XML simulation setting '/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'...
|
||
|
|
Read OpenFPGA simulation settings
|
||
|
|
Read OpenFPGA simulation settings took 0.00 seconds (max_rss 19.8 MiB, delta_rss +0.0 MiB)
|
||
|
|
|
||
|
|
Command line to execute: link_openfpga_arch --activity_file top_ace_out.act --sort_gsb_chan_node_in_edges
|
||
|
|
|
||
|
|
Confirm selected options when call command 'link_openfpga_arch':
|
||
|
|
--activity_file: top_ace_out.act
|
||
|
|
--sort_gsb_chan_node_in_edges: on
|
||
|
|
--verbose: off
|
||
|
|
Link OpenFPGA architecture to VPR architecture
|
||
|
|
|
||
|
|
Building annotation for physical modes in pb_type...Done
|
||
|
|
Check physical mode annotation for pb_types passed.
|
||
|
|
|
||
|
|
Building annotation about physical types for pb_type interconnection...Done
|
||
|
|
|
||
|
|
Building annotation between operating and physical pb_types...Done
|
||
|
|
Check physical pb_type annotation for pb_types passed.
|
||
|
|
|
||
|
|
Building annotation between physical pb_types and circuit models...Done
|
||
|
|
Check physical pb_type annotation for circuit model passed.
|
||
|
|
|
||
|
|
Building annotation between physical pb_types and mode selection bits...Done
|
||
|
|
Check pb_type annotation for mode selection bits passed.
|
||
|
|
Assigning unique indices for primitive pb_graph nodes...Done
|
||
|
|
Binding operating pb_graph nodes/pins to physical pb_graph nodes/pins...Done
|
||
|
|
Check pb_graph annotation for physical nodes and pins passed.
|
||
|
|
Binded 4 routing resource graph switches to circuit models
|
||
|
|
Binded 3 routing segments to circuit models
|
||
|
|
Binded 2 direct connections to circuit models
|
||
|
|
Annotating rr_node with routed nets...Done with 16 nodes mapping
|
||
|
|
Annotating previous nodes for rr_node...Warning 115: Override the previous node '1243' by previous node '1241' for node '1188' with in routing context annotation!
|
||
|
|
Done with 19 nodes mapping
|
||
|
|
# Build General Switch Block(GSB) annotation on top of routing resource graph
|
||
|
|
[0%] Backannotated GSB[0][0]
|
||
|
|
[1%] Backannotated GSB[0][1]
|
||
|
|
[1%] Backannotated GSB[0][2]
|
||
|
|
[2%] Backannotated GSB[0][3]
|
||
|
|
[2%] Backannotated GSB[0][4]
|
||
|
|
[3%] Backannotated GSB[0][5]
|
||
|
|
[4%] Backannotated GSB[0][6]
|
||
|
|
[4%] Backannotated GSB[0][7]
|
||
|
|
[5%] Backannotated GSB[0][8]
|
||
|
|
[5%] Backannotated GSB[0][9]
|
||
|
|
[6%] Backannotated GSB[0][10]
|
||
|
|
[7%] Backannotated GSB[0][11]
|
||
|
|
[7%] Backannotated GSB[0][12]
|
||
|
|
[8%] Backannotated GSB[1][0]
|
||
|
|
[8%] Backannotated GSB[1][1]
|
||
|
|
[9%] Backannotated GSB[1][2]
|
||
|
|
[10%] Backannotated GSB[1][3]
|
||
|
|
[10%] Backannotated GSB[1][4]
|
||
|
|
[11%] Backannotated GSB[1][5]
|
||
|
|
[11%] Backannotated GSB[1][6]
|
||
|
|
[12%] Backannotated GSB[1][7]
|
||
|
|
[13%] Backannotated GSB[1][8]
|
||
|
|
[13%] Backannotated GSB[1][9]
|
||
|
|
[14%] Backannotated GSB[1][10]
|
||
|
|
[14%] Backannotated GSB[1][11]
|
||
|
|
[15%] Backannotated GSB[1][12]
|
||
|
|
[15%] Backannotated GSB[2][0]
|
||
|
|
[16%] Backannotated GSB[2][1]
|
||
|
|
[17%] Backannotated GSB[2][2]
|
||
|
|
[17%] Backannotated GSB[2][3]
|
||
|
|
[18%] Backannotated GSB[2][4]
|
||
|
|
[18%] Backannotated GSB[2][5]
|
||
|
|
[19%] Backannotated GSB[2][6]
|
||
|
|
[20%] Backannotated GSB[2][7]
|
||
|
|
[20%] Backannotated GSB[2][8]
|
||
|
|
[21%] Backannotated GSB[2][9]
|
||
|
|
[21%] Backannotated GSB[2][10]
|
||
|
|
[22%] Backannotated GSB[2][11]
|
||
|
|
[23%] Backannotated GSB[2][12]
|
||
|
|
[23%] Backannotated GSB[3][0]
|
||
|
|
[24%] Backannotated GSB[3][1]
|
||
|
|
[24%] Backannotated GSB[3][2]
|
||
|
|
[25%] Backannotated GSB[3][3]
|
||
|
|
[26%] Backannotated GSB[3][4]
|
||
|
|
[26%] Backannotated GSB[3][5]
|
||
|
|
[27%] Backannotated GSB[3][6]
|
||
|
|
[27%] Backannotated GSB[3][7]
|
||
|
|
[28%] Backannotated GSB[3][8]
|
||
|
|
[28%] Backannotated GSB[3][9]
|
||
|
|
[29%] Backannotated GSB[3][10]
|
||
|
|
[30%] Backannotated GSB[3][11]
|
||
|
|
[30%] Backannotated GSB[3][12]
|
||
|
|
[31%] Backannotated GSB[4][0]
|
||
|
|
[31%] Backannotated GSB[4][1]
|
||
|
|
[32%] Backannotated GSB[4][2]
|
||
|
|
[33%] Backannotated GSB[4][3]
|
||
|
|
[33%] Backannotated GSB[4][4]
|
||
|
|
[34%] Backannotated GSB[4][5]
|
||
|
|
[34%] Backannotated GSB[4][6]
|
||
|
|
[35%] Backannotated GSB[4][7]
|
||
|
|
[36%] Backannotated GSB[4][8]
|
||
|
|
[36%] Backannotated GSB[4][9]
|
||
|
|
[37%] Backannotated GSB[4][10]
|
||
|
|
[37%] Backannotated GSB[4][11]
|
||
|
|
[38%] Backannotated GSB[4][12]
|
||
|
|
[39%] Backannotated GSB[5][0]
|
||
|
|
[39%] Backannotated GSB[5][1]
|
||
|
|
[40%] Backannotated GSB[5][2]
|
||
|
|
[40%] Backannotated GSB[5][3]
|
||
|
|
[41%] Backannotated GSB[5][4]
|
||
|
|
[42%] Backannotated GSB[5][5]
|
||
|
|
[42%] Backannotated GSB[5][6]
|
||
|
|
[43%] Backannotated GSB[5][7]
|
||
|
|
[43%] Backannotated GSB[5][8]
|
||
|
|
[44%] Backannotated GSB[5][9]
|
||
|
|
[44%] Backannotated GSB[5][10]
|
||
|
|
[45%] Backannotated GSB[5][11]
|
||
|
|
[46%] Backannotated GSB[5][12]
|
||
|
|
[46%] Backannotated GSB[6][0]
|
||
|
|
[47%] Backannotated GSB[6][1]
|
||
|
|
[47%] Backannotated GSB[6][2]
|
||
|
|
[48%] Backannotated GSB[6][3]
|
||
|
|
[49%] Backannotated GSB[6][4]
|
||
|
|
[49%] Backannotated GSB[6][5]
|
||
|
|
[50%] Backannotated GSB[6][6]
|
||
|
|
[50%] Backannotated GSB[6][7]
|
||
|
|
[51%] Backannotated GSB[6][8]
|
||
|
|
[52%] Backannotated GSB[6][9]
|
||
|
|
[52%] Backannotated GSB[6][10]
|
||
|
|
[53%] Backannotated GSB[6][11]
|
||
|
|
[53%] Backannotated GSB[6][12]
|
||
|
|
[54%] Backannotated GSB[7][0]
|
||
|
|
[55%] Backannotated GSB[7][1]
|
||
|
|
[55%] Backannotated GSB[7][2]
|
||
|
|
[56%] Backannotated GSB[7][3]
|
||
|
|
[56%] Backannotated GSB[7][4]
|
||
|
|
[57%] Backannotated GSB[7][5]
|
||
|
|
[57%] Backannotated GSB[7][6]
|
||
|
|
[58%] Backannotated GSB[7][7]
|
||
|
|
[59%] Backannotated GSB[7][8]
|
||
|
|
[59%] Backannotated GSB[7][9]
|
||
|
|
[60%] Backannotated GSB[7][10]
|
||
|
|
[60%] Backannotated GSB[7][11]
|
||
|
|
[61%] Backannotated GSB[7][12]
|
||
|
|
[62%] Backannotated GSB[8][0]
|
||
|
|
[62%] Backannotated GSB[8][1]
|
||
|
|
[63%] Backannotated GSB[8][2]
|
||
|
|
[63%] Backannotated GSB[8][3]
|
||
|
|
[64%] Backannotated GSB[8][4]
|
||
|
|
[65%] Backannotated GSB[8][5]
|
||
|
|
[65%] Backannotated GSB[8][6]
|
||
|
|
[66%] Backannotated GSB[8][7]
|
||
|
|
[66%] Backannotated GSB[8][8]
|
||
|
|
[67%] Backannotated GSB[8][9]
|
||
|
|
[68%] Backannotated GSB[8][10]
|
||
|
|
[68%] Backannotated GSB[8][11]
|
||
|
|
[69%] Backannotated GSB[8][12]
|
||
|
|
[69%] Backannotated GSB[9][0]
|
||
|
|
[70%] Backannotated GSB[9][1]
|
||
|
|
[71%] Backannotated GSB[9][2]
|
||
|
|
[71%] Backannotated GSB[9][3]
|
||
|
|
[72%] Backannotated GSB[9][4]
|
||
|
|
[72%] Backannotated GSB[9][5]
|
||
|
|
[73%] Backannotated GSB[9][6]
|
||
|
|
[73%] Backannotated GSB[9][7]
|
||
|
|
[74%] Backannotated GSB[9][8]
|
||
|
|
[75%] Backannotated GSB[9][9]
|
||
|
|
[75%] Backannotated GSB[9][10]
|
||
|
|
[76%] Backannotated GSB[9][11]
|
||
|
|
[76%] Backannotated GSB[9][12]
|
||
|
|
[77%] Backannotated GSB[10][0]
|
||
|
|
[78%] Backannotated GSB[10][1]
|
||
|
|
[78%] Backannotated GSB[10][2]
|
||
|
|
[79%] Backannotated GSB[10][3]
|
||
|
|
[79%] Backannotated GSB[10][4]
|
||
|
|
[80%] Backannotated GSB[10][5]
|
||
|
|
[81%] Backannotated GSB[10][6]
|
||
|
|
[81%] Backannotated GSB[10][7]
|
||
|
|
[82%] Backannotated GSB[10][8]
|
||
|
|
[82%] Backannotated GSB[10][9]
|
||
|
|
[83%] Backannotated GSB[10][10]
|
||
|
|
[84%] Backannotated GSB[10][11]
|
||
|
|
[84%] Backannotated GSB[10][12]
|
||
|
|
[85%] Backannotated GSB[11][0]
|
||
|
|
[85%] Backannotated GSB[11][1]
|
||
|
|
[86%] Backannotated GSB[11][2]
|
||
|
|
[86%] Backannotated GSB[11][3]
|
||
|
|
[87%] Backannotated GSB[11][4]
|
||
|
|
[88%] Backannotated GSB[11][5]
|
||
|
|
[88%] Backannotated GSB[11][6]
|
||
|
|
[89%] Backannotated GSB[11][7]
|
||
|
|
[89%] Backannotated GSB[11][8]
|
||
|
|
[90%] Backannotated GSB[11][9]
|
||
|
|
[91%] Backannotated GSB[11][10]
|
||
|
|
[91%] Backannotated GSB[11][11]
|
||
|
|
[92%] Backannotated GSB[11][12]
|
||
|
|
[92%] Backannotated GSB[12][0]
|
||
|
|
[93%] Backannotated GSB[12][1]
|
||
|
|
[94%] Backannotated GSB[12][2]
|
||
|
|
[94%] Backannotated GSB[12][3]
|
||
|
|
[95%] Backannotated GSB[12][4]
|
||
|
|
[95%] Backannotated GSB[12][5]
|
||
|
|
[96%] Backannotated GSB[12][6]
|
||
|
|
[97%] Backannotated GSB[12][7]
|
||
|
|
[97%] Backannotated GSB[12][8]
|
||
|
|
[98%] Backannotated GSB[12][9]
|
||
|
|
[98%] Backannotated GSB[12][10]
|
||
|
|
[99%] Backannotated GSB[12][11]
|
||
|
|
[100%] Backannotated GSB[12][12]
|
||
|
|
Backannotated 169 General Switch Blocks (GSBs).
|
||
|
|
# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 19.8 MiB, delta_rss +0.0 MiB)
|
||
|
|
# Sort incoming edges for each routing track output node of General Switch Block(GSB)
|
||
|
|
[0%] Sorted edges for GSB[0][0]
|
||
|
|
[1%] Sorted edges for GSB[0][1]
|
||
|
|
[1%] Sorted edges for GSB[0][2]
|
||
|
|
[2%] Sorted edges for GSB[0][3]
|
||
|
|
[2%] Sorted edges for GSB[0][4]
|
||
|
|
[3%] Sorted edges for GSB[0][5]
|
||
|
|
[4%] Sorted edges for GSB[0][6]
|
||
|
|
[4%] Sorted edges for GSB[0][7]
|
||
|
|
[5%] Sorted edges for GSB[0][8]
|
||
|
|
[5%] Sorted edges for GSB[0][9]
|
||
|
|
[6%] Sorted edges for GSB[0][10]
|
||
|
|
[7%] Sorted edges for GSB[0][11]
|
||
|
|
[7%] Sorted edges for GSB[0][12]
|
||
|
|
[8%] Sorted edges for GSB[1][0]
|
||
|
|
[8%] Sorted edges for GSB[1][1]
|
||
|
|
[9%] Sorted edges for GSB[1][2]
|
||
|
|
[10%] Sorted edges for GSB[1][3]
|
||
|
|
[10%] Sorted edges for GSB[1][4]
|
||
|
|
[11%] Sorted edges for GSB[1][5]
|
||
|
|
[11%] Sorted edges for GSB[1][6]
|
||
|
|
[12%] Sorted edges for GSB[1][7]
|
||
|
|
[13%] Sorted edges for GSB[1][8]
|
||
|
|
[13%] Sorted edges for GSB[1][9]
|
||
|
|
[14%] Sorted edges for GSB[1][10]
|
||
|
|
[14%] Sorted edges for GSB[1][11]
|
||
|
|
[15%] Sorted edges for GSB[1][12]
|
||
|
|
[15%] Sorted edges for GSB[2][0]
|
||
|
|
[16%] Sorted edges for GSB[2][1]
|
||
|
|
[17%] Sorted edges for GSB[2][2]
|
||
|
|
[17%] Sorted edges for GSB[2][3]
|
||
|
|
[18%] Sorted edges for GSB[2][4]
|
||
|
|
[18%] Sorted edges for GSB[2][5]
|
||
|
|
[19%] Sorted edges for GSB[2][6]
|
||
|
|
[20%] Sorted edges for GSB[2][7]
|
||
|
|
[20%] Sorted edges for GSB[2][8]
|
||
|
|
[21%] Sorted edges for GSB[2][9]
|
||
|
|
[21%] Sorted edges for GSB[2][10]
|
||
|
|
[22%] Sorted edges for GSB[2][11]
|
||
|
|
[23%] Sorted edges for GSB[2][12]
|
||
|
|
[23%] Sorted edges for GSB[3][0]
|
||
|
|
[24%] Sorted edges for GSB[3][1]
|
||
|
|
[24%] Sorted edges for GSB[3][2]
|
||
|
|
[25%] Sorted edges for GSB[3][3]
|
||
|
|
[26%] Sorted edges for GSB[3][4]
|
||
|
|
[26%] Sorted edges for GSB[3][5]
|
||
|
|
[27%] Sorted edges for GSB[3][6]
|
||
|
|
[27%] Sorted edges for GSB[3][7]
|
||
|
|
[28%] Sorted edges for GSB[3][8]
|
||
|
|
[28%] Sorted edges for GSB[3][9]
|
||
|
|
[29%] Sorted edges for GSB[3][10]
|
||
|
|
[30%] Sorted edges for GSB[3][11]
|
||
|
|
[30%] Sorted edges for GSB[3][12]
|
||
|
|
[31%] Sorted edges for GSB[4][0]
|
||
|
|
[31%] Sorted edges for GSB[4][1]
|
||
|
|
[32%] Sorted edges for GSB[4][2]
|
||
|
|
[33%] Sorted edges for GSB[4][3]
|
||
|
|
[33%] Sorted edges for GSB[4][4]
|
||
|
|
[34%] Sorted edges for GSB[4][5]
|
||
|
|
[34%] Sorted edges for GSB[4][6]
|
||
|
|
[35%] Sorted edges for GSB[4][7]
|
||
|
|
[36%] Sorted edges for GSB[4][8]
|
||
|
|
[36%] Sorted edges for GSB[4][9]
|
||
|
|
[37%] Sorted edges for GSB[4][10]
|
||
|
|
[37%] Sorted edges for GSB[4][11]
|
||
|
|
[38%] Sorted edges for GSB[4][12]
|
||
|
|
[39%] Sorted edges for GSB[5][0]
|
||
|
|
[39%] Sorted edges for GSB[5][1]
|
||
|
|
[40%] Sorted edges for GSB[5][2]
|
||
|
|
[40%] Sorted edges for GSB[5][3]
|
||
|
|
[41%] Sorted edges for GSB[5][4]
|
||
|
|
[42%] Sorted edges for GSB[5][5]
|
||
|
|
[42%] Sorted edges for GSB[5][6]
|
||
|
|
[43%] Sorted edges for GSB[5][7]
|
||
|
|
[43%] Sorted edges for GSB[5][8]
|
||
|
|
[44%] Sorted edges for GSB[5][9]
|
||
|
|
[44%] Sorted edges for GSB[5][10]
|
||
|
|
[45%] Sorted edges for GSB[5][11]
|
||
|
|
[46%] Sorted edges for GSB[5][12]
|
||
|
|
[46%] Sorted edges for GSB[6][0]
|
||
|
|
[47%] Sorted edges for GSB[6][1]
|
||
|
|
[47%] Sorted edges for GSB[6][2]
|
||
|
|
[48%] Sorted edges for GSB[6][3]
|
||
|
|
[49%] Sorted edges for GSB[6][4]
|
||
|
|
[49%] Sorted edges for GSB[6][5]
|
||
|
|
[50%] Sorted edges for GSB[6][6]
|
||
|
|
[50%] Sorted edges for GSB[6][7]
|
||
|
|
[51%] Sorted edges for GSB[6][8]
|
||
|
|
[52%] Sorted edges for GSB[6][9]
|
||
|
|
[52%] Sorted edges for GSB[6][10]
|
||
|
|
[53%] Sorted edges for GSB[6][11]
|
||
|
|
[53%] Sorted edges for GSB[6][12]
|
||
|
|
[54%] Sorted edges for GSB[7][0]
|
||
|
|
[55%] Sorted edges for GSB[7][1]
|
||
|
|
[55%] Sorted edges for GSB[7][2]
|
||
|
|
[56%] Sorted edges for GSB[7][3]
|
||
|
|
[56%] Sorted edges for GSB[7][4]
|
||
|
|
[57%] Sorted edges for GSB[7][5]
|
||
|
|
[57%] Sorted edges for GSB[7][6]
|
||
|
|
[58%] Sorted edges for GSB[7][7]
|
||
|
|
[59%] Sorted edges for GSB[7][8]
|
||
|
|
[59%] Sorted edges for GSB[7][9]
|
||
|
|
[60%] Sorted edges for GSB[7][10]
|
||
|
|
[60%] Sorted edges for GSB[7][11]
|
||
|
|
[61%] Sorted edges for GSB[7][12]
|
||
|
|
[62%] Sorted edges for GSB[8][0]
|
||
|
|
[62%] Sorted edges for GSB[8][1]
|
||
|
|
[63%] Sorted edges for GSB[8][2]
|
||
|
|
[63%] Sorted edges for GSB[8][3]
|
||
|
|
[64%] Sorted edges for GSB[8][4]
|
||
|
|
[65%] Sorted edges for GSB[8][5]
|
||
|
|
[65%] Sorted edges for GSB[8][6]
|
||
|
|
[66%] Sorted edges for GSB[8][7]
|
||
|
|
[66%] Sorted edges for GSB[8][8]
|
||
|
|
[67%] Sorted edges for GSB[8][9]
|
||
|
|
[68%] Sorted edges for GSB[8][10]
|
||
|
|
[68%] Sorted edges for GSB[8][11]
|
||
|
|
[69%] Sorted edges for GSB[8][12]
|
||
|
|
[69%] Sorted edges for GSB[9][0]
|
||
|
|
[70%] Sorted edges for GSB[9][1]
|
||
|
|
[71%] Sorted edges for GSB[9][2]
|
||
|
|
[71%] Sorted edges for GSB[9][3]
|
||
|
|
[72%] Sorted edges for GSB[9][4]
|
||
|
|
[72%] Sorted edges for GSB[9][5]
|
||
|
|
[73%] Sorted edges for GSB[9][6]
|
||
|
|
[73%] Sorted edges for GSB[9][7]
|
||
|
|
[74%] Sorted edges for GSB[9][8]
|
||
|
|
[75%] Sorted edges for GSB[9][9]
|
||
|
|
[75%] Sorted edges for GSB[9][10]
|
||
|
|
[76%] Sorted edges for GSB[9][11]
|
||
|
|
[76%] Sorted edges for GSB[9][12]
|
||
|
|
[77%] Sorted edges for GSB[10][0]
|
||
|
|
[78%] Sorted edges for GSB[10][1]
|
||
|
|
[78%] Sorted edges for GSB[10][2]
|
||
|
|
[79%] Sorted edges for GSB[10][3]
|
||
|
|
[79%] Sorted edges for GSB[10][4]
|
||
|
|
[80%] Sorted edges for GSB[10][5]
|
||
|
|
[81%] Sorted edges for GSB[10][6]
|
||
|
|
[81%] Sorted edges for GSB[10][7]
|
||
|
|
[82%] Sorted edges for GSB[10][8]
|
||
|
|
[82%] Sorted edges for GSB[10][9]
|
||
|
|
[83%] Sorted edges for GSB[10][10]
|
||
|
|
[84%] Sorted edges for GSB[10][11]
|
||
|
|
[84%] Sorted edges for GSB[10][12]
|
||
|
|
[85%] Sorted edges for GSB[11][0]
|
||
|
|
[85%] Sorted edges for GSB[11][1]
|
||
|
|
[86%] Sorted edges for GSB[11][2]
|
||
|
|
[86%] Sorted edges for GSB[11][3]
|
||
|
|
[87%] Sorted edges for GSB[11][4]
|
||
|
|
[88%] Sorted edges for GSB[11][5]
|
||
|
|
[88%] Sorted edges for GSB[11][6]
|
||
|
|
[89%] Sorted edges for GSB[11][7]
|
||
|
|
[89%] Sorted edges for GSB[11][8]
|
||
|
|
[90%] Sorted edges for GSB[11][9]
|
||
|
|
[91%] Sorted edges for GSB[11][10]
|
||
|
|
[91%] Sorted edges for GSB[11][11]
|
||
|
|
[92%] Sorted edges for GSB[11][12]
|
||
|
|
[92%] Sorted edges for GSB[12][0]
|
||
|
|
[93%] Sorted edges for GSB[12][1]
|
||
|
|
[94%] Sorted edges for GSB[12][2]
|
||
|
|
[94%] Sorted edges for GSB[12][3]
|
||
|
|
[95%] Sorted edges for GSB[12][4]
|
||
|
|
[95%] Sorted edges for GSB[12][5]
|
||
|
|
[96%] Sorted edges for GSB[12][6]
|
||
|
|
[97%] Sorted edges for GSB[12][7]
|
||
|
|
[97%] Sorted edges for GSB[12][8]
|
||
|
|
[98%] Sorted edges for GSB[12][9]
|
||
|
|
[98%] Sorted edges for GSB[12][10]
|
||
|
|
[99%] Sorted edges for GSB[12][11]
|
||
|
|
[100%] Sorted edges for GSB[12][12]
|
||
|
|
Sorted edges for 169 General Switch Blocks (GSBs).
|
||
|
|
# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.05 seconds (max_rss 20.6 MiB, delta_rss +0.8 MiB)
|
||
|
|
# Build a library of physical multiplexers
|
||
|
|
Built a multiplexer library of 14 physical multiplexers.
|
||
|
|
Maximum multiplexer size is 17.
|
||
|
|
# Build a library of physical multiplexers took 0.00 seconds (max_rss 20.6 MiB, delta_rss +0.0 MiB)
|
||
|
|
# Build the annotation about direct connection between tiles
|
||
|
|
Built 275 tile-to-tile direct connections
|
||
|
|
# Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 20.6 MiB, delta_rss +0.0 MiB)
|
||
|
|
Building annotation for mapped blocks on grid locations...Done
|
||
|
|
User specified the operating clock frequency to use VPR results
|
||
|
|
Use VPR critical path delay 1.11037e-18 [ns] with a 20 [%] slack in OpenFPGA.
|
||
|
|
Will apply operating clock frequency 900.599 [MHz] to simulations
|
||
|
|
User specified the number of operating clock cycles to be inferred from signal activities
|
||
|
|
Average net density: 0.42
|
||
|
|
Median net density: 0.00
|
||
|
|
Average net density after weighting: 0.42
|
||
|
|
Will apply 2 operating clock cycles to simulations
|
||
|
|
Link OpenFPGA architecture to VPR architecture took 0.06 seconds (max_rss 20.8 MiB, delta_rss +1.0 MiB)
|
||
|
|
|
||
|
|
Command line to execute: build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA1212_FLAT_HD_SKY_task/arch/fabric_key.xml
|
||
|
|
|
||
|
|
Confirm selected options when call command 'build_fabric':
|
||
|
|
--frame_view: off
|
||
|
|
--compress_routing: on
|
||
|
|
--duplicate_grid_pin: on
|
||
|
|
--load_fabric_key: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA1212_FLAT_HD_SKY_task/arch/fabric_key.xml
|
||
|
|
--write_fabric_key: off
|
||
|
|
--generate_random_fabric_key: off
|
||
|
|
--verbose: off
|
||
|
|
Identify unique General Switch Blocks (GSBs)
|
||
|
|
Detected 9 unique general switch blocks from a total of 169 (compression rate=1777.78%)
|
||
|
|
Identify unique General Switch Blocks (GSBs) took 0.08 seconds (max_rss 20.8 MiB, delta_rss +0.0 MiB)
|
||
|
|
|
||
|
|
Read Fabric Key
|
||
|
|
Read Fabric Key took 0.00 seconds (max_rss 20.9 MiB, delta_rss +0.1 MiB)
|
||
|
|
|
||
|
|
Build fabric module graph
|
||
|
|
# Build constant generator modules
|
||
|
|
# Build constant generator modules took 0.00 seconds (max_rss 20.9 MiB, delta_rss +0.0 MiB)
|
||
|
|
# Build user-defined modules
|
||
|
|
# Build user-defined modules took 0.00 seconds (max_rss 20.9 MiB, delta_rss +0.0 MiB)
|
||
|
|
# Build essential (inverter/buffer/logic gate) modules
|
||
|
|
# Build essential (inverter/buffer/logic gate) modules took 0.00 seconds (max_rss 20.9 MiB, delta_rss +0.0 MiB)
|
||
|
|
# Build local encoder (for multiplexers) modules
|
||
|
|
# Build local encoder (for multiplexers) modules took 0.00 seconds (max_rss 20.9 MiB, delta_rss +0.0 MiB)
|
||
|
|
# Building multiplexer modules
|
||
|
|
# Building multiplexer modules took 0.00 seconds (max_rss 21.2 MiB, delta_rss +0.3 MiB)
|
||
|
|
# Build Look-Up Table (LUT) modules
|
||
|
|
# Build Look-Up Table (LUT) modules took 0.00 seconds (max_rss 21.4 MiB, delta_rss +0.3 MiB)
|
||
|
|
# Build wire modules
|
||
|
|
# Build wire modules took 0.00 seconds (max_rss 21.4 MiB, delta_rss +0.0 MiB)
|
||
|
|
# Build memory modules
|
||
|
|
# Build memory modules took 0.00 seconds (max_rss 21.4 MiB, delta_rss +0.0 MiB)
|
||
|
|
# Build grid modules
|
||
|
|
Building logical tiles...Done
|
||
|
|
Building physical tiles...Done
|
||
|
|
# Build grid modules took 0.00 seconds (max_rss 21.9 MiB, delta_rss +0.5 MiB)
|
||
|
|
# Build unique routing modules...
|
||
|
|
# Build unique routing modules... took 0.01 seconds (max_rss 24.0 MiB, delta_rss +2.1 MiB)
|
||
|
|
# Build FPGA fabric module
|
||
|
|
## Add grid instances to top module
|
||
|
|
## Add grid instances to top module took 0.00 seconds (max_rss 25.3 MiB, delta_rss +1.3 MiB)
|
||
|
|
## Add switch block instances to top module
|
||
|
|
## Add switch block instances to top module took 0.00 seconds (max_rss 26.1 MiB, delta_rss +0.8 MiB)
|
||
|
|
## Add connection block instances to top module
|
||
|
|
## Add connection block instances to top module took 0.00 seconds (max_rss 26.6 MiB, delta_rss +0.5 MiB)
|
||
|
|
## Add connection block instances to top module
|
||
|
|
## Add connection block instances to top module took 0.00 seconds (max_rss 27.1 MiB, delta_rss +0.5 MiB)
|
||
|
|
## Add module nets between grids and GSBs
|
||
|
|
## Add module nets between grids and GSBs took 0.13 seconds (max_rss 42.8 MiB, delta_rss +15.7 MiB)
|
||
|
|
## Add module nets for inter-tile connections
|
||
|
|
## Add module nets for inter-tile connections took 0.00 seconds (max_rss 43.3 MiB, delta_rss +0.5 MiB)
|
||
|
|
## Add module nets for configuration buses
|
||
|
|
## Add module nets for configuration buses took 0.02 seconds (max_rss 44.6 MiB, delta_rss +1.0 MiB)
|
||
|
|
# Build FPGA fabric module took 0.17 seconds (max_rss 44.6 MiB, delta_rss +20.6 MiB)
|
||
|
|
Build fabric module graph took 0.19 seconds (max_rss 44.6 MiB, delta_rss +23.7 MiB)
|
||
|
|
Create I/O location mapping for top module
|
||
|
|
Create I/O location mapping for top module took 0.00 seconds (max_rss 44.6 MiB, delta_rss +0.0 MiB)
|
||
|
|
Create global port info for top module
|
||
|
|
Create global port info for top module took 0.00 seconds (max_rss 44.6 MiB, delta_rss +0.0 MiB)
|
||
|
|
|
||
|
|
Command line to execute: repack
|
||
|
|
|
||
|
|
Confirm selected options when call command 'repack':
|
||
|
|
--verbose: off
|
||
|
|
Build routing resource graph for the physical implementation of logical tile
|
||
|
|
Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 44.6 MiB, delta_rss +0.0 MiB)
|
||
|
|
Repack clustered blocks to physical implementation of logical tile
|
||
|
|
Repack clustered block 'c'...Done
|
||
|
|
Repack clustered block 'out:c'...Done
|
||
|
|
Repack clustered block 'a'...Done
|
||
|
|
Repack clustered block 'b'...Done
|
||
|
|
Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 44.6 MiB, delta_rss +0.0 MiB)
|
||
|
|
Build truth tables for physical LUTs
|
||
|
|
Build truth tables for physical LUTs took 0.00 seconds (max_rss 44.6 MiB, delta_rss +0.0 MiB)
|
||
|
|
|
||
|
|
Command line to execute: build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml
|
||
|
|
|
||
|
|
Confirm selected options when call command 'build_architecture_bitstream':
|
||
|
|
--write_file: fabric_indepenent_bitstream.xml
|
||
|
|
--read_file: off
|
||
|
|
--verbose: off
|
||
|
|
|
||
|
|
Build fabric-independent bitstream for implementation 'top'
|
||
|
|
|
||
|
|
Generating bitstream for Switch blocks...Done
|
||
|
|
Generating bitstream for X-direction Connection blocks ...Done
|
||
|
|
Generating bitstream for Y-direction Connection blocks ...Done
|
||
|
|
|
||
|
|
Build fabric-independent bitstream for implementation 'top'
|
||
|
|
took 0.13 seconds (max_rss 49.7 MiB, delta_rss +5.1 MiB)
|
||
|
|
Warning 116: Directory path is empty and nothing will be created.
|
||
|
|
Write 67960 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml'
|
||
|
|
Write 67960 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.45 seconds (max_rss 49.7 MiB, delta_rss +0.0 MiB)
|
||
|
|
|
||
|
|
Command line to execute: build_fabric_bitstream
|
||
|
|
|
||
|
|
Confirm selected options when call command 'build_fabric_bitstream':
|
||
|
|
--verbose: off
|
||
|
|
|
||
|
|
Build fabric dependent bitstream
|
||
|
|
|
||
|
|
|
||
|
|
Build fabric dependent bitstream
|
||
|
|
took 0.07 seconds (max_rss 53.6 MiB, delta_rss +3.9 MiB)
|
||
|
|
|
||
|
|
Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
|
||
|
|
|
||
|
|
Confirm selected options when call command 'write_fabric_bitstream':
|
||
|
|
--file, -f: fabric_bitstream.bit
|
||
|
|
--format: plain_text
|
||
|
|
--verbose: off
|
||
|
|
Warning 117: Directory path is empty and nothing will be created.
|
||
|
|
Write 67960 fabric bitstream into plain text file 'fabric_bitstream.bit'
|
||
|
|
Write 67960 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.01 seconds (max_rss 53.6 MiB, delta_rss +0.0 MiB)
|
||
|
|
|
||
|
|
Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml
|
||
|
|
|
||
|
|
Confirm selected options when call command 'write_fabric_bitstream':
|
||
|
|
--file, -f: fabric_bitstream.xml
|
||
|
|
--format: xml
|
||
|
|
--verbose: off
|
||
|
|
Warning 118: Directory path is empty and nothing will be created.
|
||
|
|
Write 67960 fabric bitstream into xml file 'fabric_bitstream.xml'
|
||
|
|
Write 67960 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.12 seconds (max_rss 53.6 MiB, delta_rss +0.0 MiB)
|
||
|
|
|
||
|
|
Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose
|
||
|
|
|
||
|
|
Confirm selected options when call command 'write_fabric_verilog':
|
||
|
|
--file, -f: ./SRC
|
||
|
|
--explicit_port_mapping: on
|
||
|
|
--include_timing: on
|
||
|
|
--include_signal_init: on
|
||
|
|
--support_icarus_simulator: on
|
||
|
|
--print_user_defined_template: off
|
||
|
|
--verbose: on
|
||
|
|
Write Verilog netlists for FPGA fabric
|
||
|
|
|
||
|
|
Succeed to create directory './SRC'
|
||
|
|
Succeed to create directory './SRC/sub_module'
|
||
|
|
Succeed to create directory './SRC/lb'
|
||
|
|
Succeed to create directory './SRC/routing'
|
||
|
|
Generating Verilog netlist './SRC/sub_module/inv_buf_passgate.v' for essential gates...Done
|
||
|
|
Writing Verilog netlist for configuration decoders './SRC/sub_module/arch_encoder.v'...Done
|
||
|
|
Writing Verilog netlist for local decoders for multiplexers './SRC/sub_module/local_encoder.v'...Done
|
||
|
|
Writing Verilog netlist for Multiplexers './SRC/sub_module/muxes.v' ...Done
|
||
|
|
Writing Verilog netlist for LUTs './SRC/sub_module/luts.v'...Done
|
||
|
|
Writing Verilog netlist for wires './SRC/sub_module/wires.v'...Done
|
||
|
|
Writing Verilog netlist for memories './SRC/sub_module/memories.v' ...Done
|
||
|
|
|
||
|
|
Writing logical tiles...
|
||
|
|
Writing Verilog netlists for logic tile 'io' ...
|
||
|
|
Writing Verilog netlist './SRC/lb/logical_tile_io_mode_physical__iopad.v' for primitive pb_type 'iopad' ...
|
||
|
|
Writing Verilog codes of logical tile primitive block 'logical_tile_io_mode_physical__iopad'...Done
|
||
|
|
Writing Verilog netlist './SRC/lb/logical_tile_io_mode_io_.v' for pb_type 'io' ...
|
||
|
|
Writing Verilog codes of pb_type 'logical_tile_io_mode_io_'...Done
|
||
|
|
Done
|
||
|
|
|
||
|
|
Writing Verilog netlists for logic tile 'clb' ...
|
||
|
|
Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v' for primitive pb_type 'frac_lut4' ...
|
||
|
|
Writing Verilog codes of logical tile primitive block 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4'...Done
|
||
|
|
Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v' for pb_type 'frac_logic' ...
|
||
|
|
Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic'...Done
|
||
|
|
Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v' for primitive pb_type 'ff' ...
|
||
|
|
Writing Verilog codes of logical tile primitive block 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff'...Done
|
||
|
|
Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v' for pb_type 'fabric' ...
|
||
|
|
Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle_mode_physical__fabric'...Done
|
||
|
|
Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle.v' for pb_type 'fle' ...
|
||
|
|
Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle'...Done
|
||
|
|
Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_clb_.v' for pb_type 'clb' ...
|
||
|
|
Writing Verilog codes of pb_type 'logical_tile_clb_mode_clb_'...Done
|
||
|
|
Done
|
||
|
|
|
||
|
|
Writing logical tiles...Done
|
||
|
|
|
||
|
|
Building physical tiles...
|
||
|
|
Writing Verilog Netlist './SRC/lb/grid_io_top_top.v' for physical tile 'io_top' at top side ...Done
|
||
|
|
Writing Verilog Netlist './SRC/lb/grid_io_right_right.v' for physical tile 'io_right' at right side ...Done
|
||
|
|
Writing Verilog Netlist './SRC/lb/grid_io_bottom_bottom.v' for physical tile 'io_bottom' at bottom side ...Done
|
||
|
|
Writing Verilog Netlist './SRC/lb/grid_io_left_left.v' for physical tile 'io_left' at left side ...Done
|
||
|
|
Writing Verilog Netlist './SRC/lb/grid_clb.v' for physical_tile 'clb'...Done
|
||
|
|
Building physical tiles...Done
|
||
|
|
|
||
|
|
Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done
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Written 71 Verilog modules in total
|
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Write Verilog netlists for FPGA fabric
|
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took 0.44 seconds (max_rss 56.4 MiB, delta_rss +2.8 MiB)
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Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
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Confirm selected options when call command 'write_verilog_testbench':
|
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--file, -f: ./SRC
|
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--fabric_netlist_file_path: off
|
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--reference_benchmark_file_path: top_output_verilog.v
|
||
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--print_top_testbench: on
|
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--fast_configuration: off
|
||
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--print_formal_verification_top_netlist: off
|
||
|
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--print_preconfig_top_testbench: on
|
||
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--print_simulation_ini: ./SimulationDeck/simulation_deck.ini
|
||
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--explicit_port_mapping: on
|
||
|
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--verbose: off
|
||
|
|
Warning 119: Forcely enable to print top-level Verilog netlist in formal verification purpose as print pre-configured top-level Verilog testbench is enabled
|
||
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Write Verilog testbenches for FPGA fabric
|
||
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|
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|
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Warning 120: Directory './SRC' already exists. Will overwrite contents
|
||
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# Write pre-configured FPGA top-level Verilog netlist for design 'top'
|
||
|
|
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.14 seconds (max_rss 56.5 MiB, delta_rss +0.2 MiB)
|
||
|
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# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top'
|
||
|
|
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 56.5 MiB, delta_rss +0.0 MiB)
|
||
|
|
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top'
|
||
|
|
Will use 67961 configuration clock cycles to top testbench
|
||
|
|
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.13 seconds (max_rss 56.6 MiB, delta_rss +0.1 MiB)
|
||
|
|
Succeed to create directory './SimulationDeck'
|
||
|
|
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini'
|
||
|
|
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 56.6 MiB, delta_rss +0.0 MiB)
|
||
|
|
Write Verilog testbenches for FPGA fabric
|
||
|
|
took 0.29 seconds (max_rss 56.6 MiB, delta_rss +0.2 MiB)
|
||
|
|
|
||
|
|
Command line to execute: write_pnr_sdc --file ./SDC
|
||
|
|
|
||
|
|
Confirm selected options when call command 'write_pnr_sdc':
|
||
|
|
--file, -f: ./SDC
|
||
|
|
--flatten_names: off
|
||
|
|
--hierarchical: off
|
||
|
|
--output_hierarchy: off
|
||
|
|
--time_unit: off
|
||
|
|
--constrain_global_port: off
|
||
|
|
--constrain_non_clock_global_port: off
|
||
|
|
--constrain_grid: off
|
||
|
|
--constrain_sb: off
|
||
|
|
--constrain_cb: off
|
||
|
|
--constrain_configurable_memory_outputs: off
|
||
|
|
--constrain_routing_multiplexer_outputs: off
|
||
|
|
--constrain_switch_block_outputs: off
|
||
|
|
--constrain_zero_delay_paths: off
|
||
|
|
--verbose: off
|
||
|
|
Succeed to create directory './SDC'
|
||
|
|
Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc'
|
||
|
|
Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc' took 0.00 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB)
|
||
|
|
Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc'
|
||
|
|
Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc' took 0.01 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB)
|
||
|
|
Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc'
|
||
|
|
Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc' took 0.05 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB)
|
||
|
|
Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc'
|
||
|
|
Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc' took 0.00 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB)
|
||
|
|
Write SDC for constrain Switch Block timing for P&R flow
|
||
|
|
Write SDC for constrain Switch Block timing for P&R flow took 0.05 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB)
|
||
|
|
Write SDC for constrain Connection Block timing for P&R flow
|
||
|
|
Write SDC for constrain Connection Block timing for P&R flow took 0.02 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB)
|
||
|
|
Write SDC for constraining grid timing for P&R flow
|
||
|
|
Write SDC for constraining grid timing for P&R flow took 0.02 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB)
|
||
|
|
|
||
|
|
Command line to execute: write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
|
||
|
|
|
||
|
|
Confirm selected options when call command 'write_sdc_disable_timing_configure_ports':
|
||
|
|
--file, -f: ./SDC/disable_configure_ports.sdc
|
||
|
|
--flatten_names: off
|
||
|
|
--verbose: off
|
||
|
|
Warning 121: Directory './SDC' already exists. Will overwrite contents
|
||
|
|
Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc'
|
||
|
|
Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc' took 0.12 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB)
|
||
|
|
|
||
|
|
Command line to execute: write_analysis_sdc --file ./SDC_analysis
|
||
|
|
|
||
|
|
Confirm selected options when call command 'write_analysis_sdc':
|
||
|
|
--file, -f: ./SDC_analysis
|
||
|
|
--verbose: off
|
||
|
|
--flatten_names: off
|
||
|
|
--time_unit: off
|
||
|
|
Succeed to create directory './SDC_analysis'
|
||
|
|
Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc'
|
||
|
|
Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc' took 0.76 seconds (max_rss 56.8 MiB, delta_rss +0.0 MiB)
|
||
|
|
|
||
|
|
Command line to execute: exit
|
||
|
|
|
||
|
|
Confirm selected options when call command 'exit':
|
||
|
|
|
||
|
|
Finish execution with 0 errors
|
||
|
|
|
||
|
|
The entire OpenFPGA flow took 3.11 seconds
|
||
|
|
|
||
|
|
Thank you for using OpenFPGA!
|