mirror of https://github.com/lnis-uofu/SOFA.git
47 lines
1.4 KiB
Coq
47 lines
1.4 KiB
Coq
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//-----------------------------------------------------
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// This file includes behavorial modeling
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// for digital I/O cells
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// These cells may not be directly used for physical design
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// Synthesis tools may be needed
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//-----------------------------------------------------
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`timescale 1ns/1ps
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//-----------------------------------------------------
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// Function : A minimum input pad
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//-----------------------------------------------------
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module GPIN (
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inout A, // External PAD signal
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output Y // Data input
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);
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assign Y = A;
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endmodule
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//-----------------------------------------------------
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// Function : A minimum output pad
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//-----------------------------------------------------
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module GPOUT (
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inout Y, // External PAD signal
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input A // Data output
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);
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assign Y = A;
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endmodule
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//-----------------------------------------------------
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// Function : A minimum embedded I/O
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// just an overlay to interface other components
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//-----------------------------------------------------
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module EMBEDDED_IO (
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input SOC_IN, // Input to drive the inpad signal
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output SOC_OUT, // Output the outpad signal
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output SOC_DIR, // Output the directionality
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output FPGA_IN, // Input data to FPGA
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input FPGA_OUT, // Output data from FPGA
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input FPGA_DIR // direction control
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);
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assign FPGA_IN = SOC_IN;
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assign SOC_OUT = FPGA_OUT;
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assign SOC_DIR = FPGA_DIR;
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endmodule
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