mirror of https://github.com/lnis-uofu/SOFA.git
38 lines
1.4 KiB
Plaintext
38 lines
1.4 KiB
Plaintext
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# This script is designed to generate fabric Verilog netlists
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# with a fixed device layout
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# It will only output netlists to be used by backend tools,
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# i.e., Synopsys ICC2, including
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# - Verilog netlists
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# - fabric hierarchy description for ICC2's hierarchical flow
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# - Timing/Design constraints
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#
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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# Read OpenFPGA simulation settings
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read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
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# Build the module graph
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# - Enabled compression on routing architecture modules
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# - Enable pin duplication on grid modules
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build_fabric --compress_routing #--verbose
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# Write the SDC files for PnR backend
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# - Turn on every options here
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write_pnr_sdc --file ${OPENFPGA_SDC_OUTPUT_DIR}
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# Write SDC to disable timing for configure ports
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write_sdc_disable_timing_configure_ports --file ${OPENFPGA_SDC_OUTPUT_DIR}/disable_configure_ports.sdc
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# Finish and exit OpenFPGA
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exit
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# Note :
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# To run verification at the end of the flow maintain source in ./SRC directory
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