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# ####################################################################
# A template script to report timing for A CLB from post-PnR results
# using Synopsys PrimeTime
# ####################################################################
# #################################
# Define environment variables
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#
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# set DEVICE_NAME "SOFA_HD"
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# set DEVICE_NAME "QLSOFA_HD"
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set DEVICE_NAME " S O F A _ C H D "
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set SKYWATER_PDK_HOME " . . / . . / P D K / s k y w a t e r - p d k " ;
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if { " S O F A _ H D " == $ { DEVICE_NAME } } {
set FPGA_NETLIST_HOME " . . / . . / F P G A 1 2 1 2 _ S O F A _ H D _ P N R / f p g a _ t o p " ;
set SDC_HOME " . . / . . / S D C / k 4 _ N 8 _ c a r a v e l _ i o _ F P G A _ 1 2 x 1 2 _ f d h d _ c c " ;
} elseif { " Q L S O F A _ H D " == $ { DEVICE_NAME } } {
set FPGA_NETLIST_HOME " . . / . . / F P G A 1 2 1 2 _ Q L S O F A _ H D _ P N R / f p g a _ t o p " ;
set SDC_HOME " . . / . . / S D C / k 4 _ N 8 _ r e s e t _ s o f t a d d e r _ c a r a v e l _ i o _ F P G A _ 1 2 x 1 2 _ f d h d _ c c " ;
} elseif { " S O F A _ C H D " == $ { DEVICE_NAME } } {
set FPGA_NETLIST_HOME " . . / . . / F P G A 1 2 1 2 _ S O F A _ C H D _ P N R / f p g a _ t o p " ;
set SDC_HOME " . . / . . / S D C / k 4 _ N 8 _ r e s e t _ s o f t a d d e r _ c a r a v e l _ i o _ F P G A _ 1 2 x 1 2 _ c u s t o m h d _ c c " ;
}
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set TIMING_REPORT_HOME " . . / T I M I N G _ R E P O R T S / " ;
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# Enable preprocessing in Verilog parser
set_app_var svr_enable_vpp true
# Enable reporting ALL the timing paths even those are NOT constrained
set_app_var timing_report_unconstrained_paths tr
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if { " S O F A _ C H D " == $ { DEVICE_NAME } } {
set search_path " . * $ { S K Y W A T E R _ P D K _ H O M E } / v e n d o r / s y n o p s y s / P l a c e R o u t e / s k y 1 3 0 _ f d _ s c _ h d / d b _ n l d m $ { S K Y W A T E R _ P D K _ H O M E } / . . / . . / L I B "
set link_path " * s k y 1 3 0 _ f d _ s c _ h d _ _ t t _ 0 2 5 C _ 1 v 8 0 . d b s k y 1 3 0 _ u u o p e n f p g a _ c c _ h d _ t t _ 0 2 5 C _ 1 v 8 0 . l i b "
} else {
set search_path " . * $ { S K Y W A T E R _ P D K _ H O M E } / v e n d o r / s y n o p s y s / P l a c e R o u t e / s k y 1 3 0 _ f d _ s c _ h d / d b _ n l d m "
set link_path " * s k y 1 3 0 _ f d _ s c _ h d _ _ t t _ 0 2 5 C _ 1 v 8 0 . d b "
}
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set FPGA_NETLIST_FILES " f p g a _ t o p _ i c v _ i n _ d e s i g n . p t . v "
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# #################################
# Ensure a clean start
remove_design - all
remove_lib - all
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# #################################
# Read timing libraries
read_db " $ { S K Y W A T E R _ P D K _ H O M E } / v e n d o r / s y n o p s y s / P l a c e R o u t e / s k y 1 3 0 _ f d _ s c _ h d / d b _ n l d m / s k y 1 3 0 _ f d _ s c _ h d _ _ t t _ 0 2 5 C _ 1 v 8 0 . d b "
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if { " S O F A _ C H D " == $ { DEVICE_NAME } } {
read_lib " $ { S K Y W A T E R _ P D K _ H O M E } / . . / . . / L I B / s k y 1 3 0 _ u u o p e n f p g a _ c c _ h d _ _ t t _ 0 2 5 C _ 1 v 8 0 . l i b "
}
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# #################################
# Read post-PnR netlists
read_verilog $ { FPGA_NETLIST_HOME } / $ { FPGA_NETLIST_FILES }
# Top-level module name
set DESIGN_NAME " g r i d _ c l b " ;
link_design $ { DESIGN_NAME }
# ########################################
# Setup constraints to break combinational loops
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if { $ { DEVICE_NAME } == " S O F A _ H D " } {
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set_disable_timing * / * / * / mem* / sky* _fd_sc_hd__dfxtp_* _* _/ Q
} else {
# QLSOFA and SOFA CHD use a LUT with carry logic, the memory is deeper in hierarchy
# Also QLSOFA and SOFA CHD use a different FF cell as configuration memory
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set_disable_timing * / * / * / * / * mem* / sky* _fd_sc_hd__dfrtp_* _* _/ Q
set_disable_timing * / * / * / * / * / * mem* / sky* _fd_sc_hd__dfrtp_* _* _/ Q
# Disable cin/cout paths
set_disable_timing logical_tile_clb_mode_clb__* / logical_tile_clb_mode_default__fle_* / logical_tile_clb_mode_default__fle_mode_physical__fabric_0/ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_* / frac_logic_cin
set_disable_timing logical_tile_clb_mode_clb__* / logical_tile_clb_mode_default__fle_* / logical_tile_clb_mode_default__fle_mode_physical__fabric_0/ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_* / frac_logic_cout
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}
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#
# #########################################
# # Setup constraints for clocks
# #########################################
# # Setup constraints for paths
# #################################
# Read post-PnR parasitics
read_parasitics $ { FPGA_NETLIST_HOME } / fpga_top_icv_in_design.nominal_25.spef
# #################################
# Report timing of Connect block
# LUT4 output timing
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set LUT_INPUT_PORT_NAME " l o g i c a l _ t i l e _ c l b _ m o d e _ c l b _ _ * / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ * / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ m o d e _ p h y s i c a l _ _ f a b r i c _ 0 / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ m o d e _ p h y s i c a l _ _ f a b r i c _ m o d e _ d e f a u l t _ _ f r a c _ l o g i c _ * / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ m o d e _ p h y s i c a l _ _ f a b r i c _ m o d e _ d e f a u l t _ _ f r a c _ l o g i c _ m o d e _ d e f a u l t _ _ f r a c _ l u t 4 _ * / f r a c _ l u t 4 _ * _ / i n "
set LUT4_OUTPUT_PORT_NAME " l o g i c a l _ t i l e _ c l b _ m o d e _ c l b _ _ * / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ * / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ m o d e _ p h y s i c a l _ _ f a b r i c _ * / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ m o d e _ p h y s i c a l _ _ f a b r i c _ m o d e _ d e f a u l t _ _ f r a c _ l o g i c _ * / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ m o d e _ p h y s i c a l _ _ f a b r i c _ m o d e _ d e f a u l t _ _ f r a c _ l o g i c _ m o d e _ d e f a u l t _ _ f r a c _ l u t 4 _ * / f r a c _ l u t 4 _ * _ / l u t 4 _ o u t "
# Walk through all the input pin and output pin paths
for { set ipin 0 } { $ipin < 4 } { incr ipin} {
if { 0 == $ipin } {
report_timing - from $ { LUT_INPUT_PORT_NAME } [ $ipin ] - to $ { LUT4_OUTPUT_PORT_NAME } > $ { TIMING_REPORT_HOME } / $ { DEVICE_NAME } _$ { DESIGN_NAME } _lut4_timing.rpt
} else {
report_timing - from $ { LUT_INPUT_PORT_NAME } [ $ipin ] - to $ { LUT4_OUTPUT_PORT_NAME } >> $ { TIMING_REPORT_HOME } / $ { DEVICE_NAME } _$ { DESIGN_NAME } _lut4_timing.rpt
}
}
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# LUT3 output timing
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set LUT3_OUTPUT_PORT_NAME " l o g i c a l _ t i l e _ c l b _ m o d e _ c l b _ _ * / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ * / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ m o d e _ p h y s i c a l _ _ f a b r i c _ * / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ m o d e _ p h y s i c a l _ _ f a b r i c _ m o d e _ d e f a u l t _ _ f r a c _ l o g i c _ * / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ m o d e _ p h y s i c a l _ _ f a b r i c _ m o d e _ d e f a u l t _ _ f r a c _ l o g i c _ m o d e _ d e f a u l t _ _ f r a c _ l u t 4 _ * / f r a c _ l u t 4 _ * _ / l u t 3 _ o u t "
# Walk through all the input pin and output pin paths
for { set ipin 0 } { $ipin < 3 } { incr ipin} {
for { set opin 0 } { $opin < 2 } { incr opin} {
if { 0 == $ipin && 0 == $opin } {
report_timing - from $ { LUT_INPUT_PORT_NAME } [ $ipin ] - to $ { LUT3_OUTPUT_PORT_NAME } [ $opin ] > $ { TIMING_REPORT_HOME } / $ { DEVICE_NAME } _$ { DESIGN_NAME } _lut3_timing.rpt
} else {
report_timing - from $ { LUT_INPUT_PORT_NAME } [ $ipin ] - to $ { LUT3_OUTPUT_PORT_NAME } [ $opin ] >> $ { TIMING_REPORT_HOME } / $ { DEVICE_NAME } _$ { DESIGN_NAME } _lut3_timing.rpt
}
}
}
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# Output selector timing
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set FRAC_LOGIC_OUTPUT_PORT_NAME " l o g i c a l _ t i l e _ c l b _ m o d e _ c l b _ _ * / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ * / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ m o d e _ p h y s i c a l _ _ f a b r i c _ 0 / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ m o d e _ p h y s i c a l _ _ f a b r i c _ m o d e _ d e f a u l t _ _ f r a c _ l o g i c _ 0 / f r a c _ l o g i c _ o u t [ 0 ] "
set FF_PATH " l o g i c a l _ t i l e _ c l b _ m o d e _ c l b _ _ * / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ * / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ m o d e _ p h y s i c a l _ _ f a b r i c _ 0 / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ m o d e _ p h y s i c a l _ _ f a b r i c _ m o d e _ d e f a u l t _ _ f f "
set FLE_OUTPUT_PORT_NAME " l o g i c a l _ t i l e _ c l b _ m o d e _ c l b _ _ * / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ * / l o g i c a l _ t i l e _ c l b _ m o d e _ d e f a u l t _ _ f l e _ m o d e _ p h y s i c a l _ _ f a b r i c _ 0 / f a b r i c _ o u t "
report_timing - from $ { FF_PATH } _0/ ff_Q[ 0 ] - to $ { FLE_OUTPUT_PORT_NAME } [ 0 ] > $ { TIMING_REPORT_HOME } / $ { DEVICE_NAME } _$ { DESIGN_NAME } _output_mux_timing.rpt
report_timing - from $ { FRAC_LOGIC_OUTPUT_PORT_NAME } [ 0 ] - to $ { FLE_OUTPUT_PORT_NAME } [ 0 ] >> $ { TIMING_REPORT_HOME } / $ { DEVICE_NAME } _$ { DESIGN_NAME } _output_mux_timing.rpt
report_timing - from $ { FF_PATH } _1/ ff_Q[ 0 ] - to $ { FLE_OUTPUT_PORT_NAME } [ 1 ] >> $ { TIMING_REPORT_HOME } / $ { DEVICE_NAME } _$ { DESIGN_NAME } _output_mux_timing.rpt
report_timing - from $ { FRAC_LOGIC_OUTPUT_PORT_NAME } [ 1 ] - to $ { FLE_OUTPUT_PORT_NAME } [ 1 ] >> $ { TIMING_REPORT_HOME } / $ { DEVICE_NAME } _$ { DESIGN_NAME } _output_mux_timing.rpt
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# LUT output to FF input timing
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report_timing - from $ { LUT4_OUTPUT_PORT_NAME } - to $ { FF_PATH } _0/ ff_D[ 0 ] > $ { TIMING_REPORT_HOME } / $ { DEVICE_NAME } _$ { DESIGN_NAME } _lut2ff_timing.rpt
report_timing - from $ { LUT3_OUTPUT_PORT_NAME } - to $ { FF_PATH } _0/ ff_D[ 0 ] >> $ { TIMING_REPORT_HOME } / $ { DEVICE_NAME } _$ { DESIGN_NAME } _lut2ff_timing.rpt
report_timing - from $ { LUT3_OUTPUT_PORT_NAME } - to $ { FF_PATH } _1/ ff_D[ 0 ] >> $ { TIMING_REPORT_HOME } / $ { DEVICE_NAME } _$ { DESIGN_NAME } _lut2ff_timing.rpt
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# TODO: Carry logic timing
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# #################################
# Finish and quit
# Comment it out if you want to debug
exit
