2020-11-30 19:51:35 -06:00
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#!/bin/bash
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set -e
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###############################################
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# OpenFPGA Shell with VPR8
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##############################################
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2020-11-30 22:25:02 -06:00
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##############################################
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# Initialize the repository
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# - Generate final version of architecture files
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2020-12-06 22:29:06 -06:00
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# - Run FPGA tasks to validate netlist generations
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2020-11-30 21:06:03 -06:00
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python3 SCRIPT/repo_setup.py --openfpga_root_path ./OpenFPGA
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2020-11-30 22:25:02 -06:00
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2020-12-06 22:29:06 -06:00
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# Post processing netlist to use custom cells
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2020-12-05 22:17:59 -06:00
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python3 HDL/common/custom_cell_mux_primitive_generator.py --template_netlist HDL/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/SRC/sub_module/mux_primitives.v --output_verilog HDL/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/SRC/sub_module/mux_primitives_hd.v
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2020-12-01 12:32:27 -06:00
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##############################################
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# Generate wrapper HDL codes to bridge Caravel I/Os and FPGA I/Os
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python3 HDL/common/wrapper_lines_generator.py --template_netlist HDL/common/caravel_fpga_wrapper_hd_template.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.0.json --output_verilog HDL/common/caravel_fpga_wrapper_hd_v1.0.v
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python3 HDL/common/wrapper_lines_generator.py --template_netlist HDL/common/caravel_fpga_wrapper_hd_template.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.1.json --output_verilog HDL/common/caravel_fpga_wrapper_hd_v1.1.v
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2020-12-01 12:32:27 -06:00
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##############################################
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# Generate wrapper HDL codes to bridge Caravel I/Os and FPGA I/Os
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python3 HDL/common/wrapper_lines_generator.py --template_netlist HDL/common/caravel_fpga_wrapper_hd_template.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.0.json --output_verilog HDL/common/caravel_fpga_wrapper_hd_v1.0.v
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python3 HDL/common/wrapper_lines_generator.py --template_netlist HDL/common/caravel_fpga_wrapper_hd_template.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.1.json --output_verilog HDL/common/caravel_fpga_wrapper_hd_v1.1.v
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2020-11-30 22:25:02 -06:00
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##############################################
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# Generate post-PnR testbenches
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2020-11-30 23:38:24 -06:00
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python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.0.json
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python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.1.json
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2020-12-01 21:55:10 -06:00
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python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.1.json
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