mirror of https://github.com/lnis-uofu/SOFA.git
57 lines
1.6 KiB
ReStructuredText
57 lines
1.6 KiB
ReStructuredText
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.. _clb_arch:
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Configurable Logic Block
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------------------------
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.. _clb_arch_generality:
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Generality
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~~~~~~~~~~
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Each Logic Block (CLB) consists of 8 Logic Elements (LEs) as shown in :numref:`fig_clb_arch`.
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All the pins of the LEs are directly wired to CLB pins without a local routing architecture.
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Feedback connections between LEs are implemented by the global routing architecture outside the CLBs.
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.. _fig_clb_arch:
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.. figure:: ./figures/clb_arch.png
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:scale: 20%
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:alt: Configurable Logic Block schematic
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Configurable logic block schematic
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.. _clb_arch_le:
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Multi-mode Logic Element
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~~~~~~~~~~~~~~~~~~~~~~~~
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As shown in :numref:`fig_fle_arch`, each Logic Element (LE) consists of
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- a fracturable 4-input Look-Up Table (LUT)
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- two D-type Flip-Flops (FF)
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.. _fig_fle_arch:
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.. figure:: ./figures/fle_arch.png
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:scale: 30%
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:alt: Logic element schematic
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Detailed schematic of a logic element
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The LE can operate in different modes to map logic function efficiently
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- 4-input LUT and single FF
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- Dual 3-input LUTs and 2 FFs
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- 2-bit shift registers
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.. _clb_arch_scan_chain:
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Scan Chain
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~~~~~~~~~~
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There is a built-in scan-chain in the CLB where all the `sc_in` and `sc_out` ports of LEs are connected in a chain, as illustrated in :numref:`fig_clb_arch`.
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When `Test_en` signal is active, users can readback the contents of all the D-type flip-flops of the LEs thanks to the scan-chain.
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When `Test_en` signal is disabled, D-type flip-flops of the LEs operate in regular mode to propagate datapath signal from LUT outputs.
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.. note:: The scan-chain of CLBs are connected in a chain at the top-level. See details in :ref:`fpga_arch_scan_chain`.
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