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SOFA/BENCHMARK/rs_decoder_1/rs_decoder_1_yosys.blif

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add testcases for ap3 arch evaluation
2020-12-16 09:05:53 -06:00
# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
.model rs_decoder_1
.inputs x(0) x(1) x(2) x(3) x(4) enable k(0) k(1) k(2) k(3) k(4) clk clrn
.outputs error(0) error(1) error(2) error(3) error(4) with_error valid
.names $false
.names $true
1
.names $undef
.subckt logic_1 a=$auto$hilomap.cc:39:hilomap_worker$25858
.subckt logic_0 a=x0.shift
.subckt in_buff A=clk Q=x0.clk
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
.subckt in_buff A=clrn Q=x0.clrn
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
.subckt in_buff A=enable Q=$iopadmap$enable
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
.subckt out_buff A=x2.error(0) Q=error(0)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
.subckt out_buff A=x2.error(1) Q=error(1)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
.subckt out_buff A=x2.error(2) Q=error(2)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
.subckt out_buff A=x2.error(3) Q=error(3)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
.subckt out_buff A=x2.error(4) Q=error(4)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
.subckt in_buff A=k(0) Q=$iopadmap$k(0)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
.subckt in_buff A=k(1) Q=$iopadmap$k(1)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
.subckt in_buff A=k(2) Q=$iopadmap$k(2)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
.subckt in_buff A=k(3) Q=$iopadmap$k(3)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
.subckt in_buff A=k(4) Q=$iopadmap$k(4)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
.subckt out_buff A=$iopadmap$valid Q=valid
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
.subckt out_buff A=temp Q=with_error
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
.subckt in_buff A=x(0) Q=$iopadmap$x(0)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
.subckt in_buff A=x(1) Q=$iopadmap$x(1)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
.subckt in_buff A=x(2) Q=$iopadmap$x(2)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
.subckt in_buff A=x(3) Q=$iopadmap$x(3)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
.subckt in_buff A=x(4) Q=$iopadmap$x(4)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
.subckt ff CQZ=x1.enable D=syn_shift_ff_CQZ_D QCK=x0.clk QEN=berl_enable_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=with_error_LUT4_I3_1_O I1=berl_enable_ff_CQZ_QEN_LUT4_O_I1 I2=enable_LUT4_I0_1_O I3=syn_enable_ff_CQZ_D O=berl_enable_ff_CQZ_QEN
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
.param INIT 0000000011110100
.subckt LUT4 I0=x2.load I1=x2.search I2=x2.shorten I3=x0.clrn O=chien_load_LUT4_I0_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000111011111111
.subckt LUT4 I0=x2.search I1=x2.load I2=x2.shorten I3=x0.clrn O=chien_load_LUT4_I1_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010011111111
.subckt ff CQZ=x2.load D=chien_load_ff_CQZ_D QCK=x0.clk QEN=chien_load_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=with_error_LUT4_I3_1_O O=chien_load_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I3_O I2=enable_LUT4_I2_I3 I3=chien_load_ff_CQZ_QEN_LUT4_O_I3 O=chien_load_ff_CQZ_QEN
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)"
.param INIT 00010000
.subckt LUT4 I0=enable_LUT4_I2_I3 I1=x2.search I2=chien_load_ff_CQZ_QEN_LUT4_O_I3 I3=enable_LUT4_I2_I1_LUT4_O_I3 O=chien_load_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000110100000000
.subckt LUT4 I0=x1.phase0 I1=count(3) I2=chien_load_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I3=enable_LUT4_I2_I1_LUT4_O_I2 O=chien_load_ff_CQZ_QEN_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0111111100000000
.subckt LUT4 I0=x0.shift I1=count(1) I2=count(0) I3=count(2) O=chien_load_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 01000000
.subckt ff CQZ=x2.search D=chien_search_ff_CQZ_D QCK=x0.clk QEN=chien_search_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x1.phase12 I1=x2.load I2=chien_search_ff_CQZ_D_LUT4_O_I2 I3=x0.clrn O=chien_search_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100011111111
.subckt LUT4 I0=length2(2) I1=length2(1) I2=chien_search_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=x2.search O=chien_search_ff_CQZ_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1110111100000000
.subckt LUT4 I0=x0.shift I1=length2(0) I2=length2(4) I3=length2(3) O=chien_search_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)"
.param INIT 00010000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I3_O I3=enable_LUT4_I2_I1_LUT4_O_I2 O=chien_search_ff_CQZ_QEN
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt ff CQZ=count(3) D=count_ff_CQZ_D(3) QCK=x0.clk QEN=count_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=count(2) D=count_ff_CQZ_D(2) QCK=x0.clk QEN=count_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=count(1) D=count_ff_CQZ_D(1) QCK=x0.clk QEN=count_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=count(0) D=count_ff_CQZ_D(0) QCK=x0.clk QEN=count_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=count_ff_CQZ_D_LUT4_O_I2 I3=chien_load_ff_CQZ_D O=count_ff_CQZ_D(3)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0111
.subckt LUT4 I0=count(0) I1=count(1) I2=count(2) I3=chien_load_ff_CQZ_D O=count_ff_CQZ_D(2)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0111100011111111
.subckt LUT4 I0=x0.shift I1=chien_load_ff_CQZ_D I2=count(1) I3=count(0) O=count_ff_CQZ_D(1)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=count(0) I3=chien_load_ff_CQZ_D O=count_ff_CQZ_D(0)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0111
.subckt LUT4 I0=count(0) I1=count(2) I2=count(1) I3=count(3) O=count_ff_CQZ_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
.param INIT 1000000001111111
.subckt LUT4 I0=$iopadmap$enable I1=enable_LUT4_I0_I1 I2=x0.clrn I3=enable_LUT4_I2_I1 O=shorten_ff_CQZ_QEN
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0100111100000000
.subckt LUT4 I0=$iopadmap$enable I1=syn_shift I2=x0.enable I3=x0.clrn O=enable_LUT4_I0_1_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111001011111111
.subckt LUT4 I0=x1.phase12 I1=x2.load I2=x1.enable I3=enable_LUT4_I0_1_O O=enable_LUT4_I2_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
.param INIT 0000000000000111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=with_error_LUT4_I3_1_O I3=enable_LUT4_I0_1_O O=enable_LUT4_I2_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x0.shift I1=enable_LUT4_I0_I1_LUT4_O_I1 I2=x2.shorten I3=length2(4) O=enable_LUT4_I0_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 01000000
.subckt LUT4 I0=length0(4) I1=enable_LUT4_I0_I1_LUT4_O_I1 I2=length2(4) I3=with_error_LUT4_I3_1_O O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101010111000011
.subckt LUT4 I0=x0.shift I1=x0.clrn I2=$iopadmap$k(4) I3=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(4)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01010011
.subckt LUT4 I0=x0.shift I1=x0.clrn I2=$iopadmap$k(3) I3=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_I3 O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(3)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01010011
.subckt LUT4 I0=x0.shift I1=x0.clrn I2=$iopadmap$k(2) I3=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_1_I3 O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(2)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01010011
.subckt LUT4 I0=x0.shift I1=with_error_LUT4_I3_1_O I2=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_1_I3_LUT4_O_I2 I3=length0(2) O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_1_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01010011
.subckt LUT4 I0=x0.shift I1=length2(2) I2=length2(0) I3=length2(1) O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_1_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 11100001
.subckt LUT4 I0=x0.shift I1=x0.clrn I2=$iopadmap$k(1) I3=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_2_I3 O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(1)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01010011
.subckt LUT4 I0=length0(1) I1=length2(1) I2=length2(0) I3=with_error_LUT4_I3_1_O O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_2_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101010100111100
.subckt LUT4 I0=x0.shift I1=x0.clrn I2=$iopadmap$k(0) I3=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_3_I3 O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(0)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01010011
.subckt LUT4 I0=x0.shift I1=with_error_LUT4_I3_1_O I2=length2(0) I3=length0(0) O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_3_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01011100
.subckt LUT4 I0=x0.shift I1=with_error_LUT4_I3_1_O I2=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_I3_LUT4_O_I2 I3=length0(3) O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01010011
.subckt LUT4 I0=length2(1) I1=length2(2) I2=length2(0) I3=length2(3) O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111111000000001
.subckt LUT4 I0=length2(1) I1=length2(2) I2=length2(3) I3=length2(0) O=enable_LUT4_I0_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)"
.param INIT 0000000000000001
.subckt LUT4 I0=x0.shift I1=enable_LUT4_I2_I1 I2=$iopadmap$enable I3=enable_LUT4_I2_I3 O=enable_LUT4_I2_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 11010000
.subckt LUT4 I0=enable_LUT4_I2_I3 I1=x2.search I2=enable_LUT4_I2_I1_LUT4_O_I2 I3=enable_LUT4_I2_I1_LUT4_O_I3 O=enable_LUT4_I2_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
.param INIT 0000011100000000
.subckt LUT4 I0=x1.phase12 I1=x2.load I2=with_error_LUT4_I3_O_LUT4_I1_I2 I3=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I3_O O=enable_LUT4_I2_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0111111100000000
.subckt LUT4 I0=x0.enable I1=syn_shift I2=x0.clrn I3=$iopadmap$enable O=enable_LUT4_I3_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*I2*I3)"
.param INIT 0001000000000000
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1 I2=error_LUT4_O_I2 I3=error_LUT4_O_I3 O=x2.error(4)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01100000
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1 I2=error_LUT4_O_1_I2 I3=error_LUT4_O_1_I3 O=x2.error(3)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010000
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_2_I1 I2=error_LUT4_O_2_I2 I3=error_LUT4_O_4_I3 O=error_LUT4_O_1_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10110000
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I3_LUT4_O_I2 I2=error_LUT4_O_I3_LUT4_O_I0 I3=error_LUT4_O_I3_LUT4_O_I1 O=error_LUT4_O_1_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=error_LUT4_O_4_I3 I1=error_LUT4_O_2_I1 I2=error_LUT4_O_2_I2 I3=error_LUT4_O_I1 O=x2.error(2)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0100101100000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_3_I3_LUT4_O_I1 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O O=error_LUT4_O_2_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_O I1=error_LUT4_O_2_I2_LUT4_O_I1 I2=error_LUT4_O_2_I2_LUT4_O_I2 I3=error_LUT4_O_3_I3_LUT4_O_I3 O=error_LUT4_O_2_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0111100001110111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_2_I2_LUT4_O_I1 I3=error_LUT4_O_2_I2_LUT4_O_I2 O=error_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2 I3=error_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3 O=error_LUT4_O_2_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=x2.o4(2) I1=x2.o5(2) I2=x2.o6(2) I3=x2.o7(2) O=error_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x2.o0(2) I1=x2.o1(2) I2=x2.o8(2) I3=x2.o9(2) O=error_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x2.o2(2) I1=x2.o3(2) I2=x2.o10(2) I3=x2.o11(2) O=error_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_3_I3_LUT4_O_I1 I3=error_LUT4_O_2_I2_LUT4_O_I2 O=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_2_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1110111100000000
.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I0 I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I1 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
.param INIT 0000000011101111
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I0 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I0_LUT4_I2_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001110
.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I0_LUT4_I2_O I1=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I0_LUT4_I2_O_LUT4_I0_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101110111011
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)"
.param INIT 00010000
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001101
.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I0 I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I2=x2.load I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000111000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I0 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 11100000
.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
.param INIT 00000111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*~I1*I2*I3)"
.param INIT 0001
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
.param INIT 0000000001001111
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
.param INIT 00011111
.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111000011101110
.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I1=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)"
.param INIT 0000000100000000
.subckt LUT4 I0=x2.load I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1110111100000000
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=alpha(2) I3=x2.load O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001101
.subckt LUT4 I0=s9(2) I1=x1.phase0 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 01000000
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1110111100000000
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000111101110111
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
.param INIT 00000111
.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*I2*I3)"
.param INIT 0001000000000000
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 10000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*~I1*I2*I3)"
.param INIT 0001
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1 I3=error_LUT4_O_3_I3 O=x2.error(1)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_O I1=error_LUT4_O_3_I3_LUT4_O_I1 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=error_LUT4_O_3_I3_LUT4_O_I3 O=error_LUT4_O_3_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0111100001110111
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2 I3=error_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3 O=error_LUT4_O_3_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=x2.o0(1) I1=x2.o1(1) I2=x2.o9(1) I3=x2.o10(1) O=error_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x2.o5(1) I1=x2.o6(1) I2=x2.o7(1) I3=x2.o8(1) O=error_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt LUT4 I0=x2.o2(1) I1=x2.o3(1) I2=x2.o4(1) I3=x2.o11(1) O=error_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1 I2=error_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3 O=error_LUT4_O_3_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=x2.o4(0) I1=x2.o5(0) I2=x2.o6(0) I3=x2.o9(0) O=error_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x2.o0(0) I1=x2.o1(0) I2=x2.o7(0) I3=x2.o8(0) O=error_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x2.o2(0) I1=x2.o3(0) I2=x2.o10(0) I3=x2.o11(0) O=error_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1 I3=error_LUT4_O_4_I3 O=x2.error(0)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I3 O=error_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100100000000
.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=x2.l1(2) I2=x2.l3(2) I3=x2.l11(2) O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x0.shift I1=x2.l9(2) I2=x2.l7(2) I3=x2.l5(2) O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=x0.shift I1=x2.l10(2) I2=x2.l2(2) I3=x2.l0(2) O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=D0(2) I1=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=x2.search O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001110101010
.subckt LUT4 I0=x0.shift I1=x2.l8(2) I2=x2.l6(2) I3=x2.l4(2) O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=D0(0) I1=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x2.search O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001110101010
.subckt LUT4 I0=x0.shift I1=x2.l8(0) I2=x2.l6(0) I3=x2.l4(0) O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=x0.shift I1=x2.l10(0) I2=x2.l2(0) I3=x2.l0(0) O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=x2.l1(0) I2=x2.l3(0) I3=x2.l11(0) O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x0.shift I1=x2.l9(0) I2=x2.l7(0) I3=x2.l5(0) O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=error_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100100000000
.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=x2.l1(3) I2=x2.l3(3) I3=x2.l11(3) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x0.shift I1=x2.l9(3) I2=x2.l7(3) I3=x2.l5(3) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=x0.shift I1=x2.l10(3) I2=x2.l2(3) I3=x2.l0(3) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=D0(3) I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=x2.search O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001110101010
.subckt LUT4 I0=x0.shift I1=x2.l8(3) I2=x2.l6(3) I3=x2.l4(3) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
.param INIT 0001010001000001
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=D0(4) I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=x2.search O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001110101010
.subckt LUT4 I0=x0.shift I1=x2.l8(4) I2=x2.l6(4) I3=x2.l4(4) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=x0.shift I1=x2.l10(4) I2=x2.l2(4) I3=x2.l0(4) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=x2.l1(4) I2=x2.l3(4) I3=x2.l11(4) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x0.shift I1=x2.l9(4) I2=x2.l7(4) I3=x2.l5(4) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=x2.l1(1) I2=x2.l3(1) I3=x2.l11(1) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x0.shift I1=x2.l9(1) I2=x2.l7(1) I3=x2.l5(1) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=x0.shift I1=x2.l10(1) I2=x2.l2(1) I3=x2.l0(1) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=D0(1) I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=x2.search O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001110101010
.subckt LUT4 I0=x0.shift I1=x2.l8(1) I2=x2.l6(1) I3=x2.l4(1) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I2_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I1=error_LUT4_O_3_I3_LUT4_O_I3 I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=error_LUT4_O_3_I3_LUT4_O_I1 O=error_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
.param INIT 0000011100001000
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)"
.param INIT 00010000
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
.param INIT 0000000011110100
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
.param INIT 0000000000001110
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011111000000000
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111000001110111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
.param INIT 00111010
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000111111101110
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)"
.param INIT 00010000
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I1 I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)"
.param INIT 0000000100000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=x2.load I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)"
.param INIT 0000000100000000
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 11100000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I1=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I2=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=error_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
.param INIT 0010100011010111
.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I2=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=error_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
.param INIT 0001010001000001
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=error_LUT4_O_3_I3_LUT4_O_I3 I2=error_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0100101110110100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101100000000
.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111111010111111
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001110
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111000011101110
.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I1=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*I2*I3)"
.param INIT 0001000000000000
.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I1=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)"
.param INIT 0000000100000000
.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0111011111110000
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
.param INIT 0000001100001110
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I0_LUT4_I2_O_LUT4_I0_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x0.shift I1=x2.load I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I0_LUT4_I2_O_LUT4_I0_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_1_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001011
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_1_O I1=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1 I3=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=x1.A0_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_1_O I1=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x2.l0_ff_CQZ_4_D_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_1_O O=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_3_I3_LUT4_O_I3 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_O O=error_LUT4_O_4_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x2.load I1=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I1_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1110111100000000
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=alpha(4) I3=x2.load O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I1_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001101
.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I1=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
.param INIT 0000000100110000
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I3 O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01110000
.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I1=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)"
.param INIT 0000010010110000
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
.param INIT 0000011101110111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I2 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
.param INIT 0000000010001111
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000111101110111
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 10000000
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=x2.o4(4) I2=x2.o5(4) I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100100000000
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=x2.o6(4) I3=x2.o9(4) O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x2.o2(4) I1=x2.o3(4) I2=x2.o10(4) I3=x2.o11(4) O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x2.o1(4) I1=x2.o0(4) I2=x2.o7(4) I3=x2.o8(4) O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=error_LUT4_O_I3_LUT4_O_I0 I1=error_LUT4_O_I3_LUT4_O_I1 I2=error_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_1_I2 O=error_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0100001000101011
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=error_LUT4_O_I3_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_O O=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100100000000
.subckt LUT4 I0=x2.o4(3) I1=x2.o5(3) I2=x2.o6(3) I3=x2.o7(3) O=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x2.o2(3) I1=x2.o3(3) I2=x2.o10(3) I3=x2.o11(3) O=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x2.o0(3) I1=x2.o1(3) I2=x2.o8(3) I3=x2.o9(3) O=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_3_I3_LUT4_O_I3 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=error_LUT4_O_4_I3 O=error_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_2_I2_LUT4_O_I1 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O O=error_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt ff CQZ=length0(4) D=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(4) QCK=x0.clk QEN=syn_shift_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=length0(3) D=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(3) QCK=x0.clk QEN=syn_shift_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=length0(2) D=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(2) QCK=x0.clk QEN=syn_shift_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=length0(1) D=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(1) QCK=x0.clk QEN=syn_shift_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=length0(0) D=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(0) QCK=x0.clk QEN=syn_shift_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=length2(4) D=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(4) QCK=x0.clk QEN=chien_load_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=length2(3) D=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(3) QCK=x0.clk QEN=chien_load_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=length2(2) D=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(2) QCK=x0.clk QEN=chien_load_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=length2(1) D=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(1) QCK=x0.clk QEN=chien_load_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=length2(0) D=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(0) QCK=x0.clk QEN=chien_load_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=phase(11) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(12)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 10000000
.subckt LUT4 I0=x0.shift I1=phase(10) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(11)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 10000000
.subckt LUT4 I0=x0.shift I1=phase(1) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(2)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 10000000
.subckt LUT4 I0=x0.shift I1=phase(9) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(10)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 10000000
.subckt LUT4 I0=x0.shift I1=phase(8) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(9)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 10000000
.subckt LUT4 I0=x0.shift I1=phase(7) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(8)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 10000000
.subckt LUT4 I0=x0.shift I1=phase(6) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(7)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 10000000
.subckt LUT4 I0=x0.shift I1=phase(5) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(6)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 10000000
.subckt LUT4 I0=x0.shift I1=phase(4) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(5)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 10000000
.subckt LUT4 I0=x0.shift I1=phase(3) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(4)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 10000000
.subckt LUT4 I0=x0.shift I1=phase(2) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(3)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 10000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x1.phase0_LUT4_I3_O O=phase_LUT4_I1_O(1)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt ff CQZ=phase(11) D=phase_LUT4_I1_O(11) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=phase(10) D=phase_LUT4_I1_O(10) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=phase(1) D=phase_LUT4_I1_O(1) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=phase(9) D=phase_LUT4_I1_O(9) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=phase(8) D=phase_LUT4_I1_O(8) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=phase(7) D=phase_LUT4_I1_O(7) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=phase(6) D=phase_LUT4_I1_O(6) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=phase(5) D=phase_LUT4_I1_O(5) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=phase(4) D=phase_LUT4_I1_O(4) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=phase(3) D=phase_LUT4_I1_O(3) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=phase(2) D=phase_LUT4_I1_O(2) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.shorten D=shorten_ff_CQZ_D QCK=x0.clk QEN=shorten_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.shift I3=x0.clrn O=shorten_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 01
.subckt ff CQZ=x0.enable D=syn_enable_ff_CQZ_D QCK=x0.clk QEN=$auto$hilomap.cc:39:hilomap_worker$25858 QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
.subckt LUT4 I0=syn_enable_ff_CQZ_D_LUT4_O_I0 I1=syn_enable_ff_CQZ_D_LUT4_O_I1 I2=$iopadmap$k(3) I3=syn_enable_ff_CQZ_D_LUT4_O_I3 O=syn_enable_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
.param INIT 0000000011010111
.subckt LUT4 I0=x0.shift I1=syn_enable_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=syn_enable_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=enable_LUT4_I3_O O=syn_enable_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)"
.param INIT 00010000
.subckt LUT4 I0=syn_enable_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=syn_enable_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=length0(4) I3=$iopadmap$k(4) O=syn_enable_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
.param INIT 0001010001000001
.subckt LUT4 I0=x0.shift I1=$iopadmap$k(2) I2=length0(2) I3=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=syn_enable_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=x0.shift I1=length0(3) I2=length0(2) I3=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=syn_enable_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 10000000
.subckt LUT4 I0=length0(0) I1=length0(1) I2=$iopadmap$k(1) I3=$iopadmap$k(0) O=syn_enable_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011111011010111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=syn_shift_ff_CQZ_D I3=syn_enable_ff_CQZ_D_LUT4_O_I1 O=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(3)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x0.shift I1=syn_shift_ff_CQZ_D I2=length0(4) I3=syn_enable_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(4)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01100000
.subckt LUT4 I0=x0.shift I1=syn_shift_ff_CQZ_D I2=length0(2) I3=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(2)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01100000
.subckt LUT4 I0=x0.shift I1=syn_shift_ff_CQZ_D I2=length0(1) I3=length0(0) O=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(1)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01100000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=syn_shift_ff_CQZ_D I3=length0(0) O=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(0)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x0.shift I1=length0(3) I2=length0(2) I3=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=syn_enable_ff_CQZ_D_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 10000111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=length0(1) I3=length0(0) O=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=syn_shift_ff_CQZ_D I3=enable_LUT4_I3_O O=syn_enable_ff_CQZ_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*~I1*I2*I3)"
.param INIT 0001
.subckt ff CQZ=x0.init D=enable_LUT4_I3_O QCK=x0.clk QEN=enable_LUT4_I0_1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=syn_shift_LUT4_I3_I1 I2=x1.phase0 I3=syn_shift O=syn_shift_LUT4_I3_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 10001111
.subckt LUT4 I0=x0.shift I1=x0.clrn I2=x0.init I3=x0.enable O=syn_shift_LUT4_I3_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)"
.param INIT 00010000
.subckt ff CQZ=syn_shift D=syn_shift_ff_CQZ_D QCK=x0.clk QEN=syn_shift_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x0.enable O=syn_shift_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=syn_shift_ff_CQZ_QEN_LUT4_O_I2 I3=syn_enable_ff_CQZ_D O=syn_shift_ff_CQZ_QEN
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=syn_shift_ff_CQZ_QEN_LUT4_O_I2 I3=enable_LUT4_I3_O O=syn_shift_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt ff CQZ=u(4) D=u_ff_CQZ_D(4) QCK=x0.clk QEN=enable_LUT4_I2_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=u(3) D=u_ff_CQZ_D(3) QCK=x0.clk QEN=enable_LUT4_I2_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=u(2) D=u_ff_CQZ_D(2) QCK=x0.clk QEN=enable_LUT4_I2_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=u(1) D=u_ff_CQZ_D(1) QCK=x0.clk QEN=enable_LUT4_I2_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=u(0) D=u_ff_CQZ_D(0) QCK=x0.clk QEN=enable_LUT4_I2_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.search I3=x2.shorten O=$iopadmap$valid
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.enable I3=temp O=with_error_LUT4_I3_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.enable I3=temp O=with_error_LUT4_I3_1_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=with_error_LUT4_I3_O_LUT4_I3_I2 I1=with_error_LUT4_I3_O I2=with_error_LUT4_I3_O_LUT4_I1_I2 I3=chien_load_ff_CQZ_QEN_LUT4_O_I3 O=syn_shift_ff_CQZ_QEN_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
.param INIT 0000000010001111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=enable_LUT4_I0_1_O I3=with_error_LUT4_I3_1_O O=with_error_LUT4_I3_O_LUT4_I1_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*~I1*I2*I3)"
.param INIT 0001
.subckt LUT4 I0=x0.shift I1=x0.shift I2=with_error_LUT4_I3_O I3=enable_LUT4_I0_1_O O=with_error_LUT4_I3_O_LUT4_I2_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=with_error_LUT4_I3_O_LUT4_I2_O I1=with_error_LUT4_I3_O_LUT4_I3_I2 I2=enable_LUT4_I2_I3 I3=syn_enable_ff_CQZ_D_LUT4_O_I3 O=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
.param INIT 0000011100000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=syn_enable_ff_CQZ_D_LUT4_O_I3 I3=with_error_LUT4_I3_O_LUT4_I2_O O=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I3_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=enable_LUT4_I2_I1_LUT4_O_I2 I1=x1.phase0 I2=enable_LUT4_I2_I3 I3=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I3_O O=count_ff_CQZ_QEN
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000110100000000
.subckt LUT4 I0=x2.load I1=x1.phase12 I2=with_error_LUT4_I3_O_LUT4_I3_I2 I3=with_error_LUT4_I3_O O=berl_enable_ff_CQZ_QEN_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111000010001000
.subckt LUT4 I0=count(3) I1=count(0) I2=count(2) I3=count(1) O=with_error_LUT4_I3_O_LUT4_I3_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000000000000000
.subckt LUT4 I0=with_error_LUT4_O_I0 I1=with_error_LUT4_O_I1 I2=with_error_LUT4_O_I2 I3=syn_shift O=temp
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0111111100000000
.subckt LUT4 I0=with_error_LUT4_O_I0_LUT4_O_I0 I1=with_error_LUT4_O_I0_LUT4_O_I1 I2=with_error_LUT4_O_I0_LUT4_O_I2 I3=with_error_LUT4_O_I0_LUT4_O_I3 O=with_error_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000000000000000
.subckt LUT4 I0=s1(0) I1=s1(3) I2=s2(1) I3=s2(4) O=with_error_LUT4_O_I0_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)"
.param INIT 0000000000000001
.subckt LUT4 I0=s5(1) I1=s5(2) I2=s9(1) I3=s9(2) O=with_error_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)"
.param INIT 0000000000000001
.subckt LUT4 I0=s1(4) I1=s2(0) I2=s2(2) I3=s2(3) O=with_error_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)"
.param INIT 0000000000000001
.subckt LUT4 I0=s1(1) I1=s1(2) I2=s10(0) I3=s10(1) O=with_error_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)"
.param INIT 0000000000000001
.subckt LUT4 I0=with_error_LUT4_O_I1_LUT4_O_I0 I1=with_error_LUT4_O_I1_LUT4_O_I1 I2=with_error_LUT4_O_I1_LUT4_O_I2 I3=with_error_LUT4_O_I1_LUT4_O_I3 O=with_error_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000000000000000
.subckt LUT4 I0=with_error_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=with_error_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=with_error_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=with_error_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=with_error_LUT4_O_I1_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000000000000000
.subckt LUT4 I0=s7(2) I1=s7(3) I2=s7(4) I3=s8(0) O=with_error_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)"
.param INIT 0000000000000001
.subckt LUT4 I0=s6(3) I1=s6(4) I2=s7(0) I3=s7(1) O=with_error_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)"
.param INIT 0000000000000001
.subckt LUT4 I0=s9(0) I1=s9(3) I2=s9(4) I3=s10(2) O=with_error_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)"
.param INIT 0000000000000001
.subckt LUT4 I0=s8(1) I1=s8(2) I2=s8(3) I3=s8(4) O=with_error_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)"
.param INIT 0000000000000001
.subckt LUT4 I0=s0(1) I1=s0(2) I2=s0(3) I3=s0(4) O=with_error_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)"
.param INIT 0000000000000001
.subckt LUT4 I0=s11(2) I1=s11(3) I2=s11(4) I3=s0(0) O=with_error_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)"
.param INIT 0000000000000001
.subckt LUT4 I0=s10(3) I1=s10(4) I2=s11(0) I3=s11(1) O=with_error_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)"
.param INIT 0000000000000001
.subckt LUT4 I0=with_error_LUT4_O_I2_LUT4_O_I0 I1=with_error_LUT4_O_I2_LUT4_O_I1 I2=with_error_LUT4_O_I2_LUT4_O_I2 I3=with_error_LUT4_O_I2_LUT4_O_I3 O=with_error_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000000000000000
.subckt LUT4 I0=s3(4) I1=s4(0) I2=s4(1) I3=s4(2) O=with_error_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)"
.param INIT 0000000000000001
.subckt LUT4 I0=s3(0) I1=s3(1) I2=s3(2) I3=s3(3) O=with_error_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)"
.param INIT 0000000000000001
.subckt LUT4 I0=s5(4) I1=s6(0) I2=s6(1) I3=s6(2) O=with_error_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)"
.param INIT 0000000000000001
.subckt LUT4 I0=s4(3) I1=s4(4) I2=s5(0) I3=s5(3) O=with_error_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)"
.param INIT 0000000000000001
.subckt ff CQZ=s0(4) D=x0.y0_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=s0(3) D=x0.y0_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=u(3) I1=x0.init I2=x0.y0_ff_CQZ_1_D_LUT4_O_I2 I3=x0.clrn O=x0.y0_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.y0_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I0 I1=s1(3) I2=x0.init I3=x0.enable O=x0.y0_ff_CQZ_1_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101000001100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s0(2) I3=u(3) O=x0.y0_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt ff CQZ=s0(2) D=x0.y0_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y0_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y0_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s1(2) I3=x0.y0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x0.y0_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=x0.shift I1=s0(4) I2=s0(1) I3=u(2) O=x0.y0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=s0(1) D=x0.y0_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=u(1) I1=x0.init I2=x0.y0_ff_CQZ_3_D_LUT4_O_I2 I3=x0.clrn O=x0.y0_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.y0_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0 I1=s1(1) I2=x0.init I3=x0.enable O=x0.y0_ff_CQZ_3_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101000001100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s0(0) I3=u(1) O=x0.y0_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt ff CQZ=s0(0) D=x0.y0_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=u(0) I1=x0.init I2=x0.y0_ff_CQZ_4_D_LUT4_O_I2 I3=x0.clrn O=x0.y0_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.y0_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0 I1=s1(0) I2=x0.init I3=x0.enable O=x0.y0_ff_CQZ_4_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101000001100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s0(4) I3=u(0) O=x0.y0_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt LUT4 I0=u(4) I1=x0.init I2=x0.y0_ff_CQZ_D_LUT4_O_I2 I3=x0.clrn O=x0.y0_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.y0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=s1(4) I2=x0.init I3=x0.enable O=x0.y0_ff_CQZ_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101000001100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s0(3) I3=u(4) O=x0.y0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt ff CQZ=s10(4) D=x0.y10_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=s10(3) D=x0.y10_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y10_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y10_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s11(3) I3=x0.y10_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x0.y10_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=x0.shift I1=s10(1) I2=u(3) I3=x0.y10_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=x0.y10_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt ff CQZ=s10(2) D=x0.y10_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y10_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y10_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=x0.y10_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I3=s11(2) O=x0.y10_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 11000101
.subckt LUT4 I0=u(2) I1=s10(0) I2=s10(1) I3=x0.y10_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=x0.y10_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt ff CQZ=s10(1) D=x0.y10_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y10_ff_CQZ_3_D_LUT4_O_I0 I1=u(1) I2=x0.init I3=x0.clrn O=x0.y10_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s11(1) I3=x0.y10_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x0.y10_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(1) I1=s10(0) I2=s10(1) I3=s10(4) O=x0.y10_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt ff CQZ=s10(0) D=x0.y10_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y10_ff_CQZ_4_D_LUT4_O_I0 I1=u(0) I2=x0.init I3=x0.clrn O=x0.y10_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s11(0) I3=x0.y10_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x0.y10_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(0) I1=s10(0) I2=s10(3) I3=s10(4) O=x0.y10_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=u(4) I1=x0.init I2=x0.y10_ff_CQZ_D_LUT4_O_I2 I3=x0.clrn O=x0.y10_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.y10_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=s11(4) I2=x0.init I3=x0.enable O=x0.y10_ff_CQZ_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101000001100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=u(4) I3=x0.y10_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=x0.y10_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001
.subckt LUT4 I0=x0.shift I1=s10(4) I2=s10(3) I3=s10(2) O=x0.y10_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=s11(4) D=x0.y11_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=s11(3) D=x0.y11_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y11_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y11_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s0(3) I3=x0.y11_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x0.y11_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=x0.shift I1=s11(4) I2=u(3) I3=x0.y11_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=x0.y11_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=s11(2) D=x0.y11_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=u(2) I1=x0.init I2=x0.y11_ff_CQZ_2_D_LUT4_O_I2 I3=x0.clrn O=x0.y11_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.y11_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I0 I1=s0(2) I2=x0.init I3=x0.enable O=x0.y11_ff_CQZ_2_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101000001100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=u(2) I3=x0.y11_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=x0.y11_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt LUT4 I0=s11(0) I1=s11(1) I2=s11(2) I3=s11(3) O=x0.y11_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt ff CQZ=s11(1) D=x0.y11_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y11_ff_CQZ_3_D_LUT4_O_I0 I1=u(1) I2=x0.init I3=x0.clrn O=x0.y11_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s0(1) I3=x0.y11_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x0.y11_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=x0.shift I1=s11(0) I2=u(1) I3=x0.y11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x0.y11_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=s11(0) D=x0.y11_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y11_ff_CQZ_4_D_LUT4_O_I0 I1=u(0) I2=x0.init I3=x0.clrn O=x0.y11_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s0(0) I3=x0.y11_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x0.y11_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=x0.shift I1=s11(2) I2=u(0) I3=x0.y11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x0.y11_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=x0.y11_ff_CQZ_D_LUT4_O_I0 I1=u(4) I2=x0.init I3=x0.clrn O=x0.y11_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=x0.y11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=s0(4) O=x0.y11_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
.param INIT 00110101
.subckt LUT4 I0=u(4) I1=s11(1) I2=s11(2) I3=x0.y11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x0.y11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s11(4) I3=s11(3) O=x0.y11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt ff CQZ=s1(4) D=x0.y1_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=s1(3) D=x0.y1_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y1_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y1_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.y1_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1 I2=s2(3) I3=x0.enable O=x0.y1_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001011
.subckt LUT4 I0=u(3) I1=s1(1) I2=s1(4) I3=x0.enable O=x0.y1_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011000000000
.subckt ff CQZ=s1(2) D=x0.y1_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y1_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y1_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s2(2) I3=x0.y1_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x0.y1_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=x0.shift I1=s1(3) I2=s1(0) I3=u(2) O=x0.y1_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=s1(1) D=x0.y1_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=u(1) I1=x0.init I2=x0.y1_ff_CQZ_3_D_LUT4_O_I2 I3=x0.clrn O=x0.y1_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.y1_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0 I1=s2(1) I2=x0.init I3=x0.enable O=x0.y1_ff_CQZ_3_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101000001100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s1(4) I3=u(1) O=x0.y1_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt ff CQZ=s1(0) D=x0.y1_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=u(0) I1=x0.init I2=x0.y1_ff_CQZ_4_D_LUT4_O_I2 I3=x0.clrn O=x0.y1_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.y1_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0 I1=s2(0) I2=x0.init I3=x0.enable O=x0.y1_ff_CQZ_4_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101000001100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s1(3) I3=u(0) O=x0.y1_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt LUT4 I0=u(4) I1=x0.init I2=x0.y1_ff_CQZ_D_LUT4_O_I2 I3=x0.clrn O=x0.y1_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.y1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=s2(4) I2=x0.init I3=x0.enable O=x0.y1_ff_CQZ_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101000001100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s1(2) I3=u(4) O=x0.y1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt ff CQZ=s2(4) D=x0.y2_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=s2(3) D=x0.y2_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y2_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y2_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.y2_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1 I2=s3(3) I3=x0.enable O=x0.y2_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001011
.subckt LUT4 I0=u(3) I1=s2(0) I2=s2(3) I3=x0.enable O=x0.y2_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011000000000
.subckt ff CQZ=s2(2) D=x0.y2_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y2_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y2_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.y2_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1 I2=s3(2) I3=x0.enable O=x0.y2_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001011
.subckt LUT4 I0=u(2) I1=s2(2) I2=s2(4) I3=x0.enable O=x0.y2_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011000000000
.subckt ff CQZ=s2(1) D=x0.y2_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=u(1) I1=x0.init I2=x0.y2_ff_CQZ_3_D_LUT4_O_I2 I3=x0.clrn O=x0.y2_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.y2_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0 I1=s3(1) I2=x0.init I3=x0.enable O=x0.y2_ff_CQZ_3_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101000001100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s2(3) I3=u(1) O=x0.y2_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt ff CQZ=s2(0) D=x0.y2_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=u(0) I1=x0.init I2=x0.y2_ff_CQZ_4_D_LUT4_O_I2 I3=x0.clrn O=x0.y2_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.y2_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0 I1=s3(0) I2=x0.init I3=x0.enable O=x0.y2_ff_CQZ_4_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101000001100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s2(2) I3=u(0) O=x0.y2_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt LUT4 I0=x0.y2_ff_CQZ_D_LUT4_O_I0 I1=u(4) I2=x0.init I3=x0.clrn O=x0.y2_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s3(4) I3=x0.y2_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x0.y2_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=x0.shift I1=s2(4) I2=s2(1) I3=u(4) O=x0.y2_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=s3(4) D=x0.y3_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=s3(3) D=x0.y3_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y3_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y3_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.y3_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1 I2=s4(3) I3=x0.enable O=x0.y3_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001011
.subckt LUT4 I0=u(3) I1=s3(2) I2=s3(4) I3=x0.enable O=x0.y3_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011000000000
.subckt ff CQZ=s3(2) D=x0.y3_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y3_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y3_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s4(2) I3=x0.y3_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x0.y3_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(2) I1=s3(1) I2=s3(3) I3=s3(4) O=x0.y3_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt ff CQZ=s3(1) D=x0.y3_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=u(1) I1=x0.init I2=x0.y3_ff_CQZ_3_D_LUT4_O_I2 I3=x0.clrn O=x0.y3_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.y3_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0 I1=s4(1) I2=x0.init I3=x0.enable O=x0.y3_ff_CQZ_3_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101000001100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s3(2) I3=u(1) O=x0.y3_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt ff CQZ=s3(0) D=x0.y3_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=u(0) I1=x0.init I2=x0.y3_ff_CQZ_4_D_LUT4_O_I2 I3=x0.clrn O=x0.y3_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.y3_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0 I1=s4(0) I2=x0.init I3=x0.enable O=x0.y3_ff_CQZ_4_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101000001100
.subckt LUT4 I0=x0.shift I1=s3(4) I2=s3(1) I3=u(0) O=x0.y3_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=x0.y3_ff_CQZ_D_LUT4_O_I0 I1=u(4) I2=x0.init I3=x0.clrn O=x0.y3_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.y3_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=s4(4) I3=x0.enable O=x0.y3_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001011
.subckt LUT4 I0=u(4) I1=s3(0) I2=s3(3) I3=x0.enable O=x0.y3_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011000000000
.subckt ff CQZ=s4(4) D=x0.y4_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=s4(3) D=x0.y4_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y4_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y4_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s5(3) I3=x0.y4_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x0.y4_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(3) I1=s4(1) I2=s4(3) I3=s4(4) O=x0.y4_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt ff CQZ=s4(2) D=x0.y4_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y4_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y4_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s5(2) I3=x0.y4_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x0.y4_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(2) I1=s4(0) I2=s4(2) I3=s4(3) O=x0.y4_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt ff CQZ=s4(1) D=x0.y4_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=u(1) I1=x0.init I2=x0.y4_ff_CQZ_3_D_LUT4_O_I2 I3=x0.clrn O=x0.y4_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.y4_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0 I1=s5(1) I2=x0.init I3=x0.enable O=x0.y4_ff_CQZ_3_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101000001100
.subckt LUT4 I0=x0.shift I1=s4(4) I2=s4(1) I3=u(1) O=x0.y4_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt ff CQZ=s4(0) D=x0.y4_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=u(0) I1=x0.init I2=x0.y4_ff_CQZ_4_D_LUT4_O_I2 I3=x0.clrn O=x0.y4_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.y4_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0 I1=s5(0) I2=x0.init I3=x0.enable O=x0.y4_ff_CQZ_4_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101000001100
.subckt LUT4 I0=x0.shift I1=s4(3) I2=s4(0) I3=u(0) O=x0.y4_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=x0.y4_ff_CQZ_D_LUT4_O_I0 I1=u(4) I2=x0.init I3=x0.clrn O=x0.y4_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.y4_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=s5(4) I3=x0.enable O=x0.y4_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001011
.subckt LUT4 I0=u(4) I1=s4(2) I2=s4(4) I3=x0.enable O=x0.y4_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011000000000
.subckt ff CQZ=s5(4) D=x0.y5_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=s5(3) D=x0.y5_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y5_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y5_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s6(3) I3=x0.y5_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x0.y5_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(3) I1=s5(0) I2=s5(2) I3=s5(3) O=x0.y5_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt ff CQZ=s5(2) D=x0.y5_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y5_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y5_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s6(2) I3=x0.y5_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x0.y5_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=x0.shift I1=s5(2) I2=s5(1) I3=u(2) O=x0.y5_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=s5(1) D=x0.y5_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=u(1) I1=x0.init I2=x0.y5_ff_CQZ_3_D_LUT4_O_I2 I3=x0.clrn O=x0.y5_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.y5_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0 I1=s6(1) I2=x0.init I3=x0.enable O=x0.y5_ff_CQZ_3_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101000001100
.subckt LUT4 I0=x0.shift I1=s5(3) I2=s5(0) I3=u(1) O=x0.y5_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt ff CQZ=s5(0) D=x0.y5_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y5_ff_CQZ_4_D_LUT4_O_I0 I1=u(0) I2=x0.init I3=x0.clrn O=x0.y5_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.y5_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I1 I2=s6(0) I3=x0.enable O=x0.y5_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001011
.subckt LUT4 I0=u(0) I1=s5(2) I2=s5(4) I3=x0.enable O=x0.y5_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011000000000
.subckt LUT4 I0=x0.y5_ff_CQZ_D_LUT4_O_I0 I1=u(4) I2=x0.init I3=x0.clrn O=x0.y5_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s6(4) I3=x0.y5_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x0.y5_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(4) I1=s5(1) I2=s5(3) I3=s5(4) O=x0.y5_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt ff CQZ=s6(4) D=x0.y6_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=s6(3) D=x0.y6_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y6_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y6_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.y6_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1 I2=s7(3) I3=x0.enable O=x0.y6_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001011
.subckt LUT4 I0=u(3) I1=s6(1) I2=s6(2) I3=x0.enable O=x0.y6_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011000000000
.subckt ff CQZ=s6(2) D=x0.y6_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y6_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y6_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s7(2) I3=x0.y6_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x0.y6_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(2) I1=s6(0) I2=s6(1) I3=s6(4) O=x0.y6_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt ff CQZ=s6(1) D=x0.y6_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y6_ff_CQZ_3_D_LUT4_O_I0 I1=u(1) I2=x0.init I3=x0.clrn O=x0.y6_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.y6_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I2=s7(1) I3=x0.enable O=x0.y6_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001011
.subckt LUT4 I0=u(1) I1=s6(2) I2=s6(4) I3=x0.enable O=x0.y6_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011000000000
.subckt ff CQZ=s6(0) D=x0.y6_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y6_ff_CQZ_4_D_LUT4_O_I0 I1=u(0) I2=x0.init I3=x0.clrn O=x0.y6_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s7(0) I3=x0.y6_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x0.y6_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(0) I1=s6(1) I2=s6(3) I3=s6(4) O=x0.y6_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x0.y6_ff_CQZ_D_LUT4_O_I0 I1=u(4) I2=x0.init I3=x0.clrn O=x0.y6_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s7(4) I3=x0.y6_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x0.y6_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(4) I1=s6(0) I2=s6(2) I3=s6(3) O=x0.y6_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt ff CQZ=s7(4) D=x0.y7_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=s7(3) D=x0.y7_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y7_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y7_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s8(3) I3=x0.y7_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x0.y7_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(3) I1=s7(0) I2=s7(1) I3=s7(4) O=x0.y7_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt ff CQZ=s7(2) D=x0.y7_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y7_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y7_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s8(2) I3=x0.y7_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x0.y7_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(2) I1=s7(0) I2=s7(3) I3=s7(4) O=x0.y7_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt ff CQZ=s7(1) D=x0.y7_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y7_ff_CQZ_3_D_LUT4_O_I0 I1=u(1) I2=x0.init I3=x0.clrn O=x0.y7_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s8(1) I3=x0.y7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x0.y7_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(1) I1=s7(1) I2=s7(3) I3=s7(4) O=x0.y7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt ff CQZ=s7(0) D=x0.y7_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y7_ff_CQZ_4_D_LUT4_O_I0 I1=u(0) I2=x0.init I3=x0.clrn O=x0.y7_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s8(0) I3=x0.y7_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x0.y7_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(0) I1=s7(0) I2=s7(2) I3=s7(3) O=x0.y7_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x0.y7_ff_CQZ_D_LUT4_O_I0 I1=u(4) I2=x0.init I3=x0.clrn O=x0.y7_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.y7_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=s8(4) I3=x0.enable O=x0.y7_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001011
.subckt LUT4 I0=u(4) I1=s7(1) I2=s7(2) I3=x0.enable O=x0.y7_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011000000000
.subckt ff CQZ=s8(4) D=x0.y8_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=s8(3) D=x0.y8_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y8_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y8_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s9(3) I3=x0.y8_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x0.y8_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(3) I1=s8(0) I2=s8(3) I3=s8(4) O=x0.y8_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt ff CQZ=s8(2) D=x0.y8_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y8_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y8_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s9(2) I3=x0.y8_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x0.y8_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(2) I1=s8(2) I2=s8(3) I3=s8(4) O=x0.y8_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt ff CQZ=s8(1) D=x0.y8_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y8_ff_CQZ_3_D_LUT4_O_I0 I1=u(1) I2=x0.init I3=x0.clrn O=x0.y8_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s9(1) I3=x0.y8_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x0.y8_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(1) I1=s8(0) I2=s8(2) I3=s8(3) O=x0.y8_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt ff CQZ=s8(0) D=x0.y8_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y8_ff_CQZ_4_D_LUT4_O_I0 I1=u(0) I2=x0.init I3=x0.clrn O=x0.y8_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.y8_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I1 I2=s9(0) I3=x0.enable O=x0.y8_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001011
.subckt LUT4 I0=u(0) I1=s8(1) I2=s8(2) I3=x0.enable O=x0.y8_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011000000000
.subckt LUT4 I0=x0.y8_ff_CQZ_D_LUT4_O_I0 I1=u(4) I2=x0.init I3=x0.clrn O=x0.y8_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s9(4) I3=x0.y8_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x0.y8_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(4) I1=s8(0) I2=s8(1) I3=s8(4) O=x0.y8_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt ff CQZ=s9(4) D=x0.y9_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=s9(3) D=x0.y9_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y9_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y9_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s10(3) I3=x0.y9_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x0.y9_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(3) I1=s9(2) I2=s9(3) I3=s9(4) O=x0.y9_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt ff CQZ=s9(2) D=x0.y9_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y9_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y9_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=x0.y9_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I3=s10(2) O=x0.y9_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
.param INIT 00110101
.subckt LUT4 I0=u(2) I1=s9(2) I2=s9(3) I3=x0.y9_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x0.y9_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt ff CQZ=s9(1) D=x0.y9_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y9_ff_CQZ_3_D_LUT4_O_I0 I1=u(1) I2=x0.init I3=x0.clrn O=x0.y9_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s10(1) I3=x0.y9_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x0.y9_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=x0.shift I1=s9(2) I2=s9(1) I3=u(1) O=x0.y9_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=s9(0) D=x0.y9_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.y9_ff_CQZ_4_D_LUT4_O_I0 I1=u(0) I2=x0.init I3=x0.clrn O=x0.y9_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s10(0) I3=x0.y9_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x0.y9_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=x0.shift I1=s9(0) I2=u(0) I3=x0.y9_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x0.y9_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s9(4) I3=s9(1) O=x0.y9_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt LUT4 I0=x0.y9_ff_CQZ_D_LUT4_O_I0 I1=u(4) I2=x0.init I3=x0.clrn O=x0.y9_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100010100000000
.subckt LUT4 I0=x0.shift I1=x0.enable I2=s10(4) I3=x0.y9_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x0.y9_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10100011
.subckt LUT4 I0=u(4) I1=s9(0) I2=s9(3) I3=s9(4) O=x0.y9_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt ff CQZ=x1.A0(4) D=x1.A0_ff_CQZ_D QCK=x0.clk QEN=x1.A0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.A0(3) D=x1.A0_ff_CQZ_1_D QCK=x0.clk QEN=x1.A0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x1.A0_ff_CQZ_1_D_LUT4_O_I0 I1=x1.A10(3) I2=x1.B0_ff_CQZ_D_LUT4_O_I2 I3=x1.enable O=x1.A0_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0 I1=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1 I2=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 I3=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x1.A0_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt LUT4 I0=x0.shift I1=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I2=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 I3=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1 O=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01100000
.subckt LUT4 I0=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I1=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 I2=x1.A0_ff_CQZ_4_D_LUT4_O_I0 I3=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1 O=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001000000000000
.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3 I1=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011010001001011
.subckt LUT4 I0=s9(2) I1=x1.phase0 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I2 O=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I1=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s9(3) I3=x1.phase0 O=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I0 O=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 11100000
.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I1=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.omega11(3) I3=x1.lambda3(3) O=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt ff CQZ=x1.A0(2) D=x1.A0_ff_CQZ_2_D QCK=x0.clk QEN=x1.A0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x1.A0_ff_CQZ_2_D_LUT4_O_I0 I1=x1.A10(2) I2=x1.B0_ff_CQZ_D_LUT4_O_I2 I3=x1.enable O=x1.A0_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x1.A0_ff_CQZ_4_D_LUT4_O_I0 I1=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1 I2=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I3=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x1.A0_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011010001001011
.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I1=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I2 O=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_1_O I1=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1 I3=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.omega11(2) I3=x1.lambda3(2) O=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt ff CQZ=x1.A0(1) D=x1.A0_ff_CQZ_3_D QCK=x0.clk QEN=x1.A0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I1 I1=x1.A10(1) I2=x1.B0_ff_CQZ_D_LUT4_O_I2 I3=x1.enable O=x1.A0_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt ff CQZ=x1.A0(0) D=x1.A0_ff_CQZ_4_D QCK=x0.clk QEN=x1.A0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x1.A0_ff_CQZ_4_D_LUT4_O_I0 I1=x1.A10(0) I2=x1.B0_ff_CQZ_D_LUT4_O_I2 I3=x1.enable O=x1.A0_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x1.D_ff_CQZ_D_LUT4_O_I3 I1=x1.A10(4) I2=x1.B0_ff_CQZ_D_LUT4_O_I2 I3=x1.enable O=x1.A0_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x1.B0_ff_CQZ_D_LUT4_O_I2 I1=x1.phase12 I2=x1.phase0 I3=x1.enable O=x1.A0_ff_CQZ_QEN
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101111111111
.subckt ff CQZ=x1.A10(4) D=x1.A10_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.A10(3) D=x1.A10_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A9(3) I3=x1.enable O=x1.A10_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A10(2) D=x1.A10_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A9(2) I3=x1.enable O=x1.A10_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A10(1) D=x1.A10_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A9(1) I3=x1.enable O=x1.A10_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A10(0) D=x1.A10_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A9(0) I3=x1.enable O=x1.A10_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A9(4) I3=x1.enable O=x1.A10_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A1(4) D=x1.A1_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.A1(3) D=x1.A1_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A0(3) I3=x1.enable O=x1.A1_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A1(2) D=x1.A1_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A0(2) I3=x1.enable O=x1.A1_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A1(1) D=x1.A1_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A0(1) I3=x1.enable O=x1.A1_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A1(0) D=x1.A1_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A0(0) I3=x1.enable O=x1.A1_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A0(4) I3=x1.enable O=x1.A1_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A2(4) D=x1.A2_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.A2(3) D=x1.A2_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A1(3) I3=x1.enable O=x1.A2_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A2(2) D=x1.A2_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A1(2) I3=x1.enable O=x1.A2_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A2(1) D=x1.A2_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A1(1) I3=x1.enable O=x1.A2_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A2(0) D=x1.A2_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A1(0) I3=x1.enable O=x1.A2_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A1(4) I3=x1.enable O=x1.A2_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A3(4) D=x1.A3_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.A3(3) D=x1.A3_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A2(3) I3=x1.enable O=x1.A3_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A3(2) D=x1.A3_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A2(2) I3=x1.enable O=x1.A3_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A3(1) D=x1.A3_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A2(1) I3=x1.enable O=x1.A3_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A3(0) D=x1.A3_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A2(0) I3=x1.enable O=x1.A3_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A2(4) I3=x1.enable O=x1.A3_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A4(4) D=x1.A4_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.A4(3) D=x1.A4_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A3(3) I3=x1.enable O=x1.A4_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A4(2) D=x1.A4_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A3(2) I3=x1.enable O=x1.A4_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A4(1) D=x1.A4_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A3(1) I3=x1.enable O=x1.A4_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A4(0) D=x1.A4_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A3(0) I3=x1.enable O=x1.A4_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A3(4) I3=x1.enable O=x1.A4_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A5(4) D=x1.A5_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.A5(3) D=x1.A5_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A4(3) I3=x1.enable O=x1.A5_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A5(2) D=x1.A5_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A4(2) I3=x1.enable O=x1.A5_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A5(1) D=x1.A5_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A4(1) I3=x1.enable O=x1.A5_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A5(0) D=x1.A5_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A4(0) I3=x1.enable O=x1.A5_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A4(4) I3=x1.enable O=x1.A5_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A6(4) D=x1.A6_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.A6(3) D=x1.A6_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A5(3) I3=x1.enable O=x1.A6_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A6(2) D=x1.A6_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A5(2) I3=x1.enable O=x1.A6_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A6(1) D=x1.A6_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A5(1) I3=x1.enable O=x1.A6_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A6(0) D=x1.A6_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A5(0) I3=x1.enable O=x1.A6_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A5(4) I3=x1.enable O=x1.A6_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A7(4) D=x1.A7_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.A7(3) D=x1.A7_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A6(3) I3=x1.enable O=x1.A7_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A7(2) D=x1.A7_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A6(2) I3=x1.enable O=x1.A7_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A7(1) D=x1.A7_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A6(1) I3=x1.enable O=x1.A7_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A7(0) D=x1.A7_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A6(0) I3=x1.enable O=x1.A7_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A6(4) I3=x1.enable O=x1.A7_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A8(4) D=x1.A8_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.A8(3) D=x1.A8_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A7(3) I3=x1.enable O=x1.A8_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A8(2) D=x1.A8_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A7(2) I3=x1.enable O=x1.A8_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A8(1) D=x1.A8_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A7(1) I3=x1.enable O=x1.A8_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A8(0) D=x1.A8_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A7(0) I3=x1.enable O=x1.A8_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A7(4) I3=x1.enable O=x1.A8_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A9(4) D=x1.A9_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.A9(3) D=x1.A9_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A8(3) I3=x1.enable O=x1.A9_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A9(2) D=x1.A9_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A8(2) I3=x1.enable O=x1.A9_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A9(1) D=x1.A9_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A8(1) I3=x1.enable O=x1.A9_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.A9(0) D=x1.A9_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A8(0) I3=x1.enable O=x1.A9_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A8(4) I3=x1.enable O=x1.A9_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B0(4) D=x1.B0_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.B0(3) D=x1.B0_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.enable I3=x1.B0_ff_CQZ_1_D_LUT4_O_I3 O=x1.B0_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x1.phase12 I1=x1.B10(3) I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0 I3=x1.B0_ff_CQZ_D_LUT4_O_I2 O=x1.B0_ff_CQZ_1_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000111110111011
.subckt ff CQZ=x1.B0(2) D=x1.B0_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.enable I3=x1.B0_ff_CQZ_2_D_LUT4_O_I3 O=x1.B0_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x1.phase12 I1=x1.B10(2) I2=x1.D_ff_CQZ_2_D_LUT4_O_I1 I3=x1.B0_ff_CQZ_D_LUT4_O_I2 O=x1.B0_ff_CQZ_2_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111000010111011
.subckt ff CQZ=x1.B0(1) D=x1.B0_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.enable I3=x1.B0_ff_CQZ_3_D_LUT4_O_I3 O=x1.B0_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x1.phase12 I1=x1.B10(1) I2=x1.D_ff_CQZ_3_D_LUT4_O_I0 I3=x1.B0_ff_CQZ_D_LUT4_O_I2 O=x1.B0_ff_CQZ_3_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111000010111011
.subckt ff CQZ=x1.B0(0) D=x1.B0_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.enable I3=x1.B0_ff_CQZ_4_D_LUT4_O_I3 O=x1.B0_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011
.subckt LUT4 I0=x1.phase12 I1=x1.B10(0) I2=x2.l0_ff_CQZ_4_D_LUT4_O_I1 I3=x1.B0_ff_CQZ_D_LUT4_O_I2 O=x1.B0_ff_CQZ_4_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111000001000100
.subckt LUT4 I0=x1.B0_ff_CQZ_D_LUT4_O_I0 I1=x1.B0_ff_CQZ_D_LUT4_O_I1 I2=x1.B0_ff_CQZ_D_LUT4_O_I2 I3=x1.enable O=x1.B0_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 O=x1.B0_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B10(4) I3=x1.phase12 O=x1.B0_ff_CQZ_D_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt ff CQZ=x1.B10(4) D=x1.B10_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.B10(3) D=x1.B10_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B9(3) I3=x1.enable O=x1.B10_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B10(2) D=x1.B10_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B9(2) I3=x1.enable O=x1.B10_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B10(1) D=x1.B10_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B9(1) I3=x1.enable O=x1.B10_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B10(0) D=x1.B10_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B9(0) I3=x1.enable O=x1.B10_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B9(4) I3=x1.enable O=x1.B10_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B1(4) D=x1.B1_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.B1(3) D=x1.B1_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B0(3) I3=x1.enable O=x1.B1_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B1(2) D=x1.B1_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B0(2) I3=x1.enable O=x1.B1_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B1(1) D=x1.B1_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B0(1) I3=x1.enable O=x1.B1_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B1(0) D=x1.B1_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B0(0) I3=x1.enable O=x1.B1_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B0(4) I3=x1.enable O=x1.B1_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B2(4) D=x1.B2_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.B2(3) D=x1.B2_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B1(3) I3=x1.enable O=x1.B2_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B2(2) D=x1.B2_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B1(2) I3=x1.enable O=x1.B2_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B2(1) D=x1.B2_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B1(1) I3=x1.enable O=x1.B2_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B2(0) D=x1.B2_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B1(0) I3=x1.enable O=x1.B2_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B1(4) I3=x1.enable O=x1.B2_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B3(4) D=x1.B3_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.B3(3) D=x1.B3_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B2(3) I3=x1.enable O=x1.B3_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B3(2) D=x1.B3_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B2(2) I3=x1.enable O=x1.B3_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B3(1) D=x1.B3_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B2(1) I3=x1.enable O=x1.B3_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B3(0) D=x1.B3_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B2(0) I3=x1.enable O=x1.B3_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B2(4) I3=x1.enable O=x1.B3_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B4(4) D=x1.B4_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.B4(3) D=x1.B4_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B3(3) I3=x1.enable O=x1.B4_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B4(2) D=x1.B4_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B3(2) I3=x1.enable O=x1.B4_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B4(1) D=x1.B4_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B3(1) I3=x1.enable O=x1.B4_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B4(0) D=x1.B4_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B3(0) I3=x1.enable O=x1.B4_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B3(4) I3=x1.enable O=x1.B4_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B5(4) D=x1.B5_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.B5(3) D=x1.B5_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B4(3) I3=x1.enable O=x1.B5_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B5(2) D=x1.B5_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B4(2) I3=x1.enable O=x1.B5_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B5(1) D=x1.B5_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B4(1) I3=x1.enable O=x1.B5_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B5(0) D=x1.B5_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B4(0) I3=x1.enable O=x1.B5_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B4(4) I3=x1.enable O=x1.B5_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B6(4) D=x1.B6_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.B6(3) D=x1.B6_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B5(3) I3=x1.enable O=x1.B6_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B6(2) D=x1.B6_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B5(2) I3=x1.enable O=x1.B6_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B6(1) D=x1.B6_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B5(1) I3=x1.enable O=x1.B6_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B6(0) D=x1.B6_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B5(0) I3=x1.enable O=x1.B6_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B5(4) I3=x1.enable O=x1.B6_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B7(4) D=x1.B7_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.B7(3) D=x1.B7_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B6(3) I3=x1.enable O=x1.B7_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B7(2) D=x1.B7_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B6(2) I3=x1.enable O=x1.B7_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B7(1) D=x1.B7_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B6(1) I3=x1.enable O=x1.B7_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B7(0) D=x1.B7_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B6(0) I3=x1.enable O=x1.B7_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B6(4) I3=x1.enable O=x1.B7_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B8(4) D=x1.B8_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.B8(3) D=x1.B8_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B7(3) I3=x1.enable O=x1.B8_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B8(2) D=x1.B8_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B7(2) I3=x1.enable O=x1.B8_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B8(1) D=x1.B8_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B7(1) I3=x1.enable O=x1.B8_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B8(0) D=x1.B8_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B7(0) I3=x1.enable O=x1.B8_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B7(4) I3=x1.enable O=x1.B8_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B9(4) D=x1.B9_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.B9(3) D=x1.B9_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B8(3) I3=x1.enable O=x1.B9_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B9(2) D=x1.B9_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B8(2) I3=x1.enable O=x1.B9_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B9(1) D=x1.B9_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B8(1) I3=x1.enable O=x1.B9_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.B9(0) D=x1.B9_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B8(0) I3=x1.enable O=x1.B9_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B8(4) I3=x1.enable O=x1.B9_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=D0(4) D=x1.D_ff_CQZ_D QCK=x0.clk QEN=x1.D_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:541.2-557.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=D0(3) D=x1.D_ff_CQZ_1_D QCK=x0.clk QEN=x1.D_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:541.2-557.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.clrn I2=x1.D_ff_CQZ_1_D_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3 O=x1.D_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010000
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I2 I3=x2.l0_ff_CQZ_1_D_LUT4_O_I0 O=x1.D_ff_CQZ_1_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=x0.shift I1=x1.lambda9(2) I2=s3(0) I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 01000000
.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I1=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0100101110110100
.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I1=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=s3(0) I3=x1.lambda9(4) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
.param INIT 0010110111011101
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda9(1) I3=s3(2) O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=s3(1) I1=x1.lambda9(2) I2=s3(3) I3=x1.lambda9(0) O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I1=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
.param INIT 0001111101110101
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda9(3) I3=s3(0) O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=x1.lambda9(2) I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010000
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=x1.lambda11(2) I3=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010000
.subckt LUT4 I0=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0100101110110100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda11(1) I3=s1(2) O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=x1.lambda11(1) I2=x1.lambda11(2) I3=s1(2) O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011010000000000
.subckt LUT4 I0=s1(1) I1=x1.lambda11(2) I2=s1(3) I3=x1.lambda11(0) O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
.param INIT 0001111101110101
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda11(3) I3=s1(0) O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x1.lambda11(2) I2=s1(0) I3=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 01000000
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2 I3=x1.A0_ff_CQZ_1_D_LUT4_O_I0 O=x1.D_ff_CQZ_1_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=x1.lambda10(2) I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010000
.subckt LUT4 I0=x0.shift I1=x1.lambda10(2) I2=s2(0) I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 01000000
.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
.param INIT 0010101111010100
.subckt LUT4 I0=s2(0) I1=x1.lambda10(3) I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101111000
.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=s2(0) I3=x1.lambda10(3) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
.param INIT 0010101110111011
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=x1.lambda10(2) I3=s2(1) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01111000
.subckt LUT4 I0=s2(2) I1=x1.lambda10(1) I2=s2(3) I3=x1.lambda10(0) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=s2(1) I1=s2(2) I2=x1.lambda10(0) I3=x1.lambda10(1) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000000000000000
.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt LUT4 I0=s4(1) I1=x1.lambda8(2) I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101111000
.subckt LUT4 I0=s5(0) I1=x1.lambda7(3) I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101111000
.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I2=x1.lambda7(2) I3=s5(1) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01111000
.subckt LUT4 I0=s5(1) I1=s5(2) I2=x1.lambda7(0) I3=x1.lambda7(1) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000000000000000
.subckt LUT4 I0=x0.shift I1=x1.lambda7(2) I2=s5(0) I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 01000000
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 11010100
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I2=x1.lambda7(2) I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010000
.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000111001110001
.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt LUT4 I0=s7(0) I1=x1.lambda5(4) I2=s7(2) I3=x1.lambda5(2) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s7(3) I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=s7(1) I1=x1.lambda5(0) I2=x1.lambda5(2) I3=x1.lambda5(1) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
.param INIT 1000000001111111
.subckt LUT4 I0=s7(1) I1=x1.lambda5(3) I2=s7(4) I3=x1.lambda5(0) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=x1.lambda5(2) I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010000
.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0100101110110100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda5(1) I3=s7(2) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
.param INIT 0010110001001111
.subckt LUT4 I0=s7(1) I1=x1.lambda5(2) I2=s7(3) I3=x1.lambda5(0) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda5(3) I3=s7(0) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x1.lambda5(2) I2=s7(0) I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 01000000
.subckt ff CQZ=D0(2) D=x1.D_ff_CQZ_2_D QCK=x0.clk QEN=x1.D_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:541.2-557.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x1.D_ff_CQZ_2_D_LUT4_O_I0 I1=x1.D_ff_CQZ_2_D_LUT4_O_I1 I2=x1.D_ff_CQZ_2_D_LUT4_O_I2 I3=x0.clrn O=x1.D_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011000000000
.subckt LUT4 I0=x1.A0_ff_CQZ_2_D_LUT4_O_I0 I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1 I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I3=x1.omega0_ff_CQZ_2_D_LUT4_O_I0 O=x1.D_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt LUT4 I0=s3(0) I1=x1.lambda9(2) I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101111000
.subckt LUT4 I0=x0.shift I1=x1.lambda9(1) I2=s3(0) I3=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 10000000
.subckt LUT4 I0=s3(1) I1=x1.lambda9(1) I2=s3(2) I3=x1.lambda9(0) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x0.shift I1=x1.lambda8(1) I2=s4(1) I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 01000000
.subckt LUT4 I0=s2(0) I1=x1.lambda10(2) I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101111000
.subckt LUT4 I0=s2(0) I1=s2(1) I2=x1.lambda10(0) I3=x1.lambda10(1) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000000000000000
.subckt LUT4 I0=s2(1) I1=x1.lambda10(1) I2=s2(2) I3=x1.lambda10(0) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=s4(1) I3=x1.lambda8(1) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011000000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=s4(0) I1=x1.lambda8(2) I2=s4(2) I3=x1.lambda8(0) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=s8(0) I1=x1.lambda4(2) I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I1 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101111000
.subckt LUT4 I0=s7(0) I1=x1.lambda5(2) I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101111000
.subckt LUT4 I0=x0.shift I1=x1.lambda5(1) I2=s7(0) I3=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 10000000
.subckt LUT4 I0=s7(1) I1=x1.lambda5(1) I2=s7(2) I3=x1.lambda5(0) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt LUT4 I0=s5(0) I1=x1.lambda7(2) I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101111000
.subckt LUT4 I0=s5(0) I1=s5(1) I2=x1.lambda7(0) I3=x1.lambda7(1) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000000000000000
.subckt LUT4 I0=s5(1) I1=x1.lambda7(1) I2=s5(2) I3=x1.lambda7(0) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=s6(0) I1=s6(1) I2=x1.lambda6(0) I3=x1.lambda6(1) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000000000000000
.subckt LUT4 I0=x1.lambda6(1) I1=s6(1) I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0111011100001111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda6(2) I3=s6(0) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=s6(1) I1=x1.lambda6(1) I2=s6(2) I3=x1.lambda6(0) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x2.l0_ff_CQZ_4_D_LUT4_O_I1 I1=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1 I2=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011010001001011
.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I1=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 O=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_1_O I1=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I3=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=alpha(0) I3=x2.load O=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001101
.subckt LUT4 I0=s11(2) I1=x1.phase0 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.lambda11(2) I3=x1.lambda1(2) O=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=s11(2) I1=x1.phase0 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_2_D_LUT4_O_I0 O=x1.D_ff_CQZ_2_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt LUT4 I0=s1(0) I1=x1.lambda11(2) I2=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101111000
.subckt LUT4 I0=x0.shift I1=x1.lambda11(1) I2=s1(0) I3=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 10000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda11(0) I3=s1(1) O=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=s1(1) I1=x1.lambda11(1) I2=s1(2) I3=x1.lambda11(0) O=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt ff CQZ=D0(1) D=x1.D_ff_CQZ_3_D QCK=x0.clk QEN=x1.D_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:541.2-557.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I0 I1=x1.D_ff_CQZ_3_D_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I2 I3=x0.clrn O=x1.D_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011000000000
.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I0 I1=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1110000000011111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s11(0) I3=x1.phase0 O=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.lambda11(1) I3=x1.lambda1(1) O=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I1=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=alpha(1) I3=x2.load O=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001101
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s11(1) I3=x1.phase0 O=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.lambda11(0) I3=x1.lambda1(0) O=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I0 I1=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_3_D_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1110000000011111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s9(0) I3=x1.phase0 O=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.omega11(1) I3=x1.lambda3(1) O=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I1=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s9(1) I3=x1.phase0 O=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.omega11(0) I3=x1.lambda3(0) O=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0 I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0 I3=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_3_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=s3(0) I1=x1.lambda9(1) I2=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0111100010000111
.subckt LUT4 I0=s1(0) I1=x1.lambda11(1) I2=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0111100010000111
.subckt LUT4 I0=s2(0) I1=x1.lambda10(1) I2=s2(1) I3=x1.lambda10(0) O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda9(0) I3=s3(1) O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=s7(0) I1=x1.lambda5(1) I2=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101111000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda5(0) I3=s7(1) O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=s8(0) I1=x1.lambda4(1) I2=s8(1) I3=x1.lambda4(0) O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=s4(0) I1=x1.lambda8(1) I2=s4(1) I3=x1.lambda8(0) O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=s6(0) I1=x1.lambda6(1) I2=s6(1) I3=x1.lambda6(0) O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=s5(0) I1=x1.lambda7(1) I2=s5(1) I3=x1.lambda7(0) O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt ff CQZ=D0(0) D=x1.D_ff_CQZ_4_D QCK=x0.clk QEN=x1.D_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:541.2-557.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x1.D_ff_CQZ_4_D_LUT4_O_I3 O=x1.D_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.l0_ff_CQZ_4_D_LUT4_O_I1 I1=x1.A0_ff_CQZ_4_D_LUT4_O_I0 I2=x1.D_ff_CQZ_4_D_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_4_D_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_4_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_4_D_LUT4_O_I1 I2=x1.lambda4(0) I3=s8(0) O=x1.D_ff_CQZ_4_D_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01111000
.subckt LUT4 I0=x0.shift I1=x0.clrn I2=x1.D_ff_CQZ_D_LUT4_O_I2 I3=x1.D_ff_CQZ_D_LUT4_O_I3 O=x1.D_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010000
.subckt LUT4 I0=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0 I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1 I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 I3=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1110100010001110
.subckt LUT4 I0=x0.shift I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01011100
.subckt LUT4 I0=x0.shift I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=s11(4) I1=x1.phase0 I2=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.shift I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 11101000
.subckt LUT4 I0=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_1_O I1=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
.param INIT 0000000011110100
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.lambda11(4) I3=x1.lambda1(4) O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01010011
.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_O I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O I2=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=s8(0) I1=x1.lambda4(4) I2=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0111100010000111
.subckt LUT4 I0=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I1 I1=s8(1) I2=x1.lambda4(2) I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011111101000000
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=x1.lambda4(3) I3=s8(1) O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 10000111
.subckt LUT4 I0=s8(3) I1=x1.lambda4(1) I2=s8(4) I3=x1.lambda4(0) O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s8(2) I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=s8(3) I1=x1.lambda4(0) I2=x1.lambda4(1) I3=x1.lambda4(2) O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
.param INIT 1000000001111111
.subckt LUT4 I0=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I2 I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3 I2=s8(0) I3=x1.lambda4(3) O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
.param INIT 0010101110111011
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt LUT4 I0=x0.shift I1=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01100000
.subckt LUT4 I0=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 I1=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
.param INIT 0001000011101111
.subckt LUT4 I0=x0.shift I1=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001011
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10110100
.subckt LUT4 I0=s9(4) I1=x1.phase0 I2=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=x0.shift I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=s9(2) I3=x1.phase0 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
.param INIT 00000111
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I0 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001110
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.omega11(4) I3=x1.lambda3(4) O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01010011
.subckt LUT4 I0=x0.shift I1=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 I2=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 I3=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01011100
.subckt LUT4 I0=x0.shift I1=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0 I1=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1 I2=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 I3=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1110100010001110
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x1.phase0 O=x1.D_ff_CQZ_QEN
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011
.subckt LUT4 I0=x1.L_LUT4_I2_O I1=x1.L(2) I2=count(3) I3=x1.L_LUT4_I1_I3 O=x1.B0_ff_CQZ_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
.param INIT 0000000010110010
.subckt LUT4 I0=x0.shift I1=x1.L_LUT4_I1_I3_LUT4_O_I1 I2=D0(1) I3=D0(0) O=x1.L_LUT4_I1_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)"
.param INIT 00010000
.subckt LUT4 I0=x0.shift I1=D0(4) I2=D0(3) I3=D0(2) O=x1.L_LUT4_I1_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)"
.param INIT 00000001
.subckt LUT4 I0=count(2) I1=count(1) I2=x1.L(1) I3=x1.L(0) O=x1.L_LUT4_I2_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000111010101111
.subckt ff CQZ=x1.L(2) D=x1.L_ff_CQZ_D QCK=x0.clk QEN=x1.L_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:541.2-557.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.L(1) D=x1.L_ff_CQZ_1_D QCK=x0.clk QEN=x1.L_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:541.2-557.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x1.L_ff_CQZ_1_D_LUT4_O_I0 I1=count(1) I2=x1.L(1) I3=x0.clrn O=x1.L_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=count(0) I3=x1.L(0) O=x1.L_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt ff CQZ=x1.L(0) D=x1.L_ff_CQZ_2_D QCK=x0.clk QEN=x1.L_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:541.2-557.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.clrn I2=x1.L(0) I3=count(0) O=x1.L_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x1.L_ff_CQZ_D_LUT4_O_I3 O=x1.L_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x1.L_ff_CQZ_1_D_LUT4_O_I0 I1=count(1) I2=x1.L(1) I3=x1.L_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=x1.L_ff_CQZ_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
.param INIT 0001100011100111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.L(2) I3=count(2) O=x1.L_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt LUT4 I0=x0.shift I1=x0.clrn I2=x1.phase0 I3=x1.B0_ff_CQZ_D_LUT4_O_I2 O=x1.L_ff_CQZ_QEN
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 10001111
.subckt ff CQZ=x1.lambda0(4) D=x1.lambda0_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.lambda0(3) D=x1.lambda0_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x1.lambda0_ff_CQZ_1_D_LUT4_O_I0 I1=x1.phase12 I2=x1.lambda11(3) I3=x1.enable O=x1.lambda0_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1110000100000000
.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 O=x1.lambda0_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt ff CQZ=x1.lambda0(2) D=x1.lambda0_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x1.lambda0_ff_CQZ_2_D_LUT4_O_I0 I1=x1.phase12 I2=x1.lambda11(2) I3=x1.enable O=x1.lambda0_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1110000100000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x1.lambda0_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01111000
.subckt ff CQZ=x1.lambda0(1) D=x1.lambda0_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0 I1=x1.phase12 I2=x1.lambda11(1) I3=x1.enable O=x1.lambda0_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1110000100000000
.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 10000111
.subckt LUT4 I0=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1110100000110000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I2 O=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=D0(1) I3=s0(1) O=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.B10(1) I3=x1.lambda0(1) O=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt ff CQZ=x1.lambda0(0) D=x1.lambda0_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x1.phase12 I1=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1 I2=x1.lambda11(0) I3=x1.enable O=x1.lambda0_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011010011111111
.subckt LUT4 I0=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1 I1=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I1 I2=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I2 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I3 O=x1.D_ff_CQZ_4_D_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt LUT4 I0=s5(0) I1=x1.lambda7(0) I2=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0111100010000111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda8(0) I3=s4(0) O=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=s6(0) I1=x1.lambda6(0) I2=s7(0) I3=x1.lambda5(0) O=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=s1(0) I1=x1.lambda11(0) I2=s2(0) I3=x1.lambda10(0) O=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda9(0) I3=s3(0) O=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I3_I2 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1 O=x1.lambda0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I3_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.B10(0) I3=x1.lambda0(0) O=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=D0(0) I3=s0(0) O=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0 I1=x1.phase12 I2=x1.lambda11(4) I3=x1.enable O=x1.lambda0_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1110000100000000
.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3 I1=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2 I2=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0100000110110010
.subckt LUT4 I0=s6(1) I1=s6(2) I2=x1.lambda6(1) I3=x1.lambda6(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000000000000000
.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=x1.lambda6(0) I3=s6(4) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 10000111
.subckt LUT4 I0=s6(0) I1=x1.lambda6(4) I2=s6(3) I3=x1.lambda6(1) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=s6(1) I1=x1.lambda6(3) I2=s6(2) I3=x1.lambda6(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt LUT4 I0=s5(0) I1=x1.lambda7(4) I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101111000
.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=x1.lambda7(1) I2=x1.lambda7(2) I3=s5(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0111100000000000
.subckt LUT4 I0=s5(3) I1=x1.lambda7(1) I2=s5(4) I3=x1.lambda7(0) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=x1.lambda7(2) I2=x1.lambda7(3) I3=s5(1) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011010000000000
.subckt LUT4 I0=s5(2) I1=x1.lambda7(1) I2=s5(3) I3=x1.lambda7(0) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=s5(0) I3=x1.lambda7(3) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
.param INIT 0010101110111011
.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I1=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0100110110110010
.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=x1.lambda10(2) I2=x1.lambda10(3) I3=s2(1) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011010000000000
.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt LUT4 I0=s1(0) I1=x1.lambda11(4) I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=x1.lambda11(0) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011110001000
.subckt LUT4 I0=s1(1) I1=s1(3) I2=x1.lambda11(2) I3=s1(4) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
.param INIT 1000000001111111
.subckt LUT4 I0=s1(1) I1=x1.lambda11(3) I2=s1(3) I3=x1.lambda11(1) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=s2(3) I1=x1.lambda10(1) I2=s2(4) I3=x1.lambda10(0) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=s2(0) I1=x1.lambda10(4) I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2 I3=s2(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011110001000
.subckt LUT4 I0=s2(3) I1=x1.lambda10(0) I2=x1.lambda10(1) I3=x1.lambda10(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
.param INIT 1000000001111111
.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000111001110001
.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I1=x1.lambda9(0) I2=x1.lambda9(1) I3=s3(3) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0111100000000000
.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=x1.lambda9(2) I3=s3(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 10000111
.subckt LUT4 I0=s3(1) I1=x1.lambda9(3) I2=s3(4) I3=x1.lambda9(0) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=s4(1) I3=x1.lambda8(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
.param INIT 0010101110111011
.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=x1.lambda8(1) I3=s4(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01111000
.subckt LUT4 I0=x0.shift I1=x1.lambda8(2) I2=s4(2) I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 10000000
.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=s4(3) I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0100101110110100
.subckt LUT4 I0=s4(0) I1=x1.lambda8(0) I2=x1.lambda8(3) I3=x1.lambda8(1) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
.param INIT 1000000001111111
.subckt LUT4 I0=s4(0) I1=x1.lambda8(4) I2=s4(4) I3=x1.lambda8(0) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda8(3) I3=s4(1) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=x1.lambda8(1) I2=x1.lambda8(2) I3=s4(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011010000000000
.subckt LUT4 I0=s4(0) I1=x1.lambda8(3) I2=s4(3) I3=x1.lambda8(0) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0100110110110010
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0100101110110100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 10000111
.subckt LUT4 I0=s0(3) I1=D0(3) I2=x1.phase0 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I2 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.B10(3) I3=x1.lambda0(3) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I3 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 01000000
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.B10(2) I3=x1.lambda0(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I3_I2 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I2 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 10000111
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=D0(2) I3=s0(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110100110010110
.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I1=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011010000000000
.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011010001001011
.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 10000111
.subckt LUT4 I0=s0(4) I1=D0(4) I2=x1.phase0 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I2 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=s0(3) I1=D0(3) I2=x1.phase0 I3=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x1.lambda0(4) I1=x1.B10(4) I2=x1.phase0 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x1.lambda10(4) D=x1.lambda10_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.lambda10(3) D=x1.lambda10_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda9(3) I3=x1.enable O=x1.lambda10_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda10(2) D=x1.lambda10_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda9(2) I3=x1.enable O=x1.lambda10_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda10(1) D=x1.lambda10_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda9(1) I3=x1.enable O=x1.lambda10_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda10(0) D=x1.lambda10_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda9(0) I3=x1.enable O=x1.lambda10_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda9(4) I3=x1.enable O=x1.lambda10_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda11(4) D=x1.lambda11_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.lambda11(3) D=x1.lambda11_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda10(3) I3=x1.enable O=x1.lambda11_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda11(2) D=x1.lambda11_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda10(2) I3=x1.enable O=x1.lambda11_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda11(1) D=x1.lambda11_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda10(1) I3=x1.enable O=x1.lambda11_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda11(0) D=x1.lambda11_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda10(0) I3=x1.enable O=x1.lambda11_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda10(4) I3=x1.enable O=x1.lambda11_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda1(4) D=x1.lambda1_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.lambda1(3) D=x1.lambda1_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0(3) I3=x1.enable O=x1.lambda1_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda1(2) D=x1.lambda1_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0(2) I3=x1.enable O=x1.lambda1_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda1(1) D=x1.lambda1_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0(1) I3=x1.enable O=x1.lambda1_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda1(0) D=x1.lambda1_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0(0) I3=x1.enable O=x1.lambda1_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0(4) I3=x1.enable O=x1.lambda1_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda2(4) D=x1.lambda2_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.lambda2(3) D=x1.lambda2_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda1(3) I3=x1.enable O=x1.lambda2_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda2(2) D=x1.lambda2_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda1(2) I3=x1.enable O=x1.lambda2_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda2(1) D=x1.lambda2_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda1(1) I3=x1.enable O=x1.lambda2_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda2(0) D=x1.lambda2_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda1(0) I3=x1.enable O=x1.lambda2_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda1(4) I3=x1.enable O=x1.lambda2_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda3(4) D=x1.lambda3_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.lambda3(3) D=x1.lambda3_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda2(3) I3=x1.enable O=x1.lambda3_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda3(2) D=x1.lambda3_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda2(2) I3=x1.enable O=x1.lambda3_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda3(1) D=x1.lambda3_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda2(1) I3=x1.enable O=x1.lambda3_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda3(0) D=x1.lambda3_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda2(0) I3=x1.enable O=x1.lambda3_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda2(4) I3=x1.enable O=x1.lambda3_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda4(4) D=x1.lambda4_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.lambda4(3) D=x1.lambda4_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda3(3) I3=x1.enable O=x1.lambda4_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda4(2) D=x1.lambda4_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda3(2) I3=x1.enable O=x1.lambda4_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda4(1) D=x1.lambda4_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda3(1) I3=x1.enable O=x1.lambda4_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda4(0) D=x1.lambda4_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda3(0) I3=x1.enable O=x1.lambda4_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda3(4) I3=x1.enable O=x1.lambda4_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda5(4) D=x1.lambda5_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.lambda5(3) D=x1.lambda5_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda4(3) I3=x1.enable O=x1.lambda5_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda5(2) D=x1.lambda5_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda4(2) I3=x1.enable O=x1.lambda5_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda5(1) D=x1.lambda5_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda4(1) I3=x1.enable O=x1.lambda5_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda5(0) D=x1.lambda5_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda4(0) I3=x1.enable O=x1.lambda5_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda4(4) I3=x1.enable O=x1.lambda5_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda6(4) D=x1.lambda6_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.lambda6(3) D=x1.lambda6_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda5(3) I3=x1.enable O=x1.lambda6_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda6(2) D=x1.lambda6_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda5(2) I3=x1.enable O=x1.lambda6_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda6(1) D=x1.lambda6_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda5(1) I3=x1.enable O=x1.lambda6_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda6(0) D=x1.lambda6_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda5(0) I3=x1.enable O=x1.lambda6_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda5(4) I3=x1.enable O=x1.lambda6_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda7(4) D=x1.lambda7_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.lambda7(3) D=x1.lambda7_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda6(3) I3=x1.enable O=x1.lambda7_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda7(2) D=x1.lambda7_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda6(2) I3=x1.enable O=x1.lambda7_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda7(1) D=x1.lambda7_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda6(1) I3=x1.enable O=x1.lambda7_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda7(0) D=x1.lambda7_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda6(0) I3=x1.enable O=x1.lambda7_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda6(4) I3=x1.enable O=x1.lambda7_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda8(4) D=x1.lambda8_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.lambda8(3) D=x1.lambda8_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda7(3) I3=x1.enable O=x1.lambda8_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda8(2) D=x1.lambda8_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda7(2) I3=x1.enable O=x1.lambda8_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda8(1) D=x1.lambda8_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda7(1) I3=x1.enable O=x1.lambda8_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda8(0) D=x1.lambda8_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda7(0) I3=x1.enable O=x1.lambda8_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda7(4) I3=x1.enable O=x1.lambda8_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda9(4) D=x1.lambda9_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.lambda9(3) D=x1.lambda9_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda8(3) I3=x1.enable O=x1.lambda9_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda9(2) D=x1.lambda9_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda8(2) I3=x1.enable O=x1.lambda9_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda9(1) D=x1.lambda9_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda8(1) I3=x1.enable O=x1.lambda9_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.lambda9(0) D=x1.lambda9_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda8(0) I3=x1.enable O=x1.lambda9_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda8(4) I3=x1.enable O=x1.lambda9_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega0(4) D=x1.omega0_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.omega0(3) D=x1.omega0_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x1.omega0_ff_CQZ_1_D_LUT4_O_I0 I1=x1.phase12 I2=x1.omega11(3) I3=x1.enable O=x1.omega0_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1110000100000000
.subckt LUT4 I0=x1.lambda0_ff_CQZ_1_D_LUT4_O_I0 I1=x1.omega0_ff_CQZ_1_D_LUT4_O_I0 I2=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I2 I3=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I2 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I1 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0 O=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=s6(3) I1=x1.lambda6(0) I2=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2 I3=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3 O=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101111000
.subckt LUT4 I0=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2 I1=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3 I2=s6(3) I3=x1.lambda6(0) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
.param INIT 0010101110111011
.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I2=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2 I3=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3 O=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=s6(1) I1=x1.lambda6(2) I2=s6(2) I3=x1.lambda6(1) O=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda6(3) I3=s6(0) O=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010000
.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 O=x1.omega0_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt ff CQZ=x1.omega0(2) D=x1.omega0_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x1.omega0_ff_CQZ_2_D_LUT4_O_I0 I1=x1.phase12 I2=x1.omega11(2) I3=x1.enable O=x1.omega0_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1110000100000000
.subckt LUT4 I0=x1.omega0_ff_CQZ_4_D_LUT4_O_I1 I1=x1.omega0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1 I2=x1.omega0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3_LUT4_I3_O O=x1.omega0_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011010001001011
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=x1.omega0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x1.lambda2(2) I1=x1.A10(2) I2=x1.phase0 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x1.omega0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x1.omega0(1) D=x1.omega0_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x1.omega0_ff_CQZ_3_D_LUT4_O_I0 I1=x1.phase12 I2=x1.omega11(1) I3=x1.enable O=x1.omega0_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1110000100000000
.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x1.omega0_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 10000111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3 O=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3 O=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3_LUT4_I3_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=D0(2) I3=s10(2) O=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01010011
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=D0(1) I3=s10(1) O=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.A10(0) I3=x1.lambda2(0) O=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.A10(1) I3=x1.lambda2(1) O=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=D0(0) I3=s10(0) O=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt ff CQZ=x1.omega0(0) D=x1.omega0_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x1.phase12 I1=x1.omega0_ff_CQZ_4_D_LUT4_O_I1 I2=x1.omega11(0) I3=x1.enable O=x1.omega0_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011010011111111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x1.omega0_ff_CQZ_4_D_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x1.phase12 I1=x1.omega0_ff_CQZ_D_LUT4_O_I1 I2=x1.omega11(4) I3=x1.enable O=x1.omega0_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011010000000000
.subckt LUT4 I0=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0 I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I1 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I2 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1101010000101011
.subckt LUT4 I0=s8(0) I1=x1.lambda4(3) I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I2 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101111000
.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I1 I2=x1.lambda4(2) I3=s8(1) O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01111000
.subckt LUT4 I0=s8(2) I1=x1.lambda4(1) I2=s8(3) I3=x1.lambda4(0) O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=s8(1) I1=s8(2) I2=x1.lambda4(0) I3=x1.lambda4(1) O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000000000000000
.subckt LUT4 I0=x0.shift I1=x1.lambda4(2) I2=s8(0) I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 01000000
.subckt LUT4 I0=s8(1) I1=x1.lambda4(1) I2=s8(2) I3=x1.lambda4(0) O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
.param INIT 1000011101110111
.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I1 I2=x1.lambda4(2) I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010000
.subckt LUT4 I0=s8(0) I1=s8(1) I2=x1.lambda4(0) I3=x1.lambda4(1) O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000000000000000
.subckt LUT4 I0=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1101010000101011
.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt LUT4 I0=x1.lambda2(3) I1=x1.A10(3) I2=x1.phase0 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=s10(3) I1=D0(3) I2=x1.phase0 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x1.lambda2(2) I1=x1.A10(2) I2=x1.phase0 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3_LUT4_I3_O I3=x1.omega0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01100000
.subckt LUT4 I0=x1.omega0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I1=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3_LUT4_I3_O I2=x1.omega0_ff_CQZ_4_D_LUT4_O_I1 I3=x1.omega0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001000000000000
.subckt LUT4 I0=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01110001
.subckt LUT4 I0=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3_LUT4_I3_O O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=s10(3) I1=D0(3) I2=x1.phase0 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x1.lambda2(2) I1=x1.A10(2) I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3 I3=x1.phase0 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 0000101000001100
.subckt LUT4 I0=s10(4) I1=D0(4) I2=x1.phase0 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x1.lambda2(3) I1=x1.A10(3) I2=x1.phase0 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01100000
.subckt LUT4 I0=x1.lambda2(4) I1=x1.A10(4) I2=x1.phase0 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x1.omega10(4) D=x1.omega10_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.omega10(3) D=x1.omega10_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega9(3) I3=x1.enable O=x1.omega10_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega10(2) D=x1.omega10_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega9(2) I3=x1.enable O=x1.omega10_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega10(1) D=x1.omega10_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega9(1) I3=x1.enable O=x1.omega10_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega10(0) D=x1.omega10_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega9(0) I3=x1.enable O=x1.omega10_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega9(4) I3=x1.enable O=x1.omega10_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega11(4) D=x1.omega11_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.omega11(3) D=x1.omega11_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega10(3) I3=x1.enable O=x1.omega11_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega11(2) D=x1.omega11_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega10(2) I3=x1.enable O=x1.omega11_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega11(1) D=x1.omega11_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega10(1) I3=x1.enable O=x1.omega11_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega11(0) D=x1.omega11_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega10(0) I3=x1.enable O=x1.omega11_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega10(4) I3=x1.enable O=x1.omega11_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega1(4) D=x1.omega1_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.omega1(3) D=x1.omega1_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0(3) I3=x1.enable O=x1.omega1_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega1(2) D=x1.omega1_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0(2) I3=x1.enable O=x1.omega1_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega1(1) D=x1.omega1_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0(1) I3=x1.enable O=x1.omega1_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega1(0) D=x1.omega1_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0(0) I3=x1.enable O=x1.omega1_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0(4) I3=x1.enable O=x1.omega1_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega2(4) D=x1.omega2_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.omega2(3) D=x1.omega2_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega1(3) I3=x1.enable O=x1.omega2_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega2(2) D=x1.omega2_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega1(2) I3=x1.enable O=x1.omega2_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega2(1) D=x1.omega2_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega1(1) I3=x1.enable O=x1.omega2_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega2(0) D=x1.omega2_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega1(0) I3=x1.enable O=x1.omega2_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega1(4) I3=x1.enable O=x1.omega2_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega3(4) D=x1.omega3_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.omega3(3) D=x1.omega3_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega2(3) I3=x1.enable O=x1.omega3_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega3(2) D=x1.omega3_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega2(2) I3=x1.enable O=x1.omega3_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega3(1) D=x1.omega3_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega2(1) I3=x1.enable O=x1.omega3_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega3(0) D=x1.omega3_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega2(0) I3=x1.enable O=x1.omega3_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega2(4) I3=x1.enable O=x1.omega3_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega4(4) D=x1.omega4_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.omega4(3) D=x1.omega4_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega3(3) I3=x1.enable O=x1.omega4_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega4(2) D=x1.omega4_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega3(2) I3=x1.enable O=x1.omega4_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega4(1) D=x1.omega4_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega3(1) I3=x1.enable O=x1.omega4_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega4(0) D=x1.omega4_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega3(0) I3=x1.enable O=x1.omega4_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega3(4) I3=x1.enable O=x1.omega4_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega5(4) D=x1.omega5_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.omega5(3) D=x1.omega5_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega4(3) I3=x1.enable O=x1.omega5_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega5(2) D=x1.omega5_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega4(2) I3=x1.enable O=x1.omega5_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega5(1) D=x1.omega5_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega4(1) I3=x1.enable O=x1.omega5_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega5(0) D=x1.omega5_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega4(0) I3=x1.enable O=x1.omega5_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega4(4) I3=x1.enable O=x1.omega5_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega6(4) D=x1.omega6_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.omega6(3) D=x1.omega6_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega5(3) I3=x1.enable O=x1.omega6_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega6(2) D=x1.omega6_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega5(2) I3=x1.enable O=x1.omega6_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega6(1) D=x1.omega6_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega5(1) I3=x1.enable O=x1.omega6_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega6(0) D=x1.omega6_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega5(0) I3=x1.enable O=x1.omega6_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega5(4) I3=x1.enable O=x1.omega6_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega7(4) D=x1.omega7_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.omega7(3) D=x1.omega7_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega6(3) I3=x1.enable O=x1.omega7_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega7(2) D=x1.omega7_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega6(2) I3=x1.enable O=x1.omega7_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega7(1) D=x1.omega7_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega6(1) I3=x1.enable O=x1.omega7_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega7(0) D=x1.omega7_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega6(0) I3=x1.enable O=x1.omega7_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega6(4) I3=x1.enable O=x1.omega7_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega8(4) D=x1.omega8_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.omega8(3) D=x1.omega8_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega7(3) I3=x1.enable O=x1.omega8_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega8(2) D=x1.omega8_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega7(2) I3=x1.enable O=x1.omega8_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega8(1) D=x1.omega8_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega7(1) I3=x1.enable O=x1.omega8_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega8(0) D=x1.omega8_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega7(0) I3=x1.enable O=x1.omega8_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega7(4) I3=x1.enable O=x1.omega8_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega9(4) D=x1.omega9_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x1.omega9(3) D=x1.omega9_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega8(3) I3=x1.enable O=x1.omega9_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega9(2) D=x1.omega9_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega8(2) I3=x1.enable O=x1.omega9_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega9(1) D=x1.omega9_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega8(1) I3=x1.enable O=x1.omega9_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt ff CQZ=x1.omega9(0) D=x1.omega9_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega8(0) I3=x1.enable O=x1.omega9_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega8(4) I3=x1.enable O=x1.omega9_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.enable I3=x1.phase0 O=x1.phase0_LUT4_I3_O
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0111
.subckt ff CQZ=x1.phase0 D=phase_LUT4_I1_O(0) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.clrn I2=x1.enable I3=x1.phase12 O=phase_LUT4_I1_O(0)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10111111
.subckt ff CQZ=x1.phase12 D=phase_LUT4_I1_O(12) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.a0(4) D=x2.a0_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.a0(3) D=x2.a0_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a0(3) I1=alpha(3) I2=x2.shorten I3=x0.clrn O=x2.a0_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.a0(2) D=x2.a0_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a0(2) I1=alpha(2) I2=x2.shorten I3=x0.clrn O=x2.a0_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.a0(1) D=x2.a0_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a0(1) I1=alpha(1) I2=x2.shorten I3=x0.clrn O=x2.a0_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.a0(0) D=x2.a0_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a0(0) I1=alpha(0) I2=x2.shorten I3=x0.clrn O=x2.a0_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110011111111
.subckt LUT4 I0=x2.a0(4) I1=alpha(4) I2=x2.shorten I3=x0.clrn O=x2.a0_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.a10(4) D=x2.a10_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.a10(3) D=x2.a10_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a10_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a9(3) I2=x2.shorten I3=x0.clrn O=x2.a10_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a10_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a10_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 O=x2.a10_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001
.subckt ff CQZ=x2.a10(2) D=x2.a10_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a10_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a9(2) I2=x2.shorten I3=x0.clrn O=x2.a10_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a10_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a10_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a10_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a10_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=x2.a10_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a10_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt ff CQZ=x2.a10(1) D=x2.a10_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a10_ff_CQZ_3_D_LUT4_O_I0 I1=x2.a9(1) I2=x2.shorten I3=x0.clrn O=x2.a10_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a10(1) I1=x2.l10(1) I2=x2.shorten I3=x2.a10_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a10_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l10(2) I3=x2.a10(2) O=x2.a10_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt ff CQZ=x2.a10(0) D=x2.a10_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a10_ff_CQZ_4_D_LUT4_O_I0 I1=x2.a9(0) I2=x2.shorten I3=x0.clrn O=x2.a10_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110011111111
.subckt LUT4 I0=x2.a10(0) I1=x2.l10(0) I2=x2.shorten I3=x2.a10_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a10_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110001010011
.subckt LUT4 I0=x2.a10(1) I1=x2.l10(1) I2=x2.shorten I3=x2.a10_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 O=x2.a10_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110001010011
.subckt LUT4 I0=x2.a10_ff_CQZ_D_LUT4_O_I0 I1=x2.a9(4) I2=x2.shorten I3=x0.clrn O=x2.a10_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a10_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a10_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a10_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l10(4) I3=x2.a10(4) O=x2.a10_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x2.a10(0) I1=x2.l10(0) I2=x2.shorten I3=x2.a10_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x2.a10_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l10(3) I3=x2.a10(3) O=x2.a10_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt ff CQZ=alpha(4) D=x2.a11_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=alpha(3) D=x2.a11_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a11_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a10(3) I2=x2.shorten I3=x0.clrn O=x2.a11_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a11_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a11_ff_CQZ_D_LUT4_O_I0 O=x2.a11_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l11(1) I3=alpha(1) O=x2.a11_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt ff CQZ=alpha(2) D=x2.a11_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a11_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a10(2) I2=x2.shorten I3=x0.clrn O=x2.a11_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I2=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 I3=x2.a11_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a11_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt ff CQZ=alpha(1) D=x2.a11_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a11_ff_CQZ_3_D_LUT4_O_I0 I1=x2.a10(1) I2=x2.shorten I3=x0.clrn O=x2.a11_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a11_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a11_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt LUT4 I0=alpha(0) I1=x2.l11(0) I2=x2.shorten I3=x2.a11_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 O=x2.a11_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt ff CQZ=alpha(0) D=x2.a11_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a11_ff_CQZ_4_D_LUT4_O_I0 I1=x2.a10(0) I2=x2.shorten I3=x0.clrn O=x2.a11_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110011111111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a11_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a11_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt LUT4 I0=alpha(0) I1=x2.l11(0) I2=x2.shorten I3=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x2.a11_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt LUT4 I0=x2.a11_ff_CQZ_D_LUT4_O_I0 I1=x2.a10(4) I2=x2.shorten I3=x0.clrn O=x2.a11_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a11_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l11(4) I3=alpha(4) O=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=alpha(2) I1=x2.l11(2) I2=x2.shorten I3=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l11(3) I3=alpha(3) O=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt ff CQZ=x2.a1(4) D=x2.a1_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.a1(3) D=x2.a1_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a1(2) I1=x2.a0(3) I2=x2.shorten I3=x0.clrn O=x2.a1_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.a1(2) D=x2.a1_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a1_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a0(2) I2=x2.shorten I3=x0.clrn O=x2.a1_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a1(1) I1=x2.l1(1) I2=x2.shorten I3=x2.l1_ff_CQZ_4_D_LUT4_O_I0 O=x2.a1_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt ff CQZ=x2.a1(1) D=x2.a1_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a1(0) I1=x2.a0(1) I2=x2.shorten I3=x0.clrn O=x2.a1_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.a1(0) D=x2.a1_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a1(4) I1=x2.a0(0) I2=x2.shorten I3=x0.clrn O=x2.a1_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110011111111
.subckt LUT4 I0=x2.a1(3) I1=x2.a0(4) I2=x2.shorten I3=x0.clrn O=x2.a1_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.a2(4) D=x2.a2_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.a2(3) D=x2.a2_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a2_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a1(3) I2=x2.shorten I3=x0.clrn O=x2.a2_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a2(1) I1=x2.l2(1) I2=x2.shorten I3=x2.l2_ff_CQZ_3_D_LUT4_O_I0 O=x2.a2_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt ff CQZ=x2.a2(2) D=x2.a2_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a2_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a1(2) I2=x2.shorten I3=x0.clrn O=x2.a2_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a2(0) I1=x2.l2(0) I2=x2.shorten I3=x2.l2_ff_CQZ_4_D_LUT4_O_I0 O=x2.a2_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt ff CQZ=x2.a2(1) D=x2.a2_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a2(4) I1=x2.a1(1) I2=x2.shorten I3=x0.clrn O=x2.a2_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.a2(0) D=x2.a2_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a2(3) I1=x2.a1(0) I2=x2.shorten I3=x0.clrn O=x2.a2_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110011111111
.subckt LUT4 I0=x2.a2(2) I1=x2.a1(4) I2=x2.shorten I3=x0.clrn O=x2.a2_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.a3(4) D=x2.a3_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.a3(3) D=x2.a3_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a3_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a2(3) I2=x2.shorten I3=x0.clrn O=x2.a3_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a3(0) I1=x2.l3(0) I2=x2.shorten I3=x2.l3_ff_CQZ_3_D_LUT4_O_I0 O=x2.a3_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt ff CQZ=x2.a3(2) D=x2.a3_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a3_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a2(2) I2=x2.shorten I3=x0.clrn O=x2.a3_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a3_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 I3=x2.l3_ff_CQZ_4_D_LUT4_O_I0 O=x2.a3_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt ff CQZ=x2.a3(1) D=x2.a3_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a3(3) I1=x2.a2(1) I2=x2.shorten I3=x0.clrn O=x2.a3_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.a3(0) D=x2.a3_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a3(2) I1=x2.a2(0) I2=x2.shorten I3=x0.clrn O=x2.a3_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110011111111
.subckt LUT4 I0=x2.a3_ff_CQZ_D_LUT4_O_I0 I1=x2.a2(4) I2=x2.shorten I3=x0.clrn O=x2.a3_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a3(1) I1=x2.l3(1) I2=x2.shorten I3=x2.a3_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a3_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l3(4) I3=x2.a3(4) O=x2.a3_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt ff CQZ=x2.a4(4) D=x2.a4_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.a4(3) D=x2.a4_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a4_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a3(3) I2=x2.shorten I3=x0.clrn O=x2.a4_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.l4_ff_CQZ_3_D_LUT4_O_I0 I3=x2.a4_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a4_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt ff CQZ=x2.a4(2) D=x2.a4_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a4_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a3(2) I2=x2.shorten I3=x0.clrn O=x2.a4_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a4_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 I3=x2.a4_ff_CQZ_4_D_LUT4_O_I0 O=x2.a4_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt ff CQZ=x2.a4(1) D=x2.a4_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a4(2) I1=x2.a3(1) I2=x2.shorten I3=x0.clrn O=x2.a4_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.a4(0) D=x2.a4_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a4_ff_CQZ_4_D_LUT4_O_I0 I1=x2.a3(0) I2=x2.shorten I3=x0.clrn O=x2.a4_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110011111111
.subckt LUT4 I0=x2.a4(1) I1=x2.l4(1) I2=x2.shorten I3=x2.a4_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a4_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l4(4) I3=x2.a4(4) O=x2.a4_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x2.a4_ff_CQZ_D_LUT4_O_I0 I1=x2.a3(4) I2=x2.shorten I3=x0.clrn O=x2.a4_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a4(0) I1=x2.l4(0) I2=x2.shorten I3=x2.a4_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a4_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l4(3) I3=x2.a4(3) O=x2.a4_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt ff CQZ=x2.a5(4) D=x2.a5_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.a5(3) D=x2.a5_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a5_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a4(3) I2=x2.shorten I3=x0.clrn O=x2.a5_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a5_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 I3=x2.a5_ff_CQZ_3_D_LUT4_O_I0 O=x2.a5_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt ff CQZ=x2.a5(2) D=x2.a5_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a5_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a4(2) I2=x2.shorten I3=x0.clrn O=x2.a5_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a5(2) I1=x2.l5(2) I2=x2.shorten I3=x2.a5_ff_CQZ_4_D_LUT4_O_I0 O=x2.a5_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt ff CQZ=x2.a5(1) D=x2.a5_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a5_ff_CQZ_3_D_LUT4_O_I0 I1=x2.a4(1) I2=x2.shorten I3=x0.clrn O=x2.a5_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a5(1) I1=x2.l5(1) I2=x2.shorten I3=x2.a5_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a5_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt ff CQZ=x2.a5(0) D=x2.a5_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a5_ff_CQZ_4_D_LUT4_O_I0 I1=x2.a4(0) I2=x2.shorten I3=x0.clrn O=x2.a5_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110011111111
.subckt LUT4 I0=x2.a5(0) I1=x2.l5(0) I2=x2.shorten I3=x2.a5_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a5_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l5(3) I3=x2.a5(3) O=x2.a5_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x2.a5_ff_CQZ_D_LUT4_O_I0 I1=x2.a4(4) I2=x2.shorten I3=x0.clrn O=x2.a5_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a5(2) I1=x2.l5(2) I2=x2.shorten I3=x2.a5_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a5_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l5(4) I3=x2.a5(4) O=x2.a5_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt ff CQZ=x2.a6(4) D=x2.a6_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.a6(3) D=x2.a6_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a6_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a5(3) I2=x2.shorten I3=x0.clrn O=x2.a6_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a6_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 I3=x2.a6_ff_CQZ_3_D_LUT4_O_I0 O=x2.a6_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt ff CQZ=x2.a6(2) D=x2.a6_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a6_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a5(2) I2=x2.shorten I3=x0.clrn O=x2.a6_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a6(1) I1=x2.l6(1) I2=x2.shorten I3=x2.a6_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a6_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt ff CQZ=x2.a6(1) D=x2.a6_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a6_ff_CQZ_3_D_LUT4_O_I0 I1=x2.a5(1) I2=x2.shorten I3=x0.clrn O=x2.a6_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a6(0) I1=x2.l6(0) I2=x2.shorten I3=x2.a6_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a6_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l6(3) I3=x2.a6(3) O=x2.a6_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt ff CQZ=x2.a6(0) D=x2.a6_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a6_ff_CQZ_4_D_LUT4_O_I0 I1=x2.a5(0) I2=x2.shorten I3=x0.clrn O=x2.a6_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110011111111
.subckt LUT4 I0=x2.a6(4) I1=x2.l6(4) I2=x2.shorten I3=x2.a6_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a6_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l6(2) I3=x2.a6(2) O=x2.a6_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x2.a6_ff_CQZ_D_LUT4_O_I0 I1=x2.a5(4) I2=x2.shorten I3=x0.clrn O=x2.a6_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a6(4) I1=x2.l6(4) I2=x2.shorten I3=x2.a6_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a6_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt LUT4 I0=x2.a6(1) I1=x2.l6(1) I2=x2.shorten I3=x2.a6_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a6_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt ff CQZ=x2.a7(4) D=x2.a7_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.a7(3) D=x2.a7_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a7_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a6(3) I2=x2.shorten I3=x0.clrn O=x2.a7_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a7_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I2 O=x2.a7_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt ff CQZ=x2.a7(2) D=x2.a7_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a7_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a6(2) I2=x2.shorten I3=x0.clrn O=x2.a7_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 I3=x2.a7_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x2.a7_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt LUT4 I0=x2.a7(0) I1=x2.l7(0) I2=x2.shorten I3=x2.a7_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I2 O=x2.a7_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt ff CQZ=x2.a7(1) D=x2.a7_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a7_ff_CQZ_3_D_LUT4_O_I0 I1=x2.a6(1) I2=x2.shorten I3=x0.clrn O=x2.a7_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a7_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l7(2) I3=x2.a7(2) O=x2.a7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l7(4) I3=x2.a7(4) O=x2.a7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt ff CQZ=x2.a7(0) D=x2.a7_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a7_ff_CQZ_4_D_LUT4_O_I0 I1=x2.a6(0) I2=x2.shorten I3=x0.clrn O=x2.a7_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110011111111
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a7_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a7_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a7_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l7(1) I3=x2.a7(1) O=x2.a7_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x2.a7(3) I1=x2.l7(3) I2=x2.shorten I3=x2.a7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a7_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt LUT4 I0=x2.a7_ff_CQZ_D_LUT4_O_I0 I1=x2.a6(4) I2=x2.shorten I3=x0.clrn O=x2.a7_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a7(3) I1=x2.l7(3) I2=x2.shorten I3=x2.a7_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a7_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt LUT4 I0=x2.a7(0) I1=x2.l7(0) I2=x2.shorten I3=x2.a7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 O=x2.a7_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt ff CQZ=x2.a8(4) D=x2.a8_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.a8(3) D=x2.a8_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a8_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a7(3) I2=x2.shorten I3=x0.clrn O=x2.a8_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a8(0) I1=x2.l8(0) I2=x2.shorten I3=x2.a8_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a8_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110001010011
.subckt ff CQZ=x2.a8(2) D=x2.a8_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a8_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a7(2) I2=x2.shorten I3=x0.clrn O=x2.a8_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a8(4) I1=x2.l8(4) I2=x2.shorten I3=x2.a8_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a8_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt ff CQZ=x2.a8(1) D=x2.a8_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a8_ff_CQZ_3_D_LUT4_O_I0 I1=x2.a7(1) I2=x2.shorten I3=x0.clrn O=x2.a8_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a8_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a8_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a8_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l8(3) I3=x2.a8(3) O=x2.a8_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x2.a8(4) I1=x2.l8(4) I2=x2.shorten I3=x2.a8_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a8_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110001010011
.subckt ff CQZ=x2.a8(0) D=x2.a8_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a8_ff_CQZ_4_D_LUT4_O_I0 I1=x2.a7(0) I2=x2.shorten I3=x0.clrn O=x2.a8_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110011111111
.subckt LUT4 I0=x2.a8(2) I1=x2.l8(2) I2=x2.shorten I3=x2.a8_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a8_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt LUT4 I0=x2.a8(0) I1=x2.l8(0) I2=x2.shorten I3=x2.a8_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 O=x2.a8_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt LUT4 I0=x2.a8_ff_CQZ_D_LUT4_O_I0 I1=x2.a7(4) I2=x2.shorten I3=x0.clrn O=x2.a8_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a8(2) I1=x2.l8(2) I2=x2.shorten I3=x2.a8_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a8_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l8(1) I3=x2.a8(1) O=x2.a8_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt ff CQZ=x2.a9(4) D=x2.a9_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.a9(3) D=x2.a9_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a9_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a8(3) I2=x2.shorten I3=x0.clrn O=x2.a9_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a9_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a9_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x2.a9_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l9(0) I3=x2.a9(0) O=x2.a9_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt ff CQZ=x2.a9(2) D=x2.a9_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a9_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a8(2) I2=x2.shorten I3=x0.clrn O=x2.a9_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a9_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 I3=x2.a9_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x2.a9_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001
.subckt LUT4 I0=x2.a9(3) I1=x2.l9(3) I2=x2.shorten I3=x2.a9_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 O=x2.a9_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110001010011
.subckt ff CQZ=x2.a9(1) D=x2.a9_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a9_ff_CQZ_3_D_LUT4_O_I0 I1=x2.a8(1) I2=x2.shorten I3=x0.clrn O=x2.a9_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a9_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 I3=x2.a9_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a9_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt LUT4 I0=x2.a9(3) I1=x2.l9(3) I2=x2.shorten I3=x2.a9_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 O=x2.a9_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt ff CQZ=x2.a9(0) D=x2.a9_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a9_ff_CQZ_4_D_LUT4_O_I0 I1=x2.a8(0) I2=x2.shorten I3=x0.clrn O=x2.a9_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110011111111
.subckt LUT4 I0=x2.a9(1) I1=x2.l9(1) I2=x2.shorten I3=x2.a9_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a9_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l9(2) I3=x2.a9(2) O=x2.a9_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x2.a9_ff_CQZ_D_LUT4_O_I0 I1=x2.a8(4) I2=x2.shorten I3=x0.clrn O=x2.a9_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a9_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a9_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a9_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l9(4) I3=x2.a9(4) O=x2.a9_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x2.a9(1) I1=x2.l9(1) I2=x2.shorten I3=x2.a9_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 O=x2.a9_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101001110101100
.subckt ff CQZ=x2.l0(4) D=x2.l0_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.l0(3) D=x2.l0_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.l0_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l0_ff_CQZ_1_D_LUT4_O_I1 I2=x2.search I3=x0.clrn O=x2.l0_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100101000000000
.subckt LUT4 I0=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0 I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1 I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 I3=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x2.l0_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011001101001
.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2 I2=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I3 I3=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1 O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01100000
.subckt LUT4 I0=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2 I1=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I3 I2=x2.l0_ff_CQZ_4_D_LUT4_O_I1 I3=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1 O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001000000000000
.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1011010001001011
.subckt LUT4 I0=s11(2) I1=x1.phase0 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111100000000000
.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I1=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=alpha(3) I3=x2.load O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
.param INIT 00001101
.subckt LUT4 I0=x0.shift I1=x0.shift I2=s11(3) I3=x1.phase0 O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I0 O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 11100000
.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I1=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.lambda11(3) I3=x1.lambda1(3) O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.a0(3) I3=x2.l0(3) O=x2.l0_ff_CQZ_1_D_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 11001010
.subckt ff CQZ=x2.l0(2) D=x2.l0_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.search I1=x1.D_ff_CQZ_2_D_LUT4_O_I1 I2=x2.l0_ff_CQZ_2_D_LUT4_O_I2 I3=x0.clrn O=x2.l0_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111000100000000
.subckt LUT4 I0=x2.a0(2) I1=x2.l0(2) I2=x2.shorten I3=x2.search O=x2.l0_ff_CQZ_2_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l0(1) D=x2.l0_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l0_ff_CQZ_3_D_LUT4_O_I1 I2=x2.search I3=x0.clrn O=x2.l0_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
.param INIT 0011010100000000
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l0(1) I3=x2.a0(1) O=x2.l0_ff_CQZ_3_D_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01010011
.subckt ff CQZ=x2.l0(0) D=x2.l0_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.search I1=x2.l0_ff_CQZ_4_D_LUT4_O_I1 I2=x2.l0_ff_CQZ_4_D_LUT4_O_I2 I3=x0.clrn O=x2.l0_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=x2.a0(0) I1=x2.l0(0) I2=x2.shorten I3=x2.search O=x2.l0_ff_CQZ_4_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.search I1=x1.B0_ff_CQZ_D_LUT4_O_I0 I2=x2.l0_ff_CQZ_D_LUT4_O_I2 I3=x0.clrn O=x2.l0_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=x2.a0(4) I1=x2.l0(4) I2=x2.shorten I3=x2.search O=x2.l0_ff_CQZ_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l10(4) D=x2.l10_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.l10(3) D=x2.l10_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a10_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l9(3) I2=x2.search I3=x0.clrn O=x2.l10_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt ff CQZ=x2.l10(2) D=x2.l10_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a10_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l9(2) I2=x2.search I3=x0.clrn O=x2.l10_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l10(1) D=x2.l10_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a10_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l9(1) I2=x2.search I3=x0.clrn O=x2.l10_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l10(0) D=x2.l10_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a10_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l9(0) I2=x2.search I3=x0.clrn O=x2.l10_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a10_ff_CQZ_D_LUT4_O_I0 I1=x2.l9(4) I2=x2.search I3=x0.clrn O=x2.l10_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l11(4) D=x2.l11_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.l11(3) D=x2.l11_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a11_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l10(3) I2=x2.search I3=x0.clrn O=x2.l11_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l11(2) D=x2.l11_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a11_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l10(2) I2=x2.search I3=x0.clrn O=x2.l11_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l11(1) D=x2.l11_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a11_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l10(1) I2=x2.search I3=x0.clrn O=x2.l11_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l11(0) D=x2.l11_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a11_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l10(0) I2=x2.search I3=x0.clrn O=x2.l11_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a11_ff_CQZ_D_LUT4_O_I0 I1=x2.l10(4) I2=x2.search I3=x0.clrn O=x2.l11_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l1(4) D=x2.l1_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.l1(3) D=x2.l1_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.l0(3) I1=x2.l1_ff_CQZ_1_D_LUT4_O_I1 I2=x2.search I3=x0.clrn O=x2.l1_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100101000000000
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.a1(2) I3=x2.l1(2) O=x2.l1_ff_CQZ_1_D_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 11001010
.subckt ff CQZ=x2.l1(2) D=x2.l1_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a1_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l0(2) I2=x2.search I3=x0.clrn O=x2.l1_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l1(1) D=x2.l1_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.l0(1) I1=x2.l1_ff_CQZ_3_D_LUT4_O_I1 I2=x2.search I3=x0.clrn O=x2.l1_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100101000000000
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.a1(0) I3=x2.l1(0) O=x2.l1_ff_CQZ_3_D_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 11001010
.subckt ff CQZ=x2.l1(0) D=x2.l1_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.l1_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l0(0) I2=x2.search I3=x0.clrn O=x2.l1_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l1(4) I3=x2.a1(4) O=x2.l1_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x2.l0(4) I1=x2.l1_ff_CQZ_D_LUT4_O_I1 I2=x2.search I3=x0.clrn O=x2.l1_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100101000000000
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.a1(3) I3=x2.l1(3) O=x2.l1_ff_CQZ_D_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 11001010
.subckt ff CQZ=x2.l2(4) D=x2.l2_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.l2(3) D=x2.l2_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a2_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l1(3) I2=x2.search I3=x0.clrn O=x2.l2_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l2(2) D=x2.l2_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a2_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l1(2) I2=x2.search I3=x0.clrn O=x2.l2_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l2(1) D=x2.l2_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.l2_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l1(1) I2=x2.search I3=x0.clrn O=x2.l2_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l2(4) I3=x2.a2(4) O=x2.l2_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt ff CQZ=x2.l2(0) D=x2.l2_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.l2_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l1(0) I2=x2.search I3=x0.clrn O=x2.l2_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l2(3) I3=x2.a2(3) O=x2.l2_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x2.l1(4) I1=x2.l2_ff_CQZ_D_LUT4_O_I1 I2=x2.search I3=x0.clrn O=x2.l2_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100101000000000
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.a2(2) I3=x2.l2(2) O=x2.l2_ff_CQZ_D_LUT4_O_I1
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 11001010
.subckt ff CQZ=x2.l3(4) D=x2.l3_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.l3(3) D=x2.l3_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a3_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l2(3) I2=x2.search I3=x0.clrn O=x2.l3_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l3(2) D=x2.l3_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a3_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l2(2) I2=x2.search I3=x0.clrn O=x2.l3_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l3(1) D=x2.l3_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.l3_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l2(1) I2=x2.search I3=x0.clrn O=x2.l3_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l3(3) I3=x2.a3(3) O=x2.l3_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt ff CQZ=x2.l3(0) D=x2.l3_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.l3_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l2(0) I2=x2.search I3=x0.clrn O=x2.l3_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l3(2) I3=x2.a3(2) O=x2.l3_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt LUT4 I0=x2.a3_ff_CQZ_D_LUT4_O_I0 I1=x2.l2(4) I2=x2.search I3=x0.clrn O=x2.l3_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l4(4) D=x2.l4_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.l4(3) D=x2.l4_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a4_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l3(3) I2=x2.search I3=x0.clrn O=x2.l4_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l4(2) D=x2.l4_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a4_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l3(2) I2=x2.search I3=x0.clrn O=x2.l4_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l4(1) D=x2.l4_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.l4_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l3(1) I2=x2.search I3=x0.clrn O=x2.l4_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l4(2) I3=x2.a4(2) O=x2.l4_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10101100
.subckt ff CQZ=x2.l4(0) D=x2.l4_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a4_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l3(0) I2=x2.search I3=x0.clrn O=x2.l4_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a4_ff_CQZ_D_LUT4_O_I0 I1=x2.l3(4) I2=x2.search I3=x0.clrn O=x2.l4_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l5(4) D=x2.l5_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.l5(3) D=x2.l5_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a5_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l4(3) I2=x2.search I3=x0.clrn O=x2.l5_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l5(2) D=x2.l5_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a5_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l4(2) I2=x2.search I3=x0.clrn O=x2.l5_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l5(1) D=x2.l5_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a5_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l4(1) I2=x2.search I3=x0.clrn O=x2.l5_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l5(0) D=x2.l5_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a5_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l4(0) I2=x2.search I3=x0.clrn O=x2.l5_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a5_ff_CQZ_D_LUT4_O_I0 I1=x2.l4(4) I2=x2.search I3=x0.clrn O=x2.l5_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l6(4) D=x2.l6_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.l6(3) D=x2.l6_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a6_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l5(3) I2=x2.search I3=x0.clrn O=x2.l6_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l6(2) D=x2.l6_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a6_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l5(2) I2=x2.search I3=x0.clrn O=x2.l6_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l6(1) D=x2.l6_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a6_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l5(1) I2=x2.search I3=x0.clrn O=x2.l6_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l6(0) D=x2.l6_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a6_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l5(0) I2=x2.search I3=x0.clrn O=x2.l6_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a6_ff_CQZ_D_LUT4_O_I0 I1=x2.l5(4) I2=x2.search I3=x0.clrn O=x2.l6_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l7(4) D=x2.l7_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.l7(3) D=x2.l7_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a7_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l6(3) I2=x2.search I3=x0.clrn O=x2.l7_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l7(2) D=x2.l7_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a7_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l6(2) I2=x2.search I3=x0.clrn O=x2.l7_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l7(1) D=x2.l7_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a7_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l6(1) I2=x2.search I3=x0.clrn O=x2.l7_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l7(0) D=x2.l7_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a7_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l6(0) I2=x2.search I3=x0.clrn O=x2.l7_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x2.a7_ff_CQZ_D_LUT4_O_I0 I1=x2.l6(4) I2=x2.search I3=x0.clrn O=x2.l7_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l8(4) D=x2.l8_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.l8(3) D=x2.l8_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a8_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l7(3) I2=x2.search I3=x0.clrn O=x2.l8_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l8(2) D=x2.l8_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a8_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l7(2) I2=x2.search I3=x0.clrn O=x2.l8_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l8(1) D=x2.l8_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a8_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l7(1) I2=x2.search I3=x0.clrn O=x2.l8_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l8(0) D=x2.l8_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a8_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l7(0) I2=x2.search I3=x0.clrn O=x2.l8_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a8_ff_CQZ_D_LUT4_O_I0 I1=x2.l7(4) I2=x2.search I3=x0.clrn O=x2.l8_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l9(4) D=x2.l9_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.l9(3) D=x2.l9_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a9_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l8(3) I2=x2.search I3=x0.clrn O=x2.l9_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l9(2) D=x2.l9_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a9_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l8(2) I2=x2.search I3=x0.clrn O=x2.l9_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l9(1) D=x2.l9_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a9_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l8(1) I2=x2.search I3=x0.clrn O=x2.l9_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.l9(0) D=x2.l9_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.a9_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l8(0) I2=x2.search I3=x0.clrn O=x2.l9_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.a9_ff_CQZ_D_LUT4_O_I0 I1=x2.l8(4) I2=x2.search I3=x0.clrn O=x2.l9_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.o0(4) D=x2.o0_ff_CQZ_D QCK=x0.clk QEN=x2.o0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.o0(3) D=x2.o0_ff_CQZ_1_D QCK=x0.clk QEN=x2.o0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x1.A0_ff_CQZ_1_D_LUT4_O_I0 O=x2.o0_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt ff CQZ=x2.o0(2) D=x2.o0_ff_CQZ_2_D QCK=x0.clk QEN=x2.o0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x1.A0_ff_CQZ_2_D_LUT4_O_I0 O=x2.o0_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt ff CQZ=x2.o0(1) D=x2.o0_ff_CQZ_3_D QCK=x0.clk QEN=x2.o0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x1.D_ff_CQZ_3_D_LUT4_O_I1 O=x2.o0_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt ff CQZ=x2.o0(0) D=x2.o0_ff_CQZ_4_D QCK=x0.clk QEN=x2.o0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x1.A0_ff_CQZ_4_D_LUT4_O_I0 O=x2.o0_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x1.D_ff_CQZ_D_LUT4_O_I3 O=x2.o0_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=chien_load_LUT4_I1_O I2=x0.clrn I3=x2.shorten O=x2.o0_ff_CQZ_QEN
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01110000
.subckt ff CQZ=x2.o10(4) D=x2.o10_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.o10(3) D=x2.o10_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o10_ff_CQZ_1_D_LUT4_O_I0 I1=x2.o9(3) I2=x2.search I3=x0.clrn O=x2.o10_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x2.o10(4) I2=x2.o10(3) I3=x2.o10(2) O=x2.o10_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=x2.o10(2) D=x2.o10_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o10_ff_CQZ_2_D_LUT4_O_I0 I1=x2.o9(2) I2=x2.search I3=x0.clrn O=x2.o10_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.o10(1) I3=x2.o10_ff_CQZ_1_D_LUT4_O_I0 O=x2.o10_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0110
.subckt ff CQZ=x2.o10(1) D=x2.o10_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o10_ff_CQZ_3_D_LUT4_O_I3 O=x2.o10_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o9(1) I1=x2.o10(1) I2=x2.o10(2) I3=x2.search O=x2.o10_ff_CQZ_3_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt ff CQZ=x2.o10(0) D=x2.o10_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o10_ff_CQZ_4_D_LUT4_O_I0 I1=x2.o9(0) I2=x2.search I3=x0.clrn O=x2.o10_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x2.o10(4) I2=x2.o10(1) I3=x2.o10(0) O=x2.o10_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=x2.search I1=x2.o9(4) I2=x2.o10_ff_CQZ_D_LUT4_O_I2 I3=x0.clrn O=x2.o10_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=x2.o10(0) I1=x2.o10(3) I2=x2.o10(4) I3=x2.search O=x2.o10_ff_CQZ_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011000000000
.subckt ff CQZ=x2.o11(4) D=x2.o11_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.o11(3) D=x2.o11_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o11_ff_CQZ_1_D_LUT4_O_I0 I1=x2.o10(3) I2=x2.search I3=x0.clrn O=x2.o11_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.o11(1) I3=x2.o11_ff_CQZ_D_LUT4_O_I0 O=x2.o11_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001
.subckt ff CQZ=x2.o11(2) D=x2.o11_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.search I1=x2.o10(2) I2=x2.o11_ff_CQZ_2_D_LUT4_O_I2 I3=x0.clrn O=x2.o11_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=x2.o11_ff_CQZ_D_LUT4_O_I0 I1=x2.o11(0) I2=x2.o11(1) I3=x2.search O=x2.o11_ff_CQZ_2_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011000000000
.subckt ff CQZ=x2.o11(1) D=x2.o11_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o11_ff_CQZ_3_D_LUT4_O_I0 I1=x2.o10(1) I2=x2.search I3=x0.clrn O=x2.o11_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x2.o11(1) I2=x2.o11(0) I3=x2.o11(4) O=x2.o11_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=x2.o11(0) D=x2.o11_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o11_ff_CQZ_4_D_LUT4_O_I0 I1=x2.o10(0) I2=x2.search I3=x0.clrn O=x2.o11_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x2.o11(3) I2=x2.o11(0) I3=x2.o11(4) O=x2.o11_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=x2.o11_ff_CQZ_D_LUT4_O_I0 I1=x2.o10(4) I2=x2.search I3=x0.clrn O=x2.o11_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x2.o11(3) I2=x2.o11(2) I3=x2.o11(4) O=x2.o11_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 10010110
.subckt ff CQZ=x2.o1(4) D=x2.o1_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.o1(3) D=x2.o1_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o1(2) I1=x2.o0(3) I2=x2.search I3=x0.clrn O=x2.o1_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.o1(2) D=x2.o1_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o1_ff_CQZ_2_D_LUT4_O_I3 O=x2.o1_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o0(2) I1=x2.o1(4) I2=x2.o1(1) I3=x2.search O=x2.o1_ff_CQZ_2_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt ff CQZ=x2.o1(1) D=x2.o1_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o1(0) I1=x2.o0(1) I2=x2.search I3=x0.clrn O=x2.o1_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.o1(0) D=x2.o1_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o1(4) I1=x2.o0(0) I2=x2.search I3=x0.clrn O=x2.o1_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.o1(3) I1=x2.o0(4) I2=x2.search I3=x0.clrn O=x2.o1_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.o2(4) D=x2.o2_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.o2(3) D=x2.o2_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o2_ff_CQZ_1_D_LUT4_O_I3 O=x2.o2_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o1(3) I1=x2.o2(4) I2=x2.o2(1) I3=x2.search O=x2.o2_ff_CQZ_1_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt ff CQZ=x2.o2(2) D=x2.o2_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o2_ff_CQZ_2_D_LUT4_O_I3 O=x2.o2_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o1(2) I1=x2.o2(3) I2=x2.o2(0) I3=x2.search O=x2.o2_ff_CQZ_2_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt ff CQZ=x2.o2(1) D=x2.o2_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o2(4) I1=x2.o1(1) I2=x2.search I3=x0.clrn O=x2.o2_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.o2(0) D=x2.o2_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o2(3) I1=x2.o1(0) I2=x2.search I3=x0.clrn O=x2.o2_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x2.o2(2) I1=x2.o1(4) I2=x2.search I3=x0.clrn O=x2.o2_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.o3(4) D=x2.o3_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.o3(3) D=x2.o3_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o3_ff_CQZ_1_D_LUT4_O_I3 O=x2.o3_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o2(3) I1=x2.o3(3) I2=x2.o3(0) I3=x2.search O=x2.o3_ff_CQZ_1_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt ff CQZ=x2.o3(2) D=x2.o3_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o3_ff_CQZ_2_D_LUT4_O_I3 O=x2.o3_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o2(2) I1=x2.o3(2) I2=x2.o3(4) I3=x2.search O=x2.o3_ff_CQZ_2_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt ff CQZ=x2.o3(1) D=x2.o3_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o3(3) I1=x2.o2(1) I2=x2.search I3=x0.clrn O=x2.o3_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.o3(0) D=x2.o3_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o3(2) I1=x2.o2(0) I2=x2.search I3=x0.clrn O=x2.o3_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o3_ff_CQZ_D_LUT4_O_I3 O=x2.o3_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o2(4) I1=x2.o3(1) I2=x2.o3(4) I3=x2.search O=x2.o3_ff_CQZ_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt ff CQZ=x2.o4(4) D=x2.o4_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.o4(3) D=x2.o4_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o4_ff_CQZ_1_D_LUT4_O_I3 O=x2.o4_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o3(3) I1=x2.o4(2) I2=x2.o4(4) I3=x2.search O=x2.o4_ff_CQZ_1_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt ff CQZ=x2.o4(2) D=x2.o4_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o4_ff_CQZ_2_D_LUT4_O_I0 I1=x2.o3(2) I2=x2.search I3=x0.clrn O=x2.o4_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x2.o4(4) I2=x2.o4(3) I3=x2.o4(1) O=x2.o4_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=x2.o4(1) D=x2.o4_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o4(2) I1=x2.o3(1) I2=x2.search I3=x0.clrn O=x2.o4_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1010110000000000
.subckt ff CQZ=x2.o4(0) D=x2.o4_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o4_ff_CQZ_4_D_LUT4_O_I3 O=x2.o4_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o3(0) I1=x2.o4(1) I2=x2.o4(4) I3=x2.search O=x2.o4_ff_CQZ_4_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o4_ff_CQZ_D_LUT4_O_I3 O=x2.o4_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o3(4) I1=x2.o4(0) I2=x2.o4(3) I3=x2.search O=x2.o4_ff_CQZ_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt ff CQZ=x2.o5(4) D=x2.o5_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.o5(3) D=x2.o5_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o5_ff_CQZ_1_D_LUT4_O_I0 I1=x2.o4(3) I2=x2.search I3=x0.clrn O=x2.o5_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x2.o5(4) I2=x2.o5(3) I3=x2.o5(1) O=x2.o5_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=x2.o5(2) D=x2.o5_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o5_ff_CQZ_2_D_LUT4_O_I0 I1=x2.o4(2) I2=x2.search I3=x0.clrn O=x2.o5_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x2.o5(3) I2=x2.o5(2) I3=x2.o5(0) O=x2.o5_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=x2.o5(1) D=x2.o5_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o5_ff_CQZ_3_D_LUT4_O_I3 O=x2.o5_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o4(1) I1=x2.o5(1) I2=x2.o5(4) I3=x2.search O=x2.o5_ff_CQZ_3_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt ff CQZ=x2.o5(0) D=x2.o5_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o5_ff_CQZ_4_D_LUT4_O_I3 O=x2.o5_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o4(0) I1=x2.o5(0) I2=x2.o5(3) I3=x2.search O=x2.o5_ff_CQZ_4_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o5_ff_CQZ_D_LUT4_O_I3 O=x2.o5_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o4(4) I1=x2.o5(2) I2=x2.o5(4) I3=x2.search O=x2.o5_ff_CQZ_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt ff CQZ=x2.o6(4) D=x2.o6_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.o6(3) D=x2.o6_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o6_ff_CQZ_1_D_LUT4_O_I0 I1=x2.o5(3) I2=x2.search I3=x0.clrn O=x2.o6_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x2.o6(3) I2=x2.o6(2) I3=x2.o6(0) O=x2.o6_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=x2.o6(2) D=x2.o6_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o6_ff_CQZ_2_D_LUT4_O_I3 O=x2.o6_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o5(2) I1=x2.o6(1) I2=x2.o6(2) I3=x2.search O=x2.o6_ff_CQZ_2_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt ff CQZ=x2.o6(1) D=x2.o6_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o6_ff_CQZ_3_D_LUT4_O_I3 O=x2.o6_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o5(1) I1=x2.o6(0) I2=x2.o6(3) I3=x2.search O=x2.o6_ff_CQZ_3_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt ff CQZ=x2.o6(0) D=x2.o6_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o6_ff_CQZ_4_D_LUT4_O_I3 O=x2.o6_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o5(0) I1=x2.o6(2) I2=x2.o6(4) I3=x2.search O=x2.o6_ff_CQZ_4_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt LUT4 I0=x2.o6_ff_CQZ_D_LUT4_O_I0 I1=x2.o5(4) I2=x2.search I3=x0.clrn O=x2.o6_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x2.o6(4) I2=x2.o6(3) I3=x2.o6(1) O=x2.o6_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=x2.o7(4) D=x2.o7_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.o7(3) D=x2.o7_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o7_ff_CQZ_1_D_LUT4_O_I3 O=x2.o7_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o6(3) I1=x2.o7(1) I2=x2.o7(2) I3=x2.search O=x2.o7_ff_CQZ_1_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt ff CQZ=x2.o7(2) D=x2.o7_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o7_ff_CQZ_2_D_LUT4_O_I0 I1=x2.o6(2) I2=x2.search I3=x0.clrn O=x2.o7_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x2.o7(4) I2=x2.o7(1) I3=x2.o7(0) O=x2.o7_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=x2.o7(1) D=x2.o7_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o7_ff_CQZ_3_D_LUT4_O_I3 O=x2.o7_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o6(1) I1=x2.o7(2) I2=x2.o7(4) I3=x2.search O=x2.o7_ff_CQZ_3_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt ff CQZ=x2.o7(0) D=x2.o7_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.search I1=x2.o6(0) I2=x2.o7_ff_CQZ_4_D_LUT4_O_I2 I3=x0.clrn O=x2.o7_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=x2.o7(1) I1=x2.o7(3) I2=x2.o7(4) I3=x2.search O=x2.o7_ff_CQZ_4_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011000000000
.subckt LUT4 I0=x2.o7_ff_CQZ_D_LUT4_O_I0 I1=x2.o6(4) I2=x2.search I3=x0.clrn O=x2.o7_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x2.o7(3) I2=x2.o7(2) I3=x2.o7(0) O=x2.o7_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=x2.o8(4) D=x2.o8_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.o8(3) D=x2.o8_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.search I1=x2.o7(3) I2=x2.o8_ff_CQZ_1_D_LUT4_O_I2 I3=x0.clrn O=x2.o8_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1111010000000000
.subckt LUT4 I0=x2.o8(0) I1=x2.o8(1) I2=x2.o8(4) I3=x2.search O=x2.o8_ff_CQZ_1_D_LUT4_O_I2
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1001011000000000
.subckt ff CQZ=x2.o8(2) D=x2.o8_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o8_ff_CQZ_2_D_LUT4_O_I0 I1=x2.o7(2) I2=x2.search I3=x0.clrn O=x2.o8_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x2.o8(4) I2=x2.o8(3) I3=x2.o8(0) O=x2.o8_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=x2.o8(1) D=x2.o8_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o8_ff_CQZ_3_D_LUT4_O_I0 I1=x2.o7(1) I2=x2.search I3=x0.clrn O=x2.o8_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x2.o8(4) I2=x2.o8(3) I3=x2.o8(1) O=x2.o8_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=x2.o8(0) D=x2.o8_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o8_ff_CQZ_4_D_LUT4_O_I0 I1=x2.o7(0) I2=x2.search I3=x0.clrn O=x2.o8_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x2.o8(3) I2=x2.o8(2) I3=x2.o8(0) O=x2.o8_ff_CQZ_4_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o8_ff_CQZ_D_LUT4_O_I3 O=x2.o8_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o7(4) I1=x2.o8(1) I2=x2.o8(2) I3=x2.search O=x2.o8_ff_CQZ_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt ff CQZ=x2.o9(4) D=x2.o9_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt ff CQZ=x2.o9(3) D=x2.o9_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o9_ff_CQZ_1_D_LUT4_O_I0 I1=x2.o8(3) I2=x2.search I3=x0.clrn O=x2.o9_ff_CQZ_1_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x2.o9(4) I2=x2.o9(3) I3=x2.o9(0) O=x2.o9_ff_CQZ_1_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=x2.o9(2) D=x2.o9_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o9_ff_CQZ_2_D_LUT4_O_I0 I1=x2.o8(2) I2=x2.search I3=x0.clrn O=x2.o9_ff_CQZ_2_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x2.o9(4) I2=x2.o9(3) I3=x2.o9(2) O=x2.o9_ff_CQZ_2_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=x2.o9(1) D=x2.o9_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x2.o9_ff_CQZ_3_D_LUT4_O_I0 I1=x2.o8(1) I2=x2.search I3=x0.clrn O=x2.o9_ff_CQZ_3_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x2.o9(3) I2=x2.o9(2) I3=x2.o9(0) O=x2.o9_ff_CQZ_3_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt ff CQZ=x2.o9(0) D=x2.o9_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o9_ff_CQZ_4_D_LUT4_O_I3 O=x2.o9_ff_CQZ_4_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(~I0*I1*I2*I3)"
.param INIT 0100
.subckt LUT4 I0=x2.o8(0) I1=x2.o9(1) I2=x2.o9(2) I3=x2.search O=x2.o9_ff_CQZ_4_D_LUT4_O_I3
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
.param INIT 1100001101010101
.subckt LUT4 I0=x2.o9_ff_CQZ_D_LUT4_O_I0 I1=x2.o8(4) I2=x2.search I3=x0.clrn O=x2.o9_ff_CQZ_D
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 0101110000000000
.subckt LUT4 I0=x0.shift I1=x2.o9(4) I2=x2.o9(1) I3=x2.o9(0) O=x2.o9_ff_CQZ_D_LUT4_O_I0
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
.param INIT 01101001
.subckt LUT4 I0=x0.shift I1=x0.shift I2=$iopadmap$x(4) I3=x0.clrn O=u_ff_CQZ_D(4)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=$iopadmap$x(3) I3=x0.clrn O=u_ff_CQZ_D(3)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=$iopadmap$x(2) I3=x0.clrn O=u_ff_CQZ_D(2)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=$iopadmap$x(1) I3=x0.clrn O=u_ff_CQZ_D(1)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.subckt LUT4 I0=x0.shift I1=x0.shift I2=$iopadmap$x(0) I3=x0.clrn O=u_ff_CQZ_D(0)
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
.param EQN "(I0*I1*I2*I3)"
.param INIT 1000
.end