mirror of https://github.com/lnis-uofu/SOFA.git
49 lines
1.7 KiB
XML
49 lines
1.7 KiB
XML
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<!-- Simulation Setting for OpenFPGA framework
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This file will use
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- a fixed operating clock frequency
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- a fixed programming clock frequency
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Note: all the numbers are tuned to STA results from physical layouts
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-->
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<openfpga_simulation_setting>
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<clock_setting>
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<!-- Use 50MHz as the Caravel SoC can operate at 50MHz
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As the FPGA core does not share the clock with Caravel SoC
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the actual clock frequency could be higher
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-->
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<operating frequency="50e6" num_cycles="auto" slack="0.2"/>
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<!-- Use 50MHz as the Caravel SoC can operate at 50MHz
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As the FPGA core does not share the clock with Caravel SoC
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the actual programming clock frequency could be higher
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-->
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<programming frequency="50e6"/>
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</clock_setting>
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<simulator_option>
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<operating_condition temperature="25"/>
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<output_log verbose="false" captab="false"/>
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<accuracy type="abs" value="1e-13"/>
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<runtime fast_simulation="true"/>
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</simulator_option>
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<monte_carlo num_simulation_points="2"/>
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<measurement_setting>
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<slew>
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<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
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<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
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</slew>
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<delay>
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<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
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<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
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</delay>
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</measurement_setting>
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<stimulus>
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<clock>
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<rise slew_type="abs" slew_time="20e-12" />
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<fall slew_type="abs" slew_time="20e-12" />
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</clock>
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<input>
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<rise slew_type="abs" slew_time="25e-12" />
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<fall slew_type="abs" slew_time="25e-12" />
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</input>
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</stimulus>
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</openfpga_simulation_setting>
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