mirror of https://github.com/lnis-uofu/SOFA.git
14 lines
403 B
Coq
14 lines
403 B
Coq
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//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Preprocessing flags to enable/disable features in FPGA Verilog modules
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// Author: Xifan TANG
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// Organization: University of Utah
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// Date: Thu Nov 5 10:40:44 2020
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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`define UNIT_DELAY #0.01
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`define FUNCTIONAL 1
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