mirror of https://github.com/lnis-uofu/SOFA.git
39 lines
1.2 KiB
Coq
39 lines
1.2 KiB
Coq
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//-------------------------------------------------------------------
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// Function: Binary to Decimal converter
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// Source:
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// https://verilogcodes.blogspot.com/2015/10/verilog-code-for-8-bit-binary-to-bcd.html
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//-------------------------------------------------------------------
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module bin2bcd(
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bin,
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bcd
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);
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//input ports and their sizes
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input [7:0] bin;
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//output ports and, their size
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output [11:0] bcd;
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//Internal variables
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reg [11 : 0] bcd;
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reg [3:0] i;
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//Always block - implement the Double Dabble algorithm
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always @(bin)
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begin
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bcd = 0; //initialize bcd to zero.
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for (i = 0; i < 8; i = i+1) //run for 8 iterations
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begin
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bcd = {bcd[10:0],bin[7-i]}; //concatenation
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//if a hex digit of 'bcd' is more than 4, add 3 to it.
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if(i < 7 && bcd[3:0] > 4)
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bcd[3:0] = bcd[3:0] + 3;
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if(i < 7 && bcd[7:4] > 4)
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bcd[7:4] = bcd[7:4] + 3;
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if(i < 7 && bcd[11:8] > 4)
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bcd[11:8] = bcd[11:8] + 3;
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end
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end
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endmodule
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