SOFA/.gitignore

**/SRCOriginal
**/SRCOutline
**/TaskConfigCopy
**/*_task/run001
**/*_task/latest
**/*_task/skywater
**/*_Verilog/SRC_Skeleton
**/*_Verilog/SRCBackup
**/DOC/build
**/SRC**/*_tb.v
[Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-27 00:59:20 -05:00			`**/SRCOriginal`
			`**/SRCOutline`
			`**/TaskConfigCopy`
			`*/_task/run001`
			`*/_task/latest`
dropped symbolic link 2020-10-27 12:21:20 -05:00			`*/_task/skywater`
Updated design with new architecure and merged grid_io 2020-11-06 23:35:31 -06:00			`*/_Verilog/SRC_Skeleton`
			`*/_Verilog/SRCBackup`
[Git] Add ignore files to doc compiled results 2020-11-12 20:13:20 -06:00			`**/DOC/build`
[Cleanup] Removed/Ignored testbench files from generated source 2020-12-02 13:03:24 -06:00			`/SRC/*_tb.v`