2020-10-27 00:59:20 -05:00
|
|
|
FPGA22_HIER_SKY_PNR
|
|
|
|
|
====================
|
|
|
|
|
|
2020-10-27 16:51:16 -05:00
|
|
|
2x2 FPGA designed using hierarchical flow and `SKY130_FD_SC_HD`.
|
2020-11-06 23:35:31 -06:00
|
|
|
|
|
|
|
|
Updates
|
|
|
|
|
-------------------
|
2020-11-08 19:37:55 -06:00
|
|
|
- Merged `grid_io` modules with connection blocks
|
|
|
|
|
- Pre-routed scan chain signals
|
|
|
|
|
- Created `carry_chain` feedthrough between `grid_clb` modules
|
|
|
|
|
- **Prerouting global signals (`Test_en`)**
|
|
|
|
|
- **Prerouting clock signals**
|
|
|
|
|
- **Enabled Feed through generation for clock**
|
2020-10-27 00:59:20 -05:00
|
|
|
|
|
|
|
|
Directory Structure
|
|
|
|
|
-------------------
|
2020-10-27 15:54:19 -05:00
|
|
|
- **FPGA22_HIER_SKY_task** :- OpenFPGA task directory and all related files
|
|
|
|
|
- **FPGA22_HIER_SKY_Verilog** :- Verilog-netlist used for this design
|
|
|
|
|
- **modules** :- Final files of each module (lef,def,spef,v,gds)
|
|
|
|
|
- **fpga_core** :- Final files of fpga_core (eFPGA design)
|
|
|
|
|
- **fpga_top** :- Reserved for design with GPIOs or caravel
|
2020-10-27 00:59:20 -05:00
|
|
|
|
|
|
|
|
Checks
|
|
|
|
|
---------
|
|
|
|
|
- .tech file DRC - Clean
|
|
|
|
|
- Timing SignOff - Clean
|
|
|
|
|
|
|
|
|
|
Pending
|
|
|
|
|
---------
|
|
|
|
|
- DRC SignOff
|
2020-10-27 15:54:19 -05:00
|
|
|
- LVS SignOff
|
2020-11-06 23:35:31 -06:00
|
|
|
- PostPnR functional simulation
|
