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<tspanfont-family="Times"font-size="16"font-weight="400"fill="#ff2600"x="0"y="15">Mode switch truth table:</tspan>
<tspanfont-family="Times"font-size="16"font-weight="400"fill="#ff2600"x="0"y="34">- When Caravel GPIO[25] is logic ‘1’, FPGA is interfacing the Wishbone bus</tspan>
<tspanfont-family="Times"font-size="16"font-weight="400"fill="#ff2600"x="0"y="53">- When Caravel GPIO[25] is logic ‘0’, FPGA is interfacing the logic analyzer</tspan>
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