mirror of https://github.com/lnis-uofu/SOFA.git
45 lines
1.5 KiB
Tcl
45 lines
1.5 KiB
Tcl
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#####################################################################
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# A template script to generate SDF file from post-PnR results
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# using Synopsys PrimeTime
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#####################################################################
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##################################
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# Define environment variables
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set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
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set FPGA_NETLIST_HOME "../../FPGA1212_FC_HD_SKY_PNR/fpga_core";
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set SDF_HOME "../SDF"
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#
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# Enable reporting ALL the timing paths even those are NOT constrained
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set_app_var svr_enable_vpp true
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set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/results/lib/skywater130_fd_sc_hd/db_nldm"
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set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
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# Top-level module name
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set DESIGN_NAME fpga_core;
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set FPGA_NETLIST_FILES "fpga_core_icv_in_design.pt.v"
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##################################
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# Read timing libraries
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read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/results/lib/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
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##################################
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# Read post-PnR netlists
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read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
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link_design ${DESIGN_NAME}
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##################################
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# Read post-PnR parasitics
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read_parasitics ${FPGA_NETLIST_HOME}/fpga_core_icv_in_design.nominal_25.spef
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##################################
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# Write sdf file
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write_sdf -version 3.0 ${SDF_HOME}/FPGA1212_FC_HD_SKY_PNR/fpga_core_icv_in_design.pt.sdf
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##################################
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# Finish and quit
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# Comment it out if you want to debug
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#exit
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