set DIE_HEIGHT 2800
set DIE_WIDTH 2800
set DESIGN_NAME fpga_core
set TASK_NAME FPGA1212_FC_HD_SKY_task
set VERILOG_PROJ_DIR FPGA1212_FC_HD_SKY_Verilog
set FPGA_ROW 12
set FPGA_COL 12
set INIT_DESIGN_INPUT DP_RM_NDM
set TECHNOLOGY skywater
set DP_BLOCK_REFS [list  sb_0__0_ sb_0__1_ sb_0__2_ sb_1__0_ sb_1__1_ sb_1__2_ sb_2__0_ sb_2__1_ sb_2__2_ cbx_1__0_ cbx_1__1_ cbx_1__2_ cby_0__1_ cby_1__1_ cby_2__1_ grid_clb];
set DP_FLOW "hier";
set DESIGN_STYLE "hier";
set STANDARD_CELLS sc_hd;
