//
//
//
//
//
//
module direct_interc ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_284 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_283 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_282 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_281 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_280 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_279 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_278 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_277 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_276 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_275 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_274 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_273 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_272 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_271 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_270 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_269 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_268 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_267 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_266 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_265 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_264 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_263 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_262 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_261 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_260 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_259 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_258 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_257 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_256 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_255 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_254 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_253 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_252 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_251 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_250 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_249 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_248 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_247 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_246 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_245 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_244 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_243 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_242 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_241 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_240 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_239 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_238 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_237 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_236 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_235 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_234 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_233 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_232 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_231 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_230 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_229 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_228 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_227 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_226 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_225 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_224 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_223 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_222 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_221 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_220 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_219 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_218 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_217 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_216 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_215 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_214 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_213 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_212 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_211 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_210 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_209 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_208 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_207 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_206 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_205 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_204 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_203 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_202 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_201 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_200 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_199 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_198 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_197 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_196 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_195 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_194 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_193 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_192 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_191 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_190 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_189 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_188 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_187 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_186 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_185 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_184 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_183 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_182 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_181 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_180 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_179 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_178 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_177 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_176 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_175 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_174 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_173 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_172 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_171 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_170 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_169 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_168 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_167 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_166 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_165 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_164 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_163 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_162 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_161 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_160 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_159 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_158 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_157 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_156 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_155 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_154 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_153 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_152 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_151 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_150 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_149 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_148 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_147 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_146 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_145 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_144 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_143 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module direct_interc_142 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd2_1 FTB_143__142 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_141 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

wire aps_rename_6_ ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_142__141 ( .A ( in[0] ) , 
    .X ( aps_rename_6_ ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_232 ( .A ( BUF_net_234 ) , 
    .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_234 ( .A ( BUF_net_237 ) , 
    .X ( BUF_net_234 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_237 ( .A ( BUF_net_238 ) , 
    .X ( BUF_net_237 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_238 ( .A ( BUF_net_241 ) , 
    .X ( BUF_net_238 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_241 ( .A ( aps_rename_6_ ) , 
    .X ( BUF_net_241 ) ) ;
endmodule


module direct_interc_140 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_141__140 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_139 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

wire aps_rename_5_ ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_140__139 ( .A ( in[0] ) , 
    .X ( aps_rename_5_ ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_216 ( .A ( BUF_net_218 ) , 
    .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_218 ( .A ( BUF_net_221 ) , 
    .X ( BUF_net_218 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_221 ( .A ( BUF_net_225 ) , 
    .X ( BUF_net_221 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_225 ( .A ( aps_rename_5_ ) , 
    .X ( BUF_net_225 ) ) ;
endmodule


module direct_interc_138 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

wire aps_rename_4_ ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_139__138 ( .A ( in[0] ) , 
    .X ( aps_rename_4_ ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_201 ( .A ( BUF_net_203 ) , 
    .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_203 ( .A ( BUF_net_206 ) , 
    .X ( BUF_net_203 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_206 ( .A ( BUF_net_207 ) , 
    .X ( BUF_net_206 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_207 ( .A ( BUF_net_210 ) , 
    .X ( BUF_net_207 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_210 ( .A ( aps_rename_4_ ) , 
    .X ( BUF_net_210 ) ) ;
endmodule


module direct_interc_137 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_138__137 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_136 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_137__136 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_135 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_136__135 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_134 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

wire aps_rename_3_ ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_135__134 ( .A ( in[0] ) , 
    .X ( aps_rename_3_ ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_187 ( .A ( BUF_net_189 ) , 
    .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_189 ( .A ( BUF_net_193 ) , 
    .X ( BUF_net_189 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_193 ( .A ( BUF_net_196 ) , 
    .X ( BUF_net_193 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_196 ( .A ( aps_rename_3_ ) , 
    .X ( BUF_net_196 ) ) ;
endmodule


module direct_interc_133 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

wire aps_rename_2_ ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_134__133 ( .A ( in[0] ) , 
    .X ( aps_rename_2_ ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_172 ( .A ( BUF_net_175 ) , 
    .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_175 ( .A ( BUF_net_179 ) , 
    .X ( BUF_net_175 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_179 ( .A ( BUF_net_181 ) , 
    .X ( BUF_net_179 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_181 ( .A ( aps_rename_2_ ) , 
    .X ( BUF_net_181 ) ) ;
endmodule


module direct_interc_132 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

wire aps_rename_1_ ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_133__132 ( .A ( in[0] ) , 
    .X ( aps_rename_1_ ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_155 ( .A ( BUF_net_157 ) , 
    .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_157 ( .A ( BUF_net_160 ) , 
    .X ( BUF_net_157 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_160 ( .A ( BUF_net_164 ) , 
    .X ( BUF_net_160 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_164 ( .A ( aps_rename_1_ ) , 
    .X ( BUF_net_164 ) ) ;
endmodule


module direct_interc_131 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_132__131 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_130 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_131__130 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_129 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_130__129 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_128 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_129__128 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_127 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_128__127 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_126 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_127__126 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_125 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_126__125 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_124 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_125__124 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_123 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_124__123 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_122 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_123__122 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_121 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_122__121 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_120 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_121__120 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_119 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_120__119 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_118 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_119__118 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_117 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_118__117 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_116 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_117__116 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_115 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_116__115 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_114 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_115__114 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_113 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_114__113 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_112 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_113__112 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_111 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_112__111 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_110 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_111__110 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_109 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_110__109 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_108 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_109__108 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_107 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_108__107 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_106 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_107__106 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_105 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_106__105 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_104 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_105__104 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_103 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_104__103 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_102 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_103__102 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_101 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_102__101 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_100 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_101__100 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_99 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_100__99 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_98 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_99__98 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_97 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_98__97 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_96 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_97__96 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_95 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_96__95 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_94 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_95__94 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_93 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_94__93 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_92 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_93__92 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_91 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_92__91 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_90 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_91__90 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_89 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_90__89 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_88 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_89__88 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_87 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_88__87 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_86 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_87__86 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_85 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_86__85 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_84 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_85__84 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_83 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_84__83 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_82 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_83__82 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_81 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_82__81 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_80 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_81__80 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_79 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_80__79 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_78 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_79__78 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_77 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_78__77 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_76 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_77__76 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_75 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_76__75 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_74 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_75__74 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_73 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_74__73 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_72 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_73__72 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_71 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_72__71 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_70 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_71__70 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_69 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_70__69 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_68 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_69__68 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_67 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_68__67 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_66 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_67__66 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_65 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_66__65 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_64 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_65__64 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_63 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_64__63 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_62 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_63__62 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_61 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_62__61 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_60 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_61__60 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_59 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_60__59 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_58 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_59__58 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_57 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_58__57 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_56 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_57__56 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_55 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_56__55 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_54 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_55__54 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_53 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_54__53 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_52 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_53__52 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_51 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_52__51 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_50 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_51__50 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_49 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_50__49 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_48 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_49__48 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_47 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_48__47 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_46 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_47__46 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_45 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_46__45 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_44 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_45__44 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_43 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_44__43 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_42 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_43__42 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_41 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_42__41 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_40 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_39 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_40__39 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_38 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__38 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_37 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__37 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_36 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_35 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__35 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_34 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_33 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__33 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_32 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__32 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_31 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__31 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_30 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__30 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_29 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_28 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__28 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_27 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__27 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_26 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_25 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__25 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_24 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_23 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__23 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_22 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__22 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_21 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_20 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_19 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__19 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_18 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__18 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_17 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_16 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_15 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_14 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_13 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_12 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_11 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_10 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_9 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_8 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_7 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_6 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_5 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_4 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_3 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_2 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__2 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_1 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module direct_interc_0 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( in[0] ) , .X ( out[0] ) ) ;
endmodule


module cby_2__1__direct_interc ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

assign out[0] = in[0] ;
endmodule


module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
    ccff_head , ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:0] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 FTB_20__60 ( .A ( mem_out[0] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_2__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
    FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ;
input  SOC_IN ;
output SOC_OUT ;
output SOC_DIR ;
output FPGA_IN ;
input  FPGA_OUT ;
input  FPGA_DIR ;
output p_abuf0 ;
output p_abuf1 ;

assign SOC_OUT = FPGA_OUT ;

sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__59 ( .A ( FPGA_DIR ) , 
    .X ( SOC_DIR ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ;
endmodule


module cby_2__1__logical_tile_io_mode_physical__iopad ( prog_clk , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , 
    ccff_tail , p_abuf0 , p_abuf1 ) ;
input  [0:0] prog_clk ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] iopad_outpad ;
input  [0:0] ccff_head ;
output [0:0] iopad_inpad ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf1 ;

wire [0:0] EMBEDDED_IO_0_en ;

cby_2__1__EMBEDDED_IO EMBEDDED_IO_0_ ( 
    .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , 
    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , 
    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , 
    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
    .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , 
    .p_abuf1 ( p_abuf1 ) ) ;
cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ;
endmodule


module cby_2__1__logical_tile_io_mode_io_ ( prog_clk , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , 
    ccff_tail , p_abuf0 ) ;
input  [0:0] prog_clk ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] io_outpad ;
input  [0:0] ccff_head ;
output [0:0] io_inpad ;
output [0:0] ccff_tail ;
output p_abuf0 ;

cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
    .prog_clk ( prog_clk ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , 
    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , 
    .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ;
cby_2__1__direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( { p_abuf1 } ) ) ;
cby_2__1__direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .out ( io_outpad ) ) ;
endmodule


module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__57 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_2__1__const1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cby_2__1__const1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cby_2__1__const1_15 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cby_2__1__const1_15 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cby_2__1__const1_14 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cby_2__1__const1_14 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cby_2__1__const1_13 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cby_2__1__const1_13 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cby_2__1__const1_12 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_2__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cby_2__1__const1_12 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cby_2__1__const1_11 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_2__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cby_2__1__const1_11 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cby_2__1__const1_10 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_2__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cby_2__1__const1_10 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cby_2__1__const1_9 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cby_2__1__const1_9 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_2__1__const1_8 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cby_2__1__const1_8 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cby_2__1__const1_7 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cby_2__1__const1_7 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cby_2__1__const1_6 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cby_2__1__const1_6 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cby_2__1__const1_5 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cby_2__1__const1_5 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cby_2__1__const1_4 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_2__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cby_2__1__const1_4 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cby_2__1__const1_3 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cby_2__1__const1_3 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cby_2__1__const1_2 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cby_2__1__const1_2 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cby_2__1__const1_1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cby_2__1__const1_1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cby_2__1__const1_0 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cby_2__1__const1_0 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , 
    chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , 
    left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , 
    left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , 
    left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , 
    left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , 
    left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , 
    left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower ) ;
input  [0:0] prog_clk ;
input  [0:19] chany_bottom_in ;
input  [0:19] chany_top_in ;
input  [0:0] ccff_head ;
output [0:19] chany_bottom_out ;
output [0:19] chany_top_out ;
output [0:0] right_grid_pin_0_ ;
output [0:0] left_grid_pin_16_ ;
output [0:0] left_grid_pin_17_ ;
output [0:0] left_grid_pin_18_ ;
output [0:0] left_grid_pin_19_ ;
output [0:0] left_grid_pin_20_ ;
output [0:0] left_grid_pin_21_ ;
output [0:0] left_grid_pin_22_ ;
output [0:0] left_grid_pin_23_ ;
output [0:0] left_grid_pin_24_ ;
output [0:0] left_grid_pin_25_ ;
output [0:0] left_grid_pin_26_ ;
output [0:0] left_grid_pin_27_ ;
output [0:0] left_grid_pin_28_ ;
output [0:0] left_grid_pin_29_ ;
output [0:0] left_grid_pin_30_ ;
output [0:0] left_grid_pin_31_ ;
output [0:0] ccff_tail ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] left_width_0_height_0__pin_0_ ;
output [0:0] left_width_0_height_0__pin_1_upper ;
output [0:0] left_width_0_height_0__pin_1_lower ;

wire ropt_net_104 ;
wire [0:3] mux_left_ipin_0_undriven_sram_inv ;
wire [0:3] mux_right_ipin_0_undriven_sram_inv ;
wire [0:3] mux_right_ipin_10_undriven_sram_inv ;
wire [0:3] mux_right_ipin_11_undriven_sram_inv ;
wire [0:3] mux_right_ipin_12_undriven_sram_inv ;
wire [0:3] mux_right_ipin_13_undriven_sram_inv ;
wire [0:3] mux_right_ipin_14_undriven_sram_inv ;
wire [0:3] mux_right_ipin_15_undriven_sram_inv ;
wire [0:3] mux_right_ipin_1_undriven_sram_inv ;
wire [0:3] mux_right_ipin_2_undriven_sram_inv ;
wire [0:3] mux_right_ipin_3_undriven_sram_inv ;
wire [0:3] mux_right_ipin_4_undriven_sram_inv ;
wire [0:3] mux_right_ipin_5_undriven_sram_inv ;
wire [0:3] mux_right_ipin_6_undriven_sram_inv ;
wire [0:3] mux_right_ipin_7_undriven_sram_inv ;
wire [0:3] mux_right_ipin_8_undriven_sram_inv ;
wire [0:3] mux_right_ipin_9_undriven_sram_inv ;
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
wire [0:3] mux_tree_tapbuf_size10_1_sram ;
wire [0:3] mux_tree_tapbuf_size10_2_sram ;
wire [0:3] mux_tree_tapbuf_size10_3_sram ;
wire [0:3] mux_tree_tapbuf_size10_4_sram ;
wire [0:3] mux_tree_tapbuf_size10_5_sram ;
wire [0:3] mux_tree_tapbuf_size10_6_sram ;
wire [0:3] mux_tree_tapbuf_size10_7_sram ;
wire [0:3] mux_tree_tapbuf_size10_8_sram ;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size8_0_sram ;
wire [0:3] mux_tree_tapbuf_size8_1_sram ;
wire [0:3] mux_tree_tapbuf_size8_2_sram ;
wire [0:3] mux_tree_tapbuf_size8_3_sram ;
wire [0:3] mux_tree_tapbuf_size8_4_sram ;
wire [0:3] mux_tree_tapbuf_size8_5_sram ;
wire [0:3] mux_tree_tapbuf_size8_6_sram ;
wire [0:3] mux_tree_tapbuf_size8_7_sram ;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;

cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 (
    .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , 
        chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , 
        chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , 
        chany_top_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size10_0_sram ) , 
    .sram_inv ( mux_left_ipin_0_undriven_sram_inv ) , 
    .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_100 ) ) ;
cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 (
    .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , 
        chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , 
        chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , 
        chany_top_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size10_1_sram ) , 
    .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , 
    .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_101 ) ) ;
cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_3 (
    .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , 
        chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , 
        chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , 
        chany_top_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size10_2_sram ) , 
    .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , 
    .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_101 ) ) ;
cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_4 (
    .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , 
        chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , 
        chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , 
        chany_top_in[15] } ) ,
    .sram ( mux_tree_tapbuf_size10_3_sram ) , 
    .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , 
    .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_101 ) ) ;
cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_7 (
    .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , 
        chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , 
        chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , 
        chany_top_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size10_4_sram ) , 
    .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , 
    .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_101 ) ) ;
cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_8 (
    .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , 
        chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , 
        chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , 
        chany_top_in[19] } ) ,
    .sram ( mux_tree_tapbuf_size10_5_sram ) , 
    .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , 
    .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_100 ) ) ;
cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_11 (
    .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , 
        chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , 
        chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , 
        chany_top_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size10_6_sram ) , 
    .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , 
    .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_100 ) ) ;
cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_12 (
    .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , 
        chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , 
        chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , 
        chany_top_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size10_7_sram ) , 
    .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , 
    .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_100 ) ) ;
cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_15 (
    .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , 
        chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , 
        chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , 
        chany_top_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size10_8_sram ) , 
    .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , 
    .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_100 ) ) ;
cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
    .ccff_tail ( { ccff_tail_mid } ) ,
    .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 (
    .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , 
        chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , 
        chany_bottom_in[14] , chany_top_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size8_0_sram ) , 
    .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , 
    .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_101 ) ) ;
cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 (
    .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , 
        chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , 
        chany_bottom_in[15] , chany_top_in[15] } ) ,
    .sram ( mux_tree_tapbuf_size8_1_sram ) , 
    .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , 
    .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_101 ) ) ;
cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 (
    .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , 
        chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , 
        chany_bottom_in[18] , chany_top_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size8_2_sram ) , 
    .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , 
    .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_101 ) ) ;
cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 (
    .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , 
        chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , 
        chany_bottom_in[19] , chany_top_in[19] } ) ,
    .sram ( mux_tree_tapbuf_size8_3_sram ) , 
    .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , 
    .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_101 ) ) ;
cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_9 (
    .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , 
        chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , 
        chany_bottom_in[14] , chany_top_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size8_4_sram ) , 
    .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , 
    .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_100 ) ) ;
cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 (
    .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , 
        chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , 
        chany_bottom_in[15] , chany_top_in[15] } ) ,
    .sram ( mux_tree_tapbuf_size8_5_sram ) , 
    .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , 
    .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_100 ) ) ;
cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 (
    .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , 
        chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , 
        chany_bottom_in[18] , chany_top_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size8_6_sram ) , 
    .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , 
    .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_101 ) ) ;
cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 (
    .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , 
        chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , 
        chany_bottom_in[19] , chany_top_in[19] } ) ,
    .sram ( mux_tree_tapbuf_size8_7_sram ) , 
    .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , 
    .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_101 ) ) ;
cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
    .prog_clk ( prog_clk ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , 
    .io_outpad ( left_width_0_height_0__pin_0_ ) ,
    .ccff_head ( { ccff_tail_mid } ) ,
    .io_inpad ( { aps_rename_4_ } ) ,
    .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_104 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_680 ( .A ( ropt_net_102 ) , 
    .X ( left_width_0_height_0__pin_1_lower[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , 
    .X ( chany_top_out[1] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , 
    .HI ( optlc_net_100 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , 
    .X ( chany_top_out[3] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , 
    .HI ( optlc_net_101 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_682 ( 
    .A ( chany_bottom_in[11] ) , .X ( ropt_net_111 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , 
    .X ( chany_top_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_bottom_in[7] ) , 
    .X ( chany_top_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_683 ( .A ( ropt_net_104 ) , 
    .X ( left_width_0_height_0__pin_1_upper[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , 
    .X ( chany_top_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_105 ) , 
    .X ( ropt_net_109 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_109 ) , 
    .X ( chany_bottom_out[8] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , 
    .X ( chany_top_out[12] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chany_bottom_in[2] ) , 
    .X ( chany_top_out[2] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , 
    .X ( chany_top_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , 
    .X ( chany_top_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , 
    .X ( chany_top_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_107 ) , 
    .X ( ropt_net_110 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , 
    .X ( chany_top_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , 
    .X ( chany_top_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , 
    .X ( chany_bottom_out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , 
    .X ( chany_bottom_out[1] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , 
    .X ( chany_bottom_out[2] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , 
    .X ( chany_bottom_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_top_in[4] ) , 
    .X ( chany_bottom_out[4] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , 
    .X ( chany_bottom_out[5] ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chany_top_in[6] ) , 
    .X ( chany_bottom_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( ropt_net_110 ) , 
    .X ( chany_bottom_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_111 ) , 
    .X ( chany_top_out[11] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , 
    .X ( chany_bottom_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , 
    .X ( chany_bottom_out[10] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , 
    .X ( chany_bottom_out[11] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_top_in[12] ) , 
    .X ( aps_rename_3_ ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , 
    .X ( chany_bottom_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_top_in[14] ) , 
    .X ( chany_bottom_out[14] ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 FTB_36__35 ( .A ( chany_top_in[15] ) , 
    .X ( chany_bottom_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_702 ( .A ( ropt_net_112 ) , 
    .X ( chany_top_out[8] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__37 ( .A ( chany_top_in[17] ) , 
    .X ( ropt_net_107 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chany_top_in[19] ) , 
    .X ( chany_bottom_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_65 ( .A ( chany_bottom_in[4] ) , 
    .X ( chany_top_out[4] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_bottom_in[8] ) , 
    .X ( BUF_net_67 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_bottom_in[17] ) , 
    .X ( BUF_net_70 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chany_top_in[7] ) , 
    .X ( chany_bottom_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_top_in[18] ) , 
    .X ( chany_bottom_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_75 ( .A ( aps_rename_4_ ) , 
    .X ( ropt_net_102 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[16] ) , 
    .X ( chany_bottom_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chany_bottom_in[0] ) , 
    .X ( chany_top_out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[10] ) , 
    .X ( chany_top_out[10] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( chany_top_in[8] ) , 
    .X ( ropt_net_105 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_3_ ) , 
    .X ( chany_bottom_out[12] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chany_bottom_in[5] ) , 
    .X ( chany_top_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( BUF_net_67 ) , 
    .X ( ropt_net_112 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_bottom_in[13] ) , 
    .X ( chany_top_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_95 ( .A ( BUF_net_70 ) , 
    .X ( chany_top_out[17] ) ) ;
endmodule


module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_1__1__const1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cby_1__1__const1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cby_1__1__const1_14 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cby_1__1__const1_14 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cby_1__1__const1_13 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cby_1__1__const1_13 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cby_1__1__const1_12 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cby_1__1__const1_12 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cby_1__1__const1_11 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cby_1__1__const1_11 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cby_1__1__const1_10 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cby_1__1__const1_10 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cby_1__1__const1_9 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cby_1__1__const1_9 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cby_1__1__const1_8 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cby_1__1__const1_8 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__49 ( .A ( mem_out[3] ) , 
    .X ( net_net_73 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_100 ( .A ( net_net_73 ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_1__1__const1_7 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cby_1__1__const1_7 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
endmodule


module cby_1__1__const1_6 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cby_1__1__const1_6 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cby_1__1__const1_5 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cby_1__1__const1_5 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cby_1__1__const1_4 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cby_1__1__const1_4 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cby_1__1__const1_3 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cby_1__1__const1_3 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cby_1__1__const1_2 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cby_1__1__const1_2 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cby_1__1__const1_1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cby_1__1__const1_1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cby_1__1__const1_0 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cby_1__1__const1_0 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , 
    chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , 
    left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , 
    left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , 
    left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , 
    left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , 
    left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , 
    grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , 
    grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 , 
    grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , 
    grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ;
input  [0:0] prog_clk ;
input  [0:19] chany_bottom_in ;
input  [0:19] chany_top_in ;
input  [0:0] ccff_head ;
output [0:19] chany_bottom_out ;
output [0:19] chany_top_out ;
output [0:0] left_grid_pin_16_ ;
output [0:0] left_grid_pin_17_ ;
output [0:0] left_grid_pin_18_ ;
output [0:0] left_grid_pin_19_ ;
output [0:0] left_grid_pin_20_ ;
output [0:0] left_grid_pin_21_ ;
output [0:0] left_grid_pin_22_ ;
output [0:0] left_grid_pin_23_ ;
output [0:0] left_grid_pin_24_ ;
output [0:0] left_grid_pin_25_ ;
output [0:0] left_grid_pin_26_ ;
output [0:0] left_grid_pin_27_ ;
output [0:0] left_grid_pin_28_ ;
output [0:0] left_grid_pin_29_ ;
output [0:0] left_grid_pin_30_ ;
output [0:0] left_grid_pin_31_ ;
output [0:0] ccff_tail ;
input  [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ;
output [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ;
input  [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ;
output [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ;

wire [0:3] mux_right_ipin_0_undriven_sram_inv ;
wire [0:3] mux_right_ipin_10_undriven_sram_inv ;
wire [0:3] mux_right_ipin_11_undriven_sram_inv ;
wire [0:3] mux_right_ipin_12_undriven_sram_inv ;
wire [0:3] mux_right_ipin_13_undriven_sram_inv ;
wire [0:3] mux_right_ipin_14_undriven_sram_inv ;
wire [0:3] mux_right_ipin_15_undriven_sram_inv ;
wire [0:3] mux_right_ipin_1_undriven_sram_inv ;
wire [0:3] mux_right_ipin_2_undriven_sram_inv ;
wire [0:3] mux_right_ipin_3_undriven_sram_inv ;
wire [0:3] mux_right_ipin_4_undriven_sram_inv ;
wire [0:3] mux_right_ipin_5_undriven_sram_inv ;
wire [0:3] mux_right_ipin_6_undriven_sram_inv ;
wire [0:3] mux_right_ipin_7_undriven_sram_inv ;
wire [0:3] mux_right_ipin_8_undriven_sram_inv ;
wire [0:3] mux_right_ipin_9_undriven_sram_inv ;
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
wire [0:3] mux_tree_tapbuf_size10_1_sram ;
wire [0:3] mux_tree_tapbuf_size10_2_sram ;
wire [0:3] mux_tree_tapbuf_size10_3_sram ;
wire [0:3] mux_tree_tapbuf_size10_4_sram ;
wire [0:3] mux_tree_tapbuf_size10_5_sram ;
wire [0:3] mux_tree_tapbuf_size10_6_sram ;
wire [0:3] mux_tree_tapbuf_size10_7_sram ;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size8_0_sram ;
wire [0:3] mux_tree_tapbuf_size8_1_sram ;
wire [0:3] mux_tree_tapbuf_size8_2_sram ;
wire [0:3] mux_tree_tapbuf_size8_3_sram ;
wire [0:3] mux_tree_tapbuf_size8_4_sram ;
wire [0:3] mux_tree_tapbuf_size8_5_sram ;
wire [0:3] mux_tree_tapbuf_size8_6_sram ;
wire [0:3] mux_tree_tapbuf_size8_7_sram ;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;

cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 (
    .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , 
        chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , 
        chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , 
        chany_top_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size10_0_sram ) , 
    .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , 
    .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_106 ) ) ;
cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_3 (
    .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , 
        chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , 
        chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , 
        chany_top_in[19] } ) ,
    .sram ( mux_tree_tapbuf_size10_1_sram ) , 
    .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , 
    .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_107 ) ) ;
cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_4 (
    .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , 
        chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , 
        chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , 
        chany_top_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size10_2_sram ) , 
    .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , 
    .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_106 ) ) ;
cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_7 (
    .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , 
        chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , 
        chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , 
        chany_top_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size10_3_sram ) , 
    .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , 
    .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_106 ) ) ;
cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_8 (
    .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , 
        chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , 
        chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , 
        chany_top_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size10_4_sram ) , 
    .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , 
    .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_105 ) ) ;
cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_11 (
    .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , 
        chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , 
        chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , 
        chany_top_in[15] } ) ,
    .sram ( mux_tree_tapbuf_size10_5_sram ) , 
    .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , 
    .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_107 ) ) ;
cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_12 (
    .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , 
        chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , 
        chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , 
        chany_top_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size10_6_sram ) , 
    .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , 
    .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_106 ) ) ;
cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_15 (
    .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , 
        chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , 
        chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , 
        chany_top_in[19] } ) ,
    .sram ( mux_tree_tapbuf_size10_7_sram ) , 
    .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) ,
    .out ( { ropt_net_111 } ) ,
    .p0 ( optlc_net_107 ) ) ;
cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
    .ccff_tail ( { ropt_net_120 } ) ,
    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 (
    .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , 
        chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , 
        chany_bottom_in[13] , chany_top_in[13] } ) ,
    .sram ( mux_tree_tapbuf_size8_0_sram ) , 
    .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , 
    .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_107 ) ) ;
cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 (
    .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , 
        chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , 
        chany_bottom_in[14] , chany_top_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size8_1_sram ) , 
    .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , 
    .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_106 ) ) ;
cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 (
    .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , 
        chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , 
        chany_bottom_in[17] , chany_top_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size8_2_sram ) , 
    .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , 
    .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_106 ) ) ;
cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 (
    .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , 
        chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , 
        chany_bottom_in[18] , chany_top_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size8_3_sram ) , 
    .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , 
    .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_106 ) ) ;
cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_9 (
    .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , 
        chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , 
        chany_bottom_in[13] , chany_top_in[13] } ) ,
    .sram ( mux_tree_tapbuf_size8_4_sram ) , 
    .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , 
    .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_105 ) ) ;
cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 (
    .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , 
        chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , 
        chany_bottom_in[14] , chany_top_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size8_5_sram ) , 
    .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , 
    .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_105 ) ) ;
cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 (
    .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , 
        chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , 
        chany_bottom_in[17] , chany_top_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size8_6_sram ) , 
    .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , 
    .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_105 ) ) ;
cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 (
    .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , 
        chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , 
        chany_bottom_in[18] , chany_top_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size8_7_sram ) , 
    .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , 
    .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_106 ) ) ;
cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , 
    .HI ( optlc_net_105 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , 
    .X ( chany_top_out[1] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , 
    .HI ( optlc_net_106 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , 
    .X ( chany_top_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , 
    .X ( chany_top_out[4] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , 
    .X ( chany_top_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , 
    .X ( chany_top_out[6] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , 
    .HI ( optlc_net_107 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( chany_top_in[11] ) , 
    .X ( ropt_net_127 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , 
    .X ( chany_top_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , 
    .X ( ropt_net_121 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_687 ( 
    .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , 
    .X ( ropt_net_122 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , 
    .X ( chany_top_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , 
    .X ( chany_top_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[18] ) , 
    .X ( chany_bottom_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_111 ) , 
    .X ( ropt_net_131 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , 
    .X ( chany_top_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( chany_top_in[16] ) , 
    .X ( chany_bottom_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( 
    .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , 
    .X ( chany_bottom_out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , 
    .X ( chany_bottom_out[1] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , 
    .X ( chany_bottom_out[2] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , 
    .X ( chany_bottom_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_124 ) , 
    .X ( chany_bottom_out[10] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chany_top_in[5] ) , 
    .X ( aps_rename_2_ ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , 
    .X ( chany_bottom_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_695 ( .A ( chany_top_in[7] ) , 
    .X ( chany_bottom_out[7] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chany_top_in[8] ) , 
    .X ( ropt_net_118 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , 
    .X ( chany_bottom_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_711 ( .A ( ropt_net_125 ) , 
    .X ( chany_bottom_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( chany_top_in[10] ) , 
    .X ( ropt_net_124 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_top_in[12] ) , 
    .X ( aps_rename_3_ ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , 
    .X ( chany_bottom_out[13] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chany_top_in[14] ) , 
    .X ( ropt_net_116 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chany_top_in[15] ) , 
    .X ( chany_bottom_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_697 ( .A ( ropt_net_116 ) , 
    .X ( ropt_net_125 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chany_top_in[17] ) , 
    .X ( ropt_net_130 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_126 ) , 
    .X ( chany_top_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_117 ) , 
    .X ( chany_top_out[11] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_118 ) , 
    .X ( ropt_net_129 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_119 ) , 
    .X ( ropt_net_126 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_60 ( .A ( chany_bottom_in[11] ) , 
    .X ( ropt_net_117 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( ropt_net_127 ) , 
    .X ( chany_bottom_out[11] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_120 ) , 
    .X ( ccff_tail[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_128 ) , 
    .X ( chany_bottom_out[4] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[19] ) , 
    .X ( ropt_net_119 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chany_top_in[4] ) , 
    .X ( BUF_net_65 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_121 ) , 
    .X ( chany_top_out[10] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( ropt_net_129 ) , 
    .X ( chany_bottom_out[8] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_130 ) , 
    .X ( chany_bottom_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_122 ) , 
    .X ( chany_top_out[12] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( ropt_net_131 ) , 
    .X ( left_grid_pin_31_[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_bottom_in[7] ) , 
    .X ( chany_top_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_65 ) , 
    .X ( ropt_net_128 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_80 ( .A ( aps_rename_3_ ) , 
    .X ( chany_bottom_out[12] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_top_in[19] ) , 
    .X ( chany_bottom_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_bottom_in[0] ) , 
    .X ( chany_top_out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chany_bottom_in[2] ) , 
    .X ( chany_top_out[2] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chany_bottom_in[8] ) , 
    .X ( chany_top_out[8] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_91 ( 
    .A ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , 
    .X ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( 
    .A ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , 
    .X ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[16] ) , 
    .X ( chany_top_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_94 ( .A ( aps_rename_2_ ) , 
    .X ( chany_bottom_out[5] ) ) ;
endmodule


module cby_0__1__direct_interc ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

assign out[0] = in[0] ;
endmodule


module cby_0__1__direct_interc_0 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
    ccff_head , ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:0] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) , 
    .X ( net_net_86 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_127 ( .A ( net_net_86 ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_0__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
    FPGA_OUT , FPGA_DIR , p_abuf0 ) ;
input  SOC_IN ;
output SOC_OUT ;
output SOC_DIR ;
output FPGA_IN ;
input  FPGA_OUT ;
input  FPGA_DIR ;
output p_abuf0 ;

wire aps_rename_1_ ;

assign SOC_OUT = FPGA_OUT ;

sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , 
    .X ( aps_rename_1_ ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_155 ( .A ( aps_rename_1_ ) , 
    .X ( SOC_DIR ) ) ;
endmodule


module cby_0__1__logical_tile_io_mode_physical__iopad ( prog_clk , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , 
    ccff_tail , p_abuf0 ) ;
input  [0:0] prog_clk ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] iopad_outpad ;
input  [0:0] ccff_head ;
output [0:0] iopad_inpad ;
output [0:0] ccff_tail ;
output p_abuf0 ;

wire [0:0] EMBEDDED_IO_0_en ;

cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ ( 
    .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , 
    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , 
    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , 
    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
    .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ;
cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ;
endmodule


module cby_0__1__logical_tile_io_mode_io_ ( prog_clk , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , 
    ccff_tail , p_abuf0 ) ;
input  [0:0] prog_clk ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] io_outpad ;
input  [0:0] ccff_head ;
output [0:0] io_inpad ;
output [0:0] ccff_tail ;
output p_abuf0 ;

cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
    .prog_clk ( prog_clk ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , 
    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , 
    .p_abuf0 ( p_abuf0 ) ) ;
cby_0__1__direct_interc_0 direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ;
cby_0__1__direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( io_outpad ) ) ;
endmodule


module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cby_0__1__const1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cby_0__1__const1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , 
    chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , 
    right_width_0_height_0__pin_1_upper , 
    right_width_0_height_0__pin_1_lower ) ;
input  [0:0] prog_clk ;
input  [0:19] chany_bottom_in ;
input  [0:19] chany_top_in ;
input  [0:0] ccff_head ;
output [0:19] chany_bottom_out ;
output [0:19] chany_top_out ;
output [0:0] left_grid_pin_0_ ;
output [0:0] ccff_tail ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] right_width_0_height_0__pin_0_ ;
output [0:0] right_width_0_height_0__pin_1_upper ;
output [0:0] right_width_0_height_0__pin_1_lower ;

wire ropt_net_162 ;
wire [0:3] mux_right_ipin_0_undriven_sram_inv ;
wire [0:3] mux_tree_tapbuf_size10_0_sram ;

cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 (
    .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , 
        chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , 
        chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , 
        chany_top_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size10_0_sram ) , 
    .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , 
    .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_157 ) ) ;
cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
    .ccff_tail ( { ccff_tail_mid } ) ,
    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
    .prog_clk ( prog_clk ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) ,
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_170 } ) ,
    .io_outpad ( right_width_0_height_0__pin_0_ ) ,
    .ccff_head ( { ccff_tail_mid } ) ,
    .io_inpad ( { aps_rename_13_ } ) ,
    .ccff_tail ( { ropt_net_166 } ) ,
    .p_abuf0 ( ropt_net_162 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_196 ) , 
    .X ( chany_bottom_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_197 ) , 
    .X ( chany_top_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_198 ) , 
    .X ( chany_bottom_out[4] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , 
    .HI ( optlc_net_157 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_199 ) , 
    .X ( chany_bottom_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_200 ) , 
    .X ( chany_top_out[10] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_201 ) , 
    .X ( chany_bottom_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( BUF_net_84 ) , 
    .X ( ropt_net_211 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_top_in[12] ) , 
    .X ( ropt_net_227 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_202 ) , 
    .X ( chany_bottom_out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) , 
    .X ( chany_top_out[11] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_203 ) , 
    .X ( chany_top_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chany_top_in[18] ) , 
    .X ( chany_bottom_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) , 
    .X ( ropt_net_213 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chany_top_in[8] ) , 
    .X ( ropt_net_223 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( chany_top_in[9] ) , 
    .X ( ropt_net_201 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_204 ) , 
    .X ( chany_top_out[12] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_205 ) , 
    .X ( chany_bottom_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_206 ) , 
    .X ( chany_top_out[8] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[5] ) , 
    .X ( chany_bottom_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_166 ) , 
    .X ( ropt_net_218 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( 
    .A ( chany_bottom_in[17] ) , .X ( ropt_net_220 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__22 ( .A ( chany_top_in[2] ) , 
    .X ( ropt_net_191 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chany_bottom_in[5] ) , 
    .X ( ropt_net_225 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chany_top_in[4] ) , 
    .X ( ropt_net_187 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( chany_top_in[11] ) , 
    .X ( ropt_net_224 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_170 ) , 
    .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chany_top_in[14] ) , 
    .X ( ropt_net_229 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( 
    .A ( chany_bottom_in[18] ) , .X ( ropt_net_222 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chany_bottom_in[6] ) , 
    .X ( ropt_net_219 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chany_bottom_in[1] ) , 
    .X ( ropt_net_228 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( chany_bottom_in[7] ) , 
    .X ( ropt_net_221 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chany_top_in[13] ) , 
    .X ( ropt_net_199 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( chany_top_in[15] ) , 
    .X ( ropt_net_226 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) , 
    .X ( ropt_net_203 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( chany_top_in[7] ) , 
    .X ( chany_bottom_out[7] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chany_top_in[16] ) , 
    .X ( ropt_net_193 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) , 
    .X ( ropt_net_197 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) , 
    .X ( ropt_net_200 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) , 
    .X ( ropt_net_204 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) , 
    .X ( ropt_net_196 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_47 ( .A ( chany_bottom_in[0] ) , 
    .X ( BUF_net_47 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) , 
    .X ( ropt_net_206 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( chany_bottom_in[2] ) , 
    .X ( BUF_net_49 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) , 
    .X ( ropt_net_208 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( chany_bottom_in[4] ) , 
    .X ( BUF_net_51 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) , 
    .X ( ropt_net_202 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) , 
    .X ( ropt_net_198 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_207 ) , 
    .X ( chany_bottom_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) , 
    .X ( ropt_net_209 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chany_bottom_in[9] ) , 
    .X ( BUF_net_56 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) , 
    .X ( ropt_net_215 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , 
    .X ( ropt_net_160 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) , 
    .X ( ropt_net_207 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) , 
    .X ( ropt_net_212 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) , 
    .X ( ropt_net_210 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , 
    .X ( ropt_net_178 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( chany_bottom_in[16] ) , 
    .X ( BUF_net_63 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) , 
    .X ( ropt_net_205 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_208 ) , 
    .X ( chany_top_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_209 ) , 
    .X ( chany_bottom_out[1] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_210 ) , 
    .X ( chany_top_out[14] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_68 ( .A ( chany_top_in[1] ) , 
    .X ( ropt_net_188 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_211 ) , 
    .X ( right_width_0_height_0__pin_1_lower[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_212 ) , 
    .X ( chany_bottom_out[2] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_213 ) , 
    .X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_214 ) , 
    .X ( chany_top_out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_215 ) , 
    .X ( chany_bottom_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_216 ) , 
    .X ( chany_top_out[2] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_217 ) , 
    .X ( chany_top_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_218 ) , 
    .X ( ccff_tail[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_219 ) , 
    .X ( chany_top_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_220 ) , 
    .X ( chany_top_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_221 ) , 
    .X ( chany_top_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_222 ) , 
    .X ( chany_top_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_223 ) , 
    .X ( chany_bottom_out[8] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_224 ) , 
    .X ( chany_bottom_out[11] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_225 ) , 
    .X ( chany_top_out[5] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( aps_rename_13_ ) , 
    .X ( BUF_net_84 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( BUF_net_47 ) , 
    .X ( ropt_net_214 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_226 ) , 
    .X ( chany_bottom_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_227 ) , 
    .X ( chany_bottom_out[12] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( BUF_net_51 ) , 
    .X ( chany_top_out[4] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_228 ) , 
    .X ( chany_top_out[1] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_229 ) , 
    .X ( chany_bottom_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_96 ( .A ( BUF_net_56 ) , 
    .X ( chany_top_out[9] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_106 ( .A ( chany_top_in[0] ) , 
    .X ( ropt_net_186 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_49 ) , 
    .X ( ropt_net_216 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( .A ( BUF_net_63 ) , 
    .X ( ropt_net_217 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( .A ( chany_top_in[10] ) , 
    .X ( chany_bottom_out[10] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_129 ( .A ( chany_bottom_in[3] ) , 
    .X ( chany_top_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_bottom_in[8] ) , 
    .X ( ropt_net_184 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_132 ( .A ( chany_bottom_in[10] ) , 
    .X ( ropt_net_181 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_133 ( .A ( chany_bottom_in[12] ) , 
    .X ( ropt_net_182 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chany_bottom_in[13] ) , 
    .X ( ropt_net_180 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_135 ( .A ( chany_bottom_in[14] ) , 
    .X ( ropt_net_192 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chany_bottom_in[19] ) , 
    .X ( ropt_net_185 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_140 ( .A ( chany_top_in[3] ) , 
    .X ( ropt_net_183 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_142 ( .A ( chany_top_in[6] ) , 
    .X ( ropt_net_190 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_151 ( .A ( chany_top_in[17] ) , 
    .X ( chany_bottom_out[17] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_153 ( .A ( chany_top_in[19] ) , 
    .X ( ropt_net_189 ) ) ;
endmodule


module cbx_1__2__direct_interc ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

assign out[0] = in[0] ;
endmodule


module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
    ccff_head , ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:0] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__61 ( .A ( mem_out[0] ) , 
    .X ( net_net_77 ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_77 ( .A ( net_net_77 ) , 
    .X ( net_net_76 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( net_net_76 ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__2__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
    FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ;
input  SOC_IN ;
output SOC_OUT ;
output SOC_DIR ;
output FPGA_IN ;
input  FPGA_OUT ;
input  FPGA_DIR ;
output p_abuf0 ;
output p_abuf1 ;

assign SOC_OUT = FPGA_OUT ;

sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ;
endmodule


module cbx_1__2__logical_tile_io_mode_physical__iopad ( prog_clk , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , 
    ccff_tail , p_abuf0 , p_abuf1 ) ;
input  [0:0] prog_clk ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] iopad_outpad ;
input  [0:0] ccff_head ;
output [0:0] iopad_inpad ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf1 ;

wire [0:0] EMBEDDED_IO_0_en ;

cbx_1__2__EMBEDDED_IO EMBEDDED_IO_0_ ( 
    .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , 
    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , 
    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , 
    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
    .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , 
    .p_abuf1 ( p_abuf1 ) ) ;
cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ;
endmodule


module cbx_1__2__logical_tile_io_mode_io_ ( prog_clk , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , 
    ccff_tail , p_abuf0 ) ;
input  [0:0] prog_clk ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] io_outpad ;
input  [0:0] ccff_head ;
output [0:0] io_inpad ;
output [0:0] ccff_tail ;
output p_abuf0 ;

cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
    .prog_clk ( prog_clk ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , 
    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , 
    .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ;
cbx_1__2__direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( { p_abuf1 } ) ) ;
cbx_1__2__direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .out ( io_outpad ) ) ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__58 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__56 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__55 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__53 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__52 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__51 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__2__const1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cbx_1__2__const1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cbx_1__2__const1_15 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cbx_1__2__const1_15 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cbx_1__2__const1_14 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cbx_1__2__const1_14 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cbx_1__2__const1_13 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cbx_1__2__const1_13 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cbx_1__2__const1_12 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cbx_1__2__const1_12 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cbx_1__2__const1_11 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cbx_1__2__const1_11 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cbx_1__2__const1_10 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cbx_1__2__const1_10 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cbx_1__2__const1_9 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cbx_1__2__const1_9 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__50 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__49 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__48 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__47 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__46 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__45 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__44 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__43 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__2__const1_8 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__2__const1_8 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cbx_1__2__const1_7 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__2__const1_7 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cbx_1__2__const1_6 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__2__const1_6 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cbx_1__2__const1_5 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__2__const1_5 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cbx_1__2__const1_4 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__2__const1_4 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cbx_1__2__const1_3 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__2__const1_3 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cbx_1__2__const1_2 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__2__const1_2 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cbx_1__2__const1_1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__2__const1_1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
endmodule


module cbx_1__2__const1_0 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__2__const1_0 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , 
    chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , 
    bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , 
    bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , 
    bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , 
    bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , 
    bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , 
    ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , bottom_width_0_height_0__pin_0_ , 
    bottom_width_0_height_0__pin_1_upper , 
    bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_IN_BOT , 
    SC_OUT_TOP , SC_OUT_BOT ) ;
input  [0:0] prog_clk ;
input  [0:19] chanx_left_in ;
input  [0:19] chanx_right_in ;
input  [0:0] ccff_head ;
output [0:19] chanx_left_out ;
output [0:19] chanx_right_out ;
output [0:0] top_grid_pin_0_ ;
output [0:0] bottom_grid_pin_0_ ;
output [0:0] bottom_grid_pin_1_ ;
output [0:0] bottom_grid_pin_2_ ;
output [0:0] bottom_grid_pin_3_ ;
output [0:0] bottom_grid_pin_4_ ;
output [0:0] bottom_grid_pin_5_ ;
output [0:0] bottom_grid_pin_6_ ;
output [0:0] bottom_grid_pin_7_ ;
output [0:0] bottom_grid_pin_8_ ;
output [0:0] bottom_grid_pin_9_ ;
output [0:0] bottom_grid_pin_10_ ;
output [0:0] bottom_grid_pin_11_ ;
output [0:0] bottom_grid_pin_12_ ;
output [0:0] bottom_grid_pin_13_ ;
output [0:0] bottom_grid_pin_14_ ;
output [0:0] bottom_grid_pin_15_ ;
output [0:0] ccff_tail ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] bottom_width_0_height_0__pin_0_ ;
output [0:0] bottom_width_0_height_0__pin_1_upper ;
output [0:0] bottom_width_0_height_0__pin_1_lower ;
input  SC_IN_TOP ;
input  SC_IN_BOT ;
output SC_OUT_TOP ;
output SC_OUT_BOT ;

wire ropt_net_112 ;
wire [0:3] mux_bottom_ipin_0_undriven_sram_inv ;
wire [0:3] mux_top_ipin_0_undriven_sram_inv ;
wire [0:3] mux_top_ipin_10_undriven_sram_inv ;
wire [0:3] mux_top_ipin_11_undriven_sram_inv ;
wire [0:3] mux_top_ipin_12_undriven_sram_inv ;
wire [0:3] mux_top_ipin_13_undriven_sram_inv ;
wire [0:3] mux_top_ipin_14_undriven_sram_inv ;
wire [0:3] mux_top_ipin_15_undriven_sram_inv ;
wire [0:3] mux_top_ipin_1_undriven_sram_inv ;
wire [0:3] mux_top_ipin_2_undriven_sram_inv ;
wire [0:3] mux_top_ipin_3_undriven_sram_inv ;
wire [0:3] mux_top_ipin_4_undriven_sram_inv ;
wire [0:3] mux_top_ipin_5_undriven_sram_inv ;
wire [0:3] mux_top_ipin_6_undriven_sram_inv ;
wire [0:3] mux_top_ipin_7_undriven_sram_inv ;
wire [0:3] mux_top_ipin_8_undriven_sram_inv ;
wire [0:3] mux_top_ipin_9_undriven_sram_inv ;
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
wire [0:3] mux_tree_tapbuf_size10_1_sram ;
wire [0:3] mux_tree_tapbuf_size10_2_sram ;
wire [0:3] mux_tree_tapbuf_size10_3_sram ;
wire [0:3] mux_tree_tapbuf_size10_4_sram ;
wire [0:3] mux_tree_tapbuf_size10_5_sram ;
wire [0:3] mux_tree_tapbuf_size10_6_sram ;
wire [0:3] mux_tree_tapbuf_size10_7_sram ;
wire [0:3] mux_tree_tapbuf_size10_8_sram ;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size8_0_sram ;
wire [0:3] mux_tree_tapbuf_size8_1_sram ;
wire [0:3] mux_tree_tapbuf_size8_2_sram ;
wire [0:3] mux_tree_tapbuf_size8_3_sram ;
wire [0:3] mux_tree_tapbuf_size8_4_sram ;
wire [0:3] mux_tree_tapbuf_size8_5_sram ;
wire [0:3] mux_tree_tapbuf_size8_6_sram ;
wire [0:3] mux_tree_tapbuf_size8_7_sram ;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;

assign SC_IN_TOP = SC_IN_BOT ;

cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , 
        chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , 
        chanx_right_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size10_0_sram ) , 
    .sram_inv ( mux_bottom_ipin_0_undriven_sram_inv ) , 
    .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_110 ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 (
    .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , 
        chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , 
        chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , 
        chanx_right_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size10_1_sram ) , 
    .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) ,
    .out ( { ropt_net_116 } ) ,
    .p0 ( optlc_net_110 ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_3 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , 
        chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , 
        chanx_right_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size10_2_sram ) , 
    .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_108 ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_4 (
    .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , 
        chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , 
        chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , 
        chanx_right_in[15] } ) ,
    .sram ( mux_tree_tapbuf_size10_3_sram ) , 
    .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_111 ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_7 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , 
        chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , 
        chanx_right_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size10_4_sram ) , 
    .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_109 ) ) ;
cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_8 (
    .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , 
        chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , 
        chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , 
        chanx_right_in[19] } ) ,
    .sram ( mux_tree_tapbuf_size10_5_sram ) , 
    .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_108 ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_11 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , 
        chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , 
        chanx_right_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size10_6_sram ) , 
    .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_110 ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_12 (
    .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , 
        chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , 
        chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , 
        chanx_right_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size10_7_sram ) , 
    .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_111 ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_15 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , 
        chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , 
        chanx_right_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size10_8_sram ) , 
    .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_110 ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
    .ccff_tail ( { ccff_tail_mid } ) ,
    .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , 
        chanx_left_in[14] , chanx_right_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size8_0_sram ) , 
    .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_111 ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_2 (
    .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , 
        chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , 
        chanx_left_in[15] , chanx_right_in[15] } ) ,
    .sram ( mux_tree_tapbuf_size8_1_sram ) , 
    .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_108 ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_5 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , 
        chanx_left_in[18] , chanx_right_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size8_2_sram ) , 
    .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_109 ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_6 (
    .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , 
        chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , 
        chanx_left_in[19] , chanx_right_in[19] } ) ,
    .sram ( mux_tree_tapbuf_size8_3_sram ) , 
    .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_111 ) ) ;
cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_9 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , 
        chanx_left_in[14] , chanx_right_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size8_4_sram ) , 
    .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_108 ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_10 (
    .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , 
        chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , 
        chanx_left_in[15] , chanx_right_in[15] } ) ,
    .sram ( mux_tree_tapbuf_size8_5_sram ) , 
    .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_108 ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_13 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , 
        chanx_left_in[18] , chanx_right_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size8_6_sram ) , 
    .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_109 ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_14 (
    .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , 
        chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , 
        chanx_left_in[19] , chanx_right_in[19] } ) ,
    .sram ( mux_tree_tapbuf_size8_7_sram ) , 
    .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_111 ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
    .prog_clk ( prog_clk ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) ,
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_119 } ) ,
    .io_outpad ( bottom_width_0_height_0__pin_0_ ) ,
    .ccff_head ( { ccff_tail_mid } ) ,
    .io_inpad ( { aps_rename_3_ } ) ,
    .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_112 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , 
    .X ( chanx_right_out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_137 ) , 
    .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , 
    .HI ( optlc_net_108 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , 
    .X ( ropt_net_151 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , 
    .X ( ropt_net_130 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_138 ) , 
    .X ( chanx_left_out[13] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , 
    .HI ( optlc_net_109 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , 
    .HI ( optlc_net_110 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , 
    .X ( ropt_net_149 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , 
    .HI ( optlc_net_111 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_697 ( .A ( ropt_net_112 ) , 
    .X ( ropt_net_137 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , 
    .X ( chanx_right_out[11] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , 
    .X ( ropt_net_123 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , 
    .X ( ropt_net_147 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , 
    .X ( chanx_right_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , 
    .X ( chanx_right_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , 
    .X ( chanx_right_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_698 ( .A ( ropt_net_113 ) , 
    .X ( SC_OUT_BOT ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , 
    .X ( chanx_right_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , 
    .X ( ropt_net_131 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , 
    .X ( chanx_left_out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( chanx_right_in[16] ) , 
    .X ( chanx_left_out[16] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , 
    .X ( ropt_net_133 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , 
    .X ( ropt_net_150 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , 
    .X ( chanx_left_out[4] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( chanx_right_in[5] ) , 
    .X ( chanx_left_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , 
    .X ( chanx_left_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_139 ) , 
    .X ( chanx_left_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , 
    .X ( chanx_left_out[8] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_140 ) , 
    .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , 
    .X ( chanx_left_out[10] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , 
    .X ( chanx_left_out[11] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_116 ) , 
    .X ( ropt_net_143 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , 
    .X ( ropt_net_134 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_117 ) , 
    .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( chanx_right_in[12] ) , 
    .X ( chanx_left_out[12] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( ropt_net_119 ) , 
    .X ( ropt_net_140 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_120 ) , 
    .X ( ropt_net_144 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( chanx_right_in[15] ) , 
    .X ( chanx_left_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , 
    .X ( chanx_left_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_141 ) , 
    .X ( chanx_right_out[12] ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , 
    .X ( ropt_net_113 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_65 ( .A ( chanx_left_in[17] ) , 
    .X ( chanx_right_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chanx_right_in[1] ) , 
    .X ( chanx_left_out[1] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_142 ) , 
    .X ( chanx_left_out[2] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_143 ) , 
    .X ( bottom_grid_pin_0_[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_144 ) , 
    .X ( chanx_left_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_145 ) , 
    .X ( chanx_right_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_146 ) , 
    .X ( chanx_left_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_147 ) , 
    .X ( chanx_right_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_left_in[7] ) , 
    .X ( chanx_right_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_123 ) , 
    .X ( ropt_net_141 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_75 ( .A ( aps_rename_3_ ) , 
    .X ( ropt_net_117 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_left_in[1] ) , 
    .X ( chanx_right_out[1] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chanx_right_in[7] ) , 
    .X ( ropt_net_148 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_left_in[5] ) , 
    .X ( chanx_right_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( chanx_left_in[10] ) , 
    .X ( chanx_right_out[10] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_128 ) , 
    .X ( ropt_net_145 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( chanx_right_in[14] ) , 
    .X ( ropt_net_139 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chanx_left_in[2] ) , 
    .X ( chanx_right_out[2] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_left_in[6] ) , 
    .X ( ropt_net_132 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_148 ) , 
    .X ( chanx_left_out[7] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( chanx_left_in[9] ) , 
    .X ( ropt_net_128 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_149 ) , 
    .X ( chanx_right_out[8] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_94 ( .A ( chanx_right_in[9] ) , 
    .X ( ropt_net_120 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_130 ) , 
    .X ( chanx_right_out[4] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_150 ) , 
    .X ( chanx_left_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_151 ) , 
    .X ( chanx_right_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_131 ) , 
    .X ( chanx_right_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_132 ) , 
    .X ( chanx_right_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( chanx_right_in[17] ) , 
    .X ( ropt_net_146 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[18] ) , 
    .X ( chanx_left_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_133 ) , 
    .X ( ropt_net_142 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_134 ) , 
    .X ( ropt_net_138 ) ) ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__56 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__55 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__54 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__53 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__52 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__51 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__50 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__49 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__1__const1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cbx_1__1__const1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cbx_1__1__const1_14 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cbx_1__1__const1_14 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cbx_1__1__const1_13 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cbx_1__1__const1_13 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cbx_1__1__const1_12 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cbx_1__1__const1_12 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cbx_1__1__const1_11 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cbx_1__1__const1_11 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cbx_1__1__const1_10 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cbx_1__1__const1_10 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cbx_1__1__const1_9 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cbx_1__1__const1_9 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module cbx_1__1__const1_8 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

cbx_1__1__const1_8 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( BUF_net_58 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_58 ) , 
    .X ( out[0] ) ) ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__48 ( .A ( mem_out[3] ) , 
    .X ( net_net_75 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( net_net_75 ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__47 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__46 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__45 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__1__const1_7 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__1__const1_7 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cbx_1__1__const1_6 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;

cbx_1__1__const1_6 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ;
endmodule


module cbx_1__1__const1_5 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__1__const1_5 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cbx_1__1__const1_4 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__1__const1_4 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cbx_1__1__const1_3 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__1__const1_3 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cbx_1__1__const1_2 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__1__const1_2 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cbx_1__1__const1_1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__1__const1_1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cbx_1__1__const1_0 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__1__const1_0 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , 
    chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , 
    bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , 
    bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , 
    bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , 
    bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , 
    bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , 
    ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ) ;
input  [0:0] prog_clk ;
input  [0:19] chanx_left_in ;
input  [0:19] chanx_right_in ;
input  [0:0] ccff_head ;
output [0:19] chanx_left_out ;
output [0:19] chanx_right_out ;
output [0:0] bottom_grid_pin_0_ ;
output [0:0] bottom_grid_pin_1_ ;
output [0:0] bottom_grid_pin_2_ ;
output [0:0] bottom_grid_pin_3_ ;
output [0:0] bottom_grid_pin_4_ ;
output [0:0] bottom_grid_pin_5_ ;
output [0:0] bottom_grid_pin_6_ ;
output [0:0] bottom_grid_pin_7_ ;
output [0:0] bottom_grid_pin_8_ ;
output [0:0] bottom_grid_pin_9_ ;
output [0:0] bottom_grid_pin_10_ ;
output [0:0] bottom_grid_pin_11_ ;
output [0:0] bottom_grid_pin_12_ ;
output [0:0] bottom_grid_pin_13_ ;
output [0:0] bottom_grid_pin_14_ ;
output [0:0] bottom_grid_pin_15_ ;
output [0:0] ccff_tail ;
input  SC_IN_TOP ;
input  SC_IN_BOT ;
output SC_OUT_TOP ;
output SC_OUT_BOT ;

wire [0:3] mux_top_ipin_0_undriven_sram_inv ;
wire [0:3] mux_top_ipin_10_undriven_sram_inv ;
wire [0:3] mux_top_ipin_11_undriven_sram_inv ;
wire [0:3] mux_top_ipin_12_undriven_sram_inv ;
wire [0:3] mux_top_ipin_13_undriven_sram_inv ;
wire [0:3] mux_top_ipin_14_undriven_sram_inv ;
wire [0:3] mux_top_ipin_15_undriven_sram_inv ;
wire [0:3] mux_top_ipin_1_undriven_sram_inv ;
wire [0:3] mux_top_ipin_2_undriven_sram_inv ;
wire [0:3] mux_top_ipin_3_undriven_sram_inv ;
wire [0:3] mux_top_ipin_4_undriven_sram_inv ;
wire [0:3] mux_top_ipin_5_undriven_sram_inv ;
wire [0:3] mux_top_ipin_6_undriven_sram_inv ;
wire [0:3] mux_top_ipin_7_undriven_sram_inv ;
wire [0:3] mux_top_ipin_8_undriven_sram_inv ;
wire [0:3] mux_top_ipin_9_undriven_sram_inv ;
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
wire [0:3] mux_tree_tapbuf_size10_1_sram ;
wire [0:3] mux_tree_tapbuf_size10_2_sram ;
wire [0:3] mux_tree_tapbuf_size10_3_sram ;
wire [0:3] mux_tree_tapbuf_size10_4_sram ;
wire [0:3] mux_tree_tapbuf_size10_5_sram ;
wire [0:3] mux_tree_tapbuf_size10_6_sram ;
wire [0:3] mux_tree_tapbuf_size10_7_sram ;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size8_0_sram ;
wire [0:3] mux_tree_tapbuf_size8_1_sram ;
wire [0:3] mux_tree_tapbuf_size8_2_sram ;
wire [0:3] mux_tree_tapbuf_size8_3_sram ;
wire [0:3] mux_tree_tapbuf_size8_4_sram ;
wire [0:3] mux_tree_tapbuf_size8_5_sram ;
wire [0:3] mux_tree_tapbuf_size8_6_sram ;
wire [0:3] mux_tree_tapbuf_size8_7_sram ;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;

assign SC_IN_TOP = SC_IN_BOT ;

cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , 
        chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , 
        chanx_right_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size10_0_sram ) , 
    .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_120 ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_3 (
    .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , 
        chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , 
        chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , 
        chanx_right_in[19] } ) ,
    .sram ( mux_tree_tapbuf_size10_1_sram ) , 
    .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_121 ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_4 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , 
        chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , 
        chanx_right_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size10_2_sram ) , 
    .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_120 ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_7 (
    .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , 
        chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , 
        chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , 
        chanx_right_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size10_3_sram ) , 
    .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_121 ) ) ;
cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_8 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , 
        chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , 
        chanx_right_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size10_4_sram ) , 
    .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_120 ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_11 (
    .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , 
        chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , 
        chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , 
        chanx_right_in[15] } ) ,
    .sram ( mux_tree_tapbuf_size10_5_sram ) , 
    .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_122 ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_12 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , 
        chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , 
        chanx_right_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size10_6_sram ) , 
    .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_120 ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_15 (
    .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , 
        chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , 
        chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , 
        chanx_right_in[19] } ) ,
    .sram ( mux_tree_tapbuf_size10_7_sram ) , 
    .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_121 ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
    .ccff_tail ( { ropt_net_132 } ) ,
    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 (
    .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , 
        chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , 
        chanx_left_in[13] , chanx_right_in[13] } ) ,
    .sram ( mux_tree_tapbuf_size8_0_sram ) , 
    .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_122 ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_2 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , 
        chanx_left_in[14] , chanx_right_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size8_1_sram ) , 
    .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_120 ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_5 (
    .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , 
        chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , 
        chanx_left_in[17] , chanx_right_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size8_2_sram ) , 
    .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_121 ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_6 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , 
        chanx_left_in[18] , chanx_right_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size8_3_sram ) , 
    .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_120 ) ) ;
cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_9 (
    .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , 
        chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , 
        chanx_left_in[13] , chanx_right_in[13] } ) ,
    .sram ( mux_tree_tapbuf_size8_4_sram ) , 
    .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_122 ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_10 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , 
        chanx_left_in[14] , chanx_right_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size8_5_sram ) , 
    .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_120 ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_13 (
    .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , 
        chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , 
        chanx_left_in[17] , chanx_right_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size8_6_sram ) , 
    .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_121 ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_14 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , 
        chanx_left_in[18] , chanx_right_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size8_7_sram ) , 
    .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_120 ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , 
    .HI ( optlc_net_120 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_151 ) , 
    .X ( chanx_left_out[0] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , 
    .HI ( optlc_net_121 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , 
    .X ( chanx_right_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , 
    .X ( ropt_net_161 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , 
    .HI ( optlc_net_122 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , 
    .X ( ropt_net_145 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , 
    .X ( ropt_net_142 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_123 ) , 
    .X ( SC_OUT_BOT ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_right_in[11] ) , 
    .X ( chanx_left_out[11] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , 
    .X ( chanx_right_out[10] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , 
    .X ( chanx_right_out[11] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( chanx_right_in[6] ) , 
    .X ( chanx_left_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , 
    .X ( ropt_net_160 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , 
    .X ( chanx_right_out[14] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , 
    .X ( ropt_net_146 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_126 ) , 
    .X ( ropt_net_157 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , 
    .X ( ropt_net_144 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , 
    .X ( ropt_net_149 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chanx_left_in[19] ) , 
    .X ( chanx_right_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[4] ) , 
    .X ( chanx_left_out[4] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , 
    .X ( chanx_left_out[1] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , 
    .X ( ropt_net_165 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[17] ) , 
    .X ( ropt_net_152 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[12] ) , 
    .X ( chanx_left_out[12] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_152 ) , 
    .X ( chanx_left_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( chanx_right_in[7] ) , 
    .X ( ropt_net_166 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( ropt_net_132 ) , 
    .X ( ropt_net_162 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , 
    .X ( ropt_net_164 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , 
    .X ( ropt_net_143 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( chanx_right_in[5] ) , 
    .X ( chanx_left_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[14] ) , 
    .X ( chanx_left_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chanx_right_in[15] ) , 
    .X ( ropt_net_163 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , 
    .X ( ropt_net_159 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[16] ) , 
    .X ( ropt_net_156 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chanx_left_in[5] ) , 
    .X ( chanx_right_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[0] ) , 
    .X ( chanx_right_out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_left_in[1] ) , 
    .X ( chanx_right_out[1] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , 
    .X ( chanx_left_out[18] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , 
    .X ( ropt_net_150 ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , 
    .X ( ropt_net_123 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_153 ) , 
    .X ( chanx_left_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_154 ) , 
    .X ( chanx_right_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_155 ) , 
    .X ( chanx_right_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[16] ) , 
    .X ( chanx_right_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_right_in[3] ) , 
    .X ( ropt_net_153 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_156 ) , 
    .X ( chanx_left_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[12] ) , 
    .X ( chanx_right_out[12] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_142 ) , 
    .X ( chanx_right_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_157 ) , 
    .X ( chanx_right_out[8] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_158 ) , 
    .X ( chanx_right_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_159 ) , 
    .X ( chanx_left_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_160 ) , 
    .X ( chanx_right_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_161 ) , 
    .X ( chanx_right_out[4] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_143 ) , 
    .X ( chanx_left_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_144 ) , 
    .X ( chanx_right_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_145 ) , 
    .X ( ropt_net_154 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_146 ) , 
    .X ( ropt_net_158 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_147 ) , 
    .X ( ropt_net_151 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_148 ) , 
    .X ( chanx_right_out[2] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_149 ) , 
    .X ( ropt_net_155 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_150 ) , 
    .X ( ropt_net_167 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_162 ) , 
    .X ( ccff_tail[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_163 ) , 
    .X ( chanx_left_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_164 ) , 
    .X ( chanx_left_out[8] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_165 ) , 
    .X ( chanx_left_out[2] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_166 ) , 
    .X ( chanx_left_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_167 ) , 
    .X ( chanx_left_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chanx_left_in[2] ) , 
    .X ( ropt_net_148 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chanx_left_in[9] ) , 
    .X ( chanx_right_out[9] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_98 ( .A ( chanx_right_in[0] ) , 
    .X ( ropt_net_147 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chanx_right_in[10] ) , 
    .X ( chanx_left_out[10] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_103 ( .A ( chanx_left_in[8] ) , 
    .X ( ropt_net_126 ) ) ;
endmodule


module cbx_1__0__direct_interc_3 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
    ccff_head , ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:0] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__71 ( .A ( mem_out[0] ) , 
    .X ( net_net_108 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_144 ( .A ( net_net_108 ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__0__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
    FPGA_OUT , FPGA_DIR , p_abuf0 ) ;
input  SOC_IN ;
output SOC_OUT ;
output SOC_DIR ;
output FPGA_IN ;
input  FPGA_OUT ;
input  FPGA_DIR ;
output p_abuf0 ;

assign SOC_OUT = FPGA_OUT ;

sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__69 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__70 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ;
endmodule


module cbx_1__0__logical_tile_io_mode_physical__iopad ( prog_clk , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , 
    ccff_tail , p_abuf0 ) ;
input  [0:0] prog_clk ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] iopad_outpad ;
input  [0:0] ccff_head ;
output [0:0] iopad_inpad ;
output [0:0] ccff_tail ;
output p_abuf0 ;

wire [0:0] EMBEDDED_IO_0_en ;

cbx_1__0__EMBEDDED_IO EMBEDDED_IO_0_ ( 
    .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , 
    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , 
    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , 
    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
    .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ;
cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ;
endmodule


module cbx_1__0__logical_tile_io_mode_io_ ( prog_clk , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , 
    ccff_tail , p_abuf0 ) ;
input  [0:0] prog_clk ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] io_outpad ;
input  [0:0] ccff_head ;
output [0:0] io_inpad ;
output [0:0] ccff_tail ;
output p_abuf0 ;

cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
    .prog_clk ( prog_clk ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , 
    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , 
    .p_abuf0 ( p_abuf0 ) ) ;
cbx_1__0__direct_interc_3 direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ;
cbx_1__0__direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( io_outpad ) ) ;
endmodule


module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , 
    ccff_head , ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:0] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__68 ( .A ( mem_out[0] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__0__EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
    FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ;
input  SOC_IN ;
output SOC_OUT ;
output SOC_DIR ;
output FPGA_IN ;
input  FPGA_OUT ;
input  FPGA_DIR ;
output p_abuf0 ;
output p_abuf1 ;

assign SOC_OUT = FPGA_OUT ;

sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__66 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__67 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ;
endmodule


module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( prog_clk , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , 
    ccff_tail , p_abuf0 , p_abuf1 ) ;
input  [0:0] prog_clk ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] iopad_outpad ;
input  [0:0] ccff_head ;
output [0:0] iopad_inpad ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf1 ;

wire [0:0] EMBEDDED_IO_0_en ;

cbx_1__0__EMBEDDED_IO_4 EMBEDDED_IO_0_ ( 
    .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , 
    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , 
    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , 
    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
    .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , 
    .p_abuf1 ( p_abuf1 ) ) ;
cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ;
endmodule


module cbx_1__0__logical_tile_io_mode_io__4 ( prog_clk , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , 
    ccff_tail , p_abuf0 ) ;
input  [0:0] prog_clk ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] io_outpad ;
input  [0:0] ccff_head ;
output [0:0] io_inpad ;
output [0:0] ccff_tail ;
output p_abuf0 ;

cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( 
    .prog_clk ( prog_clk ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , 
    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , 
    .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ;
cbx_1__0__direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( { p_abuf1 } ) ) ;
cbx_1__0__direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .out ( io_outpad ) ) ;
endmodule


module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , 
    ccff_head , ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:0] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__65 ( .A ( mem_out[0] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__0__EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
    FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ;
input  SOC_IN ;
output SOC_OUT ;
output SOC_DIR ;
output FPGA_IN ;
input  FPGA_OUT ;
input  FPGA_DIR ;
output p_abuf0 ;
output p_abuf1 ;

assign SOC_OUT = FPGA_OUT ;

sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__63 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__64 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ;
endmodule


module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( prog_clk , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , 
    ccff_tail , p_abuf0 , p_abuf1 ) ;
input  [0:0] prog_clk ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] iopad_outpad ;
input  [0:0] ccff_head ;
output [0:0] iopad_inpad ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf1 ;

wire [0:0] EMBEDDED_IO_0_en ;

cbx_1__0__EMBEDDED_IO_3 EMBEDDED_IO_0_ ( 
    .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , 
    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , 
    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , 
    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
    .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , 
    .p_abuf1 ( p_abuf1 ) ) ;
cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ;
endmodule


module cbx_1__0__logical_tile_io_mode_io__3 ( prog_clk , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , 
    ccff_tail , p_abuf0 ) ;
input  [0:0] prog_clk ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] io_outpad ;
input  [0:0] ccff_head ;
output [0:0] io_inpad ;
output [0:0] ccff_tail ;
output p_abuf0 ;

cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( 
    .prog_clk ( prog_clk ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , 
    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , 
    .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ;
cbx_1__0__direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( { p_abuf1 } ) ) ;
cbx_1__0__direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .out ( io_outpad ) ) ;
endmodule


module cbx_1__0__direct_interc_2 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , 
    ccff_head , ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:0] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__62 ( .A ( mem_out[0] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__0__EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
    FPGA_OUT , FPGA_DIR , p_abuf0 ) ;
input  SOC_IN ;
output SOC_OUT ;
output SOC_DIR ;
output FPGA_IN ;
input  FPGA_OUT ;
input  FPGA_DIR ;
output p_abuf0 ;

assign SOC_OUT = FPGA_OUT ;

sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__60 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__61 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ;
endmodule


module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( prog_clk , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , 
    ccff_tail , p_abuf0 ) ;
input  [0:0] prog_clk ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] iopad_outpad ;
input  [0:0] ccff_head ;
output [0:0] iopad_inpad ;
output [0:0] ccff_tail ;
output p_abuf0 ;

wire [0:0] EMBEDDED_IO_0_en ;

cbx_1__0__EMBEDDED_IO_2 EMBEDDED_IO_0_ ( 
    .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , 
    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , 
    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , 
    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
    .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ;
cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ;
endmodule


module cbx_1__0__logical_tile_io_mode_io__2 ( prog_clk , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , 
    ccff_tail , p_abuf0 ) ;
input  [0:0] prog_clk ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] io_outpad ;
input  [0:0] ccff_head ;
output [0:0] io_inpad ;
output [0:0] ccff_tail ;
output p_abuf0 ;

cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( 
    .prog_clk ( prog_clk ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , 
    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , 
    .p_abuf0 ( p_abuf0 ) ) ;
cbx_1__0__direct_interc_2 direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ;
cbx_1__0__direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( io_outpad ) ) ;
endmodule


module cbx_1__0__direct_interc_1 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , 
    ccff_head , ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:0] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__59 ( .A ( mem_out[0] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__0__EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
    FPGA_OUT , FPGA_DIR , p_abuf0 ) ;
input  SOC_IN ;
output SOC_OUT ;
output SOC_DIR ;
output FPGA_IN ;
input  FPGA_OUT ;
input  FPGA_DIR ;
output p_abuf0 ;

assign SOC_OUT = FPGA_OUT ;

sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__57 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 FTB_11__58 ( .A ( FPGA_DIR ) , 
    .X ( SOC_DIR ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ;
endmodule


module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( prog_clk , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , 
    ccff_tail , p_abuf0 ) ;
input  [0:0] prog_clk ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] iopad_outpad ;
input  [0:0] ccff_head ;
output [0:0] iopad_inpad ;
output [0:0] ccff_tail ;
output p_abuf0 ;

wire [0:0] EMBEDDED_IO_0_en ;

cbx_1__0__EMBEDDED_IO_1 EMBEDDED_IO_0_ ( 
    .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , 
    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , 
    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , 
    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
    .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ;
cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ;
endmodule


module cbx_1__0__logical_tile_io_mode_io__1 ( prog_clk , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , 
    ccff_tail , p_abuf0 ) ;
input  [0:0] prog_clk ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] io_outpad ;
input  [0:0] ccff_head ;
output [0:0] io_inpad ;
output [0:0] ccff_tail ;
output p_abuf0 ;

cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( 
    .prog_clk ( prog_clk ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , 
    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , 
    .p_abuf0 ( p_abuf0 ) ) ;
cbx_1__0__direct_interc_1 direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ;
cbx_1__0__direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( io_outpad ) ) ;
endmodule


module cbx_1__0__direct_interc ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

assign out[0] = in[0] ;
endmodule


module cbx_1__0__direct_interc_0 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , 
    ccff_head , ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:0] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__56 ( .A ( mem_out[0] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__0__EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
    FPGA_OUT , FPGA_DIR , p_abuf0 ) ;
input  SOC_IN ;
output SOC_OUT ;
output SOC_DIR ;
output FPGA_IN ;
input  FPGA_OUT ;
input  FPGA_DIR ;
output p_abuf0 ;

assign SOC_OUT = FPGA_OUT ;

sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__54 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 FTB_8__55 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ;
endmodule


module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( prog_clk , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , 
    ccff_tail , p_abuf0 ) ;
input  [0:0] prog_clk ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] iopad_outpad ;
input  [0:0] ccff_head ;
output [0:0] iopad_inpad ;
output [0:0] ccff_tail ;
output p_abuf0 ;

wire [0:0] EMBEDDED_IO_0_en ;

cbx_1__0__EMBEDDED_IO_0 EMBEDDED_IO_0_ ( 
    .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , 
    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , 
    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , 
    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
    .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ;
cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ;
endmodule


module cbx_1__0__logical_tile_io_mode_io__0 ( prog_clk , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , 
    ccff_tail , p_abuf0 ) ;
input  [0:0] prog_clk ;
input  [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] io_outpad ;
input  [0:0] ccff_head ;
output [0:0] io_inpad ;
output [0:0] ccff_tail ;
output p_abuf0 ;

cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( 
    .prog_clk ( prog_clk ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , 
    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , 
    .p_abuf0 ( p_abuf0 ) ) ;
cbx_1__0__direct_interc_0 direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ;
cbx_1__0__direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( io_outpad ) ) ;
endmodule


module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__53 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__52 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__51 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__50 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__49 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__48 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module cbx_1__0__const1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__0__const1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cbx_1__0__const1_4 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__0__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__0__const1_4 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cbx_1__0__const1_3 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__0__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__0__const1_3 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cbx_1__0__const1_2 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__0__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;

cbx_1__0__const1_2 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ;
endmodule


module cbx_1__0__const1_1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__0__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;

cbx_1__0__const1_1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ;
endmodule


module cbx_1__0__const1_0 ( const1 ) ;
output [0:0] const1 ;
endmodule


module cbx_1__0__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

cbx_1__0__const1_0 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , 
    chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , 
    bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , 
    bottom_grid_pin_8_ , bottom_grid_pin_10_ , ccff_tail , 
    gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , 
    gfpga_pad_EMBEDDED_IO_SOC_DIR , top_width_0_height_0__pin_0_ , 
    top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , 
    top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , 
    top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_1_upper , 
    top_width_0_height_0__pin_1_lower , top_width_0_height_0__pin_3_upper , 
    top_width_0_height_0__pin_3_lower , top_width_0_height_0__pin_5_upper , 
    top_width_0_height_0__pin_5_lower , top_width_0_height_0__pin_7_upper , 
    top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , 
    top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , 
    top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , 
    SC_OUT_BOT , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 ) ;
input  [0:0] prog_clk ;
input  [0:19] chanx_left_in ;
input  [0:19] chanx_right_in ;
input  [0:0] ccff_head ;
output [0:19] chanx_left_out ;
output [0:19] chanx_right_out ;
output [0:0] bottom_grid_pin_0_ ;
output [0:0] bottom_grid_pin_2_ ;
output [0:0] bottom_grid_pin_4_ ;
output [0:0] bottom_grid_pin_6_ ;
output [0:0] bottom_grid_pin_8_ ;
output [0:0] bottom_grid_pin_10_ ;
output [0:0] ccff_tail ;
input  [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] top_width_0_height_0__pin_0_ ;
input  [0:0] top_width_0_height_0__pin_2_ ;
input  [0:0] top_width_0_height_0__pin_4_ ;
input  [0:0] top_width_0_height_0__pin_6_ ;
input  [0:0] top_width_0_height_0__pin_8_ ;
input  [0:0] top_width_0_height_0__pin_10_ ;
output [0:0] top_width_0_height_0__pin_1_upper ;
output [0:0] top_width_0_height_0__pin_1_lower ;
output [0:0] top_width_0_height_0__pin_3_upper ;
output [0:0] top_width_0_height_0__pin_3_lower ;
output [0:0] top_width_0_height_0__pin_5_upper ;
output [0:0] top_width_0_height_0__pin_5_lower ;
output [0:0] top_width_0_height_0__pin_7_upper ;
output [0:0] top_width_0_height_0__pin_7_lower ;
output [0:0] top_width_0_height_0__pin_9_upper ;
output [0:0] top_width_0_height_0__pin_9_lower ;
output [0:0] top_width_0_height_0__pin_11_upper ;
output [0:0] top_width_0_height_0__pin_11_lower ;
input  SC_IN_TOP ;
input  SC_IN_BOT ;
output SC_OUT_TOP ;
output SC_OUT_BOT ;
input  [0:0] Test_en__FEEDTHRU_0 ;
output [0:0] Test_en__FEEDTHRU_1 ;

wire ropt_net_181 ;
wire ropt_net_197 ;
wire ropt_net_196 ;
wire ropt_net_193 ;
wire ropt_net_192 ;
wire ropt_net_185 ;
wire [0:3] mux_top_ipin_0_undriven_sram_inv ;
wire [0:3] mux_top_ipin_1_undriven_sram_inv ;
wire [0:3] mux_top_ipin_2_undriven_sram_inv ;
wire [0:3] mux_top_ipin_3_undriven_sram_inv ;
wire [0:3] mux_top_ipin_4_undriven_sram_inv ;
wire [0:3] mux_top_ipin_5_undriven_sram_inv ;
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
wire [0:3] mux_tree_tapbuf_size10_1_sram ;
wire [0:3] mux_tree_tapbuf_size10_2_sram ;
wire [0:3] mux_tree_tapbuf_size10_3_sram ;
wire [0:3] mux_tree_tapbuf_size10_4_sram ;
wire [0:3] mux_tree_tapbuf_size10_5_sram ;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
wire [0:0] logical_tile_io_mode_io__0_ccff_tail ;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail ;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail ;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail ;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail ;

assign SC_IN_TOP = SC_IN_BOT ;

cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , 
        chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , 
        chanx_right_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size10_0_sram ) , 
    .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_178 ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 (
    .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , 
        chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , 
        chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , 
        chanx_right_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size10_1_sram ) , 
    .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_176 ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , 
        chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , 
        chanx_right_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size10_2_sram ) , 
    .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_179 ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 (
    .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , 
        chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , 
        chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , 
        chanx_right_in[19] } ) ,
    .sram ( mux_tree_tapbuf_size10_3_sram ) , 
    .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_176 ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 (
    .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , 
        chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , 
        chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , 
        chanx_right_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size10_4_sram ) , 
    .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_177 ) ) ;
cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_5 (
    .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , 
        chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , 
        chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , 
        chanx_right_in[15] } ) ,
    .sram ( mux_tree_tapbuf_size10_5_sram ) , 
    .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , 
    .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_177 ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
    .ccff_tail ( { ccff_tail_mid } ) ,
    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( 
    .prog_clk ( prog_clk ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , 
    .io_outpad ( top_width_0_height_0__pin_0_ ) ,
    .ccff_head ( { ccff_tail_mid } ) ,
    .io_inpad ( { aps_rename_4_ } ) ,
    .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) , 
    .p_abuf0 ( ropt_net_181 ) ) ;
cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( 
    .prog_clk ( prog_clk ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , 
    .io_outpad ( top_width_0_height_0__pin_2_ ) , 
    .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) ,
    .io_inpad ( { aps_rename_5_ } ) ,
    .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) , 
    .p_abuf0 ( ropt_net_197 ) ) ;
cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( 
    .prog_clk ( prog_clk ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) ,
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) ,
    .io_outpad ( top_width_0_height_0__pin_4_ ) , 
    .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) ,
    .io_inpad ( { aps_rename_6_ } ) ,
    .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , 
    .p_abuf0 ( ropt_net_196 ) ) ;
cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( 
    .prog_clk ( prog_clk ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) ,
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_200 } ) ,
    .io_outpad ( top_width_0_height_0__pin_6_ ) , 
    .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) ,
    .io_inpad ( { aps_rename_7_ } ) ,
    .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) , 
    .p_abuf0 ( ropt_net_193 ) ) ;
cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( 
    .prog_clk ( prog_clk ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) ,
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_194 } ) ,
    .io_outpad ( top_width_0_height_0__pin_8_ ) , 
    .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) ,
    .io_inpad ( { aps_rename_8_ } ) ,
    .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) , 
    .p_abuf0 ( ropt_net_192 ) ) ;
cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( 
    .prog_clk ( prog_clk ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) ,
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_202 } ) ,
    .io_outpad ( top_width_0_height_0__pin_10_ ) , 
    .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) ,
    .io_inpad ( { aps_rename_10_ } ) ,
    .ccff_tail ( { ropt_net_222 } ) ,
    .p_abuf0 ( ropt_net_185 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , 
    .X ( ropt_net_214 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_172 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , 
    .HI ( optlc_net_176 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_174 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , 
    .HI ( optlc_net_177 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_240 ) , 
    .X ( chanx_left_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , 
    .X ( ropt_net_266 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , 
    .HI ( optlc_net_178 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , 
    .HI ( optlc_net_179 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chanx_left_in[15] ) , 
    .X ( ropt_net_275 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_181 ) , 
    .X ( ropt_net_252 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_182 ) , 
    .X ( chanx_left_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , 
    .X ( ropt_net_270 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , 
    .X ( ropt_net_223 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_183 ) , 
    .X ( top_width_0_height_0__pin_5_lower[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_184 ) , 
    .X ( ropt_net_251 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_185 ) , 
    .X ( ropt_net_263 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( BUF_net_103 ) , 
    .X ( ropt_net_262 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , 
    .X ( ropt_net_227 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_left_in[13] ) , 
    .X ( chanx_right_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chanx_right_in[18] ) , 
    .X ( ropt_net_269 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , 
    .X ( ropt_net_219 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( chanx_right_in[5] ) , 
    .X ( ropt_net_245 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , 
    .X ( chanx_left_out[1] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , 
    .X ( chanx_left_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , 
    .X ( ropt_net_225 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , 
    .X ( ropt_net_226 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( 
    .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_268 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_241 ) , 
    .X ( chanx_right_out[11] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , 
    .X ( ropt_net_216 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , 
    .X ( ropt_net_220 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( BUF_net_104 ) , 
    .X ( top_width_0_height_0__pin_11_lower[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , 
    .X ( ropt_net_224 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_192 ) , 
    .X ( ropt_net_258 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_193 ) , 
    .X ( ropt_net_257 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , 
    .X ( chanx_left_out[13] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , 
    .X ( ropt_net_229 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_194 ) , 
    .X ( ropt_net_256 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , 
    .X ( ropt_net_228 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_right_in[15] ) , 
    .X ( chanx_left_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_196 ) , 
    .X ( ropt_net_255 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , 
    .X ( ropt_net_218 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_197 ) , 
    .X ( top_width_0_height_0__pin_3_upper[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_198 ) , 
    .X ( ropt_net_250 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_43__42 ( .A ( aps_rename_6_ ) , 
    .X ( ropt_net_183 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_44__43 ( .A ( aps_rename_7_ ) , 
    .X ( ropt_net_198 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_45__44 ( .A ( aps_rename_8_ ) , 
    .X ( aps_rename_9_ ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_left_in[5] ) , 
    .X ( ropt_net_272 ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , 
    .X ( ropt_net_184 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_200 ) , 
    .X ( ropt_net_271 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_201 ) , 
    .X ( ropt_net_267 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_242 ) , 
    .X ( chanx_left_out[4] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_243 ) , 
    .X ( chanx_left_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_202 ) , 
    .X ( ropt_net_273 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( chanx_left_in[14] ) , 
    .X ( chanx_right_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_244 ) , 
    .X ( chanx_left_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_245 ) , 
    .X ( chanx_left_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[8] ) , 
    .X ( ropt_net_277 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[17] ) , 
    .X ( ropt_net_243 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( chanx_right_in[0] ) , 
    .X ( ropt_net_215 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( chanx_right_in[12] ) , 
    .X ( chanx_left_out[12] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_836 ( .A ( ropt_net_246 ) , 
    .X ( chanx_left_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_247 ) , 
    .X ( chanx_left_out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_248 ) , 
    .X ( chanx_left_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_249 ) , 
    .X ( chanx_right_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_250 ) , 
    .X ( top_width_0_height_0__pin_7_lower[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_102 ( .A ( aps_rename_4_ ) , 
    .X ( BUF_net_102 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( aps_rename_5_ ) , 
    .X ( BUF_net_103 ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_104 ( .A ( aps_rename_10_ ) , 
    .X ( BUF_net_104 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_251 ) , 
    .X ( SC_OUT_BOT ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[9] ) , 
    .X ( ropt_net_276 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( chanx_right_in[6] ) , 
    .X ( ropt_net_240 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chanx_left_in[2] ) , 
    .X ( chanx_right_out[2] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_left_in[1] ) , 
    .X ( chanx_right_out[1] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[11] ) , 
    .X ( ropt_net_278 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_left_in[3] ) , 
    .X ( ropt_net_274 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_213 ) , 
    .X ( top_width_0_height_0__pin_9_lower[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_214 ) , 
    .X ( ropt_net_261 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_252 ) , 
    .X ( top_width_0_height_0__pin_1_upper[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_215 ) , 
    .X ( ropt_net_247 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_216 ) , 
    .X ( ropt_net_253 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_217 ) , 
    .X ( ropt_net_259 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_218 ) , 
    .X ( ropt_net_244 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_219 ) , 
    .X ( ropt_net_249 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_220 ) , 
    .X ( ropt_net_254 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_221 ) , 
    .X ( ropt_net_260 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_222 ) , 
    .X ( ccff_tail[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_253 ) , 
    .X ( chanx_left_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( chanx_left_in[6] ) , 
    .X ( ropt_net_264 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( .A ( chanx_left_in[7] ) , 
    .X ( ropt_net_217 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_138 ( .A ( chanx_left_in[18] ) , 
    .X ( ropt_net_265 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_847 ( .A ( ropt_net_254 ) , 
    .X ( chanx_left_out[8] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_140 ( .A ( aps_rename_9_ ) , 
    .X ( ropt_net_213 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_142 ( .A ( chanx_left_in[12] ) , 
    .X ( chanx_right_out[12] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chanx_left_in[17] ) , 
    .X ( ropt_net_221 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_255 ) , 
    .X ( top_width_0_height_0__pin_5_upper[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_256 ) , 
    .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_223 ) , 
    .X ( ropt_net_241 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_850 ( .A ( ropt_net_257 ) , 
    .X ( top_width_0_height_0__pin_7_upper[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_224 ) , 
    .X ( chanx_left_out[10] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_225 ) , 
    .X ( ropt_net_248 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_258 ) , 
    .X ( top_width_0_height_0__pin_9_upper[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_853 ( .A ( ropt_net_259 ) , 
    .X ( chanx_right_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_160 ( .A ( chanx_right_in[9] ) , 
    .X ( ropt_net_182 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_226 ) , 
    .X ( ropt_net_242 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_854 ( .A ( ropt_net_260 ) , 
    .X ( chanx_right_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_227 ) , 
    .X ( chanx_right_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_228 ) , 
    .X ( chanx_left_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_165 ( .A ( BUF_net_102 ) , 
    .X ( top_width_0_height_0__pin_1_lower[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_261 ) , 
    .X ( chanx_right_out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_262 ) , 
    .X ( top_width_0_height_0__pin_3_lower[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_229 ) , 
    .X ( ropt_net_246 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_263 ) , 
    .X ( top_width_0_height_0__pin_11_upper[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_858 ( .A ( ropt_net_264 ) , 
    .X ( chanx_right_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_859 ( .A ( ropt_net_265 ) , 
    .X ( chanx_right_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_860 ( .A ( ropt_net_266 ) , 
    .X ( chanx_right_out[4] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_267 ) , 
    .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_863 ( .A ( ropt_net_268 ) , 
    .X ( Test_en__FEEDTHRU_1[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_269 ) , 
    .X ( chanx_left_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_865 ( .A ( ropt_net_270 ) , 
    .X ( chanx_right_out[10] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_866 ( .A ( ropt_net_271 ) , 
    .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_867 ( .A ( ropt_net_272 ) , 
    .X ( chanx_right_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_869 ( .A ( ropt_net_273 ) , 
    .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_872 ( .A ( ropt_net_274 ) , 
    .X ( chanx_right_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_873 ( .A ( ropt_net_275 ) , 
    .X ( chanx_right_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_875 ( .A ( ropt_net_276 ) , 
    .X ( chanx_right_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_876 ( .A ( ropt_net_277 ) , 
    .X ( chanx_right_out[8] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_278 ) , 
    .X ( chanx_left_out[11] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__41 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__40 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__39 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__const1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_2__2__const1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_2__2__const1_33 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_2__2__const1_33 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_2__2__const1_32 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_2__2__const1_32 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__38 ( .A ( mem_out[1] ) , 
    .X ( net_net_69 ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_69 ( .A ( net_net_69 ) , 
    .X ( net_net_68 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_98 ( .A ( net_net_68 ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__37 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__36 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__35 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__34 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__33 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__32 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__31 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__30 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__29 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__28 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__27 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__26 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__25 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__24 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__23 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__22 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__21 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__20 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__19 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__18 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__17 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__16 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__15 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__const1_31 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_31 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__2__const1_30 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_30 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_61 ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_61 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_104 ( .A ( BUF_net_61 ) , 
    .X ( out[0] ) ) ;
endmodule


module sb_2__2__const1_29 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_29 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__2__const1_28 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_28 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_2__2__const1_27 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_27 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_2__2__const1_26 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_26 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__2__const1_25 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_25 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__2__const1_24 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_24 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__2__const1_23 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_23 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__2__const1_22 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_22 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__2__const1_21 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_21 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__2__const1_20 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_20 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__2__const1_19 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_19 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__2__const1_18 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_18 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__2__const1_17 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_17 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_101 ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_2__2__const1_16 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_16 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__2__const1_15 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_15 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__2__const1_14 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_14 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__2__const1_13 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_13 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__2__const1_12 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_12 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__2__const1_11 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_11 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__2__const1_10 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_10 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_2__2__const1_9 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_9 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__2__const1_8 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__2__const1_8 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__14 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__13 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__12 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__11 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__const1_7 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:4] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;

sb_2__2__const1_7 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
endmodule


module sb_2__2__const1_6 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:4] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;

sb_2__2__const1_6 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
endmodule


module sb_2__2__const1_5 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:4] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;

sb_2__2__const1_5 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
endmodule


module sb_2__2__const1_4 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:4] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;

sb_2__2__const1_4 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__10 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__9 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__8 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__7 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__2__const1_3 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_2__2__const1_3 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_2__2__const1_2 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_2__2__const1_2 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
endmodule


module sb_2__2__const1_1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_2__2__const1_1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
endmodule


module sb_2__2__const1_0 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_2__2__const1_0 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
endmodule


module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , 
    bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , 
    bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , 
    bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , 
    bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , 
    left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , 
    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
    left_bottom_grid_pin_41_ , ccff_head , chany_bottom_out , chanx_left_out , 
    ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , 
    grid_clb_120_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , 
    grid_clb_120_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ;
input  [0:0] prog_clk ;
input  [0:19] chany_bottom_in ;
input  [0:0] bottom_right_grid_pin_1_ ;
input  [0:0] bottom_left_grid_pin_42_ ;
input  [0:0] bottom_left_grid_pin_43_ ;
input  [0:0] bottom_left_grid_pin_44_ ;
input  [0:0] bottom_left_grid_pin_45_ ;
input  [0:0] bottom_left_grid_pin_46_ ;
input  [0:0] bottom_left_grid_pin_47_ ;
input  [0:0] bottom_left_grid_pin_48_ ;
input  [0:0] bottom_left_grid_pin_49_ ;
input  [0:19] chanx_left_in ;
input  [0:0] left_top_grid_pin_1_ ;
input  [0:0] left_bottom_grid_pin_34_ ;
input  [0:0] left_bottom_grid_pin_35_ ;
input  [0:0] left_bottom_grid_pin_36_ ;
input  [0:0] left_bottom_grid_pin_37_ ;
input  [0:0] left_bottom_grid_pin_38_ ;
input  [0:0] left_bottom_grid_pin_39_ ;
input  [0:0] left_bottom_grid_pin_40_ ;
input  [0:0] left_bottom_grid_pin_41_ ;
input  [0:0] ccff_head ;
output [0:19] chany_bottom_out ;
output [0:19] chanx_left_out ;
output [0:0] ccff_tail ;
input  SC_IN_TOP ;
input  SC_IN_BOT ;
output SC_OUT_TOP ;
output SC_OUT_BOT ;
input  [0:0] grid_clb_120_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ;
output [0:0] grid_clb_120_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ;

wire [0:1] mux_bottom_track_11_undriven_sram_inv ;
wire [0:1] mux_bottom_track_13_undriven_sram_inv ;
wire [0:1] mux_bottom_track_15_undriven_sram_inv ;
wire [0:1] mux_bottom_track_17_undriven_sram_inv ;
wire [0:1] mux_bottom_track_19_undriven_sram_inv ;
wire [0:2] mux_bottom_track_1_undriven_sram_inv ;
wire [0:1] mux_bottom_track_21_undriven_sram_inv ;
wire [0:1] mux_bottom_track_23_undriven_sram_inv ;
wire [0:1] mux_bottom_track_25_undriven_sram_inv ;
wire [0:1] mux_bottom_track_27_undriven_sram_inv ;
wire [0:1] mux_bottom_track_29_undriven_sram_inv ;
wire [0:2] mux_bottom_track_3_undriven_sram_inv ;
wire [0:2] mux_bottom_track_5_undriven_sram_inv ;
wire [0:2] mux_bottom_track_7_undriven_sram_inv ;
wire [0:1] mux_bottom_track_9_undriven_sram_inv ;
wire [0:1] mux_left_track_11_undriven_sram_inv ;
wire [0:1] mux_left_track_13_undriven_sram_inv ;
wire [0:1] mux_left_track_15_undriven_sram_inv ;
wire [0:1] mux_left_track_17_undriven_sram_inv ;
wire [0:1] mux_left_track_19_undriven_sram_inv ;
wire [0:2] mux_left_track_1_undriven_sram_inv ;
wire [0:1] mux_left_track_21_undriven_sram_inv ;
wire [0:1] mux_left_track_23_undriven_sram_inv ;
wire [0:1] mux_left_track_25_undriven_sram_inv ;
wire [0:1] mux_left_track_27_undriven_sram_inv ;
wire [0:1] mux_left_track_29_undriven_sram_inv ;
wire [0:1] mux_left_track_31_undriven_sram_inv ;
wire [0:1] mux_left_track_33_undriven_sram_inv ;
wire [0:1] mux_left_track_35_undriven_sram_inv ;
wire [0:1] mux_left_track_37_undriven_sram_inv ;
wire [0:1] mux_left_track_39_undriven_sram_inv ;
wire [0:2] mux_left_track_3_undriven_sram_inv ;
wire [0:2] mux_left_track_5_undriven_sram_inv ;
wire [0:2] mux_left_track_7_undriven_sram_inv ;
wire [0:1] mux_left_track_9_undriven_sram_inv ;
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
wire [0:1] mux_tree_tapbuf_size2_10_sram ;
wire [0:1] mux_tree_tapbuf_size2_11_sram ;
wire [0:1] mux_tree_tapbuf_size2_12_sram ;
wire [0:1] mux_tree_tapbuf_size2_13_sram ;
wire [0:1] mux_tree_tapbuf_size2_14_sram ;
wire [0:1] mux_tree_tapbuf_size2_15_sram ;
wire [0:1] mux_tree_tapbuf_size2_16_sram ;
wire [0:1] mux_tree_tapbuf_size2_17_sram ;
wire [0:1] mux_tree_tapbuf_size2_18_sram ;
wire [0:1] mux_tree_tapbuf_size2_19_sram ;
wire [0:1] mux_tree_tapbuf_size2_1_sram ;
wire [0:1] mux_tree_tapbuf_size2_20_sram ;
wire [0:1] mux_tree_tapbuf_size2_21_sram ;
wire [0:1] mux_tree_tapbuf_size2_22_sram ;
wire [0:1] mux_tree_tapbuf_size2_23_sram ;
wire [0:1] mux_tree_tapbuf_size2_2_sram ;
wire [0:1] mux_tree_tapbuf_size2_3_sram ;
wire [0:1] mux_tree_tapbuf_size2_4_sram ;
wire [0:1] mux_tree_tapbuf_size2_5_sram ;
wire [0:1] mux_tree_tapbuf_size2_6_sram ;
wire [0:1] mux_tree_tapbuf_size2_7_sram ;
wire [0:1] mux_tree_tapbuf_size2_8_sram ;
wire [0:1] mux_tree_tapbuf_size2_9_sram ;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
wire [0:1] mux_tree_tapbuf_size3_2_sram ;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size5_0_sram ;
wire [0:2] mux_tree_tapbuf_size5_1_sram ;
wire [0:2] mux_tree_tapbuf_size5_2_sram ;
wire [0:2] mux_tree_tapbuf_size5_3_sram ;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size6_0_sram ;
wire [0:2] mux_tree_tapbuf_size6_1_sram ;
wire [0:2] mux_tree_tapbuf_size6_2_sram ;
wire [0:2] mux_tree_tapbuf_size6_3_sram ;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;

assign SC_IN_TOP = SC_IN_BOT ;

sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 (
    .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , 
        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
        bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) ,
    .sram ( mux_tree_tapbuf_size6_0_sram ) , 
    .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , 
    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_128 ) ) ;
sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 (
    .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , 
        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
        bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) ,
    .sram ( mux_tree_tapbuf_size6_1_sram ) , 
    .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , 
    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_126 ) ) ;
sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 (
    .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , 
        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , 
        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
    .sram ( mux_tree_tapbuf_size6_2_sram ) , 
    .sram_inv ( mux_left_track_1_undriven_sram_inv ) , 
    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_129 ) ) ;
sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 (
    .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , 
        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , 
        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
    .sram ( mux_tree_tapbuf_size6_3_sram ) , 
    .sram_inv ( mux_left_track_5_undriven_sram_inv ) ,
    .out ( { ropt_net_133 } ) ,
    .p0 ( optlc_net_129 ) ) ;
sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 (
    .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , 
        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , 
        chanx_left_in[2] } ) ,
    .sram ( mux_tree_tapbuf_size5_0_sram ) , 
    .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , 
    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_128 ) ) ;
sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 (
    .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , 
        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , 
        chanx_left_in[4] } ) ,
    .sram ( mux_tree_tapbuf_size5_1_sram ) , 
    .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , 
    .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_128 ) ) ;
sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 (
    .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , 
        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , 
        left_bottom_grid_pin_40_[0] } ) ,
    .sram ( mux_tree_tapbuf_size5_2_sram ) , 
    .sram_inv ( mux_left_track_3_undriven_sram_inv ) , 
    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_127 ) ) ;
sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 (
    .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , 
        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , 
        left_bottom_grid_pin_40_[0] } ) ,
    .sram ( mux_tree_tapbuf_size5_3_sram ) , 
    .sram_inv ( mux_left_track_7_undriven_sram_inv ) , 
    .out ( chanx_left_out[3] ) , .p0 ( optlc_net_127 ) ) ;
sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_9 (
    .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) ,
    .sram ( mux_tree_tapbuf_size2_0_sram ) , 
    .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , 
    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_126 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_11 (
    .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) ,
    .sram ( mux_tree_tapbuf_size2_1_sram ) , 
    .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , 
    .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_126 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_13 (
    .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) ,
    .sram ( mux_tree_tapbuf_size2_2_sram ) , 
    .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) ,
    .out ( { ropt_net_136 } ) ,
    .p0 ( optlc_net_129 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_15 (
    .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) ,
    .sram ( mux_tree_tapbuf_size2_3_sram ) , 
    .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , 
    .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_128 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_17 (
    .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) ,
    .sram ( mux_tree_tapbuf_size2_4_sram ) , 
    .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , 
    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_128 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_19 (
    .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) ,
    .sram ( mux_tree_tapbuf_size2_5_sram ) , 
    .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , 
    .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_128 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_21 (
    .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) ,
    .sram ( mux_tree_tapbuf_size2_6_sram ) , 
    .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , 
    .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_128 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_23 (
    .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) ,
    .sram ( mux_tree_tapbuf_size2_7_sram ) , 
    .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , 
    .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_126 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 (
    .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size2_8_sram ) , 
    .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , 
    .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_129 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_29 (
    .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) ,
    .sram ( mux_tree_tapbuf_size2_9_sram ) , 
    .sram_inv ( mux_bottom_track_29_undriven_sram_inv ) ,
    .out ( { ropt_net_140 } ) ,
    .p0 ( optlc_net_129 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 (
    .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_10_sram ) , 
    .sram_inv ( mux_left_track_11_undriven_sram_inv ) , 
    .out ( chanx_left_out[5] ) , .p0 ( optlc_net_127 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 (
    .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_11_sram ) , 
    .sram_inv ( mux_left_track_13_undriven_sram_inv ) , 
    .out ( chanx_left_out[6] ) , .p0 ( optlc_net_127 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 (
    .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_12_sram ) , 
    .sram_inv ( mux_left_track_15_undriven_sram_inv ) , 
    .out ( chanx_left_out[7] ) , .p0 ( optlc_net_127 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 (
    .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_13_sram ) , 
    .sram_inv ( mux_left_track_17_undriven_sram_inv ) , 
    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_127 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 (
    .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_14_sram ) , 
    .sram_inv ( mux_left_track_19_undriven_sram_inv ) , 
    .out ( chanx_left_out[9] ) , .p0 ( optlc_net_127 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 (
    .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_15_sram ) , 
    .sram_inv ( mux_left_track_21_undriven_sram_inv ) , 
    .out ( chanx_left_out[10] ) , .p0 ( optlc_net_126 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 (
    .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_16_sram ) , 
    .sram_inv ( mux_left_track_23_undriven_sram_inv ) , 
    .out ( chanx_left_out[11] ) , .p0 ( optlc_net_126 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 (
    .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_17_sram ) , 
    .sram_inv ( mux_left_track_27_undriven_sram_inv ) , 
    .out ( chanx_left_out[13] ) , .p0 ( optlc_net_126 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 (
    .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_18_sram ) , 
    .sram_inv ( mux_left_track_29_undriven_sram_inv ) , 
    .out ( chanx_left_out[14] ) , .p0 ( optlc_net_126 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 (
    .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_19_sram ) , 
    .sram_inv ( mux_left_track_31_undriven_sram_inv ) ,
    .out ( { ropt_net_132 } ) ,
    .p0 ( optlc_net_127 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 (
    .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_20_sram ) , 
    .sram_inv ( mux_left_track_33_undriven_sram_inv ) ,
    .out ( { ropt_net_135 } ) ,
    .p0 ( optlc_net_127 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 (
    .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_21_sram ) , 
    .sram_inv ( mux_left_track_35_undriven_sram_inv ) , 
    .out ( chanx_left_out[17] ) , .p0 ( optlc_net_126 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 (
    .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_22_sram ) , 
    .sram_inv ( mux_left_track_37_undriven_sram_inv ) ,
    .out ( { ropt_net_134 } ) ,
    .p0 ( optlc_net_129 ) ) ;
sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 (
    .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_23_sram ) , 
    .sram_inv ( mux_left_track_39_undriven_sram_inv ) , 
    .out ( chanx_left_out[19] ) , .p0 ( optlc_net_126 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) ,
    .ccff_tail ( { ropt_net_143 } ) ,
    .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 (
    .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , 
        chanx_left_in[13] } ) ,
    .sram ( mux_tree_tapbuf_size3_0_sram ) , 
    .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , 
    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_128 ) ) ;
sb_2__2__mux_tree_tapbuf_size3 mux_left_track_9 (
    .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , 
        left_bottom_grid_pin_41_[0] } ) ,
    .sram ( mux_tree_tapbuf_size3_1_sram ) , 
    .sram_inv ( mux_left_track_9_undriven_sram_inv ) , 
    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_129 ) ) ;
sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_25 (
    .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , 
        left_bottom_grid_pin_41_[0] } ) ,
    .sram ( mux_tree_tapbuf_size3_2_sram ) , 
    .sram_inv ( mux_left_track_25_undriven_sram_inv ) ,
    .out ( { ropt_net_130 } ) ,
    .p0 ( optlc_net_126 ) ) ;
sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_148 ) , 
    .X ( chanx_left_out[2] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_149 ) , 
    .X ( chanx_left_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_150 ) , 
    .X ( chanx_left_out[12] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , 
    .HI ( optlc_net_126 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_151 ) , 
    .X ( grid_clb_120_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , 
    .X ( ropt_net_131 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , 
    .HI ( optlc_net_127 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_152 ) , 
    .X ( chanx_left_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_153 ) , 
    .X ( SC_OUT_BOT ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_154 ) , 
    .X ( chany_bottom_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_155 ) , 
    .X ( chany_bottom_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_156 ) , 
    .X ( chany_bottom_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_157 ) , 
    .X ( chany_bottom_out[19] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , 
    .HI ( optlc_net_128 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_91 ( 
    .A ( grid_clb_120_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , 
    .X ( ropt_net_144 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_158 ) , 
    .X ( chany_bottom_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_159 ) , 
    .X ( chany_bottom_out[17] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , 
    .HI ( optlc_net_129 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_130 ) , 
    .X ( ropt_net_150 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( ropt_net_131 ) , 
    .X ( ropt_net_153 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_132 ) , 
    .X ( ropt_net_152 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_133 ) , 
    .X ( ropt_net_148 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_134 ) , 
    .X ( ropt_net_149 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_135 ) , 
    .X ( chanx_left_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_136 ) , 
    .X ( ropt_net_154 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[18] ) , 
    .X ( ropt_net_159 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_left_in[17] ) , 
    .X ( chany_bottom_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[16] ) , 
    .X ( ropt_net_158 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( ropt_net_140 ) , 
    .X ( ropt_net_155 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chanx_left_in[0] ) , 
    .X ( ropt_net_157 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[19] ) , 
    .X ( ropt_net_156 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_143 ) , 
    .X ( ccff_tail[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_144 ) , 
    .X ( ropt_net_151 ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__60 ( .A ( mem_out[1] ) , 
    .X ( net_net_75 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( net_net_75 ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__59 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__58 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__57 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__56 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__55 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__const1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__1__const1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__1__const1_31 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

sb_2__1__const1_31 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module sb_2__1__const1_30 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__1__const1_30 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__1__const1_29 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__1__const1_29 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__1__const1_28 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__1__const1_28 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__1__const1_27 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__1__const1_27 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__54 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__53 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__52 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__51 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__50 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__const1_26 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_2__1__const1_26 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_2__1__const1_25 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_2__1__const1_25 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_2__1__const1_24 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_2__1__const1_24 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_2__1__const1_23 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_2__1__const1_23 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_2__1__const1_22 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_2__1__const1_22 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__49 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__48 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__47 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__46 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__const1_21 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_2__1__const1_21 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
endmodule


module sb_2__1__const1_20 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_2__1__const1_20 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
endmodule


module sb_2__1__const1_19 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_2__1__const1_19 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
endmodule


module sb_2__1__const1_18 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_2__1__const1_18 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__45 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__const1_17 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
input  [0:8] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;

sb_2__1__const1_17 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__44 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__43 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__42 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__const1_16 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_2__1__const1_16 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_2__1__const1_15 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_2__1__const1_15 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
endmodule


module sb_2__1__const1_14 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_2__1__const1_14 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__41 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__40 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__39 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__38 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__37 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__36 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__35 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__const1_13 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_2__1__const1_13 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_2__1__const1_12 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_2__1__const1_12 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_2__1__const1_11 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_2__1__const1_11 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_2__1__const1_10 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_2__1__const1_10 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_2__1__const1_9 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_2__1__const1_9 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_2__1__const1_8 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_2__1__const1_8 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_2__1__const1_7 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_2__1__const1_7 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__34 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__33 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__const1_6 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:13] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_2__1__const1_6 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
endmodule


module sb_2__1__const1_5 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ;
input  [0:13] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_2__1__const1_5 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__32 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__31 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__30 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__const1_4 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

sb_2__1__const1_4 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module sb_2__1__const1_3 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

sb_2__1__const1_3 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module sb_2__1__const1_2 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

sb_2__1__const1_2 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__29 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__28 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__1__const1_1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_2__1__const1_1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module sb_2__1__const1_0 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_2__1__const1_0 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , 
    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
    top_left_grid_pin_49_ , top_right_grid_pin_1_ , chany_bottom_in , 
    bottom_right_grid_pin_1_ , bottom_left_grid_pin_42_ , 
    bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , 
    bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , 
    bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , 
    bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , 
    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
    left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , 
    chanx_left_out , ccff_tail , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 ) ;
input  [0:0] prog_clk ;
input  [0:19] chany_top_in ;
input  [0:0] top_left_grid_pin_42_ ;
input  [0:0] top_left_grid_pin_43_ ;
input  [0:0] top_left_grid_pin_44_ ;
input  [0:0] top_left_grid_pin_45_ ;
input  [0:0] top_left_grid_pin_46_ ;
input  [0:0] top_left_grid_pin_47_ ;
input  [0:0] top_left_grid_pin_48_ ;
input  [0:0] top_left_grid_pin_49_ ;
input  [0:0] top_right_grid_pin_1_ ;
input  [0:19] chany_bottom_in ;
input  [0:0] bottom_right_grid_pin_1_ ;
input  [0:0] bottom_left_grid_pin_42_ ;
input  [0:0] bottom_left_grid_pin_43_ ;
input  [0:0] bottom_left_grid_pin_44_ ;
input  [0:0] bottom_left_grid_pin_45_ ;
input  [0:0] bottom_left_grid_pin_46_ ;
input  [0:0] bottom_left_grid_pin_47_ ;
input  [0:0] bottom_left_grid_pin_48_ ;
input  [0:0] bottom_left_grid_pin_49_ ;
input  [0:19] chanx_left_in ;
input  [0:0] left_bottom_grid_pin_34_ ;
input  [0:0] left_bottom_grid_pin_35_ ;
input  [0:0] left_bottom_grid_pin_36_ ;
input  [0:0] left_bottom_grid_pin_37_ ;
input  [0:0] left_bottom_grid_pin_38_ ;
input  [0:0] left_bottom_grid_pin_39_ ;
input  [0:0] left_bottom_grid_pin_40_ ;
input  [0:0] left_bottom_grid_pin_41_ ;
input  [0:0] ccff_head ;
output [0:19] chany_top_out ;
output [0:19] chany_bottom_out ;
output [0:19] chanx_left_out ;
output [0:0] ccff_tail ;
input  [0:0] Test_en__FEEDTHRU_0 ;
output [0:0] Test_en__FEEDTHRU_1 ;

wire [0:2] mux_bottom_track_17_undriven_sram_inv ;
wire [0:3] mux_bottom_track_1_undriven_sram_inv ;
wire [0:2] mux_bottom_track_25_undriven_sram_inv ;
wire [0:2] mux_bottom_track_33_undriven_sram_inv ;
wire [0:3] mux_bottom_track_3_undriven_sram_inv ;
wire [0:3] mux_bottom_track_5_undriven_sram_inv ;
wire [0:3] mux_bottom_track_9_undriven_sram_inv ;
wire [0:2] mux_left_track_11_undriven_sram_inv ;
wire [0:2] mux_left_track_13_undriven_sram_inv ;
wire [0:2] mux_left_track_15_undriven_sram_inv ;
wire [0:1] mux_left_track_17_undriven_sram_inv ;
wire [0:1] mux_left_track_19_undriven_sram_inv ;
wire [0:2] mux_left_track_1_undriven_sram_inv ;
wire [0:1] mux_left_track_21_undriven_sram_inv ;
wire [0:1] mux_left_track_23_undriven_sram_inv ;
wire [0:1] mux_left_track_25_undriven_sram_inv ;
wire [0:1] mux_left_track_29_undriven_sram_inv ;
wire [0:1] mux_left_track_31_undriven_sram_inv ;
wire [0:1] mux_left_track_33_undriven_sram_inv ;
wire [0:1] mux_left_track_35_undriven_sram_inv ;
wire [0:1] mux_left_track_37_undriven_sram_inv ;
wire [0:1] mux_left_track_39_undriven_sram_inv ;
wire [0:2] mux_left_track_3_undriven_sram_inv ;
wire [0:2] mux_left_track_5_undriven_sram_inv ;
wire [0:2] mux_left_track_7_undriven_sram_inv ;
wire [0:2] mux_left_track_9_undriven_sram_inv ;
wire [0:3] mux_top_track_0_undriven_sram_inv ;
wire [0:2] mux_top_track_16_undriven_sram_inv ;
wire [0:2] mux_top_track_24_undriven_sram_inv ;
wire [0:3] mux_top_track_2_undriven_sram_inv ;
wire [0:2] mux_top_track_32_undriven_sram_inv ;
wire [0:3] mux_top_track_4_undriven_sram_inv ;
wire [0:3] mux_top_track_8_undriven_sram_inv ;
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
wire [0:3] mux_tree_tapbuf_size10_1_sram ;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size14_0_sram ;
wire [0:3] mux_tree_tapbuf_size14_1_sram ;
wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
wire [0:1] mux_tree_tapbuf_size2_1_sram ;
wire [0:1] mux_tree_tapbuf_size2_2_sram ;
wire [0:1] mux_tree_tapbuf_size2_3_sram ;
wire [0:1] mux_tree_tapbuf_size2_4_sram ;
wire [0:1] mux_tree_tapbuf_size2_5_sram ;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
wire [0:1] mux_tree_tapbuf_size3_2_sram ;
wire [0:1] mux_tree_tapbuf_size3_3_sram ;
wire [0:1] mux_tree_tapbuf_size3_4_sram ;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size4_0_sram ;
wire [0:2] mux_tree_tapbuf_size4_1_sram ;
wire [0:2] mux_tree_tapbuf_size4_2_sram ;
wire [0:2] mux_tree_tapbuf_size4_3_sram ;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size6_0_sram ;
wire [0:2] mux_tree_tapbuf_size6_1_sram ;
wire [0:2] mux_tree_tapbuf_size6_2_sram ;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size7_0_sram ;
wire [0:2] mux_tree_tapbuf_size7_1_sram ;
wire [0:2] mux_tree_tapbuf_size7_2_sram ;
wire [0:2] mux_tree_tapbuf_size7_3_sram ;
wire [0:2] mux_tree_tapbuf_size7_4_sram ;
wire [0:2] mux_tree_tapbuf_size7_5_sram ;
wire [0:2] mux_tree_tapbuf_size7_6_sram ;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size8_0_sram ;
wire [0:3] mux_tree_tapbuf_size8_1_sram ;
wire [0:3] mux_tree_tapbuf_size8_2_sram ;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size9_0_sram ;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;

sb_2__1__mux_tree_tapbuf_size10 mux_top_track_0 (
    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
        top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , 
        chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size10_0_sram ) , 
    .sram_inv ( mux_top_track_0_undriven_sram_inv ) , 
    .out ( chany_top_out[0] ) , .p0 ( optlc_net_112 ) ) ;
sb_2__1__mux_tree_tapbuf_size10_0 mux_bottom_track_1 (
    .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , 
        bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , 
        bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , 
        chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) ,
    .sram ( mux_tree_tapbuf_size10_1_sram ) , 
    .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , 
    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_113 ) ) ;
sb_2__1__mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( ccff_head ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_2 (
    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
        chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , 
        chanx_left_in[13] } ) ,
    .sram ( mux_tree_tapbuf_size8_0_sram ) , 
    .sram_inv ( mux_top_track_2_undriven_sram_inv ) , 
    .out ( chany_top_out[1] ) , .p0 ( optlc_net_111 ) ) ;
sb_2__1__mux_tree_tapbuf_size8 mux_top_track_8 (
    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , 
        top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , 
        chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size8_1_sram ) , 
    .sram_inv ( mux_top_track_8_undriven_sram_inv ) , 
    .out ( chany_top_out[4] ) , .p0 ( optlc_net_111 ) ) ;
sb_2__1__mux_tree_tapbuf_size8_0 mux_bottom_track_9 (
    .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , 
        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , 
        chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size8_2_sram ) , 
    .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , 
    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_111 ) ) ;
sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 (
    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , 
        top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , 
        top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , 
        top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , 
        top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , 
        chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) ,
    .sram ( mux_tree_tapbuf_size14_0_sram ) , 
    .sram_inv ( mux_top_track_4_undriven_sram_inv ) , 
    .out ( chany_top_out[2] ) , .p0 ( optlc_net_112 ) ) ;
sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 (
    .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , 
        bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , 
        bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_45_[0] , 
        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_47_[0] , 
        bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_49_[0] , 
        chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size14_1_sram ) , 
    .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , 
    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_113 ) ) ;
sb_2__1__mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size7_5 mux_top_track_16 (
    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , 
        chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , 
        chanx_left_in[10] , chanx_left_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size7_0_sram ) , 
    .sram_inv ( mux_top_track_16_undriven_sram_inv ) , 
    .out ( chany_top_out[8] ) , .p0 ( optlc_net_111 ) ) ;
sb_2__1__mux_tree_tapbuf_size7 mux_top_track_24 (
    .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , 
        chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , 
        chanx_left_in[9] , chanx_left_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size7_1_sram ) , 
    .sram_inv ( mux_top_track_24_undriven_sram_inv ) , 
    .out ( chany_top_out[12] ) , .p0 ( optlc_net_112 ) ) ;
sb_2__1__mux_tree_tapbuf_size7_0 mux_bottom_track_17 (
    .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , 
        bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , 
        chanx_left_in[19] } ) ,
    .sram ( mux_tree_tapbuf_size7_2_sram ) , 
    .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , 
    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_112 ) ) ;
sb_2__1__mux_tree_tapbuf_size7_1 mux_left_track_1 (
    .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , 
        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
    .sram ( mux_tree_tapbuf_size7_3_sram ) , 
    .sram_inv ( mux_left_track_1_undriven_sram_inv ) , 
    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_111 ) ) ;
sb_2__1__mux_tree_tapbuf_size7_2 mux_left_track_3 (
    .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , 
        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , 
        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
    .sram ( mux_tree_tapbuf_size7_4_sram ) , 
    .sram_inv ( mux_left_track_3_undriven_sram_inv ) , 
    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_114 ) ) ;
sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_5 (
    .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , 
        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
    .sram ( mux_tree_tapbuf_size7_5_sram ) , 
    .sram_inv ( mux_left_track_5_undriven_sram_inv ) , 
    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_114 ) ) ;
sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_7 (
    .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , 
        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , 
        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
    .sram ( mux_tree_tapbuf_size7_6_sram ) , 
    .sram_inv ( mux_left_track_7_undriven_sram_inv ) , 
    .out ( chanx_left_out[3] ) , .p0 ( optlc_net_114 ) ) ;
sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size6 mux_top_track_32 (
    .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , 
        chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , 
        chanx_left_in[15] } ) ,
    .sram ( mux_tree_tapbuf_size6_0_sram ) , 
    .sram_inv ( mux_top_track_32_undriven_sram_inv ) ,
    .out ( { ropt_net_116 } ) ,
    .p0 ( optlc_net_112 ) ) ;
sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_25 (
    .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , 
        bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) ,
    .sram ( mux_tree_tapbuf_size6_1_sram ) , 
    .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , 
    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_111 ) ) ;
sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_33 (
    .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , 
        bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , 
        chanx_left_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size6_2_sram ) , 
    .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) ,
    .out ( { ropt_net_115 } ) ,
    .p0 ( optlc_net_111 ) ) ;
sb_2__1__mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 (
    .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , 
        bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , 
        bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , 
        chanx_left_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size9_0_sram ) , 
    .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , 
    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_113 ) ) ;
sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size4 mux_left_track_9 (
    .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , 
        left_bottom_grid_pin_34_[0] } ) ,
    .sram ( mux_tree_tapbuf_size4_0_sram ) , 
    .sram_inv ( mux_left_track_9_undriven_sram_inv ) , 
    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_114 ) ) ;
sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_11 (
    .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , 
        left_bottom_grid_pin_35_[0] } ) ,
    .sram ( mux_tree_tapbuf_size4_1_sram ) , 
    .sram_inv ( mux_left_track_11_undriven_sram_inv ) , 
    .out ( chanx_left_out[5] ) , .p0 ( optlc_net_114 ) ) ;
sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_13 (
    .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , 
        left_bottom_grid_pin_36_[0] } ) ,
    .sram ( mux_tree_tapbuf_size4_2_sram ) , 
    .sram_inv ( mux_left_track_13_undriven_sram_inv ) , 
    .out ( chanx_left_out[6] ) , .p0 ( optlc_net_114 ) ) ;
sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_15 (
    .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , 
        left_bottom_grid_pin_37_[0] } ) ,
    .sram ( mux_tree_tapbuf_size4_3_sram ) , 
    .sram_inv ( mux_left_track_15_undriven_sram_inv ) , 
    .out ( chanx_left_out[7] ) , .p0 ( optlc_net_114 ) ) ;
sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 (
    .in ( { chany_top_in[13] , chany_bottom_in[13] , 
        left_bottom_grid_pin_38_[0] } ) ,
    .sram ( mux_tree_tapbuf_size3_0_sram ) , 
    .sram_inv ( mux_left_track_17_undriven_sram_inv ) , 
    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_114 ) ) ;
sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 (
    .in ( { chany_top_in[14] , chany_bottom_in[14] , 
        left_bottom_grid_pin_39_[0] } ) ,
    .sram ( mux_tree_tapbuf_size3_1_sram ) , 
    .sram_inv ( mux_left_track_19_undriven_sram_inv ) , 
    .out ( chanx_left_out[9] ) , .p0 ( optlc_net_111 ) ) ;
sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 (
    .in ( { chany_top_in[16] , chany_bottom_in[16] , 
        left_bottom_grid_pin_40_[0] } ) ,
    .sram ( mux_tree_tapbuf_size3_2_sram ) , 
    .sram_inv ( mux_left_track_21_undriven_sram_inv ) , 
    .out ( chanx_left_out[10] ) , .p0 ( optlc_net_114 ) ) ;
sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 (
    .in ( { chany_top_in[17] , chany_bottom_in[17] , 
        left_bottom_grid_pin_41_[0] } ) ,
    .sram ( mux_tree_tapbuf_size3_3_sram ) , 
    .sram_inv ( mux_left_track_23_undriven_sram_inv ) , 
    .out ( chanx_left_out[11] ) , .p0 ( optlc_net_111 ) ) ;
sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 (
    .in ( { chany_top_in[18] , chany_bottom_in[18] , 
        left_bottom_grid_pin_34_[0] } ) ,
    .sram ( mux_tree_tapbuf_size3_4_sram ) , 
    .sram_inv ( mux_left_track_25_undriven_sram_inv ) , 
    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_111 ) ) ;
sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 (
    .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_0_sram ) , 
    .sram_inv ( mux_left_track_29_undriven_sram_inv ) , 
    .out ( chanx_left_out[14] ) , .p0 ( optlc_net_111 ) ) ;
sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 (
    .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_1_sram ) , 
    .sram_inv ( mux_left_track_31_undriven_sram_inv ) , 
    .out ( chanx_left_out[15] ) , .p0 ( optlc_net_111 ) ) ;
sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 (
    .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_2_sram ) , 
    .sram_inv ( mux_left_track_33_undriven_sram_inv ) , 
    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_111 ) ) ;
sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 (
    .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_3_sram ) , 
    .sram_inv ( mux_left_track_35_undriven_sram_inv ) , 
    .out ( chanx_left_out[17] ) , .p0 ( optlc_net_112 ) ) ;
sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 (
    .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_4_sram ) , 
    .sram_inv ( mux_left_track_37_undriven_sram_inv ) , 
    .out ( chanx_left_out[18] ) , .p0 ( optlc_net_113 ) ) ;
sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 (
    .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_5_sram ) , 
    .sram_inv ( mux_left_track_39_undriven_sram_inv ) , 
    .out ( chanx_left_out[19] ) , .p0 ( optlc_net_113 ) ) ;
sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
    .ccff_tail ( { ropt_net_117 } ) ,
    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , 
    .X ( ropt_net_130 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , 
    .X ( ropt_net_131 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , 
    .X ( ropt_net_133 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , 
    .X ( ropt_net_137 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[8] ) , 
    .X ( ropt_net_127 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , 
    .X ( chany_bottom_out[10] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , 
    .X ( chany_bottom_out[11] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_144 ) , 
    .X ( chany_bottom_out[13] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , 
    .HI ( optlc_net_111 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , 
    .X ( chany_bottom_out[15] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[16] ) , 
    .X ( ropt_net_132 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , 
    .X ( ropt_net_138 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , 
    .X ( chany_bottom_out[19] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , 
    .HI ( optlc_net_112 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[4] ) , 
    .X ( ropt_net_141 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , 
    .X ( ropt_net_129 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , 
    .HI ( optlc_net_113 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , 
    .HI ( optlc_net_114 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_115 ) , 
    .X ( chany_bottom_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_711 ( .A ( ropt_net_116 ) , 
    .X ( ropt_net_145 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , 
    .X ( ropt_net_140 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_117 ) , 
    .X ( ropt_net_164 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , 
    .X ( ropt_net_122 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chany_bottom_in[16] ) , 
    .X ( ropt_net_136 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( chany_bottom_in[8] ) , 
    .X ( ropt_net_148 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chany_bottom_in[18] ) , 
    .X ( ropt_net_139 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__26 ( 
    .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_134 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( Test_en__FEEDTHRU_0[0] ) , 
    .X ( ropt_net_125 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_bottom_in[10] ) , 
    .X ( ropt_net_120 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( ropt_net_145 ) , 
    .X ( chany_top_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( 
    .A ( chany_bottom_in[17] ) , .X ( ropt_net_151 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_120 ) , 
    .X ( ropt_net_146 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_88 ( .A ( chany_top_in[13] ) , 
    .X ( ropt_net_123 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_89 ( .A ( chany_bottom_in[2] ) , 
    .X ( ropt_net_124 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_90 ( .A ( chany_bottom_in[6] ) , 
    .X ( ropt_net_135 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_146 ) , 
    .X ( chany_top_out[11] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_92 ( .A ( chany_bottom_in[9] ) , 
    .X ( ropt_net_126 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_93 ( .A ( chany_bottom_in[13] ) , 
    .X ( ropt_net_128 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( chany_top_in[12] ) , 
    .X ( ropt_net_144 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_122 ) , 
    .X ( ropt_net_154 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_123 ) , 
    .X ( ropt_net_152 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_124 ) , 
    .X ( ropt_net_157 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_125 ) , 
    .X ( ropt_net_155 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_126 ) , 
    .X ( ropt_net_150 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_127 ) , 
    .X ( ropt_net_149 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_128 ) , 
    .X ( ropt_net_161 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_129 ) , 
    .X ( chany_top_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_130 ) , 
    .X ( chany_bottom_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_131 ) , 
    .X ( chany_bottom_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_132 ) , 
    .X ( ropt_net_162 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_133 ) , 
    .X ( ropt_net_163 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_134 ) , 
    .X ( ropt_net_147 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_135 ) , 
    .X ( ropt_net_159 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_136 ) , 
    .X ( ropt_net_158 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_137 ) , 
    .X ( ropt_net_160 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_138 ) , 
    .X ( chany_bottom_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , 
    .X ( ropt_net_156 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_140 ) , 
    .X ( chany_top_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_141 ) , 
    .X ( ropt_net_153 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_147 ) , 
    .X ( chanx_left_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_148 ) , 
    .X ( chany_top_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_149 ) , 
    .X ( chany_bottom_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_150 ) , 
    .X ( chany_top_out[10] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_151 ) , 
    .X ( chany_top_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_152 ) , 
    .X ( chany_bottom_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_153 ) , 
    .X ( chany_top_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_154 ) , 
    .X ( chany_top_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_155 ) , 
    .X ( Test_en__FEEDTHRU_1[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_156 ) , 
    .X ( chany_top_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_157 ) , 
    .X ( chany_top_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_158 ) , 
    .X ( chany_top_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_159 ) , 
    .X ( chany_top_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_160 ) , 
    .X ( chany_bottom_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_161 ) , 
    .X ( chany_top_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_162 ) , 
    .X ( chany_bottom_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_163 ) , 
    .X ( chany_bottom_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_164 ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__const1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_2__0__const1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_53 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_96 ( .A ( BUF_net_53 ) , 
    .X ( out[0] ) ) ;
endmodule


module sb_2__0__const1_28 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_2__0__const1_28 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
endmodule


module sb_2__0__const1_27 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_2__0__const1_27 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ;
endmodule


module sb_2__0__const1_26 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_2__0__const1_26 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__35 ( .A ( mem_out[1] ) , 
    .X ( net_net_60 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( net_net_60 ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__const1_25 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__0__const1_25 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_49 ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_2__0__const1_24 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__0__const1_24 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_2__0__const1_23 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

sb_2__0__const1_23 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module sb_2__0__const1_22 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__0__const1_22 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__0__const1_21 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__0__const1_21 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__0__const1_20 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__0__const1_20 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_2__0__const1_19 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__0__const1_19 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_2__0__const1_18 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__0__const1_18 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__0__const1_17 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__0__const1_17 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__0__const1_16 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__0__const1_16 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_89 ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_2__0__const1_15 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__0__const1_15 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_2__0__const1_14 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__0__const1_14 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_40 ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_40 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_87 ( .A ( BUF_net_40 ) , 
    .X ( out[0] ) ) ;
endmodule


module sb_2__0__const1_13 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__0__const1_13 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__0__const1_12 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__0__const1_12 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__0__const1_11 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__0__const1_11 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__0__const1_10 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__0__const1_10 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__0__const1_9 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__0__const1_9 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__0__const1_8 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__0__const1_8 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__0__const1_7 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__0__const1_7 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__0__const1_6 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_2__0__const1_6 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__const1_5 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_2__0__const1_5 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_2__0__const1_4 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_2__0__const1_4 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__const1_3 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:4] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;

sb_2__0__const1_3 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
endmodule


module sb_2__0__const1_2 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:4] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;

sb_2__0__const1_2 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_2__0__const1_1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_2__0__const1_1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
endmodule


module sb_2__0__const1_0 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_2__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_2__0__const1_0 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
endmodule


module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , 
    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
    top_left_grid_pin_49_ , top_right_grid_pin_1_ , chanx_left_in , 
    left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , 
    left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , 
    left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , 
    chany_top_out , chanx_left_out , ccff_tail ) ;
input  [0:0] prog_clk ;
input  [0:19] chany_top_in ;
input  [0:0] top_left_grid_pin_42_ ;
input  [0:0] top_left_grid_pin_43_ ;
input  [0:0] top_left_grid_pin_44_ ;
input  [0:0] top_left_grid_pin_45_ ;
input  [0:0] top_left_grid_pin_46_ ;
input  [0:0] top_left_grid_pin_47_ ;
input  [0:0] top_left_grid_pin_48_ ;
input  [0:0] top_left_grid_pin_49_ ;
input  [0:0] top_right_grid_pin_1_ ;
input  [0:19] chanx_left_in ;
input  [0:0] left_bottom_grid_pin_1_ ;
input  [0:0] left_bottom_grid_pin_3_ ;
input  [0:0] left_bottom_grid_pin_5_ ;
input  [0:0] left_bottom_grid_pin_7_ ;
input  [0:0] left_bottom_grid_pin_9_ ;
input  [0:0] left_bottom_grid_pin_11_ ;
input  [0:0] ccff_head ;
output [0:19] chany_top_out ;
output [0:19] chanx_left_out ;
output [0:0] ccff_tail ;

wire [0:1] mux_left_track_11_undriven_sram_inv ;
wire [0:1] mux_left_track_13_undriven_sram_inv ;
wire [0:1] mux_left_track_15_undriven_sram_inv ;
wire [0:1] mux_left_track_17_undriven_sram_inv ;
wire [0:1] mux_left_track_19_undriven_sram_inv ;
wire [0:2] mux_left_track_1_undriven_sram_inv ;
wire [0:1] mux_left_track_25_undriven_sram_inv ;
wire [0:1] mux_left_track_27_undriven_sram_inv ;
wire [0:1] mux_left_track_29_undriven_sram_inv ;
wire [0:1] mux_left_track_31_undriven_sram_inv ;
wire [0:1] mux_left_track_33_undriven_sram_inv ;
wire [0:1] mux_left_track_35_undriven_sram_inv ;
wire [0:2] mux_left_track_3_undriven_sram_inv ;
wire [0:2] mux_left_track_5_undriven_sram_inv ;
wire [0:2] mux_left_track_7_undriven_sram_inv ;
wire [0:1] mux_left_track_9_undriven_sram_inv ;
wire [0:2] mux_top_track_0_undriven_sram_inv ;
wire [0:1] mux_top_track_10_undriven_sram_inv ;
wire [0:1] mux_top_track_12_undriven_sram_inv ;
wire [0:1] mux_top_track_14_undriven_sram_inv ;
wire [0:1] mux_top_track_16_undriven_sram_inv ;
wire [0:1] mux_top_track_18_undriven_sram_inv ;
wire [0:1] mux_top_track_20_undriven_sram_inv ;
wire [0:1] mux_top_track_22_undriven_sram_inv ;
wire [0:1] mux_top_track_24_undriven_sram_inv ;
wire [0:1] mux_top_track_26_undriven_sram_inv ;
wire [0:2] mux_top_track_2_undriven_sram_inv ;
wire [0:2] mux_top_track_4_undriven_sram_inv ;
wire [0:2] mux_top_track_6_undriven_sram_inv ;
wire [0:1] mux_top_track_8_undriven_sram_inv ;
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
wire [0:1] mux_tree_tapbuf_size2_10_sram ;
wire [0:1] mux_tree_tapbuf_size2_11_sram ;
wire [0:1] mux_tree_tapbuf_size2_12_sram ;
wire [0:1] mux_tree_tapbuf_size2_13_sram ;
wire [0:1] mux_tree_tapbuf_size2_14_sram ;
wire [0:1] mux_tree_tapbuf_size2_15_sram ;
wire [0:1] mux_tree_tapbuf_size2_16_sram ;
wire [0:1] mux_tree_tapbuf_size2_17_sram ;
wire [0:1] mux_tree_tapbuf_size2_18_sram ;
wire [0:1] mux_tree_tapbuf_size2_19_sram ;
wire [0:1] mux_tree_tapbuf_size2_1_sram ;
wire [0:1] mux_tree_tapbuf_size2_2_sram ;
wire [0:1] mux_tree_tapbuf_size2_3_sram ;
wire [0:1] mux_tree_tapbuf_size2_4_sram ;
wire [0:1] mux_tree_tapbuf_size2_5_sram ;
wire [0:1] mux_tree_tapbuf_size2_6_sram ;
wire [0:1] mux_tree_tapbuf_size2_7_sram ;
wire [0:1] mux_tree_tapbuf_size2_8_sram ;
wire [0:1] mux_tree_tapbuf_size2_9_sram ;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size4_0_sram ;
wire [0:2] mux_tree_tapbuf_size4_1_sram ;
wire [0:2] mux_tree_tapbuf_size4_2_sram ;
wire [0:2] mux_tree_tapbuf_size4_3_sram ;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size5_0_sram ;
wire [0:2] mux_tree_tapbuf_size5_1_sram ;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size6_0_sram ;
wire [0:2] mux_tree_tapbuf_size6_1_sram ;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;

sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 (
    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
        top_right_grid_pin_1_[0] , chanx_left_in[0] } ) ,
    .sram ( mux_tree_tapbuf_size6_0_sram ) , 
    .sram_inv ( mux_top_track_0_undriven_sram_inv ) , 
    .out ( chany_top_out[0] ) , .p0 ( optlc_net_111 ) ) ;
sb_2__0__mux_tree_tapbuf_size6 mux_top_track_4 (
    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
        top_right_grid_pin_1_[0] , chanx_left_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size6_1_sram ) , 
    .sram_inv ( mux_top_track_4_undriven_sram_inv ) , 
    .out ( chany_top_out[2] ) , .p0 ( optlc_net_113 ) ) ;
sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 (
    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
        chanx_left_in[19] } ) ,
    .sram ( mux_tree_tapbuf_size5_0_sram ) , 
    .sram_inv ( mux_top_track_2_undriven_sram_inv ) , 
    .out ( chany_top_out[1] ) , .p0 ( optlc_net_113 ) ) ;
sb_2__0__mux_tree_tapbuf_size5 mux_top_track_6 (
    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
        chanx_left_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size5_1_sram ) , 
    .sram_inv ( mux_top_track_6_undriven_sram_inv ) , 
    .out ( chany_top_out[3] ) , .p0 ( optlc_net_111 ) ) ;
sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size3 mux_top_track_8 (
    .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , 
        chanx_left_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size3_0_sram ) , 
    .sram_inv ( mux_top_track_8_undriven_sram_inv ) , 
    .out ( chany_top_out[4] ) , .p0 ( optlc_net_113 ) ) ;
sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_24 (
    .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , 
        chanx_left_in[8] } ) ,
    .sram ( mux_tree_tapbuf_size3_1_sram ) , 
    .sram_inv ( mux_top_track_24_undriven_sram_inv ) , 
    .out ( chany_top_out[12] ) , .p0 ( optlc_net_113 ) ) ;
sb_2__0__mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_10 (
    .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) ,
    .sram ( mux_tree_tapbuf_size2_0_sram ) , 
    .sram_inv ( mux_top_track_10_undriven_sram_inv ) , 
    .out ( chany_top_out[5] ) , .p0 ( optlc_net_113 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_12 (
    .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size2_1_sram ) , 
    .sram_inv ( mux_top_track_12_undriven_sram_inv ) , 
    .out ( chany_top_out[6] ) , .p0 ( optlc_net_113 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_14 (
    .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) ,
    .sram ( mux_tree_tapbuf_size2_2_sram ) , 
    .sram_inv ( mux_top_track_14_undriven_sram_inv ) , 
    .out ( chany_top_out[7] ) , .p0 ( optlc_net_113 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_15 mux_top_track_16 (
    .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) ,
    .sram ( mux_tree_tapbuf_size2_3_sram ) , 
    .sram_inv ( mux_top_track_16_undriven_sram_inv ) , 
    .out ( chany_top_out[8] ) , .p0 ( optlc_net_111 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_16 mux_top_track_18 (
    .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) ,
    .sram ( mux_tree_tapbuf_size2_4_sram ) , 
    .sram_inv ( mux_top_track_18_undriven_sram_inv ) , 
    .out ( chany_top_out[9] ) , .p0 ( optlc_net_111 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_17 mux_top_track_20 (
    .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) ,
    .sram ( mux_tree_tapbuf_size2_5_sram ) , 
    .sram_inv ( mux_top_track_20_undriven_sram_inv ) , 
    .out ( chany_top_out[10] ) , .p0 ( optlc_net_111 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_18 mux_top_track_22 (
    .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) ,
    .sram ( mux_tree_tapbuf_size2_6_sram ) , 
    .sram_inv ( mux_top_track_22_undriven_sram_inv ) , 
    .out ( chany_top_out[11] ) , .p0 ( optlc_net_113 ) ) ;
sb_2__0__mux_tree_tapbuf_size2 mux_top_track_26 (
    .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) ,
    .sram ( mux_tree_tapbuf_size2_7_sram ) , 
    .sram_inv ( mux_top_track_26_undriven_sram_inv ) , 
    .out ( chany_top_out[13] ) , .p0 ( optlc_net_111 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_9 (
    .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_8_sram ) , 
    .sram_inv ( mux_left_track_9_undriven_sram_inv ) ,
    .out ( { ropt_net_138 } ) ,
    .p0 ( optlc_net_110 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_0 mux_left_track_11 (
    .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_9_sram ) , 
    .sram_inv ( mux_left_track_11_undriven_sram_inv ) ,
    .out ( { ropt_net_123 } ) ,
    .p0 ( optlc_net_112 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_1 mux_left_track_13 (
    .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_10_sram ) , 
    .sram_inv ( mux_left_track_13_undriven_sram_inv ) ,
    .out ( { ropt_net_124 } ) ,
    .p0 ( optlc_net_112 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_2 mux_left_track_15 (
    .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_11_sram ) , 
    .sram_inv ( mux_left_track_15_undriven_sram_inv ) , 
    .out ( chanx_left_out[7] ) , .p0 ( optlc_net_112 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_3 mux_left_track_17 (
    .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_12_sram ) , 
    .sram_inv ( mux_left_track_17_undriven_sram_inv ) , 
    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_110 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_4 mux_left_track_19 (
    .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_13_sram ) , 
    .sram_inv ( mux_left_track_19_undriven_sram_inv ) ,
    .out ( { ropt_net_116 } ) ,
    .p0 ( optlc_net_110 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_5 mux_left_track_25 (
    .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_14_sram ) , 
    .sram_inv ( mux_left_track_25_undriven_sram_inv ) ,
    .out ( { ropt_net_117 } ) ,
    .p0 ( optlc_net_113 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_6 mux_left_track_27 (
    .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_15_sram ) , 
    .sram_inv ( mux_left_track_27_undriven_sram_inv ) , 
    .out ( chanx_left_out[13] ) , .p0 ( optlc_net_113 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_7 mux_left_track_29 (
    .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_16_sram ) , 
    .sram_inv ( mux_left_track_29_undriven_sram_inv ) , 
    .out ( chanx_left_out[14] ) , .p0 ( optlc_net_110 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_31 (
    .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_17_sram ) , 
    .sram_inv ( mux_left_track_31_undriven_sram_inv ) , 
    .out ( chanx_left_out[15] ) , .p0 ( optlc_net_110 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_33 (
    .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_18_sram ) , 
    .sram_inv ( mux_left_track_33_undriven_sram_inv ) ,
    .out ( { ropt_net_122 } ) ,
    .p0 ( optlc_net_110 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_35 (
    .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_19_sram ) , 
    .sram_inv ( mux_left_track_35_undriven_sram_inv ) ,
    .out ( { ropt_net_118 } ) ,
    .p0 ( optlc_net_113 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
    .ccff_tail ( { ropt_net_125 } ) ,
    .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size4_0 mux_left_track_1 (
    .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , 
        left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) ,
    .sram ( mux_tree_tapbuf_size4_0_sram ) , 
    .sram_inv ( mux_left_track_1_undriven_sram_inv ) , 
    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_112 ) ) ;
sb_2__0__mux_tree_tapbuf_size4_1 mux_left_track_3 (
    .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , 
        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) ,
    .sram ( mux_tree_tapbuf_size4_1_sram ) , 
    .sram_inv ( mux_left_track_3_undriven_sram_inv ) ,
    .out ( { ropt_net_115 } ) ,
    .p0 ( optlc_net_112 ) ) ;
sb_2__0__mux_tree_tapbuf_size4_2 mux_left_track_5 (
    .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , 
        left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) ,
    .sram ( mux_tree_tapbuf_size4_2_sram ) , 
    .sram_inv ( mux_left_track_5_undriven_sram_inv ) , 
    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_112 ) ) ;
sb_2__0__mux_tree_tapbuf_size4 mux_left_track_7 (
    .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , 
        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) ,
    .sram ( mux_tree_tapbuf_size4_3_sram ) , 
    .sram_inv ( mux_left_track_7_undriven_sram_inv ) ,
    .out ( { ropt_net_142 } ) ,
    .p0 ( optlc_net_110 ) ) ;
sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , 
    .HI ( optlc_net_110 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , 
    .HI ( optlc_net_111 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_137 ) , 
    .X ( chanx_left_out[1] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , 
    .HI ( optlc_net_112 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , 
    .HI ( optlc_net_113 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_711 ( .A ( ropt_net_115 ) , 
    .X ( ropt_net_137 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chanx_left_in[3] ) , 
    .X ( ropt_net_127 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_116 ) , 
    .X ( ropt_net_144 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_left_in[5] ) , 
    .X ( ropt_net_128 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_117 ) , 
    .X ( chanx_left_out[12] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_54 ( .A ( chany_top_in[1] ) , 
    .X ( chanx_left_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_138 ) , 
    .X ( chanx_left_out[4] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( ropt_net_139 ) , 
    .X ( chanx_left_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( ropt_net_140 ) , 
    .X ( chany_top_out[15] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chanx_left_in[2] ) , 
    .X ( ropt_net_130 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_118 ) , 
    .X ( chanx_left_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chany_top_in[10] ) , 
    .X ( ropt_net_149 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( chany_top_in[9] ) , 
    .X ( chanx_left_out[11] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_79 ( .A ( chanx_left_in[1] ) , 
    .X ( ropt_net_126 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_80 ( .A ( chanx_left_in[4] ) , 
    .X ( ropt_net_129 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_81 ( .A ( chanx_left_in[6] ) , 
    .X ( ropt_net_131 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_141 ) , 
    .X ( chany_top_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_121 ) , 
    .X ( ropt_net_139 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_98 ( .A ( chany_top_in[2] ) , 
    .X ( ropt_net_121 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_142 ) , 
    .X ( chanx_left_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_122 ) , 
    .X ( chanx_left_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( ropt_net_123 ) , 
    .X ( chanx_left_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( ropt_net_124 ) , 
    .X ( ropt_net_150 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_125 ) , 
    .X ( ropt_net_147 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_126 ) , 
    .X ( ropt_net_141 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_127 ) , 
    .X ( ropt_net_145 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_128 ) , 
    .X ( ropt_net_140 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_129 ) , 
    .X ( ropt_net_146 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_130 ) , 
    .X ( ropt_net_148 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_131 ) , 
    .X ( ropt_net_143 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_143 ) , 
    .X ( chany_top_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_144 ) , 
    .X ( chanx_left_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_145 ) , 
    .X ( chany_top_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( ropt_net_146 ) , 
    .X ( chany_top_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_147 ) , 
    .X ( ccff_tail[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_148 ) , 
    .X ( chany_top_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , 
    .X ( chanx_left_out[10] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_150 ) , 
    .X ( chanx_left_out[6] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__61 ( .A ( mem_out[2] ) , 
    .X ( net_net_121 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_121 ( .A ( net_net_121 ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__const1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_1__2__const1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__60 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__const1_26 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_1__2__const1_26 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__59 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__58 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__57 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__56 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__55 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__54 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__const1_25 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_1__2__const1_25 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_1__2__const1_24 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_1__2__const1_24 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_1__2__const1_23 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_1__2__const1_23 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_1__2__const1_22 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_1__2__const1_22 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_1__2__const1_21 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_1__2__const1_21 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_1__2__const1_20 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_1__2__const1_20 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_68 ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_68 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( .A ( BUF_net_68 ) , 
    .X ( out[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__53 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__52 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__51 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__const1_19 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_1__2__const1_19 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_1__2__const1_18 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_1__2__const1_18 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
endmodule


module sb_1__2__const1_17 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_1__2__const1_17 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__50 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__const1_16 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:4] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;

sb_1__2__const1_16 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__49 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__48 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__47 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__46 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__45 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__44 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__43 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__42 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__const1_15 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__2__const1_15 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_1__2__const1_14 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__2__const1_14 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_1__2__const1_13 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__2__const1_13 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_1__2__const1_12 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__2__const1_12 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_1__2__const1_11 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__2__const1_11 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_1__2__const1_10 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__2__const1_10 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_1__2__const1_9 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__2__const1_9 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_1__2__const1_8 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__2__const1_8 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__41 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__40 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__const1_7 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

sb_1__2__const1_7 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module sb_1__2__const1_6 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

sb_1__2__const1_6 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__39 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__38 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__const1_5 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:13] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__2__const1_5 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
endmodule


module sb_1__2__const1_4 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ;
input  [0:13] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__2__const1_4 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__37 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__36 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__35 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__const1_3 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:8] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;

sb_1__2__const1_3 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
endmodule


module sb_1__2__const1_2 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:8] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;

sb_1__2__const1_2 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
endmodule


module sb_1__2__const1_1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
input  [0:8] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;

sb_1__2__const1_1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
endmodule


module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__34 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__2__const1_0 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__2__const1_0 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , 
    right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , 
    right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , 
    right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , 
    right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , 
    bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , 
    bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , 
    bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , 
    bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , 
    left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , 
    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
    left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , 
    chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , 
    SC_OUT_TOP , SC_OUT_BOT , 
    grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , 
    grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ;
input  [0:0] prog_clk ;
input  [0:19] chanx_right_in ;
input  [0:0] right_top_grid_pin_1_ ;
input  [0:0] right_bottom_grid_pin_34_ ;
input  [0:0] right_bottom_grid_pin_35_ ;
input  [0:0] right_bottom_grid_pin_36_ ;
input  [0:0] right_bottom_grid_pin_37_ ;
input  [0:0] right_bottom_grid_pin_38_ ;
input  [0:0] right_bottom_grid_pin_39_ ;
input  [0:0] right_bottom_grid_pin_40_ ;
input  [0:0] right_bottom_grid_pin_41_ ;
input  [0:19] chany_bottom_in ;
input  [0:0] bottom_left_grid_pin_42_ ;
input  [0:0] bottom_left_grid_pin_43_ ;
input  [0:0] bottom_left_grid_pin_44_ ;
input  [0:0] bottom_left_grid_pin_45_ ;
input  [0:0] bottom_left_grid_pin_46_ ;
input  [0:0] bottom_left_grid_pin_47_ ;
input  [0:0] bottom_left_grid_pin_48_ ;
input  [0:0] bottom_left_grid_pin_49_ ;
input  [0:19] chanx_left_in ;
input  [0:0] left_top_grid_pin_1_ ;
input  [0:0] left_bottom_grid_pin_34_ ;
input  [0:0] left_bottom_grid_pin_35_ ;
input  [0:0] left_bottom_grid_pin_36_ ;
input  [0:0] left_bottom_grid_pin_37_ ;
input  [0:0] left_bottom_grid_pin_38_ ;
input  [0:0] left_bottom_grid_pin_39_ ;
input  [0:0] left_bottom_grid_pin_40_ ;
input  [0:0] left_bottom_grid_pin_41_ ;
input  [0:0] ccff_head ;
output [0:19] chanx_right_out ;
output [0:19] chany_bottom_out ;
output [0:19] chanx_left_out ;
output [0:0] ccff_tail ;
input  SC_IN_TOP ;
input  SC_IN_BOT ;
output SC_OUT_TOP ;
output SC_OUT_BOT ;
input  [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ;
output [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ;

wire [0:2] mux_bottom_track_11_undriven_sram_inv ;
wire [0:1] mux_bottom_track_13_undriven_sram_inv ;
wire [0:1] mux_bottom_track_15_undriven_sram_inv ;
wire [0:1] mux_bottom_track_17_undriven_sram_inv ;
wire [0:1] mux_bottom_track_19_undriven_sram_inv ;
wire [0:2] mux_bottom_track_1_undriven_sram_inv ;
wire [0:1] mux_bottom_track_21_undriven_sram_inv ;
wire [0:1] mux_bottom_track_23_undriven_sram_inv ;
wire [0:2] mux_bottom_track_25_undriven_sram_inv ;
wire [0:1] mux_bottom_track_27_undriven_sram_inv ;
wire [0:2] mux_bottom_track_3_undriven_sram_inv ;
wire [0:2] mux_bottom_track_5_undriven_sram_inv ;
wire [0:2] mux_bottom_track_7_undriven_sram_inv ;
wire [0:2] mux_bottom_track_9_undriven_sram_inv ;
wire [0:2] mux_left_track_17_undriven_sram_inv ;
wire [0:3] mux_left_track_1_undriven_sram_inv ;
wire [0:2] mux_left_track_25_undriven_sram_inv ;
wire [0:2] mux_left_track_33_undriven_sram_inv ;
wire [0:3] mux_left_track_3_undriven_sram_inv ;
wire [0:3] mux_left_track_5_undriven_sram_inv ;
wire [0:3] mux_left_track_9_undriven_sram_inv ;
wire [0:3] mux_right_track_0_undriven_sram_inv ;
wire [0:2] mux_right_track_16_undriven_sram_inv ;
wire [0:2] mux_right_track_24_undriven_sram_inv ;
wire [0:3] mux_right_track_2_undriven_sram_inv ;
wire [0:2] mux_right_track_32_undriven_sram_inv ;
wire [0:3] mux_right_track_4_undriven_sram_inv ;
wire [0:3] mux_right_track_8_undriven_sram_inv ;
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size14_0_sram ;
wire [0:3] mux_tree_tapbuf_size14_1_sram ;
wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
wire [0:1] mux_tree_tapbuf_size3_2_sram ;
wire [0:1] mux_tree_tapbuf_size3_3_sram ;
wire [0:1] mux_tree_tapbuf_size3_4_sram ;
wire [0:1] mux_tree_tapbuf_size3_5_sram ;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size4_0_sram ;
wire [0:2] mux_tree_tapbuf_size4_1_sram ;
wire [0:2] mux_tree_tapbuf_size4_2_sram ;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size5_0_sram ;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size6_0_sram ;
wire [0:2] mux_tree_tapbuf_size7_0_sram ;
wire [0:2] mux_tree_tapbuf_size7_1_sram ;
wire [0:2] mux_tree_tapbuf_size7_2_sram ;
wire [0:2] mux_tree_tapbuf_size7_3_sram ;
wire [0:2] mux_tree_tapbuf_size7_4_sram ;
wire [0:2] mux_tree_tapbuf_size7_5_sram ;
wire [0:2] mux_tree_tapbuf_size7_6_sram ;
wire [0:2] mux_tree_tapbuf_size7_7_sram ;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size8_0_sram ;
wire [0:3] mux_tree_tapbuf_size8_1_sram ;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size9_0_sram ;
wire [0:3] mux_tree_tapbuf_size9_1_sram ;
wire [0:3] mux_tree_tapbuf_size9_2_sram ;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ;

assign SC_IN_TOP = SC_IN_BOT ;

sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 (
    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , 
        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , 
        right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , 
        chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , 
        chanx_left_in[12] } ) ,
    .sram ( mux_tree_tapbuf_size10_0_sram ) , 
    .sram_inv ( mux_right_track_0_undriven_sram_inv ) , 
    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_157 ) ) ;
sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size9 mux_right_track_2 (
    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
        chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , 
        chanx_left_in[4] , chanx_left_in[13] } ) ,
    .sram ( mux_tree_tapbuf_size9_0_sram ) , 
    .sram_inv ( mux_right_track_2_undriven_sram_inv ) , 
    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_157 ) ) ;
sb_1__2__mux_tree_tapbuf_size9_0 mux_left_track_1 (
    .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , 
        chany_bottom_in[13] , left_top_grid_pin_1_[0] , 
        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , 
        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
    .sram ( mux_tree_tapbuf_size9_1_sram ) , 
    .sram_inv ( mux_left_track_1_undriven_sram_inv ) , 
    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_156 ) ) ;
sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_3 (
    .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , 
        chany_bottom_in[7] , chany_bottom_in[14] , 
        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
    .sram ( mux_tree_tapbuf_size9_2_sram ) , 
    .sram_inv ( mux_left_track_3_undriven_sram_inv ) , 
    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_156 ) ) ;
sb_1__2__mux_tree_tapbuf_size9_mem mem_right_track_2 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 (
    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , 
        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , 
        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , 
        right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_40_[0] , 
        right_bottom_grid_pin_41_[0] , chany_bottom_in[3] , 
        chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , 
        chanx_left_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size14_0_sram ) , 
    .sram_inv ( mux_right_track_4_undriven_sram_inv ) , 
    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_157 ) ) ;
sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 (
    .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , 
        chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , 
        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , 
        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , 
        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , 
        left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) ,
    .sram ( mux_tree_tapbuf_size14_1_sram ) , 
    .sram_inv ( mux_left_track_5_undriven_sram_inv ) , 
    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_156 ) ) ;
sb_1__2__mux_tree_tapbuf_size14_mem mem_right_track_4 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size8 mux_right_track_8 (
    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , 
        right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , 
        chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , 
        chanx_left_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size8_0_sram ) , 
    .sram_inv ( mux_right_track_8_undriven_sram_inv ) , 
    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_157 ) ) ;
sb_1__2__mux_tree_tapbuf_size8_0 mux_left_track_9 (
    .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , 
        chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , 
        left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) ,
    .sram ( mux_tree_tapbuf_size8_1_sram ) , 
    .sram_inv ( mux_left_track_9_undriven_sram_inv ) , 
    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_156 ) ) ;
sb_1__2__mux_tree_tapbuf_size8_mem mem_right_track_8 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size7_6 mux_right_track_16 (
    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , 
        chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , 
        chanx_left_in[8] , chanx_left_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size7_0_sram ) , 
    .sram_inv ( mux_right_track_16_undriven_sram_inv ) , 
    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_157 ) ) ;
sb_1__2__mux_tree_tapbuf_size7 mux_right_track_24 (
    .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , 
        chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , 
        chanx_left_in[9] , chanx_left_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size7_1_sram ) , 
    .sram_inv ( mux_right_track_24_undriven_sram_inv ) , 
    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_157 ) ) ;
sb_1__2__mux_tree_tapbuf_size7_0 mux_bottom_track_1 (
    .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , 
        bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , 
        bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) ,
    .sram ( mux_tree_tapbuf_size7_2_sram ) , 
    .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , 
    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_158 ) ) ;
sb_1__2__mux_tree_tapbuf_size7_1 mux_bottom_track_3 (
    .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , 
        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
        bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) ,
    .sram ( mux_tree_tapbuf_size7_3_sram ) , 
    .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , 
    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_158 ) ) ;
sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_5 (
    .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , 
        bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , 
        bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) ,
    .sram ( mux_tree_tapbuf_size7_4_sram ) , 
    .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , 
    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_158 ) ) ;
sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_7 (
    .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , 
        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , 
        bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) ,
    .sram ( mux_tree_tapbuf_size7_5_sram ) , 
    .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , 
    .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_158 ) ) ;
sb_1__2__mux_tree_tapbuf_size7_4 mux_left_track_17 (
    .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , 
        chany_bottom_in[10] , chany_bottom_in[17] , 
        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) ,
    .sram ( mux_tree_tapbuf_size7_6_sram ) , 
    .sram_inv ( mux_left_track_17_undriven_sram_inv ) , 
    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_156 ) ) ;
sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_25 (
    .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , 
        chany_bottom_in[11] , chany_bottom_in[18] , 
        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) ,
    .sram ( mux_tree_tapbuf_size7_7_sram ) , 
    .sram_inv ( mux_left_track_25_undriven_sram_inv ) , 
    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_156 ) ) ;
sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size7_mem mem_right_track_24 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 (
    .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , 
        chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) ,
    .sram ( mux_tree_tapbuf_size5_0_sram ) , 
    .sram_inv ( mux_right_track_32_undriven_sram_inv ) , 
    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_157 ) ) ;
sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_9 (
    .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , 
        chanx_left_in[8] , chanx_left_in[15] } ) ,
    .sram ( mux_tree_tapbuf_size4_0_sram ) , 
    .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , 
    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_158 ) ) ;
sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_11 (
    .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , 
        chanx_left_in[9] , chanx_left_in[19] } ) ,
    .sram ( mux_tree_tapbuf_size4_1_sram ) , 
    .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , 
    .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_158 ) ) ;
sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_25 (
    .in ( { chanx_right_in[18] , chanx_right_in[19] , 
        bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size4_2_sram ) , 
    .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) ,
    .out ( { ropt_net_167 } ) ,
    .p0 ( optlc_net_159 ) ) ;
sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 (
    .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , 
        chanx_left_in[10] } ) ,
    .sram ( mux_tree_tapbuf_size3_0_sram ) , 
    .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) ,
    .out ( { ropt_net_168 } ) ,
    .p0 ( optlc_net_159 ) ) ;
sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 (
    .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , 
        chanx_left_in[12] } ) ,
    .sram ( mux_tree_tapbuf_size3_1_sram ) , 
    .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , 
    .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_159 ) ) ;
sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 (
    .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , 
        chanx_left_in[13] } ) ,
    .sram ( mux_tree_tapbuf_size3_2_sram ) , 
    .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , 
    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_159 ) ) ;
sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 (
    .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , 
        chanx_left_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size3_3_sram ) , 
    .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , 
    .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_159 ) ) ;
sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 (
    .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , 
        chanx_left_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size3_4_sram ) , 
    .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , 
    .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_159 ) ) ;
sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 (
    .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , 
        chanx_left_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size3_5_sram ) , 
    .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , 
    .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_157 ) ) ;
sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 (
    .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_0_sram ) , 
    .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , 
    .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_157 ) ) ;
sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 (
    .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , 
        chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , 
        left_bottom_grid_pin_40_[0] } ) ,
    .sram ( mux_tree_tapbuf_size6_0_sram ) , 
    .sram_inv ( mux_left_track_33_undriven_sram_inv ) , 
    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_156 ) ) ;
sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) ,
    .ccff_tail ( { ropt_net_173 } ) ,
    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , 
    .HI ( optlc_net_156 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , 
    .HI ( optlc_net_157 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , 
    .HI ( optlc_net_158 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , 
    .HI ( optlc_net_159 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_160 ) , 
    .X ( ropt_net_195 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , 
    .X ( ropt_net_204 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_192 ) , 
    .X ( chanx_left_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( chanx_right_in[6] ) , 
    .X ( chanx_left_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_162 ) , 
    .X ( chanx_left_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chanx_right_in[17] ) , 
    .X ( chanx_left_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_193 ) , 
    .X ( chanx_left_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chanx_right_in[7] ) , 
    .X ( ropt_net_206 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_194 ) , 
    .X ( chany_bottom_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_195 ) , 
    .X ( SC_OUT_BOT ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , 
    .X ( ropt_net_203 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chanx_right_in[9] ) , 
    .X ( ropt_net_207 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( chanx_right_in[2] ) , 
    .X ( ropt_net_209 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[18] ) , 
    .X ( chanx_left_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_167 ) , 
    .X ( chany_bottom_out[12] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__19 ( .A ( chanx_left_in[2] ) , 
    .X ( ropt_net_186 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_168 ) , 
    .X ( ropt_net_198 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[5] ) , 
    .X ( ropt_net_182 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_left_in[6] ) , 
    .X ( chanx_right_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chanx_right_in[0] ) , 
    .X ( chany_bottom_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_170 ) , 
    .X ( ropt_net_194 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_196 ) , 
    .X ( chany_bottom_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_right_in[10] ) , 
    .X ( chanx_left_out[11] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( chanx_left_in[13] ) , 
    .X ( chanx_right_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_197 ) , 
    .X ( chany_bottom_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_left_in[16] ) , 
    .X ( ropt_net_184 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , 
    .X ( ropt_net_185 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_173 ) , 
    .X ( ccff_tail[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , 
    .X ( ropt_net_160 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chanx_left_in[10] ) , 
    .X ( chanx_right_out[11] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_198 ) , 
    .X ( chany_bottom_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( ropt_net_199 ) , 
    .X ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_200 ) , 
    .X ( chanx_right_out[19] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( chanx_right_in[3] ) , 
    .X ( ropt_net_180 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( chanx_right_in[8] ) , 
    .X ( ropt_net_208 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[0] ) , 
    .X ( ropt_net_212 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_201 ) , 
    .X ( chanx_right_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_202 ) , 
    .X ( chanx_right_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_203 ) , 
    .X ( chanx_left_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_left_in[9] ) , 
    .X ( ropt_net_210 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_81 ( .A ( chanx_right_in[12] ) , 
    .X ( ropt_net_162 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( chanx_right_in[16] ) , 
    .X ( ropt_net_205 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[14] ) , 
    .X ( chanx_right_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_204 ) , 
    .X ( chanx_left_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_180 ) , 
    .X ( ropt_net_197 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[8] ) , 
    .X ( chanx_right_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( chanx_right_in[13] ) , 
    .X ( ropt_net_192 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_182 ) , 
    .X ( chanx_right_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chanx_left_in[12] ) , 
    .X ( ropt_net_202 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_205 ) , 
    .X ( chanx_left_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_left_in[4] ) , 
    .X ( ropt_net_211 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_184 ) , 
    .X ( chanx_right_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_185 ) , 
    .X ( chanx_right_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_186 ) , 
    .X ( ropt_net_201 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_187 ) , 
    .X ( ropt_net_200 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_188 ) , 
    .X ( ropt_net_199 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_189 ) , 
    .X ( ropt_net_193 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_190 ) , 
    .X ( ropt_net_196 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_206 ) , 
    .X ( chany_bottom_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_207 ) , 
    .X ( chanx_left_out[10] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_208 ) , 
    .X ( chanx_left_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_209 ) , 
    .X ( chanx_left_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_210 ) , 
    .X ( chanx_right_out[10] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_211 ) , 
    .X ( chanx_right_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_212 ) , 
    .X ( chany_bottom_out[19] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_113 ( .A ( chanx_left_in[18] ) , 
    .X ( ropt_net_187 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_123 ( .A ( chanx_right_in[4] ) , 
    .X ( ropt_net_189 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_129 ( .A ( chanx_right_in[1] ) , 
    .X ( ropt_net_170 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_135 ( .A ( chanx_right_in[11] ) , 
    .X ( ropt_net_190 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_142 ( 
    .A ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , 
    .X ( ropt_net_188 ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__84 ( .A ( mem_out[2] ) , 
    .X ( net_net_108 ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_108 ( .A ( net_net_108 ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__83 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__82 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__81 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__const1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__1__const1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_1__1__const1_26 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__1__const1_26 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_1__1__const1_25 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__1__const1_25 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_145 ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_1__1__const1_24 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_1__1__const1_24 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__80 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__79 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__78 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__77 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__76 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__75 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__74 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__73 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__72 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__71 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__70 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__69 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__const1_23 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_23 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module sb_1__1__const1_22 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_22 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module sb_1__1__const1_21 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_21 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_1__1__const1_20 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_20 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module sb_1__1__const1_19 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_19 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module sb_1__1__const1_18 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_18 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module sb_1__1__const1_17 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_17 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module sb_1__1__const1_16 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;

sb_1__1__const1_16 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ;
endmodule


module sb_1__1__const1_15 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_15 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module sb_1__1__const1_14 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_14 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module sb_1__1__const1_13 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_13 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
endmodule


module sb_1__1__const1_12 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
input  [0:9] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;

sb_1__1__const1_12 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:4] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__68 ( .A ( mem_out[4] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:4] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__67 ( .A ( mem_out[4] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:4] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__66 ( .A ( mem_out[4] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:4] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__65 ( .A ( mem_out[4] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__const1_11 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:15] in ;
input  [0:4] sram ;
input  [0:4] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_11 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ;
endmodule


module sb_1__1__const1_10 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:15] in ;
input  [0:4] sram ;
input  [0:4] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_10 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( 
    .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_1__1__const1_9 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:15] in ;
input  [0:4] sram ;
input  [0:4] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_9 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ;
endmodule


module sb_1__1__const1_8 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ;
input  [0:15] in ;
input  [0:4] sram ;
input  [0:4] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_8 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( 
    .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( BUF_net_89 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_142 ( .A ( BUF_net_89 ) , 
    .X ( out[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__64 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__63 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__62 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__61 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__60 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__59 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__58 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__57 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__1__const1_7 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:11] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_7 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
endmodule


module sb_1__1__const1_6 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:11] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_6 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
endmodule


module sb_1__1__const1_5 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:11] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_5 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
endmodule


module sb_1__1__const1_4 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:11] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_4 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
endmodule


module sb_1__1__const1_3 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:11] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_3 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
endmodule


module sb_1__1__const1_2 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:11] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_2 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
endmodule


module sb_1__1__const1_1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ;
input  [0:11] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ;
endmodule


module sb_1__1__const1_0 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:11] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__1__const1_0 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ;
endmodule


module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , 
    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
    top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_34_ , 
    right_bottom_grid_pin_35_ , right_bottom_grid_pin_36_ , 
    right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , 
    right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , 
    right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_42_ , 
    bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , 
    bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , 
    bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , 
    bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , 
    left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , 
    left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , 
    left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
    left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , 
    chany_bottom_out , chanx_left_out , ccff_tail , Test_en__FEEDTHRU_0 , 
    Test_en__FEEDTHRU_1 , 
    grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , 
    grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 , 
    grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 , 
    grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , 
    grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 , 
    grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , 
    grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ;
input  [0:0] prog_clk ;
input  [0:19] chany_top_in ;
input  [0:0] top_left_grid_pin_42_ ;
input  [0:0] top_left_grid_pin_43_ ;
input  [0:0] top_left_grid_pin_44_ ;
input  [0:0] top_left_grid_pin_45_ ;
input  [0:0] top_left_grid_pin_46_ ;
input  [0:0] top_left_grid_pin_47_ ;
input  [0:0] top_left_grid_pin_48_ ;
input  [0:0] top_left_grid_pin_49_ ;
input  [0:19] chanx_right_in ;
input  [0:0] right_bottom_grid_pin_34_ ;
input  [0:0] right_bottom_grid_pin_35_ ;
input  [0:0] right_bottom_grid_pin_36_ ;
input  [0:0] right_bottom_grid_pin_37_ ;
input  [0:0] right_bottom_grid_pin_38_ ;
input  [0:0] right_bottom_grid_pin_39_ ;
input  [0:0] right_bottom_grid_pin_40_ ;
input  [0:0] right_bottom_grid_pin_41_ ;
input  [0:19] chany_bottom_in ;
input  [0:0] bottom_left_grid_pin_42_ ;
input  [0:0] bottom_left_grid_pin_43_ ;
input  [0:0] bottom_left_grid_pin_44_ ;
input  [0:0] bottom_left_grid_pin_45_ ;
input  [0:0] bottom_left_grid_pin_46_ ;
input  [0:0] bottom_left_grid_pin_47_ ;
input  [0:0] bottom_left_grid_pin_48_ ;
input  [0:0] bottom_left_grid_pin_49_ ;
input  [0:19] chanx_left_in ;
input  [0:0] left_bottom_grid_pin_34_ ;
input  [0:0] left_bottom_grid_pin_35_ ;
input  [0:0] left_bottom_grid_pin_36_ ;
input  [0:0] left_bottom_grid_pin_37_ ;
input  [0:0] left_bottom_grid_pin_38_ ;
input  [0:0] left_bottom_grid_pin_39_ ;
input  [0:0] left_bottom_grid_pin_40_ ;
input  [0:0] left_bottom_grid_pin_41_ ;
input  [0:0] ccff_head ;
output [0:19] chany_top_out ;
output [0:19] chanx_right_out ;
output [0:19] chany_bottom_out ;
output [0:19] chanx_left_out ;
output [0:0] ccff_tail ;
input  [0:0] Test_en__FEEDTHRU_0 ;
output [0:0] Test_en__FEEDTHRU_1 ;
input  [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ;
output [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ;
output [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ;
input  [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ;
output [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ;
input  [0:0] grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ;
output [0:0] grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ;

wire [0:3] mux_bottom_track_17_undriven_sram_inv ;
wire [0:3] mux_bottom_track_1_undriven_sram_inv ;
wire [0:3] mux_bottom_track_25_undriven_sram_inv ;
wire [0:2] mux_bottom_track_33_undriven_sram_inv ;
wire [0:3] mux_bottom_track_3_undriven_sram_inv ;
wire [0:4] mux_bottom_track_5_undriven_sram_inv ;
wire [0:3] mux_bottom_track_9_undriven_sram_inv ;
wire [0:3] mux_left_track_17_undriven_sram_inv ;
wire [0:3] mux_left_track_1_undriven_sram_inv ;
wire [0:3] mux_left_track_25_undriven_sram_inv ;
wire [0:2] mux_left_track_33_undriven_sram_inv ;
wire [0:3] mux_left_track_3_undriven_sram_inv ;
wire [0:4] mux_left_track_5_undriven_sram_inv ;
wire [0:3] mux_left_track_9_undriven_sram_inv ;
wire [0:3] mux_right_track_0_undriven_sram_inv ;
wire [0:3] mux_right_track_16_undriven_sram_inv ;
wire [0:3] mux_right_track_24_undriven_sram_inv ;
wire [0:3] mux_right_track_2_undriven_sram_inv ;
wire [0:2] mux_right_track_32_undriven_sram_inv ;
wire [0:4] mux_right_track_4_undriven_sram_inv ;
wire [0:3] mux_right_track_8_undriven_sram_inv ;
wire [0:3] mux_top_track_0_undriven_sram_inv ;
wire [0:3] mux_top_track_16_undriven_sram_inv ;
wire [0:3] mux_top_track_24_undriven_sram_inv ;
wire [0:3] mux_top_track_2_undriven_sram_inv ;
wire [0:2] mux_top_track_32_undriven_sram_inv ;
wire [0:4] mux_top_track_4_undriven_sram_inv ;
wire [0:3] mux_top_track_8_undriven_sram_inv ;
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
wire [0:3] mux_tree_tapbuf_size10_10_sram ;
wire [0:3] mux_tree_tapbuf_size10_11_sram ;
wire [0:3] mux_tree_tapbuf_size10_1_sram ;
wire [0:3] mux_tree_tapbuf_size10_2_sram ;
wire [0:3] mux_tree_tapbuf_size10_3_sram ;
wire [0:3] mux_tree_tapbuf_size10_4_sram ;
wire [0:3] mux_tree_tapbuf_size10_5_sram ;
wire [0:3] mux_tree_tapbuf_size10_6_sram ;
wire [0:3] mux_tree_tapbuf_size10_7_sram ;
wire [0:3] mux_tree_tapbuf_size10_8_sram ;
wire [0:3] mux_tree_tapbuf_size10_9_sram ;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size12_0_sram ;
wire [0:3] mux_tree_tapbuf_size12_1_sram ;
wire [0:3] mux_tree_tapbuf_size12_2_sram ;
wire [0:3] mux_tree_tapbuf_size12_3_sram ;
wire [0:3] mux_tree_tapbuf_size12_4_sram ;
wire [0:3] mux_tree_tapbuf_size12_5_sram ;
wire [0:3] mux_tree_tapbuf_size12_6_sram ;
wire [0:3] mux_tree_tapbuf_size12_7_sram ;
wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
wire [0:4] mux_tree_tapbuf_size16_0_sram ;
wire [0:4] mux_tree_tapbuf_size16_1_sram ;
wire [0:4] mux_tree_tapbuf_size16_2_sram ;
wire [0:4] mux_tree_tapbuf_size16_3_sram ;
wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size7_0_sram ;
wire [0:2] mux_tree_tapbuf_size7_1_sram ;
wire [0:2] mux_tree_tapbuf_size7_2_sram ;
wire [0:2] mux_tree_tapbuf_size7_3_sram ;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;

sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 (
    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
        chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , 
        chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , 
        chanx_left_in[2] , chanx_left_in[12] } ) ,
    .sram ( mux_tree_tapbuf_size12_0_sram ) , 
    .sram_inv ( mux_top_track_0_undriven_sram_inv ) , 
    .out ( chany_top_out[0] ) , .p0 ( optlc_net_165 ) ) ;
sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 (
    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
        chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , 
        chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , 
        chanx_left_in[13] , chanx_left_in[19] } ) ,
    .sram ( mux_tree_tapbuf_size12_1_sram ) , 
    .sram_inv ( mux_top_track_2_undriven_sram_inv ) , 
    .out ( chany_top_out[1] ) , .p0 ( optlc_net_162 ) ) ;
sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 (
    .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , 
        right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
        chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , 
        chanx_left_in[2] , chanx_left_in[12] } ) ,
    .sram ( mux_tree_tapbuf_size12_2_sram ) , 
    .sram_inv ( mux_right_track_0_undriven_sram_inv ) , 
    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_166 ) ) ;
sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 (
    .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , 
        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , 
        right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , 
        chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , 
        chanx_left_in[4] , chanx_left_in[13] } ) ,
    .sram ( mux_tree_tapbuf_size12_3_sram ) , 
    .sram_inv ( mux_right_track_2_undriven_sram_inv ) , 
    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_166 ) ) ;
sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 (
    .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , 
        chanx_right_in[12] , chanx_right_in[15] , 
        bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , 
        bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , 
        chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) ,
    .sram ( mux_tree_tapbuf_size12_4_sram ) , 
    .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , 
    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_163 ) ) ;
sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 (
    .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , 
        chanx_right_in[11] , chanx_right_in[13] , 
        bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , 
        bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , 
        chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) ,
    .sram ( mux_tree_tapbuf_size12_5_sram ) , 
    .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , 
    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_163 ) ) ;
sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 (
    .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , 
        chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , 
        chany_bottom_in[12] , chany_bottom_in[19] , 
        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , 
        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
    .sram ( mux_tree_tapbuf_size12_6_sram ) , 
    .sram_inv ( mux_left_track_1_undriven_sram_inv ) , 
    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_164 ) ) ;
sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 (
    .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , 
        chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , 
        chany_bottom_in[4] , chany_bottom_in[13] , 
        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , 
        left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
    .sram ( mux_tree_tapbuf_size12_7_sram ) , 
    .sram_inv ( mux_left_track_3_undriven_sram_inv ) , 
    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_165 ) ) ;
sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 (
    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , 
        top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , 
        top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , 
        top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , 
        chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , 
        chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , 
        chanx_left_in[14] , chanx_left_in[15] } ) ,
    .sram ( mux_tree_tapbuf_size16_0_sram ) , 
    .sram_inv ( mux_top_track_4_undriven_sram_inv ) , 
    .out ( chany_top_out[2] ) , .p0 ( optlc_net_165 ) ) ;
sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 (
    .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , 
        right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , 
        right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , 
        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_39_[0] , 
        right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_41_[0] , 
        chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , 
        chanx_left_in[5] , chanx_left_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size16_1_sram ) , 
    .sram_inv ( mux_right_track_4_undriven_sram_inv ) , 
    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_166 ) ) ;
sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 (
    .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , 
        chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , 
        bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , 
        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , 
        bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , 
        bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , 
        chanx_left_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size16_2_sram ) , 
    .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) ,
    .out ( { ropt_net_172 } ) ,
    .p0 ( optlc_net_165 ) ) ;
sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 (
    .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , 
        chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , 
        chany_bottom_in[5] , chany_bottom_in[14] , 
        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , 
        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , 
        left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , 
        left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) ,
    .sram ( mux_tree_tapbuf_size16_3_sram ) , 
    .sram_inv ( mux_left_track_5_undriven_sram_inv ) , 
    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_165 ) ) ;
sb_1__1__mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size16_0_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size16_1_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size16_2_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size16_3_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10 mux_top_track_8 (
    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , 
        chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , 
        chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , 
        chanx_left_in[11] , chanx_left_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size10_0_sram ) , 
    .sram_inv ( mux_top_track_8_undriven_sram_inv ) , 
    .out ( chany_top_out[4] ) , .p0 ( optlc_net_162 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 (
    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , 
        chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , 
        chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , 
        chanx_left_in[8] , chanx_left_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size10_1_sram ) , 
    .sram_inv ( mux_top_track_16_undriven_sram_inv ) , 
    .out ( chany_top_out[8] ) , .p0 ( optlc_net_162 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_10 mux_top_track_24 (
    .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , 
        chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , 
        chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , 
        chanx_left_in[9] , chanx_left_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size10_2_sram ) , 
    .sram_inv ( mux_top_track_24_undriven_sram_inv ) , 
    .out ( chany_top_out[12] ) , .p0 ( optlc_net_162 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_8 mux_right_track_8 (
    .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , 
        right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , 
        chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , 
        chanx_left_in[6] , chanx_left_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size10_3_sram ) , 
    .sram_inv ( mux_right_track_8_undriven_sram_inv ) , 
    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_167 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_6 mux_right_track_16 (
    .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , 
        right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , 
        chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , 
        chanx_left_in[8] , chanx_left_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size10_4_sram ) , 
    .sram_inv ( mux_right_track_16_undriven_sram_inv ) , 
    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_167 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_7 mux_right_track_24 (
    .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , 
        right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , 
        chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , 
        chanx_left_in[9] , chanx_left_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size10_5_sram ) , 
    .sram_inv ( mux_right_track_24_undriven_sram_inv ) , 
    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_167 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_2 mux_bottom_track_9 (
    .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , 
        chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , 
        bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , 
        chanx_left_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size10_6_sram ) , 
    .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , 
    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_165 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_0 mux_bottom_track_17 (
    .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , 
        chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , 
        bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , 
        chanx_left_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size10_7_sram ) , 
    .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , 
    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_166 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_1 mux_bottom_track_25 (
    .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , 
        chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , 
        bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , 
        chanx_left_in[19] } ) ,
    .sram ( mux_tree_tapbuf_size10_8_sram ) , 
    .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , 
    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_162 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_5 mux_left_track_9 (
    .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , 
        chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , 
        chany_bottom_in[6] , chany_bottom_in[16] , 
        left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) ,
    .sram ( mux_tree_tapbuf_size10_9_sram ) , 
    .sram_inv ( mux_left_track_9_undriven_sram_inv ) ,
    .out ( { ropt_net_173 } ) ,
    .p0 ( optlc_net_165 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_3 mux_left_track_17 (
    .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , 
        chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , 
        chany_bottom_in[8] , chany_bottom_in[17] , 
        left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) ,
    .sram ( mux_tree_tapbuf_size10_10_sram ) , 
    .sram_inv ( mux_left_track_17_undriven_sram_inv ) , 
    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_162 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_4 mux_left_track_25 (
    .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , 
        chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , 
        chany_bottom_in[11] , chany_bottom_in[18] , 
        left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) ,
    .sram ( mux_tree_tapbuf_size10_11_sram ) , 
    .sram_inv ( mux_left_track_25_undriven_sram_inv ) , 
    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_165 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size7 mux_top_track_32 (
    .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , 
        chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , 
        chanx_left_in[1] , chanx_left_in[10] } ) ,
    .sram ( mux_tree_tapbuf_size7_0_sram ) , 
    .sram_inv ( mux_top_track_32_undriven_sram_inv ) , 
    .out ( chany_top_out[16] ) , .p0 ( optlc_net_167 ) ) ;
sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 (
    .in ( { chany_top_in[10] , chany_top_in[15] , 
        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , 
        chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) ,
    .sram ( mux_tree_tapbuf_size7_1_sram ) , 
    .sram_inv ( mux_right_track_32_undriven_sram_inv ) ,
    .out ( { ropt_net_178 } ) ,
    .p0 ( optlc_net_163 ) ) ;
sb_1__1__mux_tree_tapbuf_size7_0 mux_bottom_track_33 (
    .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , 
        bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , 
        chanx_left_in[0] , chanx_left_in[10] } ) ,
    .sram ( mux_tree_tapbuf_size7_2_sram ) , 
    .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , 
    .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_163 ) ) ;
sb_1__1__mux_tree_tapbuf_size7_1 mux_left_track_33 (
    .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , 
        chany_bottom_in[10] , chany_bottom_in[15] , 
        left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) ,
    .sram ( mux_tree_tapbuf_size7_3_sram ) , 
    .sram_inv ( mux_left_track_33_undriven_sram_inv ) , 
    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_164 ) ) ;
sb_1__1__mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) ,
    .ccff_tail ( { ropt_net_174 } ) ,
    .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , 
    .X ( ropt_net_208 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[4] ) , 
    .X ( ropt_net_218 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , 
    .X ( ropt_net_251 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , 
    .X ( ropt_net_199 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , 
    .X ( chany_bottom_out[9] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , 
    .X ( ropt_net_196 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , 
    .X ( ropt_net_204 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , 
    .X ( chany_bottom_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , 
    .X ( ropt_net_216 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , 
    .HI ( optlc_net_162 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , 
    .X ( ropt_net_217 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , 
    .HI ( optlc_net_163 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , 
    .X ( ropt_net_214 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , 
    .HI ( optlc_net_164 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , 
    .X ( ropt_net_205 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chanx_right_in[5] ) , 
    .X ( ropt_net_185 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_right_in[6] ) , 
    .X ( ropt_net_247 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , 
    .X ( ropt_net_190 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , 
    .HI ( optlc_net_165 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , 
    .HI ( optlc_net_166 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_223 ) , 
    .X ( chanx_left_out[4] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_224 ) , 
    .X ( chanx_left_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , 
    .X ( chanx_left_out[15] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , 
    .X ( ropt_net_212 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , 
    .X ( chanx_left_out[18] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , 
    .HI ( optlc_net_167 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( 
    .A ( chany_bottom_in[10] ) , .X ( ropt_net_250 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chanx_right_in[9] ) , 
    .X ( chanx_left_out[10] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chany_bottom_in[5] ) , 
    .X ( ropt_net_192 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , 
    .X ( ropt_net_194 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , 
    .X ( chany_top_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , 
    .X ( ropt_net_206 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_843 ( .A ( ropt_net_225 ) , 
    .X ( chanx_right_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , 
    .X ( ropt_net_195 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , 
    .X ( ropt_net_203 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_bottom_in[14] ) , 
    .X ( ropt_net_215 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , 
    .X ( ropt_net_186 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , 
    .X ( ropt_net_197 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , 
    .X ( ropt_net_198 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_left_in[2] ) , 
    .X ( ropt_net_207 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_172 ) , 
    .X ( chany_bottom_out[2] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_173 ) , 
    .X ( ropt_net_223 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_174 ) , 
    .X ( ropt_net_233 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( chanx_left_in[5] ) , 
    .X ( ropt_net_252 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_right_in[10] ) , 
    .X ( ropt_net_248 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , 
    .X ( ropt_net_182 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , 
    .X ( chanx_right_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , 
    .X ( ropt_net_210 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_49__48 ( .A ( chanx_left_in[14] ) , 
    .X ( ropt_net_213 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_50__49 ( .A ( chanx_left_in[16] ) , 
    .X ( ropt_net_201 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_51__50 ( .A ( chanx_left_in[17] ) , 
    .X ( chanx_right_out[18] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , 
    .X ( ropt_net_211 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_right_in[18] ) , 
    .X ( chanx_left_out[19] ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 FTB_54__53 ( 
    .A ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , 
    .X ( aps_rename_1_ ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_55__54 ( 
    .A ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , 
    .X ( ropt_net_202 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_178 ) , 
    .X ( chanx_right_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_179 ) , 
    .X ( chanx_right_out[10] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_99 ( .A ( chany_bottom_in[4] ) , 
    .X ( BUF_net_99 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[12] ) , 
    .X ( ropt_net_249 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_844 ( .A ( ropt_net_226 ) , 
    .X ( chany_bottom_out[10] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_102 ( .A ( chanx_left_in[8] ) , 
    .X ( ropt_net_188 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_181 ) , 
    .X ( chany_bottom_out[18] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( Test_en__FEEDTHRU_0[0] ) , 
    .X ( ropt_net_193 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_182 ) , 
    .X ( chanx_right_out[11] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[13] ) , 
    .X ( chanx_left_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_184 ) , 
    .X ( ropt_net_244 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_185 ) , 
    .X ( ropt_net_234 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_186 ) , 
    .X ( ropt_net_239 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_187 ) , 
    .X ( ropt_net_225 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_top_in[14] ) , 
    .X ( ropt_net_209 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( .A ( chany_top_in[17] ) , 
    .X ( ropt_net_181 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( .A ( chanx_right_in[2] ) , 
    .X ( ropt_net_200 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_845 ( .A ( ropt_net_227 ) , 
    .X ( chany_top_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_228 ) , 
    .X ( chany_bottom_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_229 ) , 
    .X ( chanx_left_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( chany_bottom_in[2] ) , 
    .X ( ropt_net_191 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_132 ( .A ( chanx_left_in[4] ) , 
    .X ( ropt_net_187 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chanx_left_in[6] ) , 
    .X ( ropt_net_184 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_134 ( 
    .A ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , 
    .X ( ropt_net_219 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_137 ( .A ( aps_rename_1_ ) , 
    .X ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_138 ( 
    .A ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , 
    .X ( ropt_net_189 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( BUF_net_99 ) , 
    .X ( chany_top_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_230 ) , 
    .X ( chany_top_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_148 ( .A ( chanx_left_in[9] ) , 
    .X ( ropt_net_179 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_188 ) , 
    .X ( ropt_net_237 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_189 ) , 
    .X ( ropt_net_236 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_190 ) , 
    .X ( ropt_net_229 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_191 ) , 
    .X ( chany_top_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_192 ) , 
    .X ( ropt_net_230 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_193 ) , 
    .X ( ropt_net_241 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_194 ) , 
    .X ( chany_top_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_195 ) , 
    .X ( chany_top_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_196 ) , 
    .X ( ropt_net_226 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_197 ) , 
    .X ( ropt_net_231 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_198 ) , 
    .X ( ropt_net_227 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_199 ) , 
    .X ( chany_bottom_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_200 ) , 
    .X ( ropt_net_224 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_201 ) , 
    .X ( chanx_right_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_202 ) , 
    .X ( ropt_net_235 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_203 ) , 
    .X ( chany_top_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_204 ) , 
    .X ( ropt_net_245 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_205 ) , 
    .X ( ropt_net_240 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_206 ) , 
    .X ( chany_top_out[10] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_207 ) , 
    .X ( chanx_right_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_208 ) , 
    .X ( chany_bottom_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_209 ) , 
    .X ( ropt_net_246 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_210 ) , 
    .X ( chanx_right_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_211 ) , 
    .X ( ropt_net_243 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_212 ) , 
    .X ( ropt_net_232 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_213 ) , 
    .X ( chanx_right_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_214 ) , 
    .X ( chany_bottom_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_215 ) , 
    .X ( ropt_net_242 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_216 ) , 
    .X ( chany_bottom_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_217 ) , 
    .X ( chany_bottom_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_218 ) , 
    .X ( ropt_net_228 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_219 ) , 
    .X ( ropt_net_238 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_850 ( .A ( ropt_net_231 ) , 
    .X ( chany_top_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_232 ) , 
    .X ( chanx_left_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_233 ) , 
    .X ( ccff_tail[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_853 ( .A ( ropt_net_234 ) , 
    .X ( chanx_left_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_854 ( .A ( ropt_net_235 ) , 
    .X ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_236 ) , 
    .X ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_237 ) , 
    .X ( chanx_right_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_857 ( .A ( ropt_net_238 ) , 
    .X ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_861 ( .A ( ropt_net_239 ) , 
    .X ( chany_top_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_240 ) , 
    .X ( chanx_left_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_241 ) , 
    .X ( Test_en__FEEDTHRU_1[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_242 ) , 
    .X ( chany_top_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_869 ( .A ( ropt_net_243 ) , 
    .X ( chanx_right_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_870 ( .A ( ropt_net_244 ) , 
    .X ( chanx_right_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_245 ) , 
    .X ( chany_bottom_out[11] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_246 ) , 
    .X ( chany_bottom_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_880 ( .A ( ropt_net_247 ) , 
    .X ( chanx_left_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_248 ) , 
    .X ( chanx_left_out[11] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_884 ( .A ( ropt_net_249 ) , 
    .X ( chanx_left_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_885 ( .A ( ropt_net_250 ) , 
    .X ( chany_top_out[11] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_886 ( .A ( ropt_net_251 ) , 
    .X ( chany_bottom_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_889 ( .A ( ropt_net_252 ) , 
    .X ( chanx_right_out[6] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__67 ( .A ( mem_out[2] ) , 
    .X ( net_net_94 ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_94 ( .A ( net_net_94 ) , 
    .X ( net_net_93 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_118 ( .A ( net_net_93 ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__66 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__const1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:4] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;

sb_1__0__const1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
endmodule


module sb_1__0__const1_26 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:4] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;

sb_1__0__const1_26 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__65 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__64 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__const1_25 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;

sb_1__0__const1_25 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ;
endmodule


module sb_1__0__const1_24 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_1__0__const1_24 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__63 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__62 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__const1_23 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:10] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__0__const1_23 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
endmodule


module sb_1__0__const1_22 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ;
input  [0:10] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sb_1__0__const1_22 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__61 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__const1_21 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_1__0__const1_21 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__60 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__59 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__58 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__57 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__56 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__54 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__const1_20 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_1__0__const1_20 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_1__0__const1_19 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_1__0__const1_19 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_1__0__const1_18 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_1__0__const1_18 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_1__0__const1_17 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_1__0__const1_17 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_1__0__const1_16 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_1__0__const1_16 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_1__0__const1_15 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_1__0__const1_15 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_1__0__const1_14 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_1__0__const1_14 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__53 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__52 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__const1_13 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_1__0__const1_13 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
endmodule


module sb_1__0__const1_12 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_1__0__const1_12 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__51 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__50 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__49 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__48 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__47 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__46 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__45 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__44 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__43 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__const1_11 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__0__const1_11 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_1__0__const1_10 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__0__const1_10 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_1__0__const1_9 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__0__const1_9 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_1__0__const1_8 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__0__const1_8 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_1__0__const1_7 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__0__const1_7 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_1__0__const1_6 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__0__const1_6 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_1__0__const1_5 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__0__const1_5 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_1__0__const1_4 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__0__const1_4 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_1__0__const1_3 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_1__0__const1_3 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__42 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_1__0__const1_2 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

sb_1__0__const1_2 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module sb_1__0__const1_1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

sb_1__0__const1_1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module sb_1__0__const1_0 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
input  [0:7] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;

sb_1__0__const1_0 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
endmodule


module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , 
    top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , 
    top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , 
    top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_1_ , 
    right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , 
    right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , 
    right_bottom_grid_pin_11_ , chanx_left_in , left_bottom_grid_pin_1_ , 
    left_bottom_grid_pin_3_ , left_bottom_grid_pin_5_ , 
    left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , 
    left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , 
    chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , 
    SC_OUT_BOT , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , 
    Test_en__FEEDTHRU_2 , Test_en__FEEDTHRU_3 , Test_en__FEEDTHRU_4 , 
    Test_en__FEEDTHRU_5 , Test_en__FEEDTHRU_6 , Test_en__FEEDTHRU_7 , 
    Test_en__FEEDTHRU_8 , 
    grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , 
    grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ;
input  [0:0] prog_clk ;
input  [0:19] chany_top_in ;
input  [0:0] top_left_grid_pin_42_ ;
input  [0:0] top_left_grid_pin_43_ ;
input  [0:0] top_left_grid_pin_44_ ;
input  [0:0] top_left_grid_pin_45_ ;
input  [0:0] top_left_grid_pin_46_ ;
input  [0:0] top_left_grid_pin_47_ ;
input  [0:0] top_left_grid_pin_48_ ;
input  [0:0] top_left_grid_pin_49_ ;
input  [0:19] chanx_right_in ;
input  [0:0] right_bottom_grid_pin_1_ ;
input  [0:0] right_bottom_grid_pin_3_ ;
input  [0:0] right_bottom_grid_pin_5_ ;
input  [0:0] right_bottom_grid_pin_7_ ;
input  [0:0] right_bottom_grid_pin_9_ ;
input  [0:0] right_bottom_grid_pin_11_ ;
input  [0:19] chanx_left_in ;
input  [0:0] left_bottom_grid_pin_1_ ;
input  [0:0] left_bottom_grid_pin_3_ ;
input  [0:0] left_bottom_grid_pin_5_ ;
input  [0:0] left_bottom_grid_pin_7_ ;
input  [0:0] left_bottom_grid_pin_9_ ;
input  [0:0] left_bottom_grid_pin_11_ ;
input  [0:0] ccff_head ;
output [0:19] chany_top_out ;
output [0:19] chanx_right_out ;
output [0:19] chanx_left_out ;
output [0:0] ccff_tail ;
input  SC_IN_TOP ;
input  SC_IN_BOT ;
output SC_OUT_TOP ;
output SC_OUT_BOT ;
input  [0:0] Test_en__FEEDTHRU_0 ;
output [0:0] Test_en__FEEDTHRU_1 ;
output [0:0] Test_en__FEEDTHRU_2 ;
output [0:0] Test_en__FEEDTHRU_3 ;
input  [0:0] Test_en__FEEDTHRU_4 ;
output [0:0] Test_en__FEEDTHRU_5 ;
input  [0:0] Test_en__FEEDTHRU_6 ;
output [0:0] Test_en__FEEDTHRU_7 ;
output [0:0] Test_en__FEEDTHRU_8 ;
input  [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ;
output [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ;

wire [0:2] mux_left_track_17_undriven_sram_inv ;
wire [0:3] mux_left_track_1_undriven_sram_inv ;
wire [0:2] mux_left_track_25_undriven_sram_inv ;
wire [0:2] mux_left_track_33_undriven_sram_inv ;
wire [0:2] mux_left_track_3_undriven_sram_inv ;
wire [0:3] mux_left_track_5_undriven_sram_inv ;
wire [0:2] mux_left_track_9_undriven_sram_inv ;
wire [0:2] mux_right_track_0_undriven_sram_inv ;
wire [0:2] mux_right_track_16_undriven_sram_inv ;
wire [0:2] mux_right_track_24_undriven_sram_inv ;
wire [0:3] mux_right_track_2_undriven_sram_inv ;
wire [0:2] mux_right_track_32_undriven_sram_inv ;
wire [0:3] mux_right_track_4_undriven_sram_inv ;
wire [0:2] mux_right_track_8_undriven_sram_inv ;
wire [0:3] mux_top_track_0_undriven_sram_inv ;
wire [0:2] mux_top_track_10_undriven_sram_inv ;
wire [0:1] mux_top_track_12_undriven_sram_inv ;
wire [0:1] mux_top_track_14_undriven_sram_inv ;
wire [0:1] mux_top_track_16_undriven_sram_inv ;
wire [0:1] mux_top_track_18_undriven_sram_inv ;
wire [0:1] mux_top_track_20_undriven_sram_inv ;
wire [0:1] mux_top_track_22_undriven_sram_inv ;
wire [0:1] mux_top_track_24_undriven_sram_inv ;
wire [0:2] mux_top_track_2_undriven_sram_inv ;
wire [0:1] mux_top_track_38_undriven_sram_inv ;
wire [0:2] mux_top_track_4_undriven_sram_inv ;
wire [0:2] mux_top_track_6_undriven_sram_inv ;
wire [0:2] mux_top_track_8_undriven_sram_inv ;
wire [0:3] mux_tree_tapbuf_size11_0_sram ;
wire [0:3] mux_tree_tapbuf_size11_1_sram ;
wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
wire [0:1] mux_tree_tapbuf_size3_2_sram ;
wire [0:1] mux_tree_tapbuf_size3_3_sram ;
wire [0:1] mux_tree_tapbuf_size3_4_sram ;
wire [0:1] mux_tree_tapbuf_size3_5_sram ;
wire [0:1] mux_tree_tapbuf_size3_6_sram ;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size4_0_sram ;
wire [0:2] mux_tree_tapbuf_size4_1_sram ;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size5_0_sram ;
wire [0:2] mux_tree_tapbuf_size5_1_sram ;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size6_0_sram ;
wire [0:2] mux_tree_tapbuf_size6_1_sram ;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size7_0_sram ;
wire [0:2] mux_tree_tapbuf_size7_1_sram ;
wire [0:2] mux_tree_tapbuf_size7_2_sram ;
wire [0:2] mux_tree_tapbuf_size7_3_sram ;
wire [0:2] mux_tree_tapbuf_size7_4_sram ;
wire [0:2] mux_tree_tapbuf_size7_5_sram ;
wire [0:2] mux_tree_tapbuf_size7_6_sram ;
wire [0:2] mux_tree_tapbuf_size7_7_sram ;
wire [0:2] mux_tree_tapbuf_size7_8_sram ;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size8_0_sram ;
wire [0:3] mux_tree_tapbuf_size8_1_sram ;
wire [0:3] mux_tree_tapbuf_size8_2_sram ;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;

assign SC_IN_TOP = SC_IN_BOT ;

sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 (
    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
        chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , 
        chanx_left_in[2] } ) ,
    .sram ( mux_tree_tapbuf_size8_0_sram ) , 
    .sram_inv ( mux_top_track_0_undriven_sram_inv ) , 
    .out ( chany_top_out[0] ) , .p0 ( optlc_net_137 ) ) ;
sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_2 (
    .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , 
        right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , 
        right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) ,
    .sram ( mux_tree_tapbuf_size8_1_sram ) , 
    .sram_inv ( mux_right_track_2_undriven_sram_inv ) , 
    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_139 ) ) ;
sb_1__0__mux_tree_tapbuf_size8_0 mux_left_track_1 (
    .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , 
        chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , 
        left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) ,
    .sram ( mux_tree_tapbuf_size8_2_sram ) , 
    .sram_inv ( mux_left_track_1_undriven_sram_inv ) , 
    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_136 ) ) ;
sb_1__0__mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( ccff_head ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size7_6 mux_top_track_2 (
    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
        chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) ,
    .sram ( mux_tree_tapbuf_size7_0_sram ) , 
    .sram_inv ( mux_top_track_2_undriven_sram_inv ) , 
    .out ( chany_top_out[1] ) , .p0 ( optlc_net_137 ) ) ;
sb_1__0__mux_tree_tapbuf_size7_7 mux_top_track_4 (
    .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
        top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , 
        chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) ,
    .sram ( mux_tree_tapbuf_size7_1_sram ) , 
    .sram_inv ( mux_top_track_4_undriven_sram_inv ) , 
    .out ( chany_top_out[2] ) , .p0 ( optlc_net_137 ) ) ;
sb_1__0__mux_tree_tapbuf_size7 mux_top_track_6 (
    .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , 
        top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , 
        chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) ,
    .sram ( mux_tree_tapbuf_size7_2_sram ) , 
    .sram_inv ( mux_top_track_6_undriven_sram_inv ) , 
    .out ( chany_top_out[3] ) , .p0 ( optlc_net_137 ) ) ;
sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_0 (
    .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , 
        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , 
        chanx_left_in[2] , chanx_left_in[12] } ) ,
    .sram ( mux_tree_tapbuf_size7_3_sram ) , 
    .sram_inv ( mux_right_track_0_undriven_sram_inv ) , 
    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_139 ) ) ;
sb_1__0__mux_tree_tapbuf_size7_5 mux_right_track_8 (
    .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , 
        right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , 
        chanx_left_in[6] , chanx_left_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size7_4_sram ) , 
    .sram_inv ( mux_right_track_8_undriven_sram_inv ) , 
    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_139 ) ) ;
sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_16 (
    .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , 
        right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , 
        chanx_left_in[8] , chanx_left_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size7_5_sram ) , 
    .sram_inv ( mux_right_track_16_undriven_sram_inv ) , 
    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_139 ) ) ;
sb_1__0__mux_tree_tapbuf_size7_1 mux_left_track_3 (
    .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , 
        chanx_right_in[13] , left_bottom_grid_pin_3_[0] , 
        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) ,
    .sram ( mux_tree_tapbuf_size7_6_sram ) , 
    .sram_inv ( mux_left_track_3_undriven_sram_inv ) , 
    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_138 ) ) ;
sb_1__0__mux_tree_tapbuf_size7_2 mux_left_track_9 (
    .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , 
        chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , 
        left_bottom_grid_pin_9_[0] } ) ,
    .sram ( mux_tree_tapbuf_size7_7_sram ) , 
    .sram_inv ( mux_left_track_9_undriven_sram_inv ) , 
    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_138 ) ) ;
sb_1__0__mux_tree_tapbuf_size7_0 mux_left_track_17 (
    .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , 
        chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , 
        left_bottom_grid_pin_11_[0] } ) ,
    .sram ( mux_tree_tapbuf_size7_8_sram ) , 
    .sram_inv ( mux_left_track_17_undriven_sram_inv ) , 
    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_138 ) ) ;
sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size4 mux_top_track_8 (
    .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , 
        chanx_right_in[15] , chanx_left_in[8] } ) ,
    .sram ( mux_tree_tapbuf_size4_0_sram ) , 
    .sram_inv ( mux_top_track_8_undriven_sram_inv ) , 
    .out ( chany_top_out[4] ) , .p0 ( optlc_net_137 ) ) ;
sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_10 (
    .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , 
        chanx_right_in[19] , chanx_left_in[9] } ) ,
    .sram ( mux_tree_tapbuf_size4_1_sram ) , 
    .sram_inv ( mux_top_track_10_undriven_sram_inv ) , 
    .out ( chany_top_out[5] ) , .p0 ( optlc_net_137 ) ) ;
sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 (
    .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , 
        chanx_left_in[10] } ) ,
    .sram ( mux_tree_tapbuf_size3_0_sram ) , 
    .sram_inv ( mux_top_track_12_undriven_sram_inv ) , 
    .out ( chany_top_out[6] ) , .p0 ( optlc_net_140 ) ) ;
sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 (
    .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , 
        chanx_left_in[12] } ) ,
    .sram ( mux_tree_tapbuf_size3_1_sram ) , 
    .sram_inv ( mux_top_track_14_undriven_sram_inv ) , 
    .out ( chany_top_out[7] ) , .p0 ( optlc_net_140 ) ) ;
sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 (
    .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , 
        chanx_left_in[13] } ) ,
    .sram ( mux_tree_tapbuf_size3_2_sram ) , 
    .sram_inv ( mux_top_track_16_undriven_sram_inv ) , 
    .out ( chany_top_out[8] ) , .p0 ( optlc_net_137 ) ) ;
sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 (
    .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , 
        chanx_left_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size3_3_sram ) , 
    .sram_inv ( mux_top_track_18_undriven_sram_inv ) , 
    .out ( chany_top_out[9] ) , .p0 ( optlc_net_140 ) ) ;
sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 (
    .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , 
        chanx_left_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size3_4_sram ) , 
    .sram_inv ( mux_top_track_20_undriven_sram_inv ) , 
    .out ( chany_top_out[10] ) , .p0 ( optlc_net_138 ) ) ;
sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 (
    .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , 
        chanx_left_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size3_5_sram ) , 
    .sram_inv ( mux_top_track_22_undriven_sram_inv ) , 
    .out ( chany_top_out[11] ) , .p0 ( optlc_net_138 ) ) ;
sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 (
    .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , 
        chanx_left_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size3_6_sram ) , 
    .sram_inv ( mux_top_track_24_undriven_sram_inv ) , 
    .out ( chany_top_out[12] ) , .p0 ( optlc_net_140 ) ) ;
sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 (
    .in ( { chanx_right_in[0] , chanx_left_in[1] } ) ,
    .sram ( mux_tree_tapbuf_size2_0_sram ) , 
    .sram_inv ( mux_top_track_38_undriven_sram_inv ) , 
    .out ( chany_top_out[19] ) , .p0 ( optlc_net_140 ) ) ;
sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 (
    .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , 
        right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , 
        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , 
        right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , 
        chanx_left_in[5] , chanx_left_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size11_0_sram ) , 
    .sram_inv ( mux_right_track_4_undriven_sram_inv ) , 
    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_139 ) ) ;
sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 (
    .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , 
        chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , 
        left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , 
        left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , 
        left_bottom_grid_pin_11_[0] } ) ,
    .sram ( mux_tree_tapbuf_size11_1_sram ) , 
    .sram_inv ( mux_left_track_5_undriven_sram_inv ) , 
    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_136 ) ) ;
sb_1__0__mux_tree_tapbuf_size11_mem mem_right_track_4 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size11_0_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size11_1_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size6 mux_right_track_24 (
    .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , 
        right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size6_0_sram ) , 
    .sram_inv ( mux_right_track_24_undriven_sram_inv ) , 
    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_140 ) ) ;
sb_1__0__mux_tree_tapbuf_size6_0 mux_left_track_25 (
    .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , 
        chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) ,
    .sram ( mux_tree_tapbuf_size6_1_sram ) , 
    .sram_inv ( mux_left_track_25_undriven_sram_inv ) , 
    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_138 ) ) ;
sb_1__0__mux_tree_tapbuf_size6_mem mem_right_track_24 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size5 mux_right_track_32 (
    .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , 
        right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) ,
    .sram ( mux_tree_tapbuf_size5_0_sram ) , 
    .sram_inv ( mux_right_track_32_undriven_sram_inv ) , 
    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_140 ) ) ;
sb_1__0__mux_tree_tapbuf_size5_0 mux_left_track_33 (
    .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , 
        chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) ,
    .sram ( mux_tree_tapbuf_size5_1_sram ) , 
    .sram_inv ( mux_left_track_33_undriven_sram_inv ) , 
    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_136 ) ) ;
sb_1__0__mux_tree_tapbuf_size5_mem mem_right_track_32 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
    .ccff_tail ( { ropt_net_157 } ) ,
    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , 
    .HI ( optlc_net_136 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , 
    .HI ( optlc_net_137 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , 
    .HI ( optlc_net_138 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , 
    .HI ( optlc_net_139 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_176 ) , 
    .X ( chanx_left_out[18] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , 
    .HI ( optlc_net_140 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( ropt_net_141 ) , 
    .X ( ropt_net_194 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chanx_right_in[10] ) , 
    .X ( ropt_net_169 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_142 ) , 
    .X ( chanx_left_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chanx_right_in[8] ) , 
    .X ( ropt_net_191 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( chanx_right_in[5] ) , 
    .X ( ropt_net_178 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_177 ) , 
    .X ( chanx_left_out[10] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chanx_right_in[17] ) , 
    .X ( ropt_net_172 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( 
    .A ( Test_en__FEEDTHRU_0[0] ) , .X ( Test_en__FEEDTHRU_3[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_146 ) , 
    .X ( ropt_net_189 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_right_in[4] ) , 
    .X ( chanx_left_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , 
    .X ( ropt_net_166 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[13] ) , 
    .X ( ropt_net_192 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[6] ) , 
    .X ( ropt_net_158 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_right_in[14] ) , 
    .X ( ropt_net_193 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( chanx_left_in[11] ) , 
    .X ( ropt_net_183 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , 
    .X ( ropt_net_167 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( chanx_right_in[18] ) , 
    .X ( chanx_left_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( chanx_right_in[9] ) , 
    .X ( ropt_net_177 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_left_in[12] ) , 
    .X ( ropt_net_159 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chanx_left_in[19] ) , 
    .X ( chany_top_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[14] ) , 
    .X ( ropt_net_173 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( chanx_right_in[2] ) , 
    .X ( chanx_left_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_155 ) , 
    .X ( ropt_net_186 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chanx_left_in[8] ) , 
    .X ( chanx_right_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_left_in[18] ) , 
    .X ( chanx_right_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_157 ) , 
    .X ( ccff_tail[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , 
    .X ( ropt_net_141 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_158 ) , 
    .X ( chanx_right_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_159 ) , 
    .X ( chanx_right_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( Test_en__FEEDTHRU_0[0] ) , 
    .X ( ropt_net_190 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( Test_en__FEEDTHRU_4[0] ) , 
    .X ( Test_en__FEEDTHRU_5[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_160 ) , 
    .X ( ropt_net_179 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( Test_en__FEEDTHRU_6[0] ) , 
    .X ( Test_en__FEEDTHRU_7[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_161 ) , 
    .X ( chanx_right_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_178 ) , 
    .X ( chanx_left_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_179 ) , 
    .X ( chany_top_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_180 ) , 
    .X ( chanx_left_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_181 ) , 
    .X ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_182 ) , 
    .X ( chany_top_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_183 ) , 
    .X ( chany_top_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( ropt_net_184 ) , 
    .X ( chanx_right_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_185 ) , 
    .X ( chanx_right_out[6] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chanx_right_in[16] ) , 
    .X ( ropt_net_146 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_186 ) , 
    .X ( chany_top_out[13] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[3] ) , 
    .X ( ropt_net_163 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_162 ) , 
    .X ( ropt_net_185 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[10] ) , 
    .X ( BUF_net_84 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_187 ) , 
    .X ( Test_en__FEEDTHRU_2[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_163 ) , 
    .X ( ropt_net_182 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_87 ( .A ( chanx_left_in[15] ) , 
    .X ( ropt_net_171 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_left_in[16] ) , 
    .X ( ropt_net_161 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chanx_left_in[17] ) , 
    .X ( ropt_net_170 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_188 ) , 
    .X ( chanx_left_out[11] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_189 ) , 
    .X ( chanx_left_out[17] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( 
    .A ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , 
    .X ( ropt_net_174 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_164 ) , 
    .X ( chanx_right_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_165 ) , 
    .X ( ropt_net_184 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_166 ) , 
    .X ( chanx_right_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_167 ) , 
    .X ( chanx_right_out[10] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_168 ) , 
    .X ( ropt_net_180 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_169 ) , 
    .X ( ropt_net_188 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_170 ) , 
    .X ( chanx_right_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_171 ) , 
    .X ( chany_top_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_172 ) , 
    .X ( ropt_net_176 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( top_left_grid_pin_43_[0] ) , 
    .X ( ropt_net_155 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_109 ( .A ( chanx_right_in[12] ) , 
    .X ( ropt_net_168 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chanx_left_in[2] ) , 
    .X ( ropt_net_165 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_111 ( .A ( chanx_left_in[5] ) , 
    .X ( ropt_net_162 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_left_in[7] ) , 
    .X ( ropt_net_160 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( Test_en__FEEDTHRU_0[0] ) , 
    .X ( ropt_net_175 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_114 ( .A ( Test_en__FEEDTHRU_6[0] ) , 
    .X ( Test_en__FEEDTHRU_8[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_115 ( .A ( chanx_right_in[6] ) , 
    .X ( ropt_net_142 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_173 ) , 
    .X ( chanx_right_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chanx_left_in[13] ) , 
    .X ( ropt_net_164 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_174 ) , 
    .X ( ropt_net_181 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_175 ) , 
    .X ( ropt_net_187 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_190 ) , 
    .X ( Test_en__FEEDTHRU_1[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_191 ) , 
    .X ( chanx_left_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_192 ) , 
    .X ( chanx_left_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_193 ) , 
    .X ( chanx_left_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_194 ) , 
    .X ( SC_OUT_BOT ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_84 ) , 
    .X ( chanx_right_out[11] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__40 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__const1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__2__const1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__2__const1_22 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__2__const1_22 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__2__const1_21 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__2__const1_21 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__2__const1_20 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

sb_0__2__const1_20 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module sb_0__2__const1_19 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__2__const1_19 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__2__const1_18 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

sb_0__2__const1_18 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module sb_0__2__const1_17 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__2__const1_17 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__2__const1_16 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

sb_0__2__const1_16 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module sb_0__2__const1_15 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__2__const1_15 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__2__const1_14 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__2__const1_14 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__2__const1_13 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__2__const1_13 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__2__const1_12 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__2__const1_12 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__2__const1_11 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

sb_0__2__const1_11 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module sb_0__2__const1_10 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__2__const1_10 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__2__const1_9 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__2__const1_9 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__2__const1_8 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__2__const1_8 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__2__const1_7 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__2__const1_7 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__2__const1_6 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__2__const1_6 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__const1_5 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_0__2__const1_5 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_0__2__const1_4 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_0__2__const1_4 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__const1_3 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:4] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;

sb_0__2__const1_3 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
endmodule


module sb_0__2__const1_2 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:4] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;

sb_0__2__const1_2 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__2__const1_1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_0__2__const1_1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
endmodule


module sb_0__2__const1_0 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_0__2__const1_0 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
endmodule


module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , 
    right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , 
    right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , 
    right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , 
    right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , 
    bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , 
    ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ) ;
input  [0:0] prog_clk ;
input  [0:19] chanx_right_in ;
input  [0:0] right_top_grid_pin_1_ ;
input  [0:0] right_bottom_grid_pin_34_ ;
input  [0:0] right_bottom_grid_pin_35_ ;
input  [0:0] right_bottom_grid_pin_36_ ;
input  [0:0] right_bottom_grid_pin_37_ ;
input  [0:0] right_bottom_grid_pin_38_ ;
input  [0:0] right_bottom_grid_pin_39_ ;
input  [0:0] right_bottom_grid_pin_40_ ;
input  [0:0] right_bottom_grid_pin_41_ ;
input  [0:19] chany_bottom_in ;
input  [0:0] bottom_left_grid_pin_1_ ;
input  [0:0] ccff_head ;
output [0:19] chanx_right_out ;
output [0:19] chany_bottom_out ;
output [0:0] ccff_tail ;
input  SC_IN_TOP ;
input  SC_IN_BOT ;
output SC_OUT_TOP ;
output SC_OUT_BOT ;

wire [0:1] mux_bottom_track_1_undriven_sram_inv ;
wire [0:1] mux_bottom_track_25_undriven_sram_inv ;
wire [0:1] mux_bottom_track_5_undriven_sram_inv ;
wire [0:1] mux_bottom_track_9_undriven_sram_inv ;
wire [0:2] mux_right_track_0_undriven_sram_inv ;
wire [0:1] mux_right_track_10_undriven_sram_inv ;
wire [0:1] mux_right_track_12_undriven_sram_inv ;
wire [0:1] mux_right_track_14_undriven_sram_inv ;
wire [0:1] mux_right_track_16_undriven_sram_inv ;
wire [0:1] mux_right_track_18_undriven_sram_inv ;
wire [0:1] mux_right_track_20_undriven_sram_inv ;
wire [0:1] mux_right_track_22_undriven_sram_inv ;
wire [0:1] mux_right_track_24_undriven_sram_inv ;
wire [0:1] mux_right_track_26_undriven_sram_inv ;
wire [0:1] mux_right_track_28_undriven_sram_inv ;
wire [0:2] mux_right_track_2_undriven_sram_inv ;
wire [0:1] mux_right_track_30_undriven_sram_inv ;
wire [0:1] mux_right_track_32_undriven_sram_inv ;
wire [0:1] mux_right_track_34_undriven_sram_inv ;
wire [0:1] mux_right_track_36_undriven_sram_inv ;
wire [0:1] mux_right_track_38_undriven_sram_inv ;
wire [0:2] mux_right_track_4_undriven_sram_inv ;
wire [0:2] mux_right_track_6_undriven_sram_inv ;
wire [0:1] mux_right_track_8_undriven_sram_inv ;
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
wire [0:1] mux_tree_tapbuf_size2_10_sram ;
wire [0:1] mux_tree_tapbuf_size2_11_sram ;
wire [0:1] mux_tree_tapbuf_size2_12_sram ;
wire [0:1] mux_tree_tapbuf_size2_13_sram ;
wire [0:1] mux_tree_tapbuf_size2_14_sram ;
wire [0:1] mux_tree_tapbuf_size2_15_sram ;
wire [0:1] mux_tree_tapbuf_size2_16_sram ;
wire [0:1] mux_tree_tapbuf_size2_17_sram ;
wire [0:1] mux_tree_tapbuf_size2_1_sram ;
wire [0:1] mux_tree_tapbuf_size2_2_sram ;
wire [0:1] mux_tree_tapbuf_size2_3_sram ;
wire [0:1] mux_tree_tapbuf_size2_4_sram ;
wire [0:1] mux_tree_tapbuf_size2_5_sram ;
wire [0:1] mux_tree_tapbuf_size2_6_sram ;
wire [0:1] mux_tree_tapbuf_size2_7_sram ;
wire [0:1] mux_tree_tapbuf_size2_8_sram ;
wire [0:1] mux_tree_tapbuf_size2_9_sram ;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size5_0_sram ;
wire [0:2] mux_tree_tapbuf_size5_1_sram ;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size6_0_sram ;
wire [0:2] mux_tree_tapbuf_size6_1_sram ;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;

assign SC_IN_TOP = SC_IN_BOT ;

sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 (
    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , 
        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , 
        right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size6_0_sram ) , 
    .sram_inv ( mux_right_track_0_undriven_sram_inv ) , 
    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_109 ) ) ;
sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 (
    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , 
        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , 
        right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size6_1_sram ) , 
    .sram_inv ( mux_right_track_4_undriven_sram_inv ) , 
    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_111 ) ) ;
sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 (
    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
        chany_bottom_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size5_0_sram ) , 
    .sram_inv ( mux_right_track_2_undriven_sram_inv ) , 
    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_111 ) ) ;
sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 (
    .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , 
        right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , 
        chany_bottom_in[15] } ) ,
    .sram ( mux_tree_tapbuf_size5_1_sram ) , 
    .sram_inv ( mux_right_track_6_undriven_sram_inv ) , 
    .out ( chanx_right_out[3] ) , .p0 ( optlc_net_111 ) ) ;
sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size3 mux_right_track_8 (
    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , 
        chany_bottom_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size3_0_sram ) , 
    .sram_inv ( mux_right_track_8_undriven_sram_inv ) , 
    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_109 ) ) ;
sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_24 (
    .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , 
        chany_bottom_in[6] } ) ,
    .sram ( mux_tree_tapbuf_size3_1_sram ) , 
    .sram_inv ( mux_right_track_24_undriven_sram_inv ) ,
    .out ( { ropt_net_117 } ) ,
    .p0 ( optlc_net_111 ) ) ;
sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_8 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_10 (
    .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) ,
    .sram ( mux_tree_tapbuf_size2_0_sram ) , 
    .sram_inv ( mux_right_track_10_undriven_sram_inv ) , 
    .out ( chanx_right_out[5] ) , .p0 ( optlc_net_109 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_12 (
    .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) ,
    .sram ( mux_tree_tapbuf_size2_1_sram ) , 
    .sram_inv ( mux_right_track_12_undriven_sram_inv ) , 
    .out ( chanx_right_out[6] ) , .p0 ( optlc_net_112 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_14 (
    .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) ,
    .sram ( mux_tree_tapbuf_size2_2_sram ) , 
    .sram_inv ( mux_right_track_14_undriven_sram_inv ) , 
    .out ( chanx_right_out[7] ) , .p0 ( optlc_net_112 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_16 (
    .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) ,
    .sram ( mux_tree_tapbuf_size2_3_sram ) , 
    .sram_inv ( mux_right_track_16_undriven_sram_inv ) , 
    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_112 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_18 (
    .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) ,
    .sram ( mux_tree_tapbuf_size2_4_sram ) , 
    .sram_inv ( mux_right_track_18_undriven_sram_inv ) , 
    .out ( chanx_right_out[9] ) , .p0 ( optlc_net_110 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_20 (
    .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) ,
    .sram ( mux_tree_tapbuf_size2_5_sram ) , 
    .sram_inv ( mux_right_track_20_undriven_sram_inv ) , 
    .out ( chanx_right_out[10] ) , .p0 ( optlc_net_110 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_22 (
    .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) ,
    .sram ( mux_tree_tapbuf_size2_6_sram ) , 
    .sram_inv ( mux_right_track_22_undriven_sram_inv ) , 
    .out ( chanx_right_out[11] ) , .p0 ( optlc_net_111 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_26 (
    .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) ,
    .sram ( mux_tree_tapbuf_size2_7_sram ) , 
    .sram_inv ( mux_right_track_26_undriven_sram_inv ) , 
    .out ( chanx_right_out[13] ) , .p0 ( optlc_net_112 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_28 (
    .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) ,
    .sram ( mux_tree_tapbuf_size2_8_sram ) , 
    .sram_inv ( mux_right_track_28_undriven_sram_inv ) , 
    .out ( chanx_right_out[14] ) , .p0 ( optlc_net_112 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_30 (
    .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) ,
    .sram ( mux_tree_tapbuf_size2_9_sram ) , 
    .sram_inv ( mux_right_track_30_undriven_sram_inv ) , 
    .out ( chanx_right_out[15] ) , .p0 ( optlc_net_112 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_32 (
    .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) ,
    .sram ( mux_tree_tapbuf_size2_10_sram ) , 
    .sram_inv ( mux_right_track_32_undriven_sram_inv ) , 
    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_112 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_34 (
    .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) ,
    .sram ( mux_tree_tapbuf_size2_11_sram ) , 
    .sram_inv ( mux_right_track_34_undriven_sram_inv ) , 
    .out ( chanx_right_out[17] ) , .p0 ( optlc_net_110 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_36 (
    .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_12_sram ) , 
    .sram_inv ( mux_right_track_36_undriven_sram_inv ) ,
    .out ( { ropt_net_118 } ) ,
    .p0 ( optlc_net_110 ) ) ;
sb_0__2__mux_tree_tapbuf_size2 mux_right_track_38 (
    .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) ,
    .sram ( mux_tree_tapbuf_size2_13_sram ) , 
    .sram_inv ( mux_right_track_38_undriven_sram_inv ) , 
    .out ( chanx_right_out[19] ) , .p0 ( optlc_net_110 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_0 mux_bottom_track_1 (
    .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_14_sram ) , 
    .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , 
    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_111 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_2 mux_bottom_track_5 (
    .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_15_sram ) , 
    .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , 
    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_111 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_3 mux_bottom_track_9 (
    .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_16_sram ) , 
    .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , 
    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_111 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_1 mux_bottom_track_25 (
    .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_17_sram ) , 
    .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , 
    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_111 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem mem_right_track_38 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
    .ccff_tail ( { ropt_net_128 } ) ,
    .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_135 ) , 
    .X ( chany_bottom_out[8] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_136 ) , 
    .X ( chany_bottom_out[1] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_137 ) , 
    .X ( chany_bottom_out[10] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , 
    .HI ( optlc_net_109 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , 
    .X ( aps_rename_4_ ) ) ;
sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , 
    .HI ( optlc_net_110 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_138 ) , 
    .X ( chany_bottom_out[9] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , 
    .HI ( optlc_net_111 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , 
    .HI ( optlc_net_112 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( ropt_net_115 ) , 
    .X ( ropt_net_143 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_139 ) , 
    .X ( chany_bottom_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_140 ) , 
    .X ( chany_bottom_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[8] ) , 
    .X ( ropt_net_137 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[15] ) , 
    .X ( ropt_net_142 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_117 ) , 
    .X ( chanx_right_out[12] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_141 ) , 
    .X ( chany_bottom_out[13] ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , 
    .X ( ropt_net_115 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_142 ) , 
    .X ( chany_bottom_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_143 ) , 
    .X ( SC_OUT_BOT ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_144 ) , 
    .X ( ccff_tail[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_145 ) , 
    .X ( chany_bottom_out[11] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( aps_rename_4_ ) , 
    .X ( BUF_net_53 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_54 ( .A ( chanx_right_in[5] ) , 
    .X ( ropt_net_141 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_146 ) , 
    .X ( chany_bottom_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_147 ) , 
    .X ( chany_bottom_out[7] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( chanx_right_in[9] ) , 
    .X ( ropt_net_129 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_118 ) , 
    .X ( chanx_right_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_148 ) , 
    .X ( chany_bottom_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_149 ) , 
    .X ( chany_bottom_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( chanx_right_in[17] ) , 
    .X ( ropt_net_136 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_120 ) , 
    .X ( ropt_net_139 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[1] ) , 
    .X ( chany_bottom_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( chanx_right_in[0] ) , 
    .X ( ropt_net_146 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[12] ) , 
    .X ( ropt_net_149 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( chanx_right_in[11] ) , 
    .X ( ropt_net_147 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_83 ( .A ( BUF_net_53 ) , 
    .X ( ropt_net_140 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chanx_right_in[2] ) , 
    .X ( ropt_net_148 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_87 ( .A ( chanx_right_in[19] ) , 
    .X ( ropt_net_120 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[7] ) , 
    .X ( ropt_net_145 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( chanx_right_in[10] ) , 
    .X ( ropt_net_135 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_128 ) , 
    .X ( ropt_net_144 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_129 ) , 
    .X ( ropt_net_138 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_right_in[13] ) , 
    .X ( chany_bottom_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[3] ) , 
    .X ( chany_bottom_out[15] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__const1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__1__const1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__1__const1_31 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__1__const1_31 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__1__const1_30 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__1__const1_30 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__1__const1_29 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__1__const1_29 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__1__const1_28 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__1__const1_28 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__1__const1_27 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__1__const1_27 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__const1_26 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_0__1__const1_26 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_0__1__const1_25 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_0__1__const1_25 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_0__1__const1_24 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_0__1__const1_24 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_0__1__const1_23 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_0__1__const1_23 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_0__1__const1_22 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:2] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;

sb_0__1__const1_22 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__const1_21 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_0__1__const1_21 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_0__1__const1_20 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_0__1__const1_20 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_0__1__const1_19 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:6] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;

sb_0__1__const1_19 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__const1_18 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_0__1__const1_18 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
endmodule


module sb_0__1__const1_17 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_0__1__const1_17 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_129 ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_0__1__const1_16 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_0__1__const1_16 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_0__1__const1_15 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_0__1__const1_15 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_65 ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_0__1__const1_14 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_0__1__const1_14 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
endmodule


module sb_0__1__const1_13 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_0__1__const1_13 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
endmodule


module sb_0__1__const1_12 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_0__1__const1_12 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_126 ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__const1_11 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:4] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;

sb_0__1__const1_11 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
endmodule


module sb_0__1__const1_10 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:4] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_0__1__const1_10 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ;
endmodule


module sb_0__1__const1_9 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:4] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;

sb_0__1__const1_9 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
endmodule


module sb_0__1__const1_8 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:4] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;

sb_0__1__const1_8 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
endmodule


module sb_0__1__const1_7 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:4] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;

sb_0__1__const1_7 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__1__const1_6 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_0__1__const1_6 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_0__1__const1_5 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_0__1__const1_5 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
endmodule


module sb_0__1__const1_4 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_0__1__const1_4 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
endmodule


module sb_0__1__const1_3 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_0__1__const1_3 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
endmodule


module sb_0__1__const1_2 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_0__1__const1_2 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
endmodule


module sb_0__1__const1_1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_0__1__const1_1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_60 ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_0__1__const1_0 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:5] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;

sb_0__1__const1_0 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
endmodule


module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , 
    chanx_right_in , right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , 
    right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , 
    right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , 
    right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , 
    bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , 
    chany_bottom_out , ccff_tail ) ;
input  [0:0] prog_clk ;
input  [0:19] chany_top_in ;
input  [0:0] top_left_grid_pin_1_ ;
input  [0:19] chanx_right_in ;
input  [0:0] right_bottom_grid_pin_34_ ;
input  [0:0] right_bottom_grid_pin_35_ ;
input  [0:0] right_bottom_grid_pin_36_ ;
input  [0:0] right_bottom_grid_pin_37_ ;
input  [0:0] right_bottom_grid_pin_38_ ;
input  [0:0] right_bottom_grid_pin_39_ ;
input  [0:0] right_bottom_grid_pin_40_ ;
input  [0:0] right_bottom_grid_pin_41_ ;
input  [0:19] chany_bottom_in ;
input  [0:0] bottom_left_grid_pin_1_ ;
input  [0:0] ccff_head ;
output [0:19] chany_top_out ;
output [0:19] chanx_right_out ;
output [0:19] chany_bottom_out ;
output [0:0] ccff_tail ;

wire [0:2] mux_bottom_track_17_undriven_sram_inv ;
wire [0:2] mux_bottom_track_1_undriven_sram_inv ;
wire [0:2] mux_bottom_track_25_undriven_sram_inv ;
wire [0:1] mux_bottom_track_33_undriven_sram_inv ;
wire [0:2] mux_bottom_track_3_undriven_sram_inv ;
wire [0:2] mux_bottom_track_5_undriven_sram_inv ;
wire [0:2] mux_bottom_track_9_undriven_sram_inv ;
wire [0:2] mux_right_track_0_undriven_sram_inv ;
wire [0:2] mux_right_track_10_undriven_sram_inv ;
wire [0:2] mux_right_track_12_undriven_sram_inv ;
wire [0:2] mux_right_track_14_undriven_sram_inv ;
wire [0:1] mux_right_track_16_undriven_sram_inv ;
wire [0:1] mux_right_track_18_undriven_sram_inv ;
wire [0:1] mux_right_track_20_undriven_sram_inv ;
wire [0:1] mux_right_track_22_undriven_sram_inv ;
wire [0:2] mux_right_track_24_undriven_sram_inv ;
wire [0:1] mux_right_track_26_undriven_sram_inv ;
wire [0:1] mux_right_track_28_undriven_sram_inv ;
wire [0:2] mux_right_track_2_undriven_sram_inv ;
wire [0:1] mux_right_track_30_undriven_sram_inv ;
wire [0:1] mux_right_track_32_undriven_sram_inv ;
wire [0:1] mux_right_track_34_undriven_sram_inv ;
wire [0:1] mux_right_track_36_undriven_sram_inv ;
wire [0:2] mux_right_track_4_undriven_sram_inv ;
wire [0:2] mux_right_track_6_undriven_sram_inv ;
wire [0:2] mux_right_track_8_undriven_sram_inv ;
wire [0:2] mux_top_track_0_undriven_sram_inv ;
wire [0:2] mux_top_track_16_undriven_sram_inv ;
wire [0:2] mux_top_track_24_undriven_sram_inv ;
wire [0:2] mux_top_track_2_undriven_sram_inv ;
wire [0:2] mux_top_track_32_undriven_sram_inv ;
wire [0:2] mux_top_track_4_undriven_sram_inv ;
wire [0:2] mux_top_track_8_undriven_sram_inv ;
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
wire [0:1] mux_tree_tapbuf_size2_1_sram ;
wire [0:1] mux_tree_tapbuf_size2_2_sram ;
wire [0:1] mux_tree_tapbuf_size2_3_sram ;
wire [0:1] mux_tree_tapbuf_size2_4_sram ;
wire [0:1] mux_tree_tapbuf_size2_5_sram ;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
wire [0:1] mux_tree_tapbuf_size3_2_sram ;
wire [0:1] mux_tree_tapbuf_size3_3_sram ;
wire [0:1] mux_tree_tapbuf_size3_4_sram ;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size4_0_sram ;
wire [0:2] mux_tree_tapbuf_size4_1_sram ;
wire [0:2] mux_tree_tapbuf_size4_2_sram ;
wire [0:2] mux_tree_tapbuf_size4_3_sram ;
wire [0:2] mux_tree_tapbuf_size4_4_sram ;
wire [0:2] mux_tree_tapbuf_size4_5_sram ;
wire [0:2] mux_tree_tapbuf_size4_6_sram ;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size5_0_sram ;
wire [0:2] mux_tree_tapbuf_size5_1_sram ;
wire [0:2] mux_tree_tapbuf_size5_2_sram ;
wire [0:2] mux_tree_tapbuf_size5_3_sram ;
wire [0:2] mux_tree_tapbuf_size5_4_sram ;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size6_0_sram ;
wire [0:2] mux_tree_tapbuf_size6_1_sram ;
wire [0:2] mux_tree_tapbuf_size6_2_sram ;
wire [0:2] mux_tree_tapbuf_size6_3_sram ;
wire [0:2] mux_tree_tapbuf_size6_4_sram ;
wire [0:2] mux_tree_tapbuf_size6_5_sram ;
wire [0:2] mux_tree_tapbuf_size6_6_sram ;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size7_0_sram ;
wire [0:2] mux_tree_tapbuf_size7_1_sram ;
wire [0:2] mux_tree_tapbuf_size7_2_sram ;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;

sb_0__1__mux_tree_tapbuf_size6_4 mux_top_track_0 (
    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , 
        chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) ,
    .sram ( mux_tree_tapbuf_size6_0_sram ) , 
    .sram_inv ( mux_top_track_0_undriven_sram_inv ) , 
    .out ( chany_top_out[0] ) , .p0 ( optlc_net_155 ) ) ;
sb_0__1__mux_tree_tapbuf_size6_5 mux_top_track_4 (
    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , 
        chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size6_1_sram ) , 
    .sram_inv ( mux_top_track_4_undriven_sram_inv ) ,
    .out ( { ropt_net_159 } ) ,
    .p0 ( optlc_net_158 ) ) ;
sb_0__1__mux_tree_tapbuf_size6 mux_top_track_8 (
    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , 
        chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size6_2_sram ) , 
    .sram_inv ( mux_top_track_8_undriven_sram_inv ) , 
    .out ( chany_top_out[4] ) , .p0 ( optlc_net_156 ) ) ;
sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 (
    .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , 
        right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , 
        right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) ,
    .sram ( mux_tree_tapbuf_size6_3_sram ) , 
    .sram_inv ( mux_right_track_0_undriven_sram_inv ) , 
    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_158 ) ) ;
sb_0__1__mux_tree_tapbuf_size6_0 mux_bottom_track_1 (
    .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , 
        chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) ,
    .sram ( mux_tree_tapbuf_size6_4_sram ) , 
    .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , 
    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_157 ) ) ;
sb_0__1__mux_tree_tapbuf_size6_1 mux_bottom_track_5 (
    .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , 
        chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) ,
    .sram ( mux_tree_tapbuf_size6_5_sram ) , 
    .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , 
    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_155 ) ) ;
sb_0__1__mux_tree_tapbuf_size6_2 mux_bottom_track_9 (
    .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , 
        chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) ,
    .sram ( mux_tree_tapbuf_size6_6_sram ) , 
    .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) ,
    .out ( { ropt_net_163 } ) ,
    .p0 ( optlc_net_155 ) ) ;
sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size5 mux_top_track_2 (
    .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , 
        chany_bottom_in[4] , chany_bottom_in[13] } ) ,
    .sram ( mux_tree_tapbuf_size5_0_sram ) , 
    .sram_inv ( mux_top_track_2_undriven_sram_inv ) , 
    .out ( chany_top_out[1] ) , .p0 ( optlc_net_158 ) ) ;
sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_16 (
    .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , 
        chany_bottom_in[8] , chany_bottom_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size5_1_sram ) , 
    .sram_inv ( mux_top_track_16_undriven_sram_inv ) , 
    .out ( chany_top_out[8] ) , .p0 ( optlc_net_156 ) ) ;
sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 (
    .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , 
        chanx_right_in[11] , chanx_right_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size5_2_sram ) , 
    .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , 
    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_157 ) ) ;
sb_0__1__mux_tree_tapbuf_size5_0 mux_bottom_track_17 (
    .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , 
        chanx_right_in[8] , chanx_right_in[15] } ) ,
    .sram ( mux_tree_tapbuf_size5_3_sram ) , 
    .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , 
    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_157 ) ) ;
sb_0__1__mux_tree_tapbuf_size5_1 mux_bottom_track_25 (
    .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , 
        chanx_right_in[7] , chanx_right_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size5_4_sram ) , 
    .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , 
    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_157 ) ) ;
sb_0__1__mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size4_5 mux_top_track_24 (
    .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , 
        chany_bottom_in[18] } ) ,
    .sram ( mux_tree_tapbuf_size4_0_sram ) , 
    .sram_inv ( mux_top_track_24_undriven_sram_inv ) ,
    .out ( { ropt_net_164 } ) ,
    .p0 ( optlc_net_156 ) ) ;
sb_0__1__mux_tree_tapbuf_size4 mux_top_track_32 (
    .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , 
        chany_bottom_in[10] } ) ,
    .sram ( mux_tree_tapbuf_size4_1_sram ) , 
    .sram_inv ( mux_top_track_32_undriven_sram_inv ) , 
    .out ( chany_top_out[16] ) , .p0 ( optlc_net_156 ) ) ;
sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_8 (
    .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , 
        chany_bottom_in[8] } ) ,
    .sram ( mux_tree_tapbuf_size4_2_sram ) , 
    .sram_inv ( mux_right_track_8_undriven_sram_inv ) , 
    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_158 ) ) ;
sb_0__1__mux_tree_tapbuf_size4_0 mux_right_track_10 (
    .in ( { chany_top_in[9] , chany_top_in[11] , 
        right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) ,
    .sram ( mux_tree_tapbuf_size4_3_sram ) , 
    .sram_inv ( mux_right_track_10_undriven_sram_inv ) ,
    .out ( { ropt_net_160 } ) ,
    .p0 ( optlc_net_156 ) ) ;
sb_0__1__mux_tree_tapbuf_size4_1 mux_right_track_12 (
    .in ( { chany_top_in[10] , chany_top_in[15] , 
        right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) ,
    .sram ( mux_tree_tapbuf_size4_4_sram ) , 
    .sram_inv ( mux_right_track_12_undriven_sram_inv ) ,
    .out ( { ropt_net_161 } ) ,
    .p0 ( optlc_net_158 ) ) ;
sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_14 (
    .in ( { chany_top_in[12] , chany_top_in[19] , 
        right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) ,
    .sram ( mux_tree_tapbuf_size4_5_sram ) , 
    .sram_inv ( mux_right_track_14_undriven_sram_inv ) ,
    .out ( { ropt_net_167 } ) ,
    .p0 ( optlc_net_158 ) ) ;
sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_24 (
    .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , 
        chany_bottom_in[18] , chany_bottom_in[19] } ) ,
    .sram ( mux_tree_tapbuf_size4_6_sram ) , 
    .sram_inv ( mux_right_track_24_undriven_sram_inv ) , 
    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_157 ) ) ;
sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 (
    .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , 
        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , 
        right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) ,
    .sram ( mux_tree_tapbuf_size7_0_sram ) , 
    .sram_inv ( mux_right_track_2_undriven_sram_inv ) , 
    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_158 ) ) ;
sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 (
    .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , 
        right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , 
        right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) ,
    .sram ( mux_tree_tapbuf_size7_1_sram ) , 
    .sram_inv ( mux_right_track_4_undriven_sram_inv ) , 
    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_158 ) ) ;
sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 (
    .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , 
        right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , 
        right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) ,
    .sram ( mux_tree_tapbuf_size7_2_sram ) , 
    .sram_inv ( mux_right_track_6_undriven_sram_inv ) ,
    .out ( { ropt_net_162 } ) ,
    .p0 ( optlc_net_158 ) ) ;
sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_16 (
    .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , 
        chany_bottom_in[13] } ) ,
    .sram ( mux_tree_tapbuf_size3_0_sram ) , 
    .sram_inv ( mux_right_track_16_undriven_sram_inv ) , 
    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_158 ) ) ;
sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_18 (
    .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , 
        chany_bottom_in[14] } ) ,
    .sram ( mux_tree_tapbuf_size3_1_sram ) , 
    .sram_inv ( mux_right_track_18_undriven_sram_inv ) , 
    .out ( chanx_right_out[9] ) , .p0 ( optlc_net_157 ) ) ;
sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_20 (
    .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , 
        chany_bottom_in[16] } ) ,
    .sram ( mux_tree_tapbuf_size3_2_sram ) , 
    .sram_inv ( mux_right_track_20_undriven_sram_inv ) , 
    .out ( chanx_right_out[10] ) , .p0 ( optlc_net_157 ) ) ;
sb_0__1__mux_tree_tapbuf_size3 mux_right_track_22 (
    .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , 
        chany_bottom_in[17] } ) ,
    .sram ( mux_tree_tapbuf_size3_3_sram ) , 
    .sram_inv ( mux_right_track_22_undriven_sram_inv ) , 
    .out ( chanx_right_out[11] ) , .p0 ( optlc_net_155 ) ) ;
sb_0__1__mux_tree_tapbuf_size3_0 mux_bottom_track_33 (
    .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) ,
    .sram ( mux_tree_tapbuf_size3_4_sram ) , 
    .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , 
    .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_157 ) ) ;
sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size3_mem mem_right_track_22 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) ,
    .ccff_tail ( { ropt_net_174 } ) ,
    .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 (
    .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) ,
    .sram ( mux_tree_tapbuf_size2_0_sram ) , 
    .sram_inv ( mux_right_track_26_undriven_sram_inv ) , 
    .out ( chanx_right_out[13] ) , .p0 ( optlc_net_155 ) ) ;
sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 (
    .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) ,
    .sram ( mux_tree_tapbuf_size2_1_sram ) , 
    .sram_inv ( mux_right_track_28_undriven_sram_inv ) , 
    .out ( chanx_right_out[14] ) , .p0 ( optlc_net_155 ) ) ;
sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 (
    .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) ,
    .sram ( mux_tree_tapbuf_size2_2_sram ) , 
    .sram_inv ( mux_right_track_30_undriven_sram_inv ) , 
    .out ( chanx_right_out[15] ) , .p0 ( optlc_net_155 ) ) ;
sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 (
    .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) ,
    .sram ( mux_tree_tapbuf_size2_3_sram ) , 
    .sram_inv ( mux_right_track_32_undriven_sram_inv ) , 
    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_155 ) ) ;
sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 (
    .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) ,
    .sram ( mux_tree_tapbuf_size2_4_sram ) , 
    .sram_inv ( mux_right_track_34_undriven_sram_inv ) , 
    .out ( chanx_right_out[17] ) , .p0 ( optlc_net_155 ) ) ;
sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 (
    .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_5_sram ) , 
    .sram_inv ( mux_right_track_36_undriven_sram_inv ) , 
    .out ( chanx_right_out[18] ) , .p0 ( optlc_net_155 ) ) ;
sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , 
    .HI ( optlc_net_155 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , 
    .HI ( optlc_net_156 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_159 ) , 
    .X ( ropt_net_199 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , 
    .HI ( optlc_net_157 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chany_top_in[8] ) , 
    .X ( ropt_net_188 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_194 ) , 
    .X ( chany_top_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , 
    .X ( ropt_net_215 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , 
    .HI ( optlc_net_158 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_160 ) , 
    .X ( ropt_net_209 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_161 ) , 
    .X ( chanx_right_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_162 ) , 
    .X ( chanx_right_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_195 ) , 
    .X ( chany_top_out[13] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , 
    .X ( ropt_net_187 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( 
    .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_181 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_163 ) , 
    .X ( ropt_net_208 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_164 ) , 
    .X ( ropt_net_205 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , 
    .X ( ropt_net_179 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , 
    .X ( ropt_net_186 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , 
    .X ( ropt_net_180 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chany_top_in[12] ) , 
    .X ( chany_bottom_out[13] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , 
    .X ( ropt_net_184 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( 
    .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__22 ( .A ( chany_bottom_in[13] ) , 
    .X ( aps_rename_1_ ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_167 ) , 
    .X ( chanx_right_out[7] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chany_bottom_in[16] ) , 
    .X ( ropt_net_182 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__25 ( .A ( chany_bottom_in[17] ) , 
    .X ( aps_rename_2_ ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_top_in[6] ) , 
    .X ( ropt_net_217 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_196 ) , 
    .X ( chany_bottom_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_197 ) , 
    .X ( chany_bottom_out[14] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( chany_top_in[5] ) , 
    .X ( ropt_net_183 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_198 ) , 
    .X ( chany_top_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_199 ) , 
    .X ( chany_top_out[2] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_200 ) , 
    .X ( chany_top_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chany_top_in[4] ) , 
    .X ( chany_bottom_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chany_top_in[2] ) , 
    .X ( ropt_net_216 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_201 ) , 
    .X ( ccff_tail[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( chany_bottom_in[2] ) , 
    .X ( ropt_net_200 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_202 ) , 
    .X ( chany_bottom_out[10] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( aps_rename_1_ ) , 
    .X ( BUF_net_85 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_203 ) , 
    .X ( chany_bottom_out[9] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( aps_rename_2_ ) , 
    .X ( BUF_net_87 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_204 ) , 
    .X ( chany_top_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( chany_top_in[17] ) , 
    .X ( ropt_net_196 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_205 ) , 
    .X ( chany_top_out[12] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( 
    .A ( chany_bottom_in[12] ) , .X ( ropt_net_195 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_174 ) , 
    .X ( ropt_net_201 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( chany_top_in[13] ) , 
    .X ( ropt_net_197 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( 
    .A ( chany_bottom_in[14] ) , .X ( chany_top_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( chany_top_in[9] ) , 
    .X ( ropt_net_202 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_178 ) , 
    .X ( ropt_net_194 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_179 ) , 
    .X ( ropt_net_206 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_206 ) , 
    .X ( chany_top_out[6] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_114 ( .A ( chany_bottom_in[4] ) , 
    .X ( ropt_net_178 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_180 ) , 
    .X ( ropt_net_210 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_181 ) , 
    .X ( ropt_net_212 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chany_top_in[16] ) , 
    .X ( ropt_net_214 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_120 ( .A ( BUF_net_85 ) , 
    .X ( chany_top_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_121 ( .A ( BUF_net_87 ) , 
    .X ( chany_top_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_207 ) , 
    .X ( chany_top_out[11] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_208 ) , 
    .X ( chany_bottom_out[4] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_209 ) , 
    .X ( chanx_right_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_210 ) , 
    .X ( chany_top_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chany_top_in[14] ) , 
    .X ( ropt_net_218 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_182 ) , 
    .X ( ropt_net_204 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chany_bottom_in[9] ) , 
    .X ( ropt_net_185 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_183 ) , 
    .X ( ropt_net_211 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_184 ) , 
    .X ( ropt_net_207 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_185 ) , 
    .X ( ropt_net_213 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_186 ) , 
    .X ( ropt_net_198 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_187 ) , 
    .X ( chany_bottom_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_188 ) , 
    .X ( ropt_net_203 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_211 ) , 
    .X ( chany_bottom_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_212 ) , 
    .X ( chanx_right_out[19] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_213 ) , 
    .X ( chany_top_out[10] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_214 ) , 
    .X ( chany_bottom_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_215 ) , 
    .X ( chany_bottom_out[11] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_216 ) , 
    .X ( chany_bottom_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_217 ) , 
    .X ( chany_bottom_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_218 ) , 
    .X ( chany_bottom_out[15] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__40 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__39 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__38 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:2] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__37 ( .A ( mem_out[2] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__const1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_0__0__const1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
endmodule


module sb_0__0__const1_18 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_0__0__const1_18 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_47 ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_47 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( BUF_net_47 ) , 
    .X ( out[0] ) ) ;
endmodule


module sb_0__0__const1_17 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_0__0__const1_17 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
endmodule


module sb_0__0__const1_16 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:3] in ;
input  [0:2] sram ;
input  [0:2] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;

sb_0__0__const1_16 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , 
    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__36 ( .A ( mem_out[1] ) , 
    .X ( net_aps_36 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( net_aps_36 ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__35 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__34 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__33 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__32 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__31 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__30 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__29 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__28 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__27 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__26 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__25 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__24 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__23 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__22 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , 
    ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__21 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module sb_0__0__const1_15 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__0__const1_15 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__0__const1_14 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__0__const1_14 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__0__const1_13 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__0__const1_13 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__0__const1_12 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__0__const1_12 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_0__0__const1_11 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__0__const1_11 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__0__const1_10 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__0__const1_10 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_0__0__const1_9 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__0__const1_9 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_0__0__const1_8 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__0__const1_8 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__0__const1_7 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__0__const1_7 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__0__const1_6 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__0__const1_6 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__0__const1_5 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__0__const1_5 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__0__const1_4 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__0__const1_4 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
endmodule


module sb_0__0__const1_3 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__0__const1_3 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__0__const1_2 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__0__const1_2 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__0__const1_1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__0__const1_1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__0__const1_0 ( const1 ) ;
output [0:0] const1 ;
endmodule


module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;

sb_0__0__const1_0 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
endmodule


module sb_0__0_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , 
    chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , 
    right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , 
    right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , ccff_head , 
    chany_top_out , chanx_right_out , ccff_tail , 
    grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , 
    grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ;
input  [0:0] prog_clk ;
input  [0:19] chany_top_in ;
input  [0:0] top_left_grid_pin_1_ ;
input  [0:19] chanx_right_in ;
input  [0:0] right_bottom_grid_pin_1_ ;
input  [0:0] right_bottom_grid_pin_3_ ;
input  [0:0] right_bottom_grid_pin_5_ ;
input  [0:0] right_bottom_grid_pin_7_ ;
input  [0:0] right_bottom_grid_pin_9_ ;
input  [0:0] right_bottom_grid_pin_11_ ;
input  [0:0] ccff_head ;
output [0:19] chany_top_out ;
output [0:19] chanx_right_out ;
output [0:0] ccff_tail ;
input  [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ;
output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ;

wire [0:2] mux_right_track_0_undriven_sram_inv ;
wire [0:1] mux_right_track_10_undriven_sram_inv ;
wire [0:1] mux_right_track_12_undriven_sram_inv ;
wire [0:1] mux_right_track_14_undriven_sram_inv ;
wire [0:1] mux_right_track_16_undriven_sram_inv ;
wire [0:1] mux_right_track_18_undriven_sram_inv ;
wire [0:1] mux_right_track_24_undriven_sram_inv ;
wire [0:1] mux_right_track_26_undriven_sram_inv ;
wire [0:1] mux_right_track_28_undriven_sram_inv ;
wire [0:2] mux_right_track_2_undriven_sram_inv ;
wire [0:1] mux_right_track_30_undriven_sram_inv ;
wire [0:1] mux_right_track_32_undriven_sram_inv ;
wire [0:1] mux_right_track_34_undriven_sram_inv ;
wire [0:2] mux_right_track_4_undriven_sram_inv ;
wire [0:2] mux_right_track_6_undriven_sram_inv ;
wire [0:1] mux_right_track_8_undriven_sram_inv ;
wire [0:1] mux_top_track_0_undriven_sram_inv ;
wire [0:1] mux_top_track_24_undriven_sram_inv ;
wire [0:1] mux_top_track_4_undriven_sram_inv ;
wire [0:1] mux_top_track_8_undriven_sram_inv ;
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
wire [0:1] mux_tree_tapbuf_size2_10_sram ;
wire [0:1] mux_tree_tapbuf_size2_11_sram ;
wire [0:1] mux_tree_tapbuf_size2_12_sram ;
wire [0:1] mux_tree_tapbuf_size2_13_sram ;
wire [0:1] mux_tree_tapbuf_size2_14_sram ;
wire [0:1] mux_tree_tapbuf_size2_15_sram ;
wire [0:1] mux_tree_tapbuf_size2_1_sram ;
wire [0:1] mux_tree_tapbuf_size2_2_sram ;
wire [0:1] mux_tree_tapbuf_size2_3_sram ;
wire [0:1] mux_tree_tapbuf_size2_4_sram ;
wire [0:1] mux_tree_tapbuf_size2_5_sram ;
wire [0:1] mux_tree_tapbuf_size2_6_sram ;
wire [0:1] mux_tree_tapbuf_size2_7_sram ;
wire [0:1] mux_tree_tapbuf_size2_8_sram ;
wire [0:1] mux_tree_tapbuf_size2_9_sram ;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size4_0_sram ;
wire [0:2] mux_tree_tapbuf_size4_1_sram ;
wire [0:2] mux_tree_tapbuf_size4_2_sram ;
wire [0:2] mux_tree_tapbuf_size4_3_sram ;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;

sb_0__0__mux_tree_tapbuf_size2_12 mux_top_track_0 (
    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) ,
    .sram ( mux_tree_tapbuf_size2_0_sram ) , 
    .sram_inv ( mux_top_track_0_undriven_sram_inv ) , 
    .out ( chany_top_out[0] ) , .p0 ( optlc_net_99 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_14 mux_top_track_4 (
    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) ,
    .sram ( mux_tree_tapbuf_size2_1_sram ) , 
    .sram_inv ( mux_top_track_4_undriven_sram_inv ) , 
    .out ( chany_top_out[2] ) , .p0 ( optlc_net_99 ) ) ;
sb_0__0__mux_tree_tapbuf_size2 mux_top_track_8 (
    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) ,
    .sram ( mux_tree_tapbuf_size2_2_sram ) , 
    .sram_inv ( mux_top_track_8_undriven_sram_inv ) , 
    .out ( chany_top_out[4] ) , .p0 ( optlc_net_99 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_13 mux_top_track_24 (
    .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) ,
    .sram ( mux_tree_tapbuf_size2_3_sram ) , 
    .sram_inv ( mux_top_track_24_undriven_sram_inv ) , 
    .out ( chany_top_out[12] ) , .p0 ( optlc_net_101 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_8 (
    .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_4_sram ) , 
    .sram_inv ( mux_right_track_8_undriven_sram_inv ) ,
    .out ( { ropt_net_102 } ) ,
    .p0 ( optlc_net_98 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_0 mux_right_track_10 (
    .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_5_sram ) , 
    .sram_inv ( mux_right_track_10_undriven_sram_inv ) , 
    .out ( chanx_right_out[5] ) , .p0 ( optlc_net_98 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_1 mux_right_track_12 (
    .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_6_sram ) , 
    .sram_inv ( mux_right_track_12_undriven_sram_inv ) , 
    .out ( chanx_right_out[6] ) , .p0 ( optlc_net_98 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_2 mux_right_track_14 (
    .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_7_sram ) , 
    .sram_inv ( mux_right_track_14_undriven_sram_inv ) , 
    .out ( chanx_right_out[7] ) , .p0 ( optlc_net_98 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_3 mux_right_track_16 (
    .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_8_sram ) , 
    .sram_inv ( mux_right_track_16_undriven_sram_inv ) , 
    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_101 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_18 (
    .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_9_sram ) , 
    .sram_inv ( mux_right_track_18_undriven_sram_inv ) ,
    .out ( { ropt_net_105 } ) ,
    .p0 ( optlc_net_101 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_24 (
    .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_10_sram ) , 
    .sram_inv ( mux_right_track_24_undriven_sram_inv ) ,
    .out ( { ropt_net_107 } ) ,
    .p0 ( optlc_net_98 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_26 (
    .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_11_sram ) , 
    .sram_inv ( mux_right_track_26_undriven_sram_inv ) , 
    .out ( chanx_right_out[13] ) , .p0 ( optlc_net_98 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_28 (
    .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_12_sram ) , 
    .sram_inv ( mux_right_track_28_undriven_sram_inv ) ,
    .out ( { ropt_net_104 } ) ,
    .p0 ( optlc_net_98 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_30 (
    .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_13_sram ) , 
    .sram_inv ( mux_right_track_30_undriven_sram_inv ) , 
    .out ( chanx_right_out[15] ) , .p0 ( optlc_net_99 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_32 (
    .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_14_sram ) , 
    .sram_inv ( mux_right_track_32_undriven_sram_inv ) , 
    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_101 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_34 (
    .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) ,
    .sram ( mux_tree_tapbuf_size2_15_sram ) , 
    .sram_inv ( mux_right_track_34_undriven_sram_inv ) , 
    .out ( chanx_right_out[17] ) , .p0 ( optlc_net_100 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
    .ccff_tail ( { ropt_net_103 } ) ,
    .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 (
    .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , 
        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) ,
    .sram ( mux_tree_tapbuf_size4_0_sram ) , 
    .sram_inv ( mux_right_track_0_undriven_sram_inv ) , 
    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_100 ) ) ;
sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 (
    .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , 
        right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) ,
    .sram ( mux_tree_tapbuf_size4_1_sram ) , 
    .sram_inv ( mux_right_track_2_undriven_sram_inv ) , 
    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_101 ) ) ;
sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 (
    .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , 
        right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) ,
    .sram ( mux_tree_tapbuf_size4_2_sram ) , 
    .sram_inv ( mux_right_track_4_undriven_sram_inv ) ,
    .out ( { ropt_net_108 } ) ,
    .p0 ( optlc_net_100 ) ) ;
sb_0__0__mux_tree_tapbuf_size4 mux_right_track_6 (
    .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , 
        right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) ,
    .sram ( mux_tree_tapbuf_size4_3_sram ) , 
    .sram_inv ( mux_right_track_6_undriven_sram_inv ) , 
    .out ( chanx_right_out[3] ) , .p0 ( optlc_net_98 ) ) ;
sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_6 ( 
    .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , 
    .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , 
    .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , 
    .HI ( optlc_net_98 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , 
    .HI ( optlc_net_99 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , 
    .HI ( optlc_net_100 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , 
    .HI ( optlc_net_101 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_102 ) , 
    .X ( chanx_right_out[4] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_103 ) , 
    .X ( ropt_net_140 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_104 ) , 
    .X ( ropt_net_144 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_right_in[6] ) , 
    .X ( ropt_net_114 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[7] ) , 
    .X ( ropt_net_123 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_105 ) , 
    .X ( chanx_right_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( chanx_right_in[8] ) , 
    .X ( chany_top_out[7] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_107 ) , 
    .X ( ropt_net_143 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_108 ) , 
    .X ( chanx_right_out[2] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chany_top_in[10] ) , 
    .X ( ropt_net_146 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chany_top_in[18] ) , 
    .X ( ropt_net_147 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chany_top_in[9] ) , 
    .X ( ropt_net_145 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chanx_right_in[16] ) , 
    .X ( ropt_net_116 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[17] ) , 
    .X ( ropt_net_127 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[14] ) , 
    .X ( ropt_net_135 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[19] ) , 
    .X ( ropt_net_138 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_114 ) , 
    .X ( ropt_net_132 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_132 ) , 
    .X ( chany_top_out[5] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , 
    .X ( chany_top_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( chanx_right_in[18] ) , 
    .X ( chany_top_out[17] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , 
    .X ( chany_top_out[15] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[2] ) , 
    .X ( chany_top_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chanx_right_in[4] ) , 
    .X ( ropt_net_126 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_135 ) , 
    .X ( chany_top_out[13] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chanx_right_in[9] ) , 
    .X ( ropt_net_124 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_57 ( .A ( chanx_right_in[10] ) , 
    .X ( ropt_net_125 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chanx_right_in[11] ) , 
    .X ( ropt_net_122 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chanx_right_in[12] ) , 
    .X ( ropt_net_120 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_136 ) , 
    .X ( chany_top_out[19] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_61 ( .A ( chanx_right_in[15] ) , 
    .X ( ropt_net_117 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_137 ) , 
    .X ( chany_top_out[8] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_138 ) , 
    .X ( chany_top_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_116 ) , 
    .X ( ropt_net_134 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_117 ) , 
    .X ( ropt_net_133 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_118 ) , 
    .X ( chanx_right_out[18] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_119 ) , 
    .X ( ropt_net_136 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_120 ) , 
    .X ( chany_top_out[11] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_79 ( .A ( chanx_right_in[0] ) , 
    .X ( ropt_net_119 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_80 ( 
    .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , 
    .X ( ropt_net_121 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_139 ) , 
    .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_140 ) , 
    .X ( ccff_tail[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[17] ) , 
    .X ( ropt_net_118 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_141 ) , 
    .X ( chany_top_out[10] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_121 ) , 
    .X ( ropt_net_139 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_122 ) , 
    .X ( ropt_net_141 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_123 ) , 
    .X ( chany_top_out[6] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_124 ) , 
    .X ( ropt_net_137 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_125 ) , 
    .X ( chany_top_out[9] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_126 ) , 
    .X ( ropt_net_142 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_127 ) , 
    .X ( chany_top_out[16] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( ropt_net_142 ) , 
    .X ( chany_top_out[3] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_143 ) , 
    .X ( chanx_right_out[12] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_144 ) , 
    .X ( chanx_right_out[14] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_145 ) , 
    .X ( chanx_right_out[10] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_146 ) , 
    .X ( chanx_right_out[11] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_147 ) , 
    .X ( chanx_right_out[19] ) ) ;
endmodule


module grid_clb_direct_interc_13 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module grid_clb_direct_interc_12 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module grid_clb_direct_interc_11 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module grid_clb_direct_interc_10 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module grid_clb_direct_interc_9 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module grid_clb_direct_interc_8 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module grid_clb_direct_interc_7 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module grid_clb_direct_interc_6 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module grid_clb_mux_tree_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__60 ( .A ( mem_out[1] ) , 
    .X ( net_net_110 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_110 ( .A ( net_net_110 ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__59 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__58 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_const1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_23 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module grid_clb_const1_30 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_22 ( in , sram , sram_inv , out , p_abuf0 , 
    p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
output p_abuf0 ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_30 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ;
endmodule


module grid_clb_const1_29 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_21 ( in , sram , sram_inv , out , p_abuf0 , 
    p_abuf1 , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
output p_abuf0 ;
output p_abuf1 ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_29 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_93 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_94 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( 
    Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , p_abuf0 , p_abuf1 , 
    p_abuf2 ) ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:0] ff_D ;
input  [0:0] ff_DI ;
output [0:0] ff_Q ;
input  [0:0] ff_clk ;
output p_abuf0 ;
output p_abuf1 ;
output p_abuf2 ;

sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , 
    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , 
    .Q ( p_abuf2 ) ) ;
sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_64 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( ff_Q[0] ) , .X ( p_abuf1 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_111 ( .A ( ff_Q[0] ) , 
    .X ( p_abuf0 ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 ( 
    Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:0] ff_D ;
input  [0:0] ff_DI ;
output [0:0] ff_Q ;
input  [0:0] ff_clk ;

sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , 
    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , 
    .Q ( ff_Q[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__57 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_const1_28 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_28 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
    ccff_head , ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:16] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__56 ( .A ( mem_out[16] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_frac_lut4_mux ( in , sram , sram_inv , lut3_out , lut4_out ) ;
input  [0:15] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:1] lut3_out ;
output [0:0] lut4_out ;

wire [0:0] sky130_fd_sc_hd__buf_2_3_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_4_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_5_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
endmodule


module grid_clb_frac_lut4 ( in , sram , sram_inv , mode , mode_inv , 
    lut3_out , lut4_out ) ;
input  [0:3] in ;
input  [0:15] sram ;
input  [0:15] sram_inv ;
input  [0:0] mode ;
input  [0:0] mode_inv ;
output [0:1] lut3_out ;
output [0:0] lut4_out ;

wire [0:0] sky130_fd_sc_hd__buf_2_0_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_1_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_2_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_3_X ;
wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;

sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , 
    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( 
    .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , 
    .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , 
    .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( 
    .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ;
grid_clb_frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) ,
    .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , 
        sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) ,
    .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , 
        sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , 
        sky130_fd_sc_hd__inv_1_3_Y[0] } ) ,
    .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 ( 
    prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , 
    frac_lut4_lut4_out , ccff_tail ) ;
input  [0:0] prog_clk ;
input  [0:3] frac_lut4_in ;
input  [0:0] ccff_head ;
output [0:1] frac_lut4_lut3_out ;
output [0:0] frac_lut4_lut4_out ;
output [0:0] ccff_tail ;

wire [0:15] frac_lut4_0__undriven_sram_inv ;
wire [0:0] frac_lut4_0_mode ;
wire [0:15] frac_lut4_0_sram ;

grid_clb_frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , 
    .sram ( frac_lut4_0_sram ) , 
    .sram_inv ( frac_lut4_0__undriven_sram_inv ) , 
    .mode ( frac_lut4_0_mode ) ,
    .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ;
grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( ccff_tail ) ,
    .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , 
        frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , 
        frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , 
        frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , 
        frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , 
        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic ( 
    prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ;
input  [0:0] prog_clk ;
input  [0:3] frac_logic_in ;
input  [0:0] ccff_head ;
output [0:1] frac_logic_out ;
output [0:0] ccff_tail ;
input  p0 ;

wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ;
wire [0:1] mux_tree_size2_0_sram ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( 
    .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , 
    .ccff_head ( ccff_head ) ,
    .frac_lut4_lut3_out ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , 
        frac_logic_out[1] } ) ,
    
    .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
grid_clb_mux_tree_size2 mux_frac_logic_out_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
         } ) ,
    .sram ( mux_tree_size2_0_sram ) , 
    .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , 
    .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ;
grid_clb_mux_tree_size2_mem mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( frac_logic_out[1] ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .out ( frac_logic_in[0] ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( frac_logic_in[1] ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( frac_logic_in[2] ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( frac_logic_in[3] ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( 
    prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , 
    fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , 
    ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p_abuf5 , 
    p0 ) ;
input  [0:0] prog_clk ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:3] fabric_in ;
input  [0:0] fabric_regin ;
input  [0:0] fabric_sc_in ;
input  [0:0] fabric_clk ;
input  [0:0] ccff_head ;
output [0:1] fabric_out ;
output [0:0] fabric_regout ;
output [0:0] fabric_sc_out ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf1 ;
output p_abuf2 ;
output p_abuf3 ;
output p_abuf4 ;
output p_abuf5 ;
input  p0 ;

wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
wire [0:1] mux_fabric_out_0_undriven_sram_inv ;
wire [0:1] mux_fabric_out_1_undriven_sram_inv ;
wire [0:1] mux_ff_0_D_0_undriven_sram_inv ;
wire [0:1] mux_tree_size2_0_sram ;
wire [0:1] mux_tree_size2_1_sram ;
wire [0:0] mux_tree_size2_2_out ;
wire [0:1] mux_tree_size2_2_sram ;
wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_size2_mem_1_ccff_tail ;

assign p_abuf1 = p_abuf2 ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( 
    .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , 
    .ccff_head ( ccff_head ) , 
    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
    .p0 ( p0 ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( 
    .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , 
    .ff_DI ( fabric_sc_in ) , 
    .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
    .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( 
    .Test_en ( Test_en ) , .clk ( clk ) , 
    .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , 
    .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
    .ff_Q ( fabric_sc_out ) ,
    .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .p_abuf0 ( fabric_regout[0] ) , .p_abuf1 ( p_abuf0 ) , 
    .p_abuf2 ( p_abuf2 ) ) ;
grid_clb_mux_tree_size2_21 mux_fabric_out_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
         } ) ,
    .sram ( mux_tree_size2_0_sram ) , 
    .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , 
    .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , 
    .p0 ( p0 ) ) ;
grid_clb_mux_tree_size2_22 mux_fabric_out_1 (
    .in ( { p_abuf2 , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
         } ) ,
    .sram ( mux_tree_size2_1_sram ) , 
    .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , 
    .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf5 ) , .p0 ( p0 ) ) ;
grid_clb_mux_tree_size2_23 mux_ff_0_D_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , 
        fabric_regin[0] } ) ,
    .sram ( mux_tree_size2_2_sram ) , 
    .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , 
    .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ;
grid_clb_mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_size2_0_sram ) ) ;
grid_clb_mux_tree_size2_mem_22 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_size2_1_sram ) ) ;
grid_clb_mux_tree_size2_mem_23 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , 
    .mem_out ( mux_tree_size2_2_sram ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( { p_abuf2 } ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( { p_abuf2 } ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( fabric_in[0] ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_6 } ) ,
    .out ( fabric_in[1] ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_7 } ) ,
    .out ( fabric_in[2] ) ) ;
grid_clb_direct_interc direct_interc_5_ (
    .in ( { SYNOPSYS_UNCONNECTED_8 } ) ,
    .out ( fabric_in[3] ) ) ;
grid_clb_direct_interc direct_interc_6_ (
    .in ( { SYNOPSYS_UNCONNECTED_9 } ) ,
    .out ( fabric_sc_in ) ) ;
grid_clb_direct_interc direct_interc_7_ (
    .in ( { SYNOPSYS_UNCONNECTED_10 } ) ,
    .out ( fabric_clk ) ) ;
grid_clb_direct_interc direct_interc_8_ (
    .in ( { SYNOPSYS_UNCONNECTED_11 } ) ,
    
    .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ;
grid_clb_direct_interc direct_interc_9_ (
    .in ( { SYNOPSYS_UNCONNECTED_12 } ) ,
    
    .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ;
grid_clb_direct_interc direct_interc_10_ (
    .in ( { SYNOPSYS_UNCONNECTED_13 } ) ,
    .out ( fabric_clk ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle ( prog_clk , Test_en , 
    clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , 
    fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , 
    p_abuf3 , p_abuf4 , p_abuf5 , p0 ) ;
input  [0:0] prog_clk ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:3] fle_in ;
input  [0:0] fle_regin ;
input  [0:0] fle_sc_in ;
input  [0:0] fle_clk ;
input  [0:0] ccff_head ;
output [0:1] fle_out ;
output [0:0] fle_regout ;
output [0:0] fle_sc_out ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf1 ;
output p_abuf2 ;
output p_abuf3 ;
output p_abuf4 ;
output p_abuf5 ;
input  p0 ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( 
    .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , 
    .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , 
    .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , 
    .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , 
    .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , 
    .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , 
    .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p_abuf4 ( p_abuf4 ) , 
    .p_abuf5 ( p_abuf5 ) , .p0 ( p0 ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( { p_abuf4 } ) ) ;
grid_clb_direct_interc_6 direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( { p_abuf1 } ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( { p_abuf2 } ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_6 } ) ,
    .out ( fle_in[0] ) ) ;
grid_clb_direct_interc direct_interc_5_ (
    .in ( { SYNOPSYS_UNCONNECTED_7 } ) ,
    .out ( fle_in[1] ) ) ;
grid_clb_direct_interc direct_interc_6_ (
    .in ( { SYNOPSYS_UNCONNECTED_8 } ) ,
    .out ( fle_in[2] ) ) ;
grid_clb_direct_interc direct_interc_7_ (
    .in ( { SYNOPSYS_UNCONNECTED_9 } ) ,
    .out ( fle_in[3] ) ) ;
grid_clb_direct_interc direct_interc_8_ (
    .in ( { SYNOPSYS_UNCONNECTED_10 } ) ,
    .out ( fle_regin ) ) ;
grid_clb_direct_interc direct_interc_9_ (
    .in ( { SYNOPSYS_UNCONNECTED_11 } ) ,
    .out ( fle_sc_in ) ) ;
grid_clb_direct_interc direct_interc_10_ (
    .in ( { SYNOPSYS_UNCONNECTED_12 } ) ,
    .out ( fle_clk ) ) ;
endmodule


module grid_clb_direct_interc_5 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module grid_clb_direct_interc_4 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module grid_clb_mux_tree_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__55 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__54 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__53 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_const1_27 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , p3 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p3 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_27 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module grid_clb_const1_26 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_19 ( in , sram , sram_inv , out , p_abuf0 , 
    p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
output p_abuf0 ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_26 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ;
endmodule


module grid_clb_const1_25 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , p_abuf0 , 
    p3 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
output p_abuf0 ;
input  p3 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_25 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p3 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 ( 
    Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:0] ff_D ;
input  [0:0] ff_DI ;
output [0:0] ff_Q ;
input  [0:0] ff_clk ;

sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , 
    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , 
    .Q ( ff_Q[0] ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 ( 
    Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:0] ff_D ;
input  [0:0] ff_DI ;
output [0:0] ff_Q ;
input  [0:0] ff_clk ;

sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , 
    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , 
    .Q ( ff_Q[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_30 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__52 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_const1_24 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_30 ( in , sram , sram_inv , out , p3 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p3 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_24 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_6 ( prog_clk , 
    ccff_head , ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:16] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__51 ( .A ( mem_out[16] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_frac_lut4_mux_6 ( in , sram , sram_inv , lut3_out , lut4_out ) ;
input  [0:15] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:1] lut3_out ;
output [0:0] lut4_out ;

wire [0:0] sky130_fd_sc_hd__buf_2_3_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_4_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_5_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
endmodule


module grid_clb_frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv , 
    lut3_out , lut4_out ) ;
input  [0:3] in ;
input  [0:15] sram ;
input  [0:15] sram_inv ;
input  [0:0] mode ;
input  [0:0] mode_inv ;
output [0:1] lut3_out ;
output [0:0] lut4_out ;

wire [0:0] sky130_fd_sc_hd__buf_2_0_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_1_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_2_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_3_X ;
wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;

sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , 
    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( 
    .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ;
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , 
    .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , 
    .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ;
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( 
    .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ;
grid_clb_frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) ,
    .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , 
        sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) ,
    .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , 
        sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , 
        sky130_fd_sc_hd__inv_1_3_Y[0] } ) ,
    .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 ( 
    prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , 
    frac_lut4_lut4_out , ccff_tail ) ;
input  [0:0] prog_clk ;
input  [0:3] frac_lut4_in ;
input  [0:0] ccff_head ;
output [0:1] frac_lut4_lut3_out ;
output [0:0] frac_lut4_lut4_out ;
output [0:0] ccff_tail ;

wire [0:15] frac_lut4_0__undriven_sram_inv ;
wire [0:0] frac_lut4_0_mode ;
wire [0:15] frac_lut4_0_sram ;

grid_clb_frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , 
    .sram ( frac_lut4_0_sram ) , 
    .sram_inv ( frac_lut4_0__undriven_sram_inv ) , 
    .mode ( frac_lut4_0_mode ) ,
    .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ;
grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( ccff_tail ) ,
    .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , 
        frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , 
        frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , 
        frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , 
        frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , 
        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( 
    prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p3 ) ;
input  [0:0] prog_clk ;
input  [0:3] frac_logic_in ;
input  [0:0] ccff_head ;
output [0:1] frac_logic_out ;
output [0:0] ccff_tail ;
input  p3 ;

wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ;
wire [0:1] mux_tree_size2_0_sram ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( 
    .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , 
    .ccff_head ( ccff_head ) ,
    .frac_lut4_lut3_out ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , 
        frac_logic_out[1] } ) ,
    
    .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
grid_clb_mux_tree_size2_30 mux_frac_logic_out_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
         } ) ,
    .sram ( mux_tree_size2_0_sram ) , 
    .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , 
    .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ;
grid_clb_mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( frac_logic_out[1] ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .out ( frac_logic_in[0] ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( frac_logic_in[1] ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( frac_logic_in[2] ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( frac_logic_in[3] ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( 
    prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , 
    fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , 
    ccff_tail , p_abuf0 , p_abuf2 , p0 , p3 ) ;
input  [0:0] prog_clk ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:3] fabric_in ;
input  [0:0] fabric_regin ;
input  [0:0] fabric_sc_in ;
input  [0:0] fabric_clk ;
input  [0:0] ccff_head ;
output [0:1] fabric_out ;
output [0:0] fabric_regout ;
output [0:0] fabric_sc_out ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf2 ;
input  p0 ;
input  p3 ;

wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
wire [0:1] mux_fabric_out_0_undriven_sram_inv ;
wire [0:1] mux_fabric_out_1_undriven_sram_inv ;
wire [0:1] mux_ff_0_D_0_undriven_sram_inv ;
wire [0:1] mux_tree_size2_0_sram ;
wire [0:1] mux_tree_size2_1_sram ;
wire [0:0] mux_tree_size2_2_out ;
wire [0:1] mux_tree_size2_2_sram ;
wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_size2_mem_1_ccff_tail ;

assign fabric_regout[0] = fabric_sc_out[0] ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( 
    .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , 
    .ccff_head ( ccff_head ) , 
    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
    .p3 ( p3 ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( 
    .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , 
    .ff_DI ( fabric_sc_in ) , 
    .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
    .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( 
    .Test_en ( Test_en ) , .clk ( clk ) , 
    .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , 
    .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
    .ff_Q ( fabric_sc_out ) ,
    .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ;
grid_clb_mux_tree_size2_18 mux_fabric_out_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
         } ) ,
    .sram ( mux_tree_size2_0_sram ) , 
    .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , 
    .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ;
grid_clb_mux_tree_size2_19 mux_fabric_out_1 (
    .in ( { fabric_sc_out[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
         } ) ,
    .sram ( mux_tree_size2_1_sram ) , 
    .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , 
    .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ;
grid_clb_mux_tree_size2_20 mux_ff_0_D_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , 
        fabric_regin[0] } ) ,
    .sram ( mux_tree_size2_2_sram ) , 
    .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , 
    .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ;
grid_clb_mux_tree_size2_mem_18 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_size2_0_sram ) ) ;
grid_clb_mux_tree_size2_mem_19 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_size2_1_sram ) ) ;
grid_clb_mux_tree_size2_mem_20 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , 
    .mem_out ( mux_tree_size2_2_sram ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( fabric_sc_out ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( fabric_sc_out ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( fabric_in[0] ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_6 } ) ,
    .out ( fabric_in[1] ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_7 } ) ,
    .out ( fabric_in[2] ) ) ;
grid_clb_direct_interc direct_interc_5_ (
    .in ( { SYNOPSYS_UNCONNECTED_8 } ) ,
    .out ( fabric_in[3] ) ) ;
grid_clb_direct_interc direct_interc_6_ (
    .in ( { SYNOPSYS_UNCONNECTED_9 } ) ,
    .out ( fabric_sc_in ) ) ;
grid_clb_direct_interc direct_interc_7_ (
    .in ( { SYNOPSYS_UNCONNECTED_10 } ) ,
    .out ( fabric_clk ) ) ;
grid_clb_direct_interc direct_interc_8_ (
    .in ( { SYNOPSYS_UNCONNECTED_11 } ) ,
    
    .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ;
grid_clb_direct_interc direct_interc_9_ (
    .in ( { SYNOPSYS_UNCONNECTED_12 } ) ,
    
    .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ;
grid_clb_direct_interc direct_interc_10_ (
    .in ( { SYNOPSYS_UNCONNECTED_13 } ) ,
    .out ( fabric_clk ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , 
    clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , 
    fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p0 , p3 ) ;
input  [0:0] prog_clk ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:3] fle_in ;
input  [0:0] fle_regin ;
input  [0:0] fle_sc_in ;
input  [0:0] fle_clk ;
input  [0:0] ccff_head ;
output [0:1] fle_out ;
output [0:0] fle_regout ;
output [0:0] fle_sc_out ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf2 ;
input  p0 ;
input  p3 ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( 
    .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , 
    .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , 
    .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , 
    .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , 
    .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , 
    .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , 
    .p0 ( p0 ) , .p3 ( p3 ) ) ;
grid_clb_direct_interc_4 direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ;
grid_clb_direct_interc_5 direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_4 } ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( fle_regout ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_6 } ) ,
    .out ( fle_sc_out ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_7 } ) ,
    .out ( fle_in[0] ) ) ;
grid_clb_direct_interc direct_interc_5_ (
    .in ( { SYNOPSYS_UNCONNECTED_8 } ) ,
    .out ( fle_in[1] ) ) ;
grid_clb_direct_interc direct_interc_6_ (
    .in ( { SYNOPSYS_UNCONNECTED_9 } ) ,
    .out ( fle_in[2] ) ) ;
grid_clb_direct_interc direct_interc_7_ (
    .in ( { SYNOPSYS_UNCONNECTED_10 } ) ,
    .out ( fle_in[3] ) ) ;
grid_clb_direct_interc direct_interc_8_ (
    .in ( { SYNOPSYS_UNCONNECTED_11 } ) ,
    .out ( fle_regin ) ) ;
grid_clb_direct_interc direct_interc_9_ (
    .in ( { SYNOPSYS_UNCONNECTED_12 } ) ,
    .out ( fle_sc_in ) ) ;
grid_clb_direct_interc direct_interc_10_ (
    .in ( { SYNOPSYS_UNCONNECTED_13 } ) ,
    .out ( fle_clk ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__50 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__49 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__48 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_const1_23 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_17 ( in , sram , sram_inv , out , p3 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p3 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_23 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module grid_clb_const1_22 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_16 ( in , sram , sram_inv , out , p_abuf0 , 
    p_abuf1 , p3 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
output p_abuf0 ;
output p_abuf1 ;
input  p3 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_22 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ;
endmodule


module grid_clb_const1_21 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , p_abuf0 , 
    p_abuf1 , p3 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
output p_abuf0 ;
output p_abuf1 ;
input  p3 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_21 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_85 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( .A ( p_abuf1 ) , 
    .X ( BUF_net_86 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_125 ( .A ( BUF_net_86 ) , 
    .X ( p_abuf0 ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 ( 
    Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:0] ff_D ;
input  [0:0] ff_DI ;
output [0:0] ff_Q ;
input  [0:0] ff_clk ;

sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , 
    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , 
    .Q ( ff_Q[0] ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 ( 
    Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:0] ff_D ;
input  [0:0] ff_DI ;
output [0:0] ff_Q ;
input  [0:0] ff_clk ;

sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , 
    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , 
    .Q ( ff_Q[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_29 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__47 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_const1_20 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_29 ( in , sram , sram_inv , out , p3 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p3 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_20 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_5 ( prog_clk , 
    ccff_head , ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:16] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__46 ( .A ( mem_out[16] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_frac_lut4_mux_5 ( in , sram , sram_inv , lut3_out , lut4_out ) ;
input  [0:15] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:1] lut3_out ;
output [0:0] lut4_out ;

wire [0:0] sky130_fd_sc_hd__buf_2_3_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_4_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_5_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
endmodule


module grid_clb_frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv , 
    lut3_out , lut4_out ) ;
input  [0:3] in ;
input  [0:15] sram ;
input  [0:15] sram_inv ;
input  [0:0] mode ;
input  [0:0] mode_inv ;
output [0:1] lut3_out ;
output [0:0] lut4_out ;

wire [0:0] sky130_fd_sc_hd__buf_2_0_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_1_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_2_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_3_X ;
wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;

sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , 
    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( 
    .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , 
    .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , 
    .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( 
    .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ;
grid_clb_frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) ,
    .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , 
        sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) ,
    .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , 
        sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , 
        sky130_fd_sc_hd__inv_1_3_Y[0] } ) ,
    .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 ( 
    prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , 
    frac_lut4_lut4_out , ccff_tail ) ;
input  [0:0] prog_clk ;
input  [0:3] frac_lut4_in ;
input  [0:0] ccff_head ;
output [0:1] frac_lut4_lut3_out ;
output [0:0] frac_lut4_lut4_out ;
output [0:0] ccff_tail ;

wire [0:15] frac_lut4_0__undriven_sram_inv ;
wire [0:0] frac_lut4_0_mode ;
wire [0:15] frac_lut4_0_sram ;

grid_clb_frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , 
    .sram ( frac_lut4_0_sram ) , 
    .sram_inv ( frac_lut4_0__undriven_sram_inv ) , 
    .mode ( frac_lut4_0_mode ) ,
    .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ;
grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( ccff_tail ) ,
    .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , 
        frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , 
        frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , 
        frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , 
        frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , 
        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( 
    prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p3 ) ;
input  [0:0] prog_clk ;
input  [0:3] frac_logic_in ;
input  [0:0] ccff_head ;
output [0:1] frac_logic_out ;
output [0:0] ccff_tail ;
input  p3 ;

wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ;
wire [0:1] mux_tree_size2_0_sram ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( 
    .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , 
    .ccff_head ( ccff_head ) ,
    .frac_lut4_lut3_out ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , 
        frac_logic_out[1] } ) ,
    
    .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
grid_clb_mux_tree_size2_29 mux_frac_logic_out_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
         } ) ,
    .sram ( mux_tree_size2_0_sram ) , 
    .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , 
    .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ;
grid_clb_mux_tree_size2_mem_29 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( frac_logic_out[1] ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .out ( frac_logic_in[0] ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( frac_logic_in[1] ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( frac_logic_in[2] ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( frac_logic_in[3] ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( 
    prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , 
    fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , 
    ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p3 ) ;
input  [0:0] prog_clk ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:3] fabric_in ;
input  [0:0] fabric_regin ;
input  [0:0] fabric_sc_in ;
input  [0:0] fabric_clk ;
input  [0:0] ccff_head ;
output [0:1] fabric_out ;
output [0:0] fabric_regout ;
output [0:0] fabric_sc_out ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf1 ;
output p_abuf2 ;
output p_abuf3 ;
input  p3 ;

wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
wire [0:1] mux_fabric_out_0_undriven_sram_inv ;
wire [0:1] mux_fabric_out_1_undriven_sram_inv ;
wire [0:1] mux_ff_0_D_0_undriven_sram_inv ;
wire [0:1] mux_tree_size2_0_sram ;
wire [0:1] mux_tree_size2_1_sram ;
wire [0:0] mux_tree_size2_2_out ;
wire [0:1] mux_tree_size2_2_sram ;
wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_size2_mem_1_ccff_tail ;

assign fabric_regout[0] = fabric_sc_out[0] ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( 
    .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , 
    .ccff_head ( ccff_head ) , 
    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
    .p3 ( p3 ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( 
    .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , 
    .ff_DI ( fabric_sc_in ) , 
    .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
    .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( 
    .Test_en ( Test_en ) , .clk ( clk ) , 
    .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , 
    .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
    .ff_Q ( fabric_sc_out ) ,
    .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ;
grid_clb_mux_tree_size2_15 mux_fabric_out_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
         } ) ,
    .sram ( mux_tree_size2_0_sram ) , 
    .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , 
    .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , 
    .p3 ( p3 ) ) ;
grid_clb_mux_tree_size2_16 mux_fabric_out_1 (
    .in ( { fabric_sc_out[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
         } ) ,
    .sram ( mux_tree_size2_1_sram ) , 
    .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , 
    .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , 
    .p3 ( p3 ) ) ;
grid_clb_mux_tree_size2_17 mux_ff_0_D_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , 
        fabric_regin[0] } ) ,
    .sram ( mux_tree_size2_2_sram ) , 
    .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , 
    .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ;
grid_clb_mux_tree_size2_mem_15 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_size2_0_sram ) ) ;
grid_clb_mux_tree_size2_mem_16 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_size2_1_sram ) ) ;
grid_clb_mux_tree_size2_mem_17 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , 
    .mem_out ( mux_tree_size2_2_sram ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( fabric_sc_out ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( fabric_sc_out ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( fabric_in[0] ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_6 } ) ,
    .out ( fabric_in[1] ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_7 } ) ,
    .out ( fabric_in[2] ) ) ;
grid_clb_direct_interc direct_interc_5_ (
    .in ( { SYNOPSYS_UNCONNECTED_8 } ) ,
    .out ( fabric_in[3] ) ) ;
grid_clb_direct_interc direct_interc_6_ (
    .in ( { SYNOPSYS_UNCONNECTED_9 } ) ,
    .out ( fabric_sc_in ) ) ;
grid_clb_direct_interc direct_interc_7_ (
    .in ( { SYNOPSYS_UNCONNECTED_10 } ) ,
    .out ( fabric_clk ) ) ;
grid_clb_direct_interc direct_interc_8_ (
    .in ( { SYNOPSYS_UNCONNECTED_11 } ) ,
    
    .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ;
grid_clb_direct_interc direct_interc_9_ (
    .in ( { SYNOPSYS_UNCONNECTED_12 } ) ,
    
    .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ;
grid_clb_direct_interc direct_interc_10_ (
    .in ( { SYNOPSYS_UNCONNECTED_13 } ) ,
    .out ( fabric_clk ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , 
    clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , 
    fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , 
    p_abuf3 , p3 ) ;
input  [0:0] prog_clk ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:3] fle_in ;
input  [0:0] fle_regin ;
input  [0:0] fle_sc_in ;
input  [0:0] fle_clk ;
input  [0:0] ccff_head ;
output [0:1] fle_out ;
output [0:0] fle_regout ;
output [0:0] fle_sc_out ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf1 ;
output p_abuf2 ;
output p_abuf3 ;
input  p3 ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( 
    .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , 
    .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , 
    .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , 
    .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , 
    .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , 
    .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , 
    .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p3 ( p3 ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( { p_abuf1 } ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .out ( { p_abuf3 } ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( fle_regout ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( fle_sc_out ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( fle_in[0] ) ) ;
grid_clb_direct_interc direct_interc_5_ (
    .in ( { SYNOPSYS_UNCONNECTED_6 } ) ,
    .out ( fle_in[1] ) ) ;
grid_clb_direct_interc direct_interc_6_ (
    .in ( { SYNOPSYS_UNCONNECTED_7 } ) ,
    .out ( fle_in[2] ) ) ;
grid_clb_direct_interc direct_interc_7_ (
    .in ( { SYNOPSYS_UNCONNECTED_8 } ) ,
    .out ( fle_in[3] ) ) ;
grid_clb_direct_interc direct_interc_8_ (
    .in ( { SYNOPSYS_UNCONNECTED_9 } ) ,
    .out ( fle_regin ) ) ;
grid_clb_direct_interc direct_interc_9_ (
    .in ( { SYNOPSYS_UNCONNECTED_10 } ) ,
    .out ( fle_sc_in ) ) ;
grid_clb_direct_interc direct_interc_10_ (
    .in ( { SYNOPSYS_UNCONNECTED_11 } ) ,
    .out ( fle_clk ) ) ;
endmodule


module grid_clb_direct_interc_3 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module grid_clb_direct_interc_2 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module grid_clb_mux_tree_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__45 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__44 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__43 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_const1_19 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_14 ( in , sram , sram_inv , out , p2 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p2 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_19 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module grid_clb_const1_18 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_13 ( in , sram , sram_inv , out , p_abuf0 , 
    p2 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
output p_abuf0 ;
input  p2 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_18 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_84 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ;
endmodule


module grid_clb_const1_17 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , p_abuf0 , 
    p2 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
output p_abuf0 ;
input  p2 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_17 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 ( 
    Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:0] ff_D ;
input  [0:0] ff_DI ;
output [0:0] ff_Q ;
input  [0:0] ff_clk ;

sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , 
    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , 
    .Q ( ff_Q[0] ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 ( 
    Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:0] ff_D ;
input  [0:0] ff_DI ;
output [0:0] ff_Q ;
input  [0:0] ff_clk ;

sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , 
    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , 
    .Q ( ff_Q[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_28 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__42 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_const1_16 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , p2 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p2 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_16 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , 
    ccff_head , ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:16] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__41 ( .A ( mem_out[16] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_frac_lut4_mux_4 ( in , sram , sram_inv , lut3_out , lut4_out ) ;
input  [0:15] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:1] lut3_out ;
output [0:0] lut4_out ;

wire [0:0] sky130_fd_sc_hd__buf_2_3_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_4_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_5_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
endmodule


module grid_clb_frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv , 
    lut3_out , lut4_out ) ;
input  [0:3] in ;
input  [0:15] sram ;
input  [0:15] sram_inv ;
input  [0:0] mode ;
input  [0:0] mode_inv ;
output [0:1] lut3_out ;
output [0:0] lut4_out ;

wire [0:0] sky130_fd_sc_hd__buf_2_0_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_1_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_2_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_3_X ;
wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;

sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , 
    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( 
    .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ;
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , 
    .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , 
    .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( 
    .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ;
grid_clb_frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) ,
    .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , 
        sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) ,
    .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , 
        sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , 
        sky130_fd_sc_hd__inv_1_3_Y[0] } ) ,
    .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 ( 
    prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , 
    frac_lut4_lut4_out , ccff_tail ) ;
input  [0:0] prog_clk ;
input  [0:3] frac_lut4_in ;
input  [0:0] ccff_head ;
output [0:1] frac_lut4_lut3_out ;
output [0:0] frac_lut4_lut4_out ;
output [0:0] ccff_tail ;

wire [0:15] frac_lut4_0__undriven_sram_inv ;
wire [0:0] frac_lut4_0_mode ;
wire [0:15] frac_lut4_0_sram ;

grid_clb_frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , 
    .sram ( frac_lut4_0_sram ) , 
    .sram_inv ( frac_lut4_0__undriven_sram_inv ) , 
    .mode ( frac_lut4_0_mode ) ,
    .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ;
grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( ccff_tail ) ,
    .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , 
        frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , 
        frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , 
        frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , 
        frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , 
        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( 
    prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ;
input  [0:0] prog_clk ;
input  [0:3] frac_logic_in ;
input  [0:0] ccff_head ;
output [0:1] frac_logic_out ;
output [0:0] ccff_tail ;
input  p2 ;

wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ;
wire [0:1] mux_tree_size2_0_sram ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( 
    .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , 
    .ccff_head ( ccff_head ) ,
    .frac_lut4_lut3_out ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , 
        frac_logic_out[1] } ) ,
    
    .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
grid_clb_mux_tree_size2_28 mux_frac_logic_out_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
         } ) ,
    .sram ( mux_tree_size2_0_sram ) , 
    .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , 
    .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ;
grid_clb_mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( frac_logic_out[1] ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .out ( frac_logic_in[0] ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( frac_logic_in[1] ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( frac_logic_in[2] ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( frac_logic_in[3] ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( 
    prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , 
    fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , 
    ccff_tail , p_abuf0 , p_abuf2 , p2 ) ;
input  [0:0] prog_clk ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:3] fabric_in ;
input  [0:0] fabric_regin ;
input  [0:0] fabric_sc_in ;
input  [0:0] fabric_clk ;
input  [0:0] ccff_head ;
output [0:1] fabric_out ;
output [0:0] fabric_regout ;
output [0:0] fabric_sc_out ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf2 ;
input  p2 ;

wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
wire [0:1] mux_fabric_out_0_undriven_sram_inv ;
wire [0:1] mux_fabric_out_1_undriven_sram_inv ;
wire [0:1] mux_ff_0_D_0_undriven_sram_inv ;
wire [0:1] mux_tree_size2_0_sram ;
wire [0:1] mux_tree_size2_1_sram ;
wire [0:0] mux_tree_size2_2_out ;
wire [0:1] mux_tree_size2_2_sram ;
wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_size2_mem_1_ccff_tail ;

assign fabric_regout[0] = fabric_sc_out[0] ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( 
    .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , 
    .ccff_head ( ccff_head ) , 
    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
    .p2 ( p2 ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( 
    .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , 
    .ff_DI ( fabric_sc_in ) , 
    .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
    .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( 
    .Test_en ( Test_en ) , .clk ( clk ) , 
    .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , 
    .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
    .ff_Q ( fabric_sc_out ) ,
    .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ;
grid_clb_mux_tree_size2_12 mux_fabric_out_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
         } ) ,
    .sram ( mux_tree_size2_0_sram ) , 
    .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , 
    .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ;
grid_clb_mux_tree_size2_13 mux_fabric_out_1 (
    .in ( { fabric_sc_out[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
         } ) ,
    .sram ( mux_tree_size2_1_sram ) , 
    .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , 
    .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p2 ( p2 ) ) ;
grid_clb_mux_tree_size2_14 mux_ff_0_D_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , 
        fabric_regin[0] } ) ,
    .sram ( mux_tree_size2_2_sram ) , 
    .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , 
    .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ;
grid_clb_mux_tree_size2_mem_12 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_size2_0_sram ) ) ;
grid_clb_mux_tree_size2_mem_13 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_size2_1_sram ) ) ;
grid_clb_mux_tree_size2_mem_14 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , 
    .mem_out ( mux_tree_size2_2_sram ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( fabric_sc_out ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( fabric_sc_out ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( fabric_in[0] ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_6 } ) ,
    .out ( fabric_in[1] ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_7 } ) ,
    .out ( fabric_in[2] ) ) ;
grid_clb_direct_interc direct_interc_5_ (
    .in ( { SYNOPSYS_UNCONNECTED_8 } ) ,
    .out ( fabric_in[3] ) ) ;
grid_clb_direct_interc direct_interc_6_ (
    .in ( { SYNOPSYS_UNCONNECTED_9 } ) ,
    .out ( fabric_sc_in ) ) ;
grid_clb_direct_interc direct_interc_7_ (
    .in ( { SYNOPSYS_UNCONNECTED_10 } ) ,
    .out ( fabric_clk ) ) ;
grid_clb_direct_interc direct_interc_8_ (
    .in ( { SYNOPSYS_UNCONNECTED_11 } ) ,
    
    .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ;
grid_clb_direct_interc direct_interc_9_ (
    .in ( { SYNOPSYS_UNCONNECTED_12 } ) ,
    
    .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ;
grid_clb_direct_interc direct_interc_10_ (
    .in ( { SYNOPSYS_UNCONNECTED_13 } ) ,
    .out ( fabric_clk ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en , 
    clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , 
    fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p2 ) ;
input  [0:0] prog_clk ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:3] fle_in ;
input  [0:0] fle_regin ;
input  [0:0] fle_sc_in ;
input  [0:0] fle_clk ;
input  [0:0] ccff_head ;
output [0:1] fle_out ;
output [0:0] fle_regout ;
output [0:0] fle_sc_out ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf2 ;
input  p2 ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( 
    .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , 
    .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , 
    .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , 
    .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , 
    .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , 
    .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , 
    .p2 ( p2 ) ) ;
grid_clb_direct_interc_2 direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ;
grid_clb_direct_interc_3 direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_4 } ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( fle_regout ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_6 } ) ,
    .out ( fle_sc_out ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_7 } ) ,
    .out ( fle_in[0] ) ) ;
grid_clb_direct_interc direct_interc_5_ (
    .in ( { SYNOPSYS_UNCONNECTED_8 } ) ,
    .out ( fle_in[1] ) ) ;
grid_clb_direct_interc direct_interc_6_ (
    .in ( { SYNOPSYS_UNCONNECTED_9 } ) ,
    .out ( fle_in[2] ) ) ;
grid_clb_direct_interc direct_interc_7_ (
    .in ( { SYNOPSYS_UNCONNECTED_10 } ) ,
    .out ( fle_in[3] ) ) ;
grid_clb_direct_interc direct_interc_8_ (
    .in ( { SYNOPSYS_UNCONNECTED_11 } ) ,
    .out ( fle_regin ) ) ;
grid_clb_direct_interc direct_interc_9_ (
    .in ( { SYNOPSYS_UNCONNECTED_12 } ) ,
    .out ( fle_sc_in ) ) ;
grid_clb_direct_interc direct_interc_10_ (
    .in ( { SYNOPSYS_UNCONNECTED_13 } ) ,
    .out ( fle_clk ) ) ;
endmodule


module grid_clb_direct_interc_1 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module grid_clb_mux_tree_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__40 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__39 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__38 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_const1_15 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_11 ( in , sram , sram_inv , out , p2 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p2 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_15 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module grid_clb_const1_14 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , p_abuf0 , 
    p_abuf1 , p2 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
output p_abuf0 ;
output p_abuf1 ;
input  p2 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_14 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ;
endmodule


module grid_clb_const1_13 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_9 ( in , sram , sram_inv , out , p_abuf0 , p2 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
output p_abuf0 ;
input  p2 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_13 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p2 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 ( 
    Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:0] ff_D ;
input  [0:0] ff_DI ;
output [0:0] ff_Q ;
input  [0:0] ff_clk ;

sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , 
    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , 
    .Q ( ff_Q[0] ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 ( 
    Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:0] ff_D ;
input  [0:0] ff_DI ;
output [0:0] ff_Q ;
input  [0:0] ff_clk ;

sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , 
    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , 
    .Q ( ff_Q[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_27 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__37 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_const1_12 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_27 ( in , sram , sram_inv , out , p2 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p2 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_12 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , 
    ccff_head , ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:16] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__36 ( .A ( mem_out[16] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_frac_lut4_mux_3 ( in , sram , sram_inv , lut3_out , lut4_out ) ;
input  [0:15] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:1] lut3_out ;
output [0:0] lut4_out ;

wire [0:0] sky130_fd_sc_hd__buf_2_3_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_4_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_5_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ;
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
endmodule


module grid_clb_frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv , 
    lut3_out , lut4_out ) ;
input  [0:3] in ;
input  [0:15] sram ;
input  [0:15] sram_inv ;
input  [0:0] mode ;
input  [0:0] mode_inv ;
output [0:1] lut3_out ;
output [0:0] lut4_out ;

wire [0:0] sky130_fd_sc_hd__buf_2_0_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_1_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_2_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_3_X ;
wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;

sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , 
    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( 
    .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , 
    .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , 
    .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( 
    .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ;
grid_clb_frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) ,
    .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , 
        sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) ,
    .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , 
        sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , 
        sky130_fd_sc_hd__inv_1_3_Y[0] } ) ,
    .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 ( 
    prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , 
    frac_lut4_lut4_out , ccff_tail ) ;
input  [0:0] prog_clk ;
input  [0:3] frac_lut4_in ;
input  [0:0] ccff_head ;
output [0:1] frac_lut4_lut3_out ;
output [0:0] frac_lut4_lut4_out ;
output [0:0] ccff_tail ;

wire [0:15] frac_lut4_0__undriven_sram_inv ;
wire [0:0] frac_lut4_0_mode ;
wire [0:15] frac_lut4_0_sram ;

grid_clb_frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , 
    .sram ( frac_lut4_0_sram ) , 
    .sram_inv ( frac_lut4_0__undriven_sram_inv ) , 
    .mode ( frac_lut4_0_mode ) ,
    .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ;
grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( ccff_tail ) ,
    .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , 
        frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , 
        frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , 
        frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , 
        frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , 
        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( 
    prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ;
input  [0:0] prog_clk ;
input  [0:3] frac_logic_in ;
input  [0:0] ccff_head ;
output [0:1] frac_logic_out ;
output [0:0] ccff_tail ;
input  p2 ;

wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ;
wire [0:1] mux_tree_size2_0_sram ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( 
    .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , 
    .ccff_head ( ccff_head ) ,
    .frac_lut4_lut3_out ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , 
        frac_logic_out[1] } ) ,
    
    .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
grid_clb_mux_tree_size2_27 mux_frac_logic_out_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
         } ) ,
    .sram ( mux_tree_size2_0_sram ) , 
    .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , 
    .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ;
grid_clb_mux_tree_size2_mem_27 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( frac_logic_out[1] ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .out ( frac_logic_in[0] ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( frac_logic_in[1] ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( frac_logic_in[2] ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( frac_logic_in[3] ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( 
    prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , 
    fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , 
    ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p2 ) ;
input  [0:0] prog_clk ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:3] fabric_in ;
input  [0:0] fabric_regin ;
input  [0:0] fabric_sc_in ;
input  [0:0] fabric_clk ;
input  [0:0] ccff_head ;
output [0:1] fabric_out ;
output [0:0] fabric_regout ;
output [0:0] fabric_sc_out ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf2 ;
output p_abuf3 ;
input  p2 ;

wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
wire [0:1] mux_fabric_out_0_undriven_sram_inv ;
wire [0:1] mux_fabric_out_1_undriven_sram_inv ;
wire [0:1] mux_ff_0_D_0_undriven_sram_inv ;
wire [0:1] mux_tree_size2_0_sram ;
wire [0:1] mux_tree_size2_1_sram ;
wire [0:0] mux_tree_size2_2_out ;
wire [0:1] mux_tree_size2_2_sram ;
wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_size2_mem_1_ccff_tail ;

assign fabric_regout[0] = fabric_sc_out[0] ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( 
    .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , 
    .ccff_head ( ccff_head ) , 
    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
    .p2 ( p2 ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( 
    .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , 
    .ff_DI ( fabric_sc_in ) , 
    .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
    .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( 
    .Test_en ( Test_en ) , .clk ( clk ) , 
    .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , 
    .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
    .ff_Q ( fabric_sc_out ) ,
    .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ;
grid_clb_mux_tree_size2_9 mux_fabric_out_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
         } ) ,
    .sram ( mux_tree_size2_0_sram ) , 
    .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , 
    .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ;
grid_clb_mux_tree_size2_10 mux_fabric_out_1 (
    .in ( { fabric_sc_out[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
         } ) ,
    .sram ( mux_tree_size2_1_sram ) , 
    .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , 
    .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , 
    .p2 ( p2 ) ) ;
grid_clb_mux_tree_size2_11 mux_ff_0_D_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , 
        fabric_regin[0] } ) ,
    .sram ( mux_tree_size2_2_sram ) , 
    .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , 
    .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ;
grid_clb_mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_size2_0_sram ) ) ;
grid_clb_mux_tree_size2_mem_10 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_size2_1_sram ) ) ;
grid_clb_mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , 
    .mem_out ( mux_tree_size2_2_sram ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( fabric_sc_out ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( fabric_sc_out ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( fabric_in[0] ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_6 } ) ,
    .out ( fabric_in[1] ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_7 } ) ,
    .out ( fabric_in[2] ) ) ;
grid_clb_direct_interc direct_interc_5_ (
    .in ( { SYNOPSYS_UNCONNECTED_8 } ) ,
    .out ( fabric_in[3] ) ) ;
grid_clb_direct_interc direct_interc_6_ (
    .in ( { SYNOPSYS_UNCONNECTED_9 } ) ,
    .out ( fabric_sc_in ) ) ;
grid_clb_direct_interc direct_interc_7_ (
    .in ( { SYNOPSYS_UNCONNECTED_10 } ) ,
    .out ( fabric_clk ) ) ;
grid_clb_direct_interc direct_interc_8_ (
    .in ( { SYNOPSYS_UNCONNECTED_11 } ) ,
    
    .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ;
grid_clb_direct_interc direct_interc_9_ (
    .in ( { SYNOPSYS_UNCONNECTED_12 } ) ,
    
    .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ;
grid_clb_direct_interc direct_interc_10_ (
    .in ( { SYNOPSYS_UNCONNECTED_13 } ) ,
    .out ( fabric_clk ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , 
    clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , 
    fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p2 ) ;
input  [0:0] prog_clk ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:3] fle_in ;
input  [0:0] fle_regin ;
input  [0:0] fle_sc_in ;
input  [0:0] fle_clk ;
input  [0:0] ccff_head ;
output [0:1] fle_out ;
output [0:0] fle_regout ;
output [0:0] fle_sc_out ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf2 ;
output p_abuf3 ;
input  p2 ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( 
    .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , 
    .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , 
    .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , 
    .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , 
    .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , 
    .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , 
    .p_abuf3 ( p_abuf3 ) , .p2 ( p2 ) ) ;
grid_clb_direct_interc_1 direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( { p_abuf3 } ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( fle_regout ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( fle_sc_out ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_6 } ) ,
    .out ( fle_in[0] ) ) ;
grid_clb_direct_interc direct_interc_5_ (
    .in ( { SYNOPSYS_UNCONNECTED_7 } ) ,
    .out ( fle_in[1] ) ) ;
grid_clb_direct_interc direct_interc_6_ (
    .in ( { SYNOPSYS_UNCONNECTED_8 } ) ,
    .out ( fle_in[2] ) ) ;
grid_clb_direct_interc direct_interc_7_ (
    .in ( { SYNOPSYS_UNCONNECTED_9 } ) ,
    .out ( fle_in[3] ) ) ;
grid_clb_direct_interc direct_interc_8_ (
    .in ( { SYNOPSYS_UNCONNECTED_10 } ) ,
    .out ( fle_regin ) ) ;
grid_clb_direct_interc direct_interc_9_ (
    .in ( { SYNOPSYS_UNCONNECTED_11 } ) ,
    .out ( fle_sc_in ) ) ;
grid_clb_direct_interc direct_interc_10_ (
    .in ( { SYNOPSYS_UNCONNECTED_12 } ) ,
    .out ( fle_clk ) ) ;
endmodule


module grid_clb_direct_interc_0 ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;
endmodule


module grid_clb_mux_tree_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__35 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__34 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__33 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_const1_11 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_11 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module grid_clb_const1_10 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_7 ( in , sram , sram_inv , out , p_abuf0 , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
output p_abuf0 ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_10 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ;
endmodule


module grid_clb_const1_9 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_6 ( in , sram , sram_inv , out , p_abuf0 , 
    p_abuf1 , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
output p_abuf0 ;
output p_abuf1 ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_9 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 ( 
    Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:0] ff_D ;
input  [0:0] ff_DI ;
output [0:0] ff_Q ;
input  [0:0] ff_clk ;

sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , 
    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , 
    .Q ( ff_Q[0] ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 ( 
    Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:0] ff_D ;
input  [0:0] ff_DI ;
output [0:0] ff_Q ;
input  [0:0] ff_clk ;

sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , 
    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , 
    .Q ( ff_Q[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_26 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__32 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_const1_8 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_8 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , 
    ccff_head , ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:16] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__31 ( .A ( mem_out[16] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_frac_lut4_mux_2 ( in , sram , sram_inv , lut3_out , lut4_out ) ;
input  [0:15] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:1] lut3_out ;
output [0:0] lut4_out ;

wire [0:0] sky130_fd_sc_hd__buf_2_3_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_4_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_5_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
endmodule


module grid_clb_frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv , 
    lut3_out , lut4_out ) ;
input  [0:3] in ;
input  [0:15] sram ;
input  [0:15] sram_inv ;
input  [0:0] mode ;
input  [0:0] mode_inv ;
output [0:1] lut3_out ;
output [0:0] lut4_out ;

wire [0:0] sky130_fd_sc_hd__buf_2_0_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_1_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_2_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_3_X ;
wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;

sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , 
    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( 
    .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , 
    .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , 
    .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( 
    .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ;
grid_clb_frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) ,
    .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , 
        sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) ,
    .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , 
        sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , 
        sky130_fd_sc_hd__inv_1_3_Y[0] } ) ,
    .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 ( 
    prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , 
    frac_lut4_lut4_out , ccff_tail ) ;
input  [0:0] prog_clk ;
input  [0:3] frac_lut4_in ;
input  [0:0] ccff_head ;
output [0:1] frac_lut4_lut3_out ;
output [0:0] frac_lut4_lut4_out ;
output [0:0] ccff_tail ;

wire [0:15] frac_lut4_0__undriven_sram_inv ;
wire [0:0] frac_lut4_0_mode ;
wire [0:15] frac_lut4_0_sram ;

grid_clb_frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , 
    .sram ( frac_lut4_0_sram ) , 
    .sram_inv ( frac_lut4_0__undriven_sram_inv ) , 
    .mode ( frac_lut4_0_mode ) ,
    .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ;
grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( ccff_tail ) ,
    .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , 
        frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , 
        frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , 
        frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , 
        frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , 
        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( 
    prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ;
input  [0:0] prog_clk ;
input  [0:3] frac_logic_in ;
input  [0:0] ccff_head ;
output [0:1] frac_logic_out ;
output [0:0] ccff_tail ;
input  p0 ;

wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ;
wire [0:1] mux_tree_size2_0_sram ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( 
    .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , 
    .ccff_head ( ccff_head ) ,
    .frac_lut4_lut3_out ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , 
        frac_logic_out[1] } ) ,
    
    .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
grid_clb_mux_tree_size2_26 mux_frac_logic_out_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
         } ) ,
    .sram ( mux_tree_size2_0_sram ) , 
    .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , 
    .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ;
grid_clb_mux_tree_size2_mem_26 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( frac_logic_out[1] ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .out ( frac_logic_in[0] ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( frac_logic_in[1] ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( frac_logic_in[2] ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( frac_logic_in[3] ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( 
    prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , 
    fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , 
    ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 ) ;
input  [0:0] prog_clk ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:3] fabric_in ;
input  [0:0] fabric_regin ;
input  [0:0] fabric_sc_in ;
input  [0:0] fabric_clk ;
input  [0:0] ccff_head ;
output [0:1] fabric_out ;
output [0:0] fabric_regout ;
output [0:0] fabric_sc_out ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf1 ;
output p_abuf2 ;
input  p0 ;

wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
wire [0:1] mux_fabric_out_0_undriven_sram_inv ;
wire [0:1] mux_fabric_out_1_undriven_sram_inv ;
wire [0:1] mux_ff_0_D_0_undriven_sram_inv ;
wire [0:1] mux_tree_size2_0_sram ;
wire [0:1] mux_tree_size2_1_sram ;
wire [0:0] mux_tree_size2_2_out ;
wire [0:1] mux_tree_size2_2_sram ;
wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_size2_mem_1_ccff_tail ;

assign fabric_regout[0] = fabric_sc_out[0] ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( 
    .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , 
    .ccff_head ( ccff_head ) , 
    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
    .p0 ( p0 ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( 
    .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , 
    .ff_DI ( fabric_sc_in ) , 
    .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
    .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( 
    .Test_en ( Test_en ) , .clk ( clk ) , 
    .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , 
    .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
    .ff_Q ( fabric_sc_out ) ,
    .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ;
grid_clb_mux_tree_size2_6 mux_fabric_out_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
         } ) ,
    .sram ( mux_tree_size2_0_sram ) , 
    .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , 
    .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , 
    .p0 ( p0 ) ) ;
grid_clb_mux_tree_size2_7 mux_fabric_out_1 (
    .in ( { fabric_sc_out[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
         } ) ,
    .sram ( mux_tree_size2_1_sram ) , 
    .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , 
    .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ;
grid_clb_mux_tree_size2_8 mux_ff_0_D_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , 
        fabric_regin[0] } ) ,
    .sram ( mux_tree_size2_2_sram ) , 
    .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , 
    .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ;
grid_clb_mux_tree_size2_mem_6 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_size2_0_sram ) ) ;
grid_clb_mux_tree_size2_mem_7 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_size2_1_sram ) ) ;
grid_clb_mux_tree_size2_mem_8 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , 
    .mem_out ( mux_tree_size2_2_sram ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( fabric_sc_out ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( fabric_sc_out ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( fabric_in[0] ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_6 } ) ,
    .out ( fabric_in[1] ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_7 } ) ,
    .out ( fabric_in[2] ) ) ;
grid_clb_direct_interc direct_interc_5_ (
    .in ( { SYNOPSYS_UNCONNECTED_8 } ) ,
    .out ( fabric_in[3] ) ) ;
grid_clb_direct_interc direct_interc_6_ (
    .in ( { SYNOPSYS_UNCONNECTED_9 } ) ,
    .out ( fabric_sc_in ) ) ;
grid_clb_direct_interc direct_interc_7_ (
    .in ( { SYNOPSYS_UNCONNECTED_10 } ) ,
    .out ( fabric_clk ) ) ;
grid_clb_direct_interc direct_interc_8_ (
    .in ( { SYNOPSYS_UNCONNECTED_11 } ) ,
    
    .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ;
grid_clb_direct_interc direct_interc_9_ (
    .in ( { SYNOPSYS_UNCONNECTED_12 } ) ,
    
    .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ;
grid_clb_direct_interc direct_interc_10_ (
    .in ( { SYNOPSYS_UNCONNECTED_13 } ) ,
    .out ( fabric_clk ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , 
    clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , 
    fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 ) ;
input  [0:0] prog_clk ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:3] fle_in ;
input  [0:0] fle_regin ;
input  [0:0] fle_sc_in ;
input  [0:0] fle_clk ;
input  [0:0] ccff_head ;
output [0:1] fle_out ;
output [0:0] fle_regout ;
output [0:0] fle_sc_out ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf1 ;
output p_abuf2 ;
input  p0 ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( 
    .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , 
    .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , 
    .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , 
    .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , 
    .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , 
    .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , 
    .p_abuf2 ( p_abuf2 ) , .p0 ( p0 ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( { p_abuf1 } ) ) ;
grid_clb_direct_interc_0 direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( fle_regout ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( fle_sc_out ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_6 } ) ,
    .out ( fle_in[0] ) ) ;
grid_clb_direct_interc direct_interc_5_ (
    .in ( { SYNOPSYS_UNCONNECTED_7 } ) ,
    .out ( fle_in[1] ) ) ;
grid_clb_direct_interc direct_interc_6_ (
    .in ( { SYNOPSYS_UNCONNECTED_8 } ) ,
    .out ( fle_in[2] ) ) ;
grid_clb_direct_interc direct_interc_7_ (
    .in ( { SYNOPSYS_UNCONNECTED_9 } ) ,
    .out ( fle_in[3] ) ) ;
grid_clb_direct_interc direct_interc_8_ (
    .in ( { SYNOPSYS_UNCONNECTED_10 } ) ,
    .out ( fle_regin ) ) ;
grid_clb_direct_interc direct_interc_9_ (
    .in ( { SYNOPSYS_UNCONNECTED_11 } ) ,
    .out ( fle_sc_in ) ) ;
grid_clb_direct_interc direct_interc_10_ (
    .in ( { SYNOPSYS_UNCONNECTED_12 } ) ,
    .out ( fle_clk ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__30 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__29 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__28 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_const1_7 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_5 ( in , sram , sram_inv , out , p1 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p1 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_7 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module grid_clb_const1_6 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_4 ( in , sram , sram_inv , out , p_abuf0 , 
    p_abuf1 , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
output p_abuf0 ;
output p_abuf1 ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_6 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_72 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ;
endmodule


module grid_clb_const1_5 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_3 ( in , sram , sram_inv , out , p_abuf0 , 
    p_abuf1 , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
output p_abuf0 ;
output p_abuf1 ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_5 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_70 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 ( 
    Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:0] ff_D ;
input  [0:0] ff_DI ;
output [0:0] ff_Q ;
input  [0:0] ff_clk ;

sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , 
    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , 
    .Q ( ff_Q[0] ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 ( 
    Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:0] ff_D ;
input  [0:0] ff_DI ;
output [0:0] ff_Q ;
input  [0:0] ff_clk ;

sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , 
    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , 
    .Q ( ff_Q[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_25 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__27 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_const1_4 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_25 ( in , sram , sram_inv , out , p0 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p0 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_4 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , 
    ccff_head , ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:16] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__26 ( .A ( mem_out[16] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_frac_lut4_mux_1 ( in , sram , sram_inv , lut3_out , lut4_out ) ;
input  [0:15] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:1] lut3_out ;
output [0:0] lut4_out ;

wire [0:0] sky130_fd_sc_hd__buf_2_3_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_4_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_5_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
endmodule


module grid_clb_frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv , 
    lut3_out , lut4_out ) ;
input  [0:3] in ;
input  [0:15] sram ;
input  [0:15] sram_inv ;
input  [0:0] mode ;
input  [0:0] mode_inv ;
output [0:1] lut3_out ;
output [0:0] lut4_out ;

wire [0:0] sky130_fd_sc_hd__buf_2_0_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_1_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_2_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_3_X ;
wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;

sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , 
    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( 
    .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ;
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , 
    .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , 
    .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( 
    .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ;
grid_clb_frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) ,
    .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , 
        sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) ,
    .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , 
        sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , 
        sky130_fd_sc_hd__inv_1_3_Y[0] } ) ,
    .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 ( 
    prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , 
    frac_lut4_lut4_out , ccff_tail ) ;
input  [0:0] prog_clk ;
input  [0:3] frac_lut4_in ;
input  [0:0] ccff_head ;
output [0:1] frac_lut4_lut3_out ;
output [0:0] frac_lut4_lut4_out ;
output [0:0] ccff_tail ;

wire [0:15] frac_lut4_0__undriven_sram_inv ;
wire [0:0] frac_lut4_0_mode ;
wire [0:15] frac_lut4_0_sram ;

grid_clb_frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , 
    .sram ( frac_lut4_0_sram ) , 
    .sram_inv ( frac_lut4_0__undriven_sram_inv ) , 
    .mode ( frac_lut4_0_mode ) ,
    .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ;
grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( ccff_tail ) ,
    .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , 
        frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , 
        frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , 
        frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , 
        frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , 
        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( 
    prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ;
input  [0:0] prog_clk ;
input  [0:3] frac_logic_in ;
input  [0:0] ccff_head ;
output [0:1] frac_logic_out ;
output [0:0] ccff_tail ;
input  p0 ;

wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ;
wire [0:1] mux_tree_size2_0_sram ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( 
    .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , 
    .ccff_head ( ccff_head ) ,
    .frac_lut4_lut3_out ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , 
        frac_logic_out[1] } ) ,
    
    .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
grid_clb_mux_tree_size2_25 mux_frac_logic_out_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
         } ) ,
    .sram ( mux_tree_size2_0_sram ) , 
    .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , 
    .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ;
grid_clb_mux_tree_size2_mem_25 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( frac_logic_out[1] ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .out ( frac_logic_in[0] ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( frac_logic_in[1] ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( frac_logic_in[2] ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( frac_logic_in[3] ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( 
    prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , 
    fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , 
    ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p0 , p1 ) ;
input  [0:0] prog_clk ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:3] fabric_in ;
input  [0:0] fabric_regin ;
input  [0:0] fabric_sc_in ;
input  [0:0] fabric_clk ;
input  [0:0] ccff_head ;
output [0:1] fabric_out ;
output [0:0] fabric_regout ;
output [0:0] fabric_sc_out ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf1 ;
output p_abuf2 ;
output p_abuf3 ;
input  p0 ;
input  p1 ;

wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
wire [0:1] mux_fabric_out_0_undriven_sram_inv ;
wire [0:1] mux_fabric_out_1_undriven_sram_inv ;
wire [0:1] mux_ff_0_D_0_undriven_sram_inv ;
wire [0:1] mux_tree_size2_0_sram ;
wire [0:1] mux_tree_size2_1_sram ;
wire [0:0] mux_tree_size2_2_out ;
wire [0:1] mux_tree_size2_2_sram ;
wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_size2_mem_1_ccff_tail ;

assign fabric_regout[0] = fabric_sc_out[0] ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( 
    .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , 
    .ccff_head ( ccff_head ) , 
    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
    .p0 ( p0 ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( 
    .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , 
    .ff_DI ( fabric_sc_in ) , 
    .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
    .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( 
    .Test_en ( Test_en ) , .clk ( clk ) , 
    .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , 
    .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
    .ff_Q ( fabric_sc_out ) ,
    .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ;
grid_clb_mux_tree_size2_3 mux_fabric_out_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
         } ) ,
    .sram ( mux_tree_size2_0_sram ) , 
    .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , 
    .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , 
    .p0 ( p0 ) ) ;
grid_clb_mux_tree_size2_4 mux_fabric_out_1 (
    .in ( { fabric_sc_out[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
         } ) ,
    .sram ( mux_tree_size2_1_sram ) , 
    .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , 
    .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , 
    .p0 ( p0 ) ) ;
grid_clb_mux_tree_size2_5 mux_ff_0_D_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , 
        fabric_regin[0] } ) ,
    .sram ( mux_tree_size2_2_sram ) , 
    .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , 
    .out ( mux_tree_size2_2_out ) , .p1 ( p1 ) ) ;
grid_clb_mux_tree_size2_mem_3 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_size2_0_sram ) ) ;
grid_clb_mux_tree_size2_mem_4 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_size2_1_sram ) ) ;
grid_clb_mux_tree_size2_mem_5 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , 
    .mem_out ( mux_tree_size2_2_sram ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( fabric_sc_out ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( fabric_sc_out ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( fabric_in[0] ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_6 } ) ,
    .out ( fabric_in[1] ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_7 } ) ,
    .out ( fabric_in[2] ) ) ;
grid_clb_direct_interc direct_interc_5_ (
    .in ( { SYNOPSYS_UNCONNECTED_8 } ) ,
    .out ( fabric_in[3] ) ) ;
grid_clb_direct_interc direct_interc_6_ (
    .in ( { SYNOPSYS_UNCONNECTED_9 } ) ,
    .out ( fabric_sc_in ) ) ;
grid_clb_direct_interc direct_interc_7_ (
    .in ( { SYNOPSYS_UNCONNECTED_10 } ) ,
    .out ( fabric_clk ) ) ;
grid_clb_direct_interc direct_interc_8_ (
    .in ( { SYNOPSYS_UNCONNECTED_11 } ) ,
    
    .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ;
grid_clb_direct_interc direct_interc_9_ (
    .in ( { SYNOPSYS_UNCONNECTED_12 } ) ,
    
    .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ;
grid_clb_direct_interc direct_interc_10_ (
    .in ( { SYNOPSYS_UNCONNECTED_13 } ) ,
    .out ( fabric_clk ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en , 
    clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , 
    fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , 
    p_abuf3 , p0 , p1 ) ;
input  [0:0] prog_clk ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:3] fle_in ;
input  [0:0] fle_regin ;
input  [0:0] fle_sc_in ;
input  [0:0] fle_clk ;
input  [0:0] ccff_head ;
output [0:1] fle_out ;
output [0:0] fle_regout ;
output [0:0] fle_sc_out ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf1 ;
output p_abuf2 ;
output p_abuf3 ;
input  p0 ;
input  p1 ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( 
    .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , 
    .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , 
    .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , 
    .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , 
    .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , 
    .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , 
    .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( { p_abuf1 } ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .out ( { p_abuf3 } ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( fle_regout ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( fle_sc_out ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( fle_in[0] ) ) ;
grid_clb_direct_interc direct_interc_5_ (
    .in ( { SYNOPSYS_UNCONNECTED_6 } ) ,
    .out ( fle_in[1] ) ) ;
grid_clb_direct_interc direct_interc_6_ (
    .in ( { SYNOPSYS_UNCONNECTED_7 } ) ,
    .out ( fle_in[2] ) ) ;
grid_clb_direct_interc direct_interc_7_ (
    .in ( { SYNOPSYS_UNCONNECTED_8 } ) ,
    .out ( fle_in[3] ) ) ;
grid_clb_direct_interc direct_interc_8_ (
    .in ( { SYNOPSYS_UNCONNECTED_9 } ) ,
    .out ( fle_regin ) ) ;
grid_clb_direct_interc direct_interc_9_ (
    .in ( { SYNOPSYS_UNCONNECTED_10 } ) ,
    .out ( fle_sc_in ) ) ;
grid_clb_direct_interc direct_interc_10_ (
    .in ( { SYNOPSYS_UNCONNECTED_11 } ) ,
    .out ( fle_clk ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__25 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__24 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_mux_tree_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__23 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_const1_3 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_2 ( in , sram , sram_inv , out , p1 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p1 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_3 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module grid_clb_const1_2 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_1 ( in , sram , sram_inv , out , p_abuf0 , 
    p_abuf1 , p1 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
output p_abuf0 ;
output p_abuf1 ;
input  p1 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_2 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_68 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ;
endmodule


module grid_clb_const1_1 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , p_abuf0 , 
    p_abuf1 , p1 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
output p_abuf0 ;
output p_abuf1 ;
input  p1 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_1 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( .A ( p_abuf1 ) , 
    .X ( BUF_net_66 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_66 ) , 
    .X ( p_abuf0 ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( 
    Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:0] ff_D ;
input  [0:0] ff_DI ;
output [0:0] ff_Q ;
input  [0:0] ff_clk ;

sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , 
    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , 
    .Q ( ff_Q[0] ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( 
    Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:0] ff_D ;
input  [0:0] ff_DI ;
output [0:0] ff_Q ;
input  [0:0] ff_clk ;

sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , 
    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , 
    .Q ( ff_Q[0] ) ) ;
endmodule


module grid_clb_direct_interc ( in , out ) ;
input  [0:0] in ;
output [0:0] out ;

assign out[0] = in[0] ;
endmodule


module grid_clb_mux_tree_size2_mem_24 ( prog_clk , ccff_head , ccff_tail , 
    mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:1] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__22 ( .A ( mem_out[1] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_const1_0 ( const1 ) ;
output [0:0] const1 ;
endmodule


module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p1 ) ;
input  [0:1] in ;
input  [0:1] sram ;
input  [0:1] sram_inv ;
output [0:0] out ;
input  p1 ;

wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;

grid_clb_const1_0 const1_0_ (
    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ;
endmodule


module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , 
    ccff_head , ccff_tail , mem_out ) ;
input  [0:0] prog_clk ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:16] mem_out ;

sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ;
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , 
    .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__21 ( .A ( mem_out[16] ) , 
    .X ( ccff_tail[0] ) ) ;
endmodule


module grid_clb_frac_lut4_mux_0 ( in , sram , sram_inv , lut3_out , lut4_out ) ;
input  [0:15] in ;
input  [0:3] sram ;
input  [0:3] sram_inv ;
output [0:1] lut3_out ;
output [0:0] lut4_out ;

wire [0:0] sky130_fd_sc_hd__buf_2_3_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_4_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_5_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;

sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ;
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ;
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ ( 
    .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , 
    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
    .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , 
    .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , 
    .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ;
endmodule


module grid_clb_frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv , 
    lut3_out , lut4_out ) ;
input  [0:3] in ;
input  [0:15] sram ;
input  [0:15] sram_inv ;
input  [0:0] mode ;
input  [0:0] mode_inv ;
output [0:1] lut3_out ;
output [0:0] lut4_out ;

wire [0:0] sky130_fd_sc_hd__buf_2_0_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_1_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_2_X ;
wire [0:0] sky130_fd_sc_hd__buf_2_3_X ;
wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;

sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , 
    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( 
    .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ;
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , 
    .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ;
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , 
    .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( 
    .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
    .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ;
grid_clb_frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) ,
    .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , 
        sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) ,
    .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , 
        sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , 
        sky130_fd_sc_hd__inv_1_3_Y[0] } ) ,
    .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( 
    prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , 
    frac_lut4_lut4_out , ccff_tail ) ;
input  [0:0] prog_clk ;
input  [0:3] frac_lut4_in ;
input  [0:0] ccff_head ;
output [0:1] frac_lut4_lut3_out ;
output [0:0] frac_lut4_lut4_out ;
output [0:0] ccff_tail ;

wire [0:15] frac_lut4_0__undriven_sram_inv ;
wire [0:0] frac_lut4_0_mode ;
wire [0:15] frac_lut4_0_sram ;

grid_clb_frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , 
    .sram ( frac_lut4_0_sram ) , 
    .sram_inv ( frac_lut4_0__undriven_sram_inv ) , 
    .mode ( frac_lut4_0_mode ) ,
    .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ;
grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( 
    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
    .ccff_tail ( ccff_tail ) ,
    .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , 
        frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , 
        frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , 
        frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , 
        frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , 
        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( 
    prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p1 ) ;
input  [0:0] prog_clk ;
input  [0:3] frac_logic_in ;
input  [0:0] ccff_head ;
output [0:1] frac_logic_out ;
output [0:0] ccff_tail ;
input  p1 ;

wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ;
wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ;
wire [0:1] mux_tree_size2_0_sram ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( 
    .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , 
    .ccff_head ( ccff_head ) ,
    .frac_lut4_lut3_out ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , 
        frac_logic_out[1] } ) ,
    
    .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
         } ) ,
    .sram ( mux_tree_size2_0_sram ) , 
    .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , 
    .out ( frac_logic_out[0] ) , .p1 ( p1 ) ) ;
grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
    .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( frac_logic_out[1] ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .out ( frac_logic_in[0] ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( frac_logic_in[1] ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( frac_logic_in[2] ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( frac_logic_in[3] ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( 
    prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , 
    fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , 
    ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p1 ) ;
input  [0:0] prog_clk ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:3] fabric_in ;
input  [0:0] fabric_regin ;
input  [0:0] fabric_sc_in ;
input  [0:0] fabric_clk ;
input  [0:0] ccff_head ;
output [0:1] fabric_out ;
output [0:0] fabric_regout ;
output [0:0] fabric_sc_out ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf1 ;
output p_abuf2 ;
output p_abuf3 ;
input  p1 ;

wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
wire [0:1] mux_fabric_out_0_undriven_sram_inv ;
wire [0:1] mux_fabric_out_1_undriven_sram_inv ;
wire [0:1] mux_ff_0_D_0_undriven_sram_inv ;
wire [0:1] mux_tree_size2_0_sram ;
wire [0:1] mux_tree_size2_1_sram ;
wire [0:0] mux_tree_size2_2_out ;
wire [0:1] mux_tree_size2_2_sram ;
wire [0:0] mux_tree_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_size2_mem_1_ccff_tail ;

assign fabric_regout[0] = fabric_sc_out[0] ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( 
    .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , 
    .ccff_head ( ccff_head ) , 
    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
    .p1 ( p1 ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( 
    .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , 
    .ff_DI ( fabric_sc_in ) , 
    .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ,
    .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( 
    .Test_en ( Test_en ) , .clk ( clk ) , 
    .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , 
    .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
    .ff_Q ( fabric_sc_out ) ,
    .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ;
grid_clb_mux_tree_size2_0 mux_fabric_out_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
         } ) ,
    .sram ( mux_tree_size2_0_sram ) , 
    .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , 
    .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , 
    .p1 ( p1 ) ) ;
grid_clb_mux_tree_size2_1 mux_fabric_out_1 (
    .in ( { fabric_sc_out[0] , 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
         } ) ,
    .sram ( mux_tree_size2_1_sram ) , 
    .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , 
    .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , 
    .p1 ( p1 ) ) ;
grid_clb_mux_tree_size2_2 mux_ff_0_D_0 (
    .in ( { 
        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , 
        fabric_regin[0] } ) ,
    .sram ( mux_tree_size2_2_sram ) , 
    .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , 
    .out ( mux_tree_size2_2_out ) , .p1 ( p1 ) ) ;
grid_clb_mux_tree_size2_mem_0 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , 
    .mem_out ( mux_tree_size2_0_sram ) ) ;
grid_clb_mux_tree_size2_mem_1 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , 
    .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , 
    .mem_out ( mux_tree_size2_1_sram ) ) ;
grid_clb_mux_tree_size2_mem_2 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , 
    .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , 
    .mem_out ( mux_tree_size2_2_sram ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( fabric_sc_out ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( fabric_sc_out ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( fabric_in[0] ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_6 } ) ,
    .out ( fabric_in[1] ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_7 } ) ,
    .out ( fabric_in[2] ) ) ;
grid_clb_direct_interc direct_interc_5_ (
    .in ( { SYNOPSYS_UNCONNECTED_8 } ) ,
    .out ( fabric_in[3] ) ) ;
grid_clb_direct_interc direct_interc_6_ (
    .in ( { SYNOPSYS_UNCONNECTED_9 } ) ,
    .out ( fabric_sc_in ) ) ;
grid_clb_direct_interc direct_interc_7_ (
    .in ( { SYNOPSYS_UNCONNECTED_10 } ) ,
    .out ( fabric_clk ) ) ;
grid_clb_direct_interc direct_interc_8_ (
    .in ( { SYNOPSYS_UNCONNECTED_11 } ) ,
    
    .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ;
grid_clb_direct_interc direct_interc_9_ (
    .in ( { SYNOPSYS_UNCONNECTED_12 } ) ,
    
    .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ;
grid_clb_direct_interc direct_interc_10_ (
    .in ( { SYNOPSYS_UNCONNECTED_13 } ) ,
    .out ( fabric_clk ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en , 
    clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , 
    fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , 
    p_abuf3 , p1 ) ;
input  [0:0] prog_clk ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:3] fle_in ;
input  [0:0] fle_regin ;
input  [0:0] fle_sc_in ;
input  [0:0] fle_clk ;
input  [0:0] ccff_head ;
output [0:1] fle_out ;
output [0:0] fle_regout ;
output [0:0] fle_sc_out ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf1 ;
output p_abuf2 ;
output p_abuf3 ;
input  p1 ;

grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( 
    .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , 
    .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , 
    .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , 
    .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , 
    .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , 
    .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , 
    .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p1 ( p1 ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( { p_abuf1 } ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .out ( { p_abuf3 } ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( fle_regout ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( fle_sc_out ) ) ;
grid_clb_direct_interc direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( fle_in[0] ) ) ;
grid_clb_direct_interc direct_interc_5_ (
    .in ( { SYNOPSYS_UNCONNECTED_6 } ) ,
    .out ( fle_in[1] ) ) ;
grid_clb_direct_interc direct_interc_6_ (
    .in ( { SYNOPSYS_UNCONNECTED_7 } ) ,
    .out ( fle_in[2] ) ) ;
grid_clb_direct_interc direct_interc_7_ (
    .in ( { SYNOPSYS_UNCONNECTED_8 } ) ,
    .out ( fle_in[3] ) ) ;
grid_clb_direct_interc direct_interc_8_ (
    .in ( { SYNOPSYS_UNCONNECTED_9 } ) ,
    .out ( fle_regin ) ) ;
grid_clb_direct_interc direct_interc_9_ (
    .in ( { SYNOPSYS_UNCONNECTED_10 } ) ,
    .out ( fle_sc_in ) ) ;
grid_clb_direct_interc direct_interc_10_ (
    .in ( { SYNOPSYS_UNCONNECTED_11 } ) ,
    .out ( fle_clk ) ) ;
endmodule


module grid_clb_logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clk , 
    clb_I0 , clb_I0i , clb_I1 , clb_I1i , clb_I2 , clb_I2i , clb_I3 , 
    clb_I3i , clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , 
    clb_I7 , clb_I7i , clb_regin , clb_sc_in , clb_clk , ccff_head , clb_O , 
    clb_regout , clb_sc_out , ccff_tail , p_abuf0 , p_abuf3 , p_abuf5 , 
    p_abuf7 , p_abuf9 , p_abuf11 , p_abuf13 , p_abuf15 , p_abuf17 , p_abuf19 , 
    p_abuf21 , p_abuf23 , p_abuf25 , p_abuf27 , p_abuf29 , p_abuf31 , 
    p_abuf33 , p0 , p1 , p2 , p3 , p4 ) ;
input  [0:0] prog_clk ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:2] clb_I0 ;
input  [0:0] clb_I0i ;
input  [0:2] clb_I1 ;
input  [0:0] clb_I1i ;
input  [0:2] clb_I2 ;
input  [0:0] clb_I2i ;
input  [0:2] clb_I3 ;
input  [0:0] clb_I3i ;
input  [0:2] clb_I4 ;
input  [0:0] clb_I4i ;
input  [0:2] clb_I5 ;
input  [0:0] clb_I5i ;
input  [0:2] clb_I6 ;
input  [0:0] clb_I6i ;
input  [0:2] clb_I7 ;
input  [0:0] clb_I7i ;
input  [0:0] clb_regin ;
input  [0:0] clb_sc_in ;
input  [0:0] clb_clk ;
input  [0:0] ccff_head ;
output [0:15] clb_O ;
output [0:0] clb_regout ;
output [0:0] clb_sc_out ;
output [0:0] ccff_tail ;
output p_abuf0 ;
output p_abuf3 ;
output p_abuf5 ;
output p_abuf7 ;
output p_abuf9 ;
output p_abuf11 ;
output p_abuf13 ;
output p_abuf15 ;
output p_abuf17 ;
output p_abuf19 ;
output p_abuf21 ;
output p_abuf23 ;
output p_abuf25 ;
output p_abuf27 ;
output p_abuf29 ;
output p_abuf31 ;
output p_abuf33 ;
input  p0 ;
input  p1 ;
input  p2 ;
input  p3 ;
input  p4 ;

wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ;
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout ;
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out ;
wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ;
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_regout ;
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out ;
wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail ;
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout ;
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out ;
wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail ;
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout ;
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out ;
wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail ;
wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout ;
wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out ;
wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail ;
wire [0:0] logical_tile_clb_mode_default__fle_5_fle_regout ;
wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out ;
wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail ;
wire [0:0] logical_tile_clb_mode_default__fle_6_fle_regout ;
wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ;

grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( 
    .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) ,
    .fle_in ( { clb_I0[0] , clb_I0[1] , clb_I0[2] , clb_I0i[0] } ) ,
    .fle_regin ( clb_regin ) , .fle_sc_in ( clb_sc_in ) , 
    .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) ,
    .fle_out ( { clb_O[1] , clb_O[0] } ) ,
    .fle_regout ( logical_tile_clb_mode_default__fle_0_fle_regout ) , 
    .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , 
    .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , .p_abuf2 ( p_abuf5 ) , 
    .p_abuf3 ( p_abuf6 ) , .p1 ( p2 ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( 
    .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) ,
    .fle_in ( { clb_I1[0] , clb_I1[1] , clb_I1[2] , clb_I1i[0] } ) ,
    .fle_regin ( logical_tile_clb_mode_default__fle_0_fle_regout ) , 
    .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , 
    .fle_clk ( clb_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) ,
    .fle_out ( { clb_O[3] , clb_O[2] } ) ,
    .fle_regout ( logical_tile_clb_mode_default__fle_1_fle_regout ) , 
    .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , 
    .p_abuf0 ( p_abuf7 ) , .p_abuf1 ( p_abuf8 ) , .p_abuf2 ( p_abuf9 ) , 
    .p_abuf3 ( p_abuf10 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( 
    .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) ,
    .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2[2] , clb_I2i[0] } ) ,
    .fle_regin ( logical_tile_clb_mode_default__fle_1_fle_regout ) , 
    .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , 
    .fle_clk ( clb_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) ,
    .fle_out ( { clb_O[5] , clb_O[4] } ) ,
    .fle_regout ( logical_tile_clb_mode_default__fle_2_fle_regout ) , 
    .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , 
    .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p_abuf2 ( p_abuf13 ) , 
    .p0 ( p0 ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( 
    .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) ,
    .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3[2] , clb_I3i[0] } ) ,
    .fle_regin ( logical_tile_clb_mode_default__fle_2_fle_regout ) , 
    .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , 
    .fle_clk ( clb_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) ,
    .fle_out ( { clb_O[7] , clb_O[6] } ) ,
    .fle_regout ( logical_tile_clb_mode_default__fle_3_fle_regout ) , 
    .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , 
    .p_abuf0 ( p_abuf15 ) , .p_abuf2 ( p_abuf17 ) , .p_abuf3 ( p_abuf18 ) , 
    .p2 ( p3 ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( 
    .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) ,
    .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4[2] , clb_I4i[0] } ) ,
    .fle_regin ( logical_tile_clb_mode_default__fle_3_fle_regout ) , 
    .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , 
    .fle_clk ( clb_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) ,
    .fle_out ( { clb_O[9] , clb_O[8] } ) ,
    .fle_regout ( logical_tile_clb_mode_default__fle_4_fle_regout ) , 
    .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , 
    .p_abuf0 ( p_abuf19 ) , .p_abuf2 ( p_abuf21 ) , .p2 ( p3 ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( 
    .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) ,
    .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5[2] , clb_I5i[0] } ) ,
    .fle_regin ( logical_tile_clb_mode_default__fle_4_fle_regout ) , 
    .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , 
    .fle_clk ( clb_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) ,
    .fle_out ( { clb_O[11] , clb_O[10] } ) ,
    .fle_regout ( logical_tile_clb_mode_default__fle_5_fle_regout ) , 
    .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , 
    .p_abuf0 ( p_abuf23 ) , .p_abuf1 ( p_abuf24 ) , .p_abuf2 ( p_abuf25 ) , 
    .p_abuf3 ( p_abuf26 ) , .p3 ( p4 ) ) ;
grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( 
    .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) ,
    .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6[2] , clb_I6i[0] } ) ,
    .fle_regin ( logical_tile_clb_mode_default__fle_5_fle_regout ) , 
    .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , 
    .fle_clk ( clb_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) ,
    .fle_out ( { clb_O[13] , clb_O[12] } ) ,
    .fle_regout ( logical_tile_clb_mode_default__fle_6_fle_regout ) , 
    .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , 
    .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , 
    .p_abuf0 ( p_abuf27 ) , .p_abuf2 ( p_abuf29 ) , .p0 ( p1 ) , .p3 ( p4 ) ) ;
grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( 
    .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) ,
    .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7[2] , clb_I7i[0] } ) ,
    .fle_regin ( logical_tile_clb_mode_default__fle_6_fle_regout ) , 
    .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , 
    .fle_clk ( clb_clk ) , 
    .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) ,
    .fle_out ( { clb_O[15] , clb_O[14] } ) ,
    .fle_regout ( clb_regout ) , .fle_sc_out ( clb_sc_out ) , 
    .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , 
    .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf31 ) , .p_abuf4 ( p_abuf32 ) , 
    .p_abuf5 ( p_abuf33 ) , .p0 ( p1 ) ) ;
grid_clb_direct_interc direct_interc_0_ (
    .in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .out ( { p_abuf6 } ) ) ;
grid_clb_direct_interc direct_interc_1_ (
    .in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .out ( { p_abuf4 } ) ) ;
grid_clb_direct_interc direct_interc_2_ (
    .in ( { SYNOPSYS_UNCONNECTED_3 } ) ,
    .out ( { p_abuf10 } ) ) ;
grid_clb_direct_interc direct_interc_3_ (
    .in ( { SYNOPSYS_UNCONNECTED_4 } ) ,
    .out ( { p_abuf8 } ) ) ;
grid_clb_direct_interc_7 direct_interc_4_ (
    .in ( { SYNOPSYS_UNCONNECTED_5 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_6 } ) ) ;
grid_clb_direct_interc direct_interc_5_ (
    .in ( { SYNOPSYS_UNCONNECTED_7 } ) ,
    .out ( { p_abuf12 } ) ) ;
grid_clb_direct_interc direct_interc_6_ (
    .in ( { SYNOPSYS_UNCONNECTED_8 } ) ,
    .out ( { p_abuf18 } ) ) ;
grid_clb_direct_interc_8 direct_interc_7_ (
    .in ( { SYNOPSYS_UNCONNECTED_9 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_10 } ) ) ;
grid_clb_direct_interc_9 direct_interc_8_ (
    .in ( { SYNOPSYS_UNCONNECTED_11 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_12 } ) ) ;
grid_clb_direct_interc_10 direct_interc_9_ (
    .in ( { SYNOPSYS_UNCONNECTED_13 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_14 } ) ) ;
grid_clb_direct_interc direct_interc_10_ (
    .in ( { SYNOPSYS_UNCONNECTED_15 } ) ,
    .out ( { p_abuf26 } ) ) ;
grid_clb_direct_interc direct_interc_11_ (
    .in ( { SYNOPSYS_UNCONNECTED_16 } ) ,
    .out ( { p_abuf24 } ) ) ;
grid_clb_direct_interc_11 direct_interc_12_ (
    .in ( { SYNOPSYS_UNCONNECTED_17 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_18 } ) ) ;
grid_clb_direct_interc_12 direct_interc_13_ (
    .in ( { SYNOPSYS_UNCONNECTED_19 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_20 } ) ) ;
grid_clb_direct_interc_13 direct_interc_14_ (
    .in ( { SYNOPSYS_UNCONNECTED_21 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_22 } ) ) ;
grid_clb_direct_interc direct_interc_15_ (
    .in ( { SYNOPSYS_UNCONNECTED_23 } ) ,
    .out ( { p_abuf32 } ) ) ;
grid_clb_direct_interc direct_interc_16_ (
    .in ( { SYNOPSYS_UNCONNECTED_24 } ) ,
    .out ( { p_abuf1 } ) ) ;
grid_clb_direct_interc direct_interc_17_ (
    .in ( { SYNOPSYS_UNCONNECTED_25 } ) ,
    .out ( { p_abuf2 } ) ) ;
grid_clb_direct_interc direct_interc_18_ (
    .in ( { SYNOPSYS_UNCONNECTED_26 } ) ,
    .out ( clb_I0[0] ) ) ;
grid_clb_direct_interc direct_interc_19_ (
    .in ( { SYNOPSYS_UNCONNECTED_27 } ) ,
    .out ( clb_I0[1] ) ) ;
grid_clb_direct_interc direct_interc_20_ (
    .in ( { SYNOPSYS_UNCONNECTED_28 } ) ,
    .out ( clb_I0[2] ) ) ;
grid_clb_direct_interc direct_interc_21_ (
    .in ( { SYNOPSYS_UNCONNECTED_29 } ) ,
    .out ( clb_I0i ) ) ;
grid_clb_direct_interc direct_interc_22_ (
    .in ( { SYNOPSYS_UNCONNECTED_30 } ) ,
    .out ( clb_regin ) ) ;
grid_clb_direct_interc direct_interc_23_ (
    .in ( { SYNOPSYS_UNCONNECTED_31 } ) ,
    .out ( clb_sc_in ) ) ;
grid_clb_direct_interc direct_interc_24_ (
    .in ( { SYNOPSYS_UNCONNECTED_32 } ) ,
    .out ( clb_clk ) ) ;
grid_clb_direct_interc direct_interc_25_ (
    .in ( { SYNOPSYS_UNCONNECTED_33 } ) ,
    .out ( clb_I1[0] ) ) ;
grid_clb_direct_interc direct_interc_26_ (
    .in ( { SYNOPSYS_UNCONNECTED_34 } ) ,
    .out ( clb_I1[1] ) ) ;
grid_clb_direct_interc direct_interc_27_ (
    .in ( { SYNOPSYS_UNCONNECTED_35 } ) ,
    .out ( clb_I1[2] ) ) ;
grid_clb_direct_interc direct_interc_28_ (
    .in ( { SYNOPSYS_UNCONNECTED_36 } ) ,
    .out ( clb_I1i ) ) ;
grid_clb_direct_interc direct_interc_29_ (
    .in ( { SYNOPSYS_UNCONNECTED_37 } ) ,
    .out ( logical_tile_clb_mode_default__fle_0_fle_regout ) ) ;
grid_clb_direct_interc direct_interc_30_ (
    .in ( { SYNOPSYS_UNCONNECTED_38 } ) ,
    .out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ) ;
grid_clb_direct_interc direct_interc_31_ (
    .in ( { SYNOPSYS_UNCONNECTED_39 } ) ,
    .out ( clb_clk ) ) ;
grid_clb_direct_interc direct_interc_32_ (
    .in ( { SYNOPSYS_UNCONNECTED_40 } ) ,
    .out ( clb_I2[0] ) ) ;
grid_clb_direct_interc direct_interc_33_ (
    .in ( { SYNOPSYS_UNCONNECTED_41 } ) ,
    .out ( clb_I2[1] ) ) ;
grid_clb_direct_interc direct_interc_34_ (
    .in ( { SYNOPSYS_UNCONNECTED_42 } ) ,
    .out ( clb_I2[2] ) ) ;
grid_clb_direct_interc direct_interc_35_ (
    .in ( { SYNOPSYS_UNCONNECTED_43 } ) ,
    .out ( clb_I2i ) ) ;
grid_clb_direct_interc direct_interc_36_ (
    .in ( { SYNOPSYS_UNCONNECTED_44 } ) ,
    .out ( logical_tile_clb_mode_default__fle_1_fle_regout ) ) ;
grid_clb_direct_interc direct_interc_37_ (
    .in ( { SYNOPSYS_UNCONNECTED_45 } ) ,
    .out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ) ;
grid_clb_direct_interc direct_interc_38_ (
    .in ( { SYNOPSYS_UNCONNECTED_46 } ) ,
    .out ( clb_clk ) ) ;
grid_clb_direct_interc direct_interc_39_ (
    .in ( { SYNOPSYS_UNCONNECTED_47 } ) ,
    .out ( clb_I3[0] ) ) ;
grid_clb_direct_interc direct_interc_40_ (
    .in ( { SYNOPSYS_UNCONNECTED_48 } ) ,
    .out ( clb_I3[1] ) ) ;
grid_clb_direct_interc direct_interc_41_ (
    .in ( { SYNOPSYS_UNCONNECTED_49 } ) ,
    .out ( clb_I3[2] ) ) ;
grid_clb_direct_interc direct_interc_42_ (
    .in ( { SYNOPSYS_UNCONNECTED_50 } ) ,
    .out ( clb_I3i ) ) ;
grid_clb_direct_interc direct_interc_43_ (
    .in ( { SYNOPSYS_UNCONNECTED_51 } ) ,
    .out ( logical_tile_clb_mode_default__fle_2_fle_regout ) ) ;
grid_clb_direct_interc direct_interc_44_ (
    .in ( { SYNOPSYS_UNCONNECTED_52 } ) ,
    .out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ) ;
grid_clb_direct_interc direct_interc_45_ (
    .in ( { SYNOPSYS_UNCONNECTED_53 } ) ,
    .out ( clb_clk ) ) ;
grid_clb_direct_interc direct_interc_46_ (
    .in ( { SYNOPSYS_UNCONNECTED_54 } ) ,
    .out ( clb_I4[0] ) ) ;
grid_clb_direct_interc direct_interc_47_ (
    .in ( { SYNOPSYS_UNCONNECTED_55 } ) ,
    .out ( clb_I4[1] ) ) ;
grid_clb_direct_interc direct_interc_48_ (
    .in ( { SYNOPSYS_UNCONNECTED_56 } ) ,
    .out ( clb_I4[2] ) ) ;
grid_clb_direct_interc direct_interc_49_ (
    .in ( { SYNOPSYS_UNCONNECTED_57 } ) ,
    .out ( clb_I4i ) ) ;
grid_clb_direct_interc direct_interc_50_ (
    .in ( { SYNOPSYS_UNCONNECTED_58 } ) ,
    .out ( logical_tile_clb_mode_default__fle_3_fle_regout ) ) ;
grid_clb_direct_interc direct_interc_51_ (
    .in ( { SYNOPSYS_UNCONNECTED_59 } ) ,
    .out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ) ;
grid_clb_direct_interc direct_interc_52_ (
    .in ( { SYNOPSYS_UNCONNECTED_60 } ) ,
    .out ( clb_clk ) ) ;
grid_clb_direct_interc direct_interc_53_ (
    .in ( { SYNOPSYS_UNCONNECTED_61 } ) ,
    .out ( clb_I5[0] ) ) ;
grid_clb_direct_interc direct_interc_54_ (
    .in ( { SYNOPSYS_UNCONNECTED_62 } ) ,
    .out ( clb_I5[1] ) ) ;
grid_clb_direct_interc direct_interc_55_ (
    .in ( { SYNOPSYS_UNCONNECTED_63 } ) ,
    .out ( clb_I5[2] ) ) ;
grid_clb_direct_interc direct_interc_56_ (
    .in ( { SYNOPSYS_UNCONNECTED_64 } ) ,
    .out ( clb_I5i ) ) ;
grid_clb_direct_interc direct_interc_57_ (
    .in ( { SYNOPSYS_UNCONNECTED_65 } ) ,
    .out ( logical_tile_clb_mode_default__fle_4_fle_regout ) ) ;
grid_clb_direct_interc direct_interc_58_ (
    .in ( { SYNOPSYS_UNCONNECTED_66 } ) ,
    .out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ) ;
grid_clb_direct_interc direct_interc_59_ (
    .in ( { SYNOPSYS_UNCONNECTED_67 } ) ,
    .out ( clb_clk ) ) ;
grid_clb_direct_interc direct_interc_60_ (
    .in ( { SYNOPSYS_UNCONNECTED_68 } ) ,
    .out ( clb_I6[0] ) ) ;
grid_clb_direct_interc direct_interc_61_ (
    .in ( { SYNOPSYS_UNCONNECTED_69 } ) ,
    .out ( clb_I6[1] ) ) ;
grid_clb_direct_interc direct_interc_62_ (
    .in ( { SYNOPSYS_UNCONNECTED_70 } ) ,
    .out ( clb_I6[2] ) ) ;
grid_clb_direct_interc direct_interc_63_ (
    .in ( { SYNOPSYS_UNCONNECTED_71 } ) ,
    .out ( clb_I6i ) ) ;
grid_clb_direct_interc direct_interc_64_ (
    .in ( { SYNOPSYS_UNCONNECTED_72 } ) ,
    .out ( logical_tile_clb_mode_default__fle_5_fle_regout ) ) ;
grid_clb_direct_interc direct_interc_65_ (
    .in ( { SYNOPSYS_UNCONNECTED_73 } ) ,
    .out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ) ;
grid_clb_direct_interc direct_interc_66_ (
    .in ( { SYNOPSYS_UNCONNECTED_74 } ) ,
    .out ( clb_clk ) ) ;
grid_clb_direct_interc direct_interc_67_ (
    .in ( { SYNOPSYS_UNCONNECTED_75 } ) ,
    .out ( clb_I7[0] ) ) ;
grid_clb_direct_interc direct_interc_68_ (
    .in ( { SYNOPSYS_UNCONNECTED_76 } ) ,
    .out ( clb_I7[1] ) ) ;
grid_clb_direct_interc direct_interc_69_ (
    .in ( { SYNOPSYS_UNCONNECTED_77 } ) ,
    .out ( clb_I7[2] ) ) ;
grid_clb_direct_interc direct_interc_70_ (
    .in ( { SYNOPSYS_UNCONNECTED_78 } ) ,
    .out ( clb_I7i ) ) ;
grid_clb_direct_interc direct_interc_71_ (
    .in ( { SYNOPSYS_UNCONNECTED_79 } ) ,
    .out ( logical_tile_clb_mode_default__fle_6_fle_regout ) ) ;
grid_clb_direct_interc direct_interc_72_ (
    .in ( { SYNOPSYS_UNCONNECTED_80 } ) ,
    .out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ) ;
grid_clb_direct_interc direct_interc_73_ (
    .in ( { SYNOPSYS_UNCONNECTED_81 } ) ,
    .out ( clb_clk ) ) ;
endmodule


module grid_clb ( prog_clk , Test_en , clk , top_width_0_height_0__pin_0_ , 
    top_width_0_height_0__pin_1_ , top_width_0_height_0__pin_2_ , 
    top_width_0_height_0__pin_3_ , top_width_0_height_0__pin_4_ , 
    top_width_0_height_0__pin_5_ , top_width_0_height_0__pin_6_ , 
    top_width_0_height_0__pin_7_ , top_width_0_height_0__pin_8_ , 
    top_width_0_height_0__pin_9_ , top_width_0_height_0__pin_10_ , 
    top_width_0_height_0__pin_11_ , top_width_0_height_0__pin_12_ , 
    top_width_0_height_0__pin_13_ , top_width_0_height_0__pin_14_ , 
    top_width_0_height_0__pin_15_ , top_width_0_height_0__pin_32_ , 
    top_width_0_height_0__pin_33_ , right_width_0_height_0__pin_16_ , 
    right_width_0_height_0__pin_17_ , right_width_0_height_0__pin_18_ , 
    right_width_0_height_0__pin_19_ , right_width_0_height_0__pin_20_ , 
    right_width_0_height_0__pin_21_ , right_width_0_height_0__pin_22_ , 
    right_width_0_height_0__pin_23_ , right_width_0_height_0__pin_24_ , 
    right_width_0_height_0__pin_25_ , right_width_0_height_0__pin_26_ , 
    right_width_0_height_0__pin_27_ , right_width_0_height_0__pin_28_ , 
    right_width_0_height_0__pin_29_ , right_width_0_height_0__pin_30_ , 
    right_width_0_height_0__pin_31_ , left_width_0_height_0__pin_52_ , 
    ccff_head , top_width_0_height_0__pin_34_upper , 
    top_width_0_height_0__pin_34_lower , top_width_0_height_0__pin_35_upper , 
    top_width_0_height_0__pin_35_lower , top_width_0_height_0__pin_36_upper , 
    top_width_0_height_0__pin_36_lower , top_width_0_height_0__pin_37_upper , 
    top_width_0_height_0__pin_37_lower , top_width_0_height_0__pin_38_upper , 
    top_width_0_height_0__pin_38_lower , top_width_0_height_0__pin_39_upper , 
    top_width_0_height_0__pin_39_lower , top_width_0_height_0__pin_40_upper , 
    top_width_0_height_0__pin_40_lower , top_width_0_height_0__pin_41_upper , 
    top_width_0_height_0__pin_41_lower , 
    right_width_0_height_0__pin_42_upper , 
    right_width_0_height_0__pin_42_lower , 
    right_width_0_height_0__pin_43_upper , 
    right_width_0_height_0__pin_43_lower , 
    right_width_0_height_0__pin_44_upper , 
    right_width_0_height_0__pin_44_lower , 
    right_width_0_height_0__pin_45_upper , 
    right_width_0_height_0__pin_45_lower , 
    right_width_0_height_0__pin_46_upper , 
    right_width_0_height_0__pin_46_lower , 
    right_width_0_height_0__pin_47_upper , 
    right_width_0_height_0__pin_47_lower , 
    right_width_0_height_0__pin_48_upper , 
    right_width_0_height_0__pin_48_lower , 
    right_width_0_height_0__pin_49_upper , 
    right_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ , 
    bottom_width_0_height_0__pin_51_ , ccff_tail , SC_IN_TOP , SC_IN_BOT , 
    SC_OUT_TOP , SC_OUT_BOT , Test_en__FEEDTHRU_1 , clk__FEEDTHRU_1 , 
    grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , 
    grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 , 
    grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 , 
    scff_Wires__FEEDTHRU_0 , scff_Wires__FEEDTHRU_1 ) ;
input  [0:0] prog_clk ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:0] top_width_0_height_0__pin_0_ ;
input  [0:0] top_width_0_height_0__pin_1_ ;
input  [0:0] top_width_0_height_0__pin_2_ ;
input  [0:0] top_width_0_height_0__pin_3_ ;
input  [0:0] top_width_0_height_0__pin_4_ ;
input  [0:0] top_width_0_height_0__pin_5_ ;
input  [0:0] top_width_0_height_0__pin_6_ ;
input  [0:0] top_width_0_height_0__pin_7_ ;
input  [0:0] top_width_0_height_0__pin_8_ ;
input  [0:0] top_width_0_height_0__pin_9_ ;
input  [0:0] top_width_0_height_0__pin_10_ ;
input  [0:0] top_width_0_height_0__pin_11_ ;
input  [0:0] top_width_0_height_0__pin_12_ ;
input  [0:0] top_width_0_height_0__pin_13_ ;
input  [0:0] top_width_0_height_0__pin_14_ ;
input  [0:0] top_width_0_height_0__pin_15_ ;
input  [0:0] top_width_0_height_0__pin_32_ ;
input  [0:0] top_width_0_height_0__pin_33_ ;
input  [0:0] right_width_0_height_0__pin_16_ ;
input  [0:0] right_width_0_height_0__pin_17_ ;
input  [0:0] right_width_0_height_0__pin_18_ ;
input  [0:0] right_width_0_height_0__pin_19_ ;
input  [0:0] right_width_0_height_0__pin_20_ ;
input  [0:0] right_width_0_height_0__pin_21_ ;
input  [0:0] right_width_0_height_0__pin_22_ ;
input  [0:0] right_width_0_height_0__pin_23_ ;
input  [0:0] right_width_0_height_0__pin_24_ ;
input  [0:0] right_width_0_height_0__pin_25_ ;
input  [0:0] right_width_0_height_0__pin_26_ ;
input  [0:0] right_width_0_height_0__pin_27_ ;
input  [0:0] right_width_0_height_0__pin_28_ ;
input  [0:0] right_width_0_height_0__pin_29_ ;
input  [0:0] right_width_0_height_0__pin_30_ ;
input  [0:0] right_width_0_height_0__pin_31_ ;
input  [0:0] left_width_0_height_0__pin_52_ ;
input  [0:0] ccff_head ;
output [0:0] top_width_0_height_0__pin_34_upper ;
output [0:0] top_width_0_height_0__pin_34_lower ;
output [0:0] top_width_0_height_0__pin_35_upper ;
output [0:0] top_width_0_height_0__pin_35_lower ;
output [0:0] top_width_0_height_0__pin_36_upper ;
output [0:0] top_width_0_height_0__pin_36_lower ;
output [0:0] top_width_0_height_0__pin_37_upper ;
output [0:0] top_width_0_height_0__pin_37_lower ;
output [0:0] top_width_0_height_0__pin_38_upper ;
output [0:0] top_width_0_height_0__pin_38_lower ;
output [0:0] top_width_0_height_0__pin_39_upper ;
output [0:0] top_width_0_height_0__pin_39_lower ;
output [0:0] top_width_0_height_0__pin_40_upper ;
output [0:0] top_width_0_height_0__pin_40_lower ;
output [0:0] top_width_0_height_0__pin_41_upper ;
output [0:0] top_width_0_height_0__pin_41_lower ;
output [0:0] right_width_0_height_0__pin_42_upper ;
output [0:0] right_width_0_height_0__pin_42_lower ;
output [0:0] right_width_0_height_0__pin_43_upper ;
output [0:0] right_width_0_height_0__pin_43_lower ;
output [0:0] right_width_0_height_0__pin_44_upper ;
output [0:0] right_width_0_height_0__pin_44_lower ;
output [0:0] right_width_0_height_0__pin_45_upper ;
output [0:0] right_width_0_height_0__pin_45_lower ;
output [0:0] right_width_0_height_0__pin_46_upper ;
output [0:0] right_width_0_height_0__pin_46_lower ;
output [0:0] right_width_0_height_0__pin_47_upper ;
output [0:0] right_width_0_height_0__pin_47_lower ;
output [0:0] right_width_0_height_0__pin_48_upper ;
output [0:0] right_width_0_height_0__pin_48_lower ;
output [0:0] right_width_0_height_0__pin_49_upper ;
output [0:0] right_width_0_height_0__pin_49_lower ;
output [0:0] bottom_width_0_height_0__pin_50_ ;
output [0:0] bottom_width_0_height_0__pin_51_ ;
output [0:0] ccff_tail ;
input  SC_IN_TOP ;
input  SC_IN_BOT ;
output SC_OUT_TOP ;
output SC_OUT_BOT ;
output [0:0] Test_en__FEEDTHRU_1 ;
output [0:0] clk__FEEDTHRU_1 ;
input  [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ;
output [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ;
output [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ;
input  [27:27] scff_Wires__FEEDTHRU_0 ;
output [27:27] scff_Wires__FEEDTHRU_1 ;

wire ropt_net_146 ;
wire ropt_net_145 ;
wire ropt_net_141 ;
wire ropt_net_147 ;
wire ropt_net_142 ;
wire ropt_net_144 ;
wire ropt_net_139 ;
wire ropt_net_149 ;
wire ropt_net_154 ;

assign SC_IN_TOP = SC_IN_BOT ;

grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( 
    .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) ,
    .clb_I0 ( { top_width_0_height_0__pin_0_[0] , 
        top_width_0_height_0__pin_1_[0] , top_width_0_height_0__pin_2_[0] } ) ,
    .clb_I0i ( top_width_0_height_0__pin_3_ ) ,
    .clb_I1 ( { top_width_0_height_0__pin_4_[0] , 
        top_width_0_height_0__pin_5_[0] , top_width_0_height_0__pin_6_[0] } ) ,
    .clb_I1i ( top_width_0_height_0__pin_7_ ) ,
    .clb_I2 ( { top_width_0_height_0__pin_8_[0] , 
        top_width_0_height_0__pin_9_[0] , top_width_0_height_0__pin_10_[0] } ) ,
    .clb_I2i ( top_width_0_height_0__pin_11_ ) ,
    .clb_I3 ( { top_width_0_height_0__pin_12_[0] , 
        top_width_0_height_0__pin_13_[0] , top_width_0_height_0__pin_14_[0] } ) ,
    .clb_I3i ( top_width_0_height_0__pin_15_ ) ,
    .clb_I4 ( { right_width_0_height_0__pin_16_[0] , 
        right_width_0_height_0__pin_17_[0] , 
        right_width_0_height_0__pin_18_[0] } ) ,
    .clb_I4i ( right_width_0_height_0__pin_19_ ) ,
    .clb_I5 ( { right_width_0_height_0__pin_20_[0] , 
        right_width_0_height_0__pin_21_[0] , 
        right_width_0_height_0__pin_22_[0] } ) ,
    .clb_I5i ( right_width_0_height_0__pin_23_ ) ,
    .clb_I6 ( { right_width_0_height_0__pin_24_[0] , 
        right_width_0_height_0__pin_25_[0] , 
        right_width_0_height_0__pin_26_[0] } ) ,
    .clb_I6i ( right_width_0_height_0__pin_27_ ) ,
    .clb_I7 ( { right_width_0_height_0__pin_28_[0] , 
        right_width_0_height_0__pin_29_[0] , 
        right_width_0_height_0__pin_30_[0] } ) ,
    .clb_I7i ( right_width_0_height_0__pin_31_ ) , 
    .clb_regin ( top_width_0_height_0__pin_32_ ) ,
    .clb_sc_in ( { SC_IN_BOT } ) ,
    .clb_clk ( left_width_0_height_0__pin_52_ ) , .ccff_head ( ccff_head ) ,
    .clb_O ( { aps_rename_137_ , aps_rename_138_ , aps_rename_139_ , 
        aps_rename_141_ , aps_rename_143_ , aps_rename_144_ , 
        aps_rename_146_ , top_width_0_height_0__pin_41_lower[0] , 
        aps_rename_149_ , aps_rename_151_ , aps_rename_153_ , 
        aps_rename_154_ , right_width_0_height_0__pin_46_lower[0] , 
        right_width_0_height_0__pin_47_lower[0] , 
        right_width_0_height_0__pin_48_lower[0] , aps_rename_158_ } ) ,
    .clb_regout ( { ropt_net_155 } ) ,
    .clb_sc_out ( { aps_rename_159_ } ) ,
    .ccff_tail ( { ropt_net_150 } ) ,
    .p_abuf0 ( ropt_net_154 ) , 
    .p_abuf3 ( top_width_0_height_0__pin_35_upper[0] ) , 
    .p_abuf5 ( top_width_0_height_0__pin_34_upper[0] ) , 
    .p_abuf7 ( ropt_net_145 ) , .p_abuf9 ( ropt_net_146 ) , 
    .p_abuf11 ( ropt_net_147 ) , .p_abuf13 ( ropt_net_141 ) , 
    .p_abuf15 ( top_width_0_height_0__pin_41_upper[0] ) , 
    .p_abuf17 ( top_width_0_height_0__pin_40_upper[0] ) , 
    .p_abuf19 ( ropt_net_144 ) , .p_abuf21 ( ropt_net_142 ) , 
    .p_abuf23 ( ropt_net_149 ) , .p_abuf25 ( ropt_net_139 ) , 
    .p_abuf27 ( right_width_0_height_0__pin_47_upper[0] ) , 
    .p_abuf29 ( right_width_0_height_0__pin_46_upper[0] ) , 
    .p_abuf31 ( right_width_0_height_0__pin_49_upper[0] ) , 
    .p_abuf33 ( right_width_0_height_0__pin_48_upper[0] ) , 
    .p0 ( optlc_net_133 ) , .p1 ( optlc_net_134 ) , .p2 ( optlc_net_135 ) , 
    .p3 ( optlc_net_136 ) , .p4 ( optlc_net_137 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( Test_en[0] ) , 
    .X ( Test_en__FEEDTHRU_1[0] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , 
    .HI ( optlc_net_133 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , 
    .HI ( optlc_net_134 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_956 ( .A ( ropt_net_160 ) , 
    .X ( right_width_0_height_0__pin_43_lower[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( aps_rename_141_ ) , 
    .X ( aps_rename_142_ ) ) ;
sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , 
    .HI ( optlc_net_135 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( aps_rename_144_ ) , 
    .X ( aps_rename_145_ ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( aps_rename_146_ ) , 
    .X ( aps_rename_147_ ) ) ;
sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , 
    .HI ( optlc_net_136 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_925 ( .A ( ropt_net_139 ) , 
    .X ( right_width_0_height_0__pin_44_upper[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_926 ( .A ( ropt_net_140 ) , 
    .X ( top_width_0_height_0__pin_34_lower[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 FTB_12__11 ( .A ( aps_rename_153_ ) , 
    .X ( ropt_net_152 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , 
    .HI ( optlc_net_137 ) ) ;
sky130_fd_sc_hd__buf_2 \clk[0]_bip534 ( .A ( clk[0] ) , 
    .X ( ctsbuf_net_1138 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_927 ( .A ( ropt_net_141 ) , 
    .X ( ropt_net_162 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_928 ( .A ( ropt_net_142 ) , 
    .X ( right_width_0_height_0__pin_42_upper[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 FTB_17__16 ( .A ( aps_rename_158_ ) , 
    .X ( ropt_net_153 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( aps_rename_159_ ) , 
    .X ( ropt_net_148 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( 
    .A ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , 
    .X ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3[0] ) ) ;
sky130_fd_sc_hd__buf_6 cts_buf_364898 ( .A ( ctsbuf_net_1138 ) , 
    .X ( clk__FEEDTHRU_1[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_929 ( .A ( ropt_net_143 ) , 
    .X ( top_width_0_height_0__pin_35_lower[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_97 ( .A ( aps_rename_137_ ) , 
    .X ( ropt_net_140 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_98 ( .A ( aps_rename_138_ ) , 
    .X ( ropt_net_143 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_99 ( .A ( aps_rename_139_ ) , 
    .X ( ropt_net_157 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_100 ( .A ( aps_rename_142_ ) , 
    .X ( ropt_net_156 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( aps_rename_143_ ) , 
    .X ( BUF_net_101 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_930 ( .A ( ropt_net_144 ) , 
    .X ( right_width_0_height_0__pin_43_upper[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_103 ( .A ( aps_rename_147_ ) , 
    .X ( top_width_0_height_0__pin_40_lower[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_932 ( .A ( ropt_net_145 ) , 
    .X ( top_width_0_height_0__pin_37_upper[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_105 ( .A ( aps_rename_149_ ) , 
    .X ( BUF_net_105 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_106 ( .A ( aps_rename_151_ ) , 
    .X ( BUF_net_106 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_933 ( .A ( ropt_net_146 ) , 
    .X ( top_width_0_height_0__pin_36_upper[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( 
    .A ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , 
    .X ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_937 ( .A ( ropt_net_147 ) , 
    .X ( top_width_0_height_0__pin_39_upper[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_116 ( .A ( BUF_net_101 ) , 
    .X ( top_width_0_height_0__pin_38_lower[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_117 ( .A ( aps_rename_145_ ) , 
    .X ( top_width_0_height_0__pin_39_lower[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_940 ( .A ( ropt_net_148 ) , 
    .X ( SC_OUT_BOT ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_941 ( .A ( ropt_net_149 ) , 
    .X ( right_width_0_height_0__pin_45_upper[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_120 ( .A ( aps_rename_154_ ) , 
    .X ( right_width_0_height_0__pin_45_lower[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_942 ( .A ( ropt_net_150 ) , 
    .X ( ropt_net_161 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_944 ( .A ( ropt_net_151 ) , 
    .X ( ropt_net_160 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_127 ( .A ( BUF_net_105 ) , 
    .X ( ropt_net_163 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( .A ( BUF_net_106 ) , 
    .X ( ropt_net_151 ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_946 ( .A ( ropt_net_152 ) , 
    .X ( right_width_0_height_0__pin_44_lower[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_959 ( .A ( ropt_net_161 ) , 
    .X ( ccff_tail[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_949 ( .A ( ropt_net_153 ) , 
    .X ( right_width_0_height_0__pin_49_lower[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_951 ( .A ( ropt_net_154 ) , 
    .X ( ropt_net_164 ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_952 ( .A ( ropt_net_155 ) , 
    .X ( bottom_width_0_height_0__pin_50_[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_953 ( .A ( ropt_net_156 ) , 
    .X ( top_width_0_height_0__pin_37_lower[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_954 ( .A ( ropt_net_157 ) , 
    .X ( top_width_0_height_0__pin_36_lower[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_955 ( 
    .A ( scff_Wires__FEEDTHRU_0[27] ) , .X ( scff_Wires__FEEDTHRU_1[27] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_960 ( .A ( ropt_net_162 ) , 
    .X ( top_width_0_height_0__pin_38_upper[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_962 ( .A ( ropt_net_163 ) , 
    .X ( right_width_0_height_0__pin_42_lower[0] ) ) ;
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_965 ( .A ( ropt_net_164 ) , 
    .X ( SC_OUT_TOP ) ) ;
endmodule


module fpga_core ( prog_clk , Test_en , clk , gfpga_pad_EMBEDDED_IO_SOC_IN , 
    gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , 
    ccff_head , ccff_tail , sc_head , sc_tail ) ;
input  [0:0] prog_clk ;
input  [0:0] Test_en ;
input  [0:0] clk ;
input  [0:107] gfpga_pad_EMBEDDED_IO_SOC_IN ;
output [0:107] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
output [0:107] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
input  [0:0] ccff_head ;
output [0:0] ccff_tail ;
input  sc_head ;
output sc_tail ;

wire [0:0] cbx_1__0__0_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__0__0_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__0__0_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__0__0_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__0__0_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__0__0_bottom_grid_pin_8_ ;
wire [0:19] cbx_1__0__0_chanx_left_out ;
wire [0:19] cbx_1__0__0_chanx_right_out ;
wire [0:0] cbx_1__0__10_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__0__10_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__0__10_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__0__10_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__0__10_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__0__10_bottom_grid_pin_8_ ;
wire [0:19] cbx_1__0__10_chanx_left_out ;
wire [0:19] cbx_1__0__10_chanx_right_out ;
wire [0:0] cbx_1__0__11_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__0__11_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__0__11_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__0__11_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__0__11_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__0__11_bottom_grid_pin_8_ ;
wire [0:19] cbx_1__0__11_chanx_left_out ;
wire [0:19] cbx_1__0__11_chanx_right_out ;
wire [0:0] cbx_1__0__1_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__0__1_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__0__1_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__0__1_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__0__1_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__0__1_bottom_grid_pin_8_ ;
wire [0:19] cbx_1__0__1_chanx_left_out ;
wire [0:19] cbx_1__0__1_chanx_right_out ;
wire [0:0] cbx_1__0__2_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__0__2_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__0__2_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__0__2_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__0__2_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__0__2_bottom_grid_pin_8_ ;
wire [0:19] cbx_1__0__2_chanx_left_out ;
wire [0:19] cbx_1__0__2_chanx_right_out ;
wire [0:0] cbx_1__0__3_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__0__3_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__0__3_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__0__3_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__0__3_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__0__3_bottom_grid_pin_8_ ;
wire [0:19] cbx_1__0__3_chanx_left_out ;
wire [0:19] cbx_1__0__3_chanx_right_out ;
wire [0:0] cbx_1__0__4_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__0__4_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__0__4_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__0__4_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__0__4_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__0__4_bottom_grid_pin_8_ ;
wire [0:19] cbx_1__0__4_chanx_left_out ;
wire [0:19] cbx_1__0__4_chanx_right_out ;
wire [0:0] cbx_1__0__5_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__0__5_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__0__5_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__0__5_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__0__5_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__0__5_bottom_grid_pin_8_ ;
wire [0:19] cbx_1__0__5_chanx_left_out ;
wire [0:19] cbx_1__0__5_chanx_right_out ;
wire [0:0] cbx_1__0__6_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__0__6_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__0__6_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__0__6_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__0__6_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__0__6_bottom_grid_pin_8_ ;
wire [0:19] cbx_1__0__6_chanx_left_out ;
wire [0:19] cbx_1__0__6_chanx_right_out ;
wire [0:0] cbx_1__0__7_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__0__7_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__0__7_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__0__7_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__0__7_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__0__7_bottom_grid_pin_8_ ;
wire [0:19] cbx_1__0__7_chanx_left_out ;
wire [0:19] cbx_1__0__7_chanx_right_out ;
wire [0:0] cbx_1__0__8_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__0__8_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__0__8_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__0__8_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__0__8_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__0__8_bottom_grid_pin_8_ ;
wire [0:19] cbx_1__0__8_chanx_left_out ;
wire [0:19] cbx_1__0__8_chanx_right_out ;
wire [0:0] cbx_1__0__9_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__0__9_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__0__9_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__0__9_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__0__9_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__0__9_bottom_grid_pin_8_ ;
wire [0:19] cbx_1__0__9_chanx_left_out ;
wire [0:19] cbx_1__0__9_chanx_right_out ;
wire [0:0] cbx_1__12__0_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__12__0_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__12__0_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__12__0_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__12__0_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__12__0_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__12__0_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__12__0_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__12__0_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__12__0_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__12__0_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__12__0_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__12__0_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__12__0_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__12__0_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__12__0_bottom_grid_pin_9_ ;
wire [0:19] cbx_1__12__0_chanx_left_out ;
wire [0:19] cbx_1__12__0_chanx_right_out ;
wire [0:0] cbx_1__12__0_top_grid_pin_0_ ;
wire [0:0] cbx_1__12__10_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__12__10_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__12__10_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__12__10_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__12__10_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__12__10_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__12__10_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__12__10_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__12__10_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__12__10_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__12__10_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__12__10_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__12__10_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__12__10_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__12__10_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__12__10_bottom_grid_pin_9_ ;
wire [0:19] cbx_1__12__10_chanx_left_out ;
wire [0:19] cbx_1__12__10_chanx_right_out ;
wire [0:0] cbx_1__12__10_top_grid_pin_0_ ;
wire [0:0] cbx_1__12__11_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__12__11_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__12__11_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__12__11_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__12__11_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__12__11_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__12__11_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__12__11_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__12__11_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__12__11_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__12__11_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__12__11_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__12__11_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__12__11_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__12__11_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__12__11_bottom_grid_pin_9_ ;
wire [0:19] cbx_1__12__11_chanx_left_out ;
wire [0:19] cbx_1__12__11_chanx_right_out ;
wire [0:0] cbx_1__12__11_top_grid_pin_0_ ;
wire [0:0] cbx_1__12__1_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__12__1_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__12__1_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__12__1_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__12__1_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__12__1_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__12__1_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__12__1_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__12__1_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__12__1_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__12__1_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__12__1_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__12__1_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__12__1_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__12__1_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__12__1_bottom_grid_pin_9_ ;
wire [0:19] cbx_1__12__1_chanx_left_out ;
wire [0:19] cbx_1__12__1_chanx_right_out ;
wire [0:0] cbx_1__12__1_top_grid_pin_0_ ;
wire [0:0] cbx_1__12__2_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__12__2_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__12__2_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__12__2_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__12__2_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__12__2_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__12__2_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__12__2_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__12__2_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__12__2_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__12__2_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__12__2_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__12__2_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__12__2_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__12__2_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__12__2_bottom_grid_pin_9_ ;
wire [0:19] cbx_1__12__2_chanx_left_out ;
wire [0:19] cbx_1__12__2_chanx_right_out ;
wire [0:0] cbx_1__12__2_top_grid_pin_0_ ;
wire [0:0] cbx_1__12__3_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__12__3_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__12__3_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__12__3_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__12__3_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__12__3_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__12__3_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__12__3_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__12__3_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__12__3_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__12__3_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__12__3_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__12__3_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__12__3_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__12__3_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__12__3_bottom_grid_pin_9_ ;
wire [0:19] cbx_1__12__3_chanx_left_out ;
wire [0:19] cbx_1__12__3_chanx_right_out ;
wire [0:0] cbx_1__12__3_top_grid_pin_0_ ;
wire [0:0] cbx_1__12__4_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__12__4_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__12__4_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__12__4_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__12__4_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__12__4_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__12__4_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__12__4_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__12__4_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__12__4_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__12__4_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__12__4_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__12__4_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__12__4_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__12__4_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__12__4_bottom_grid_pin_9_ ;
wire [0:19] cbx_1__12__4_chanx_left_out ;
wire [0:19] cbx_1__12__4_chanx_right_out ;
wire [0:0] cbx_1__12__4_top_grid_pin_0_ ;
wire [0:0] cbx_1__12__5_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__12__5_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__12__5_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__12__5_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__12__5_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__12__5_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__12__5_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__12__5_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__12__5_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__12__5_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__12__5_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__12__5_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__12__5_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__12__5_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__12__5_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__12__5_bottom_grid_pin_9_ ;
wire [0:19] cbx_1__12__5_chanx_left_out ;
wire [0:19] cbx_1__12__5_chanx_right_out ;
wire [0:0] cbx_1__12__5_top_grid_pin_0_ ;
wire [0:0] cbx_1__12__6_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__12__6_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__12__6_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__12__6_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__12__6_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__12__6_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__12__6_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__12__6_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__12__6_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__12__6_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__12__6_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__12__6_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__12__6_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__12__6_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__12__6_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__12__6_bottom_grid_pin_9_ ;
wire [0:19] cbx_1__12__6_chanx_left_out ;
wire [0:19] cbx_1__12__6_chanx_right_out ;
wire [0:0] cbx_1__12__6_top_grid_pin_0_ ;
wire [0:0] cbx_1__12__7_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__12__7_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__12__7_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__12__7_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__12__7_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__12__7_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__12__7_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__12__7_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__12__7_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__12__7_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__12__7_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__12__7_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__12__7_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__12__7_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__12__7_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__12__7_bottom_grid_pin_9_ ;
wire [0:19] cbx_1__12__7_chanx_left_out ;
wire [0:19] cbx_1__12__7_chanx_right_out ;
wire [0:0] cbx_1__12__7_top_grid_pin_0_ ;
wire [0:0] cbx_1__12__8_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__12__8_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__12__8_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__12__8_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__12__8_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__12__8_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__12__8_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__12__8_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__12__8_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__12__8_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__12__8_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__12__8_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__12__8_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__12__8_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__12__8_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__12__8_bottom_grid_pin_9_ ;
wire [0:19] cbx_1__12__8_chanx_left_out ;
wire [0:19] cbx_1__12__8_chanx_right_out ;
wire [0:0] cbx_1__12__8_top_grid_pin_0_ ;
wire [0:0] cbx_1__12__9_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__12__9_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__12__9_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__12__9_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__12__9_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__12__9_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__12__9_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__12__9_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__12__9_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__12__9_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__12__9_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__12__9_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__12__9_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__12__9_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__12__9_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__12__9_bottom_grid_pin_9_ ;
wire [0:19] cbx_1__12__9_chanx_left_out ;
wire [0:19] cbx_1__12__9_chanx_right_out ;
wire [0:0] cbx_1__12__9_top_grid_pin_0_ ;
wire [0:0] cbx_1__1__0_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__0_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__0_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__0_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__0_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__0_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__0_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__0_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__0_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__0_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__0_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__0_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__0_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__0_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__0_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__0_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__0_ccff_tail ;
wire [0:19] cbx_1__1__0_chanx_left_out ;
wire [0:19] cbx_1__1__0_chanx_right_out ;
wire [0:0] cbx_1__1__100_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__100_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__100_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__100_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__100_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__100_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__100_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__100_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__100_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__100_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__100_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__100_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__100_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__100_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__100_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__100_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__100_ccff_tail ;
wire [0:19] cbx_1__1__100_chanx_left_out ;
wire [0:19] cbx_1__1__100_chanx_right_out ;
wire [0:0] cbx_1__1__101_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__101_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__101_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__101_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__101_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__101_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__101_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__101_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__101_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__101_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__101_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__101_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__101_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__101_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__101_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__101_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__101_ccff_tail ;
wire [0:19] cbx_1__1__101_chanx_left_out ;
wire [0:19] cbx_1__1__101_chanx_right_out ;
wire [0:0] cbx_1__1__102_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__102_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__102_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__102_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__102_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__102_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__102_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__102_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__102_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__102_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__102_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__102_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__102_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__102_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__102_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__102_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__102_ccff_tail ;
wire [0:19] cbx_1__1__102_chanx_left_out ;
wire [0:19] cbx_1__1__102_chanx_right_out ;
wire [0:0] cbx_1__1__103_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__103_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__103_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__103_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__103_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__103_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__103_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__103_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__103_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__103_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__103_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__103_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__103_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__103_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__103_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__103_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__103_ccff_tail ;
wire [0:19] cbx_1__1__103_chanx_left_out ;
wire [0:19] cbx_1__1__103_chanx_right_out ;
wire [0:0] cbx_1__1__104_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__104_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__104_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__104_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__104_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__104_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__104_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__104_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__104_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__104_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__104_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__104_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__104_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__104_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__104_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__104_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__104_ccff_tail ;
wire [0:19] cbx_1__1__104_chanx_left_out ;
wire [0:19] cbx_1__1__104_chanx_right_out ;
wire [0:0] cbx_1__1__105_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__105_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__105_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__105_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__105_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__105_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__105_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__105_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__105_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__105_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__105_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__105_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__105_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__105_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__105_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__105_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__105_ccff_tail ;
wire [0:19] cbx_1__1__105_chanx_left_out ;
wire [0:19] cbx_1__1__105_chanx_right_out ;
wire [0:0] cbx_1__1__106_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__106_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__106_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__106_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__106_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__106_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__106_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__106_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__106_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__106_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__106_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__106_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__106_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__106_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__106_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__106_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__106_ccff_tail ;
wire [0:19] cbx_1__1__106_chanx_left_out ;
wire [0:19] cbx_1__1__106_chanx_right_out ;
wire [0:0] cbx_1__1__107_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__107_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__107_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__107_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__107_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__107_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__107_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__107_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__107_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__107_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__107_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__107_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__107_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__107_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__107_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__107_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__107_ccff_tail ;
wire [0:19] cbx_1__1__107_chanx_left_out ;
wire [0:19] cbx_1__1__107_chanx_right_out ;
wire [0:0] cbx_1__1__108_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__108_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__108_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__108_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__108_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__108_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__108_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__108_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__108_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__108_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__108_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__108_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__108_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__108_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__108_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__108_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__108_ccff_tail ;
wire [0:19] cbx_1__1__108_chanx_left_out ;
wire [0:19] cbx_1__1__108_chanx_right_out ;
wire [0:0] cbx_1__1__109_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__109_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__109_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__109_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__109_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__109_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__109_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__109_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__109_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__109_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__109_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__109_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__109_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__109_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__109_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__109_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__109_ccff_tail ;
wire [0:19] cbx_1__1__109_chanx_left_out ;
wire [0:19] cbx_1__1__109_chanx_right_out ;
wire [0:0] cbx_1__1__10_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__10_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__10_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__10_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__10_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__10_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__10_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__10_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__10_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__10_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__10_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__10_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__10_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__10_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__10_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__10_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__10_ccff_tail ;
wire [0:19] cbx_1__1__10_chanx_left_out ;
wire [0:19] cbx_1__1__10_chanx_right_out ;
wire [0:0] cbx_1__1__110_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__110_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__110_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__110_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__110_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__110_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__110_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__110_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__110_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__110_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__110_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__110_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__110_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__110_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__110_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__110_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__110_ccff_tail ;
wire [0:19] cbx_1__1__110_chanx_left_out ;
wire [0:19] cbx_1__1__110_chanx_right_out ;
wire [0:0] cbx_1__1__111_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__111_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__111_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__111_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__111_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__111_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__111_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__111_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__111_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__111_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__111_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__111_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__111_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__111_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__111_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__111_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__111_ccff_tail ;
wire [0:19] cbx_1__1__111_chanx_left_out ;
wire [0:19] cbx_1__1__111_chanx_right_out ;
wire [0:0] cbx_1__1__112_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__112_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__112_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__112_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__112_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__112_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__112_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__112_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__112_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__112_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__112_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__112_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__112_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__112_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__112_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__112_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__112_ccff_tail ;
wire [0:19] cbx_1__1__112_chanx_left_out ;
wire [0:19] cbx_1__1__112_chanx_right_out ;
wire [0:0] cbx_1__1__113_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__113_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__113_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__113_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__113_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__113_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__113_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__113_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__113_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__113_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__113_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__113_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__113_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__113_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__113_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__113_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__113_ccff_tail ;
wire [0:19] cbx_1__1__113_chanx_left_out ;
wire [0:19] cbx_1__1__113_chanx_right_out ;
wire [0:0] cbx_1__1__114_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__114_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__114_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__114_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__114_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__114_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__114_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__114_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__114_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__114_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__114_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__114_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__114_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__114_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__114_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__114_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__114_ccff_tail ;
wire [0:19] cbx_1__1__114_chanx_left_out ;
wire [0:19] cbx_1__1__114_chanx_right_out ;
wire [0:0] cbx_1__1__115_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__115_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__115_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__115_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__115_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__115_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__115_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__115_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__115_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__115_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__115_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__115_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__115_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__115_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__115_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__115_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__115_ccff_tail ;
wire [0:19] cbx_1__1__115_chanx_left_out ;
wire [0:19] cbx_1__1__115_chanx_right_out ;
wire [0:0] cbx_1__1__116_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__116_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__116_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__116_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__116_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__116_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__116_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__116_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__116_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__116_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__116_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__116_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__116_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__116_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__116_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__116_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__116_ccff_tail ;
wire [0:19] cbx_1__1__116_chanx_left_out ;
wire [0:19] cbx_1__1__116_chanx_right_out ;
wire [0:0] cbx_1__1__117_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__117_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__117_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__117_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__117_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__117_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__117_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__117_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__117_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__117_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__117_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__117_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__117_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__117_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__117_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__117_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__117_ccff_tail ;
wire [0:19] cbx_1__1__117_chanx_left_out ;
wire [0:19] cbx_1__1__117_chanx_right_out ;
wire [0:0] cbx_1__1__118_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__118_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__118_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__118_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__118_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__118_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__118_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__118_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__118_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__118_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__118_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__118_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__118_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__118_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__118_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__118_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__118_ccff_tail ;
wire [0:19] cbx_1__1__118_chanx_left_out ;
wire [0:19] cbx_1__1__118_chanx_right_out ;
wire [0:0] cbx_1__1__119_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__119_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__119_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__119_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__119_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__119_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__119_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__119_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__119_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__119_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__119_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__119_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__119_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__119_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__119_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__119_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__119_ccff_tail ;
wire [0:19] cbx_1__1__119_chanx_left_out ;
wire [0:19] cbx_1__1__119_chanx_right_out ;
wire [0:0] cbx_1__1__11_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__11_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__11_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__11_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__11_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__11_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__11_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__11_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__11_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__11_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__11_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__11_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__11_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__11_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__11_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__11_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__11_ccff_tail ;
wire [0:19] cbx_1__1__11_chanx_left_out ;
wire [0:19] cbx_1__1__11_chanx_right_out ;
wire [0:0] cbx_1__1__120_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__120_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__120_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__120_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__120_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__120_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__120_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__120_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__120_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__120_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__120_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__120_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__120_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__120_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__120_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__120_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__120_ccff_tail ;
wire [0:19] cbx_1__1__120_chanx_left_out ;
wire [0:19] cbx_1__1__120_chanx_right_out ;
wire [0:0] cbx_1__1__121_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__121_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__121_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__121_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__121_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__121_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__121_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__121_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__121_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__121_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__121_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__121_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__121_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__121_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__121_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__121_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__121_ccff_tail ;
wire [0:19] cbx_1__1__121_chanx_left_out ;
wire [0:19] cbx_1__1__121_chanx_right_out ;
wire [0:0] cbx_1__1__122_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__122_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__122_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__122_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__122_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__122_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__122_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__122_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__122_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__122_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__122_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__122_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__122_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__122_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__122_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__122_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__122_ccff_tail ;
wire [0:19] cbx_1__1__122_chanx_left_out ;
wire [0:19] cbx_1__1__122_chanx_right_out ;
wire [0:0] cbx_1__1__123_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__123_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__123_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__123_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__123_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__123_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__123_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__123_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__123_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__123_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__123_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__123_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__123_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__123_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__123_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__123_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__123_ccff_tail ;
wire [0:19] cbx_1__1__123_chanx_left_out ;
wire [0:19] cbx_1__1__123_chanx_right_out ;
wire [0:0] cbx_1__1__124_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__124_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__124_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__124_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__124_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__124_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__124_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__124_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__124_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__124_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__124_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__124_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__124_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__124_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__124_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__124_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__124_ccff_tail ;
wire [0:19] cbx_1__1__124_chanx_left_out ;
wire [0:19] cbx_1__1__124_chanx_right_out ;
wire [0:0] cbx_1__1__125_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__125_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__125_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__125_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__125_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__125_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__125_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__125_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__125_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__125_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__125_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__125_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__125_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__125_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__125_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__125_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__125_ccff_tail ;
wire [0:19] cbx_1__1__125_chanx_left_out ;
wire [0:19] cbx_1__1__125_chanx_right_out ;
wire [0:0] cbx_1__1__126_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__126_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__126_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__126_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__126_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__126_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__126_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__126_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__126_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__126_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__126_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__126_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__126_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__126_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__126_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__126_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__126_ccff_tail ;
wire [0:19] cbx_1__1__126_chanx_left_out ;
wire [0:19] cbx_1__1__126_chanx_right_out ;
wire [0:0] cbx_1__1__127_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__127_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__127_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__127_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__127_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__127_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__127_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__127_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__127_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__127_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__127_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__127_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__127_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__127_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__127_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__127_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__127_ccff_tail ;
wire [0:19] cbx_1__1__127_chanx_left_out ;
wire [0:19] cbx_1__1__127_chanx_right_out ;
wire [0:0] cbx_1__1__128_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__128_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__128_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__128_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__128_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__128_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__128_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__128_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__128_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__128_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__128_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__128_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__128_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__128_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__128_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__128_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__128_ccff_tail ;
wire [0:19] cbx_1__1__128_chanx_left_out ;
wire [0:19] cbx_1__1__128_chanx_right_out ;
wire [0:0] cbx_1__1__129_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__129_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__129_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__129_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__129_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__129_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__129_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__129_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__129_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__129_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__129_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__129_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__129_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__129_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__129_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__129_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__129_ccff_tail ;
wire [0:19] cbx_1__1__129_chanx_left_out ;
wire [0:19] cbx_1__1__129_chanx_right_out ;
wire [0:0] cbx_1__1__12_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__12_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__12_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__12_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__12_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__12_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__12_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__12_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__12_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__12_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__12_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__12_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__12_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__12_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__12_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__12_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__12_ccff_tail ;
wire [0:19] cbx_1__1__12_chanx_left_out ;
wire [0:19] cbx_1__1__12_chanx_right_out ;
wire [0:0] cbx_1__1__130_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__130_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__130_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__130_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__130_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__130_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__130_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__130_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__130_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__130_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__130_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__130_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__130_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__130_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__130_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__130_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__130_ccff_tail ;
wire [0:19] cbx_1__1__130_chanx_left_out ;
wire [0:19] cbx_1__1__130_chanx_right_out ;
wire [0:0] cbx_1__1__131_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__131_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__131_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__131_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__131_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__131_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__131_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__131_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__131_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__131_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__131_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__131_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__131_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__131_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__131_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__131_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__131_ccff_tail ;
wire [0:19] cbx_1__1__131_chanx_left_out ;
wire [0:19] cbx_1__1__131_chanx_right_out ;
wire [0:0] cbx_1__1__13_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__13_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__13_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__13_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__13_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__13_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__13_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__13_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__13_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__13_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__13_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__13_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__13_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__13_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__13_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__13_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__13_ccff_tail ;
wire [0:19] cbx_1__1__13_chanx_left_out ;
wire [0:19] cbx_1__1__13_chanx_right_out ;
wire [0:0] cbx_1__1__14_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__14_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__14_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__14_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__14_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__14_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__14_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__14_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__14_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__14_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__14_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__14_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__14_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__14_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__14_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__14_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__14_ccff_tail ;
wire [0:19] cbx_1__1__14_chanx_left_out ;
wire [0:19] cbx_1__1__14_chanx_right_out ;
wire [0:0] cbx_1__1__15_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__15_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__15_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__15_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__15_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__15_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__15_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__15_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__15_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__15_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__15_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__15_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__15_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__15_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__15_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__15_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__15_ccff_tail ;
wire [0:19] cbx_1__1__15_chanx_left_out ;
wire [0:19] cbx_1__1__15_chanx_right_out ;
wire [0:0] cbx_1__1__16_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__16_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__16_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__16_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__16_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__16_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__16_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__16_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__16_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__16_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__16_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__16_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__16_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__16_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__16_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__16_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__16_ccff_tail ;
wire [0:19] cbx_1__1__16_chanx_left_out ;
wire [0:19] cbx_1__1__16_chanx_right_out ;
wire [0:0] cbx_1__1__17_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__17_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__17_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__17_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__17_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__17_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__17_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__17_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__17_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__17_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__17_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__17_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__17_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__17_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__17_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__17_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__17_ccff_tail ;
wire [0:19] cbx_1__1__17_chanx_left_out ;
wire [0:19] cbx_1__1__17_chanx_right_out ;
wire [0:0] cbx_1__1__18_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__18_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__18_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__18_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__18_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__18_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__18_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__18_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__18_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__18_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__18_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__18_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__18_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__18_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__18_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__18_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__18_ccff_tail ;
wire [0:19] cbx_1__1__18_chanx_left_out ;
wire [0:19] cbx_1__1__18_chanx_right_out ;
wire [0:0] cbx_1__1__19_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__19_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__19_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__19_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__19_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__19_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__19_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__19_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__19_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__19_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__19_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__19_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__19_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__19_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__19_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__19_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__19_ccff_tail ;
wire [0:19] cbx_1__1__19_chanx_left_out ;
wire [0:19] cbx_1__1__19_chanx_right_out ;
wire [0:0] cbx_1__1__1_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__1_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__1_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__1_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__1_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__1_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__1_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__1_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__1_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__1_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__1_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__1_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__1_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__1_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__1_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__1_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__1_ccff_tail ;
wire [0:19] cbx_1__1__1_chanx_left_out ;
wire [0:19] cbx_1__1__1_chanx_right_out ;
wire [0:0] cbx_1__1__20_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__20_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__20_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__20_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__20_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__20_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__20_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__20_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__20_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__20_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__20_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__20_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__20_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__20_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__20_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__20_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__20_ccff_tail ;
wire [0:19] cbx_1__1__20_chanx_left_out ;
wire [0:19] cbx_1__1__20_chanx_right_out ;
wire [0:0] cbx_1__1__21_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__21_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__21_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__21_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__21_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__21_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__21_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__21_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__21_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__21_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__21_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__21_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__21_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__21_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__21_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__21_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__21_ccff_tail ;
wire [0:19] cbx_1__1__21_chanx_left_out ;
wire [0:19] cbx_1__1__21_chanx_right_out ;
wire [0:0] cbx_1__1__22_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__22_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__22_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__22_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__22_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__22_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__22_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__22_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__22_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__22_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__22_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__22_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__22_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__22_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__22_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__22_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__22_ccff_tail ;
wire [0:19] cbx_1__1__22_chanx_left_out ;
wire [0:19] cbx_1__1__22_chanx_right_out ;
wire [0:0] cbx_1__1__23_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__23_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__23_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__23_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__23_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__23_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__23_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__23_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__23_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__23_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__23_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__23_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__23_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__23_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__23_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__23_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__23_ccff_tail ;
wire [0:19] cbx_1__1__23_chanx_left_out ;
wire [0:19] cbx_1__1__23_chanx_right_out ;
wire [0:0] cbx_1__1__24_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__24_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__24_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__24_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__24_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__24_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__24_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__24_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__24_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__24_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__24_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__24_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__24_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__24_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__24_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__24_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__24_ccff_tail ;
wire [0:19] cbx_1__1__24_chanx_left_out ;
wire [0:19] cbx_1__1__24_chanx_right_out ;
wire [0:0] cbx_1__1__25_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__25_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__25_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__25_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__25_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__25_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__25_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__25_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__25_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__25_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__25_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__25_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__25_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__25_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__25_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__25_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__25_ccff_tail ;
wire [0:19] cbx_1__1__25_chanx_left_out ;
wire [0:19] cbx_1__1__25_chanx_right_out ;
wire [0:0] cbx_1__1__26_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__26_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__26_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__26_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__26_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__26_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__26_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__26_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__26_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__26_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__26_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__26_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__26_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__26_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__26_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__26_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__26_ccff_tail ;
wire [0:19] cbx_1__1__26_chanx_left_out ;
wire [0:19] cbx_1__1__26_chanx_right_out ;
wire [0:0] cbx_1__1__27_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__27_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__27_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__27_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__27_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__27_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__27_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__27_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__27_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__27_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__27_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__27_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__27_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__27_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__27_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__27_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__27_ccff_tail ;
wire [0:19] cbx_1__1__27_chanx_left_out ;
wire [0:19] cbx_1__1__27_chanx_right_out ;
wire [0:0] cbx_1__1__28_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__28_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__28_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__28_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__28_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__28_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__28_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__28_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__28_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__28_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__28_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__28_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__28_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__28_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__28_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__28_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__28_ccff_tail ;
wire [0:19] cbx_1__1__28_chanx_left_out ;
wire [0:19] cbx_1__1__28_chanx_right_out ;
wire [0:0] cbx_1__1__29_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__29_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__29_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__29_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__29_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__29_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__29_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__29_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__29_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__29_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__29_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__29_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__29_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__29_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__29_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__29_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__29_ccff_tail ;
wire [0:19] cbx_1__1__29_chanx_left_out ;
wire [0:19] cbx_1__1__29_chanx_right_out ;
wire [0:0] cbx_1__1__2_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__2_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__2_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__2_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__2_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__2_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__2_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__2_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__2_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__2_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__2_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__2_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__2_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__2_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__2_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__2_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__2_ccff_tail ;
wire [0:19] cbx_1__1__2_chanx_left_out ;
wire [0:19] cbx_1__1__2_chanx_right_out ;
wire [0:0] cbx_1__1__30_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__30_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__30_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__30_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__30_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__30_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__30_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__30_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__30_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__30_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__30_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__30_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__30_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__30_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__30_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__30_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__30_ccff_tail ;
wire [0:19] cbx_1__1__30_chanx_left_out ;
wire [0:19] cbx_1__1__30_chanx_right_out ;
wire [0:0] cbx_1__1__31_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__31_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__31_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__31_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__31_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__31_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__31_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__31_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__31_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__31_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__31_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__31_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__31_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__31_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__31_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__31_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__31_ccff_tail ;
wire [0:19] cbx_1__1__31_chanx_left_out ;
wire [0:19] cbx_1__1__31_chanx_right_out ;
wire [0:0] cbx_1__1__32_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__32_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__32_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__32_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__32_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__32_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__32_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__32_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__32_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__32_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__32_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__32_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__32_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__32_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__32_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__32_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__32_ccff_tail ;
wire [0:19] cbx_1__1__32_chanx_left_out ;
wire [0:19] cbx_1__1__32_chanx_right_out ;
wire [0:0] cbx_1__1__33_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__33_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__33_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__33_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__33_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__33_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__33_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__33_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__33_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__33_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__33_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__33_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__33_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__33_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__33_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__33_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__33_ccff_tail ;
wire [0:19] cbx_1__1__33_chanx_left_out ;
wire [0:19] cbx_1__1__33_chanx_right_out ;
wire [0:0] cbx_1__1__34_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__34_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__34_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__34_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__34_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__34_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__34_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__34_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__34_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__34_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__34_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__34_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__34_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__34_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__34_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__34_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__34_ccff_tail ;
wire [0:19] cbx_1__1__34_chanx_left_out ;
wire [0:19] cbx_1__1__34_chanx_right_out ;
wire [0:0] cbx_1__1__35_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__35_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__35_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__35_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__35_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__35_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__35_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__35_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__35_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__35_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__35_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__35_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__35_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__35_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__35_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__35_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__35_ccff_tail ;
wire [0:19] cbx_1__1__35_chanx_left_out ;
wire [0:19] cbx_1__1__35_chanx_right_out ;
wire [0:0] cbx_1__1__36_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__36_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__36_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__36_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__36_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__36_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__36_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__36_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__36_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__36_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__36_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__36_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__36_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__36_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__36_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__36_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__36_ccff_tail ;
wire [0:19] cbx_1__1__36_chanx_left_out ;
wire [0:19] cbx_1__1__36_chanx_right_out ;
wire [0:0] cbx_1__1__37_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__37_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__37_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__37_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__37_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__37_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__37_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__37_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__37_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__37_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__37_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__37_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__37_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__37_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__37_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__37_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__37_ccff_tail ;
wire [0:19] cbx_1__1__37_chanx_left_out ;
wire [0:19] cbx_1__1__37_chanx_right_out ;
wire [0:0] cbx_1__1__38_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__38_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__38_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__38_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__38_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__38_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__38_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__38_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__38_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__38_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__38_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__38_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__38_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__38_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__38_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__38_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__38_ccff_tail ;
wire [0:19] cbx_1__1__38_chanx_left_out ;
wire [0:19] cbx_1__1__38_chanx_right_out ;
wire [0:0] cbx_1__1__39_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__39_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__39_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__39_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__39_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__39_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__39_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__39_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__39_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__39_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__39_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__39_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__39_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__39_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__39_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__39_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__39_ccff_tail ;
wire [0:19] cbx_1__1__39_chanx_left_out ;
wire [0:19] cbx_1__1__39_chanx_right_out ;
wire [0:0] cbx_1__1__3_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__3_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__3_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__3_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__3_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__3_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__3_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__3_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__3_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__3_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__3_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__3_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__3_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__3_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__3_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__3_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__3_ccff_tail ;
wire [0:19] cbx_1__1__3_chanx_left_out ;
wire [0:19] cbx_1__1__3_chanx_right_out ;
wire [0:0] cbx_1__1__40_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__40_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__40_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__40_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__40_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__40_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__40_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__40_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__40_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__40_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__40_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__40_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__40_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__40_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__40_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__40_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__40_ccff_tail ;
wire [0:19] cbx_1__1__40_chanx_left_out ;
wire [0:19] cbx_1__1__40_chanx_right_out ;
wire [0:0] cbx_1__1__41_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__41_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__41_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__41_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__41_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__41_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__41_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__41_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__41_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__41_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__41_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__41_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__41_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__41_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__41_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__41_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__41_ccff_tail ;
wire [0:19] cbx_1__1__41_chanx_left_out ;
wire [0:19] cbx_1__1__41_chanx_right_out ;
wire [0:0] cbx_1__1__42_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__42_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__42_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__42_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__42_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__42_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__42_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__42_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__42_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__42_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__42_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__42_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__42_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__42_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__42_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__42_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__42_ccff_tail ;
wire [0:19] cbx_1__1__42_chanx_left_out ;
wire [0:19] cbx_1__1__42_chanx_right_out ;
wire [0:0] cbx_1__1__43_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__43_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__43_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__43_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__43_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__43_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__43_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__43_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__43_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__43_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__43_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__43_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__43_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__43_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__43_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__43_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__43_ccff_tail ;
wire [0:19] cbx_1__1__43_chanx_left_out ;
wire [0:19] cbx_1__1__43_chanx_right_out ;
wire [0:0] cbx_1__1__44_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__44_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__44_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__44_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__44_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__44_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__44_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__44_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__44_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__44_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__44_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__44_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__44_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__44_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__44_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__44_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__44_ccff_tail ;
wire [0:19] cbx_1__1__44_chanx_left_out ;
wire [0:19] cbx_1__1__44_chanx_right_out ;
wire [0:0] cbx_1__1__45_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__45_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__45_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__45_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__45_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__45_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__45_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__45_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__45_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__45_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__45_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__45_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__45_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__45_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__45_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__45_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__45_ccff_tail ;
wire [0:19] cbx_1__1__45_chanx_left_out ;
wire [0:19] cbx_1__1__45_chanx_right_out ;
wire [0:0] cbx_1__1__46_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__46_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__46_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__46_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__46_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__46_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__46_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__46_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__46_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__46_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__46_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__46_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__46_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__46_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__46_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__46_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__46_ccff_tail ;
wire [0:19] cbx_1__1__46_chanx_left_out ;
wire [0:19] cbx_1__1__46_chanx_right_out ;
wire [0:0] cbx_1__1__47_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__47_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__47_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__47_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__47_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__47_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__47_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__47_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__47_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__47_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__47_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__47_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__47_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__47_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__47_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__47_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__47_ccff_tail ;
wire [0:19] cbx_1__1__47_chanx_left_out ;
wire [0:19] cbx_1__1__47_chanx_right_out ;
wire [0:0] cbx_1__1__48_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__48_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__48_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__48_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__48_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__48_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__48_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__48_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__48_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__48_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__48_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__48_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__48_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__48_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__48_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__48_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__48_ccff_tail ;
wire [0:19] cbx_1__1__48_chanx_left_out ;
wire [0:19] cbx_1__1__48_chanx_right_out ;
wire [0:0] cbx_1__1__49_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__49_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__49_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__49_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__49_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__49_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__49_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__49_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__49_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__49_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__49_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__49_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__49_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__49_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__49_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__49_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__49_ccff_tail ;
wire [0:19] cbx_1__1__49_chanx_left_out ;
wire [0:19] cbx_1__1__49_chanx_right_out ;
wire [0:0] cbx_1__1__4_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__4_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__4_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__4_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__4_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__4_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__4_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__4_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__4_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__4_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__4_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__4_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__4_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__4_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__4_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__4_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__4_ccff_tail ;
wire [0:19] cbx_1__1__4_chanx_left_out ;
wire [0:19] cbx_1__1__4_chanx_right_out ;
wire [0:0] cbx_1__1__50_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__50_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__50_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__50_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__50_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__50_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__50_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__50_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__50_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__50_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__50_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__50_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__50_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__50_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__50_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__50_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__50_ccff_tail ;
wire [0:19] cbx_1__1__50_chanx_left_out ;
wire [0:19] cbx_1__1__50_chanx_right_out ;
wire [0:0] cbx_1__1__51_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__51_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__51_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__51_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__51_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__51_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__51_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__51_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__51_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__51_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__51_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__51_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__51_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__51_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__51_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__51_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__51_ccff_tail ;
wire [0:19] cbx_1__1__51_chanx_left_out ;
wire [0:19] cbx_1__1__51_chanx_right_out ;
wire [0:0] cbx_1__1__52_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__52_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__52_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__52_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__52_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__52_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__52_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__52_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__52_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__52_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__52_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__52_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__52_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__52_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__52_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__52_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__52_ccff_tail ;
wire [0:19] cbx_1__1__52_chanx_left_out ;
wire [0:19] cbx_1__1__52_chanx_right_out ;
wire [0:0] cbx_1__1__53_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__53_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__53_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__53_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__53_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__53_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__53_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__53_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__53_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__53_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__53_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__53_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__53_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__53_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__53_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__53_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__53_ccff_tail ;
wire [0:19] cbx_1__1__53_chanx_left_out ;
wire [0:19] cbx_1__1__53_chanx_right_out ;
wire [0:0] cbx_1__1__54_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__54_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__54_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__54_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__54_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__54_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__54_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__54_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__54_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__54_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__54_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__54_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__54_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__54_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__54_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__54_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__54_ccff_tail ;
wire [0:19] cbx_1__1__54_chanx_left_out ;
wire [0:19] cbx_1__1__54_chanx_right_out ;
wire [0:0] cbx_1__1__55_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__55_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__55_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__55_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__55_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__55_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__55_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__55_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__55_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__55_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__55_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__55_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__55_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__55_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__55_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__55_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__55_ccff_tail ;
wire [0:19] cbx_1__1__55_chanx_left_out ;
wire [0:19] cbx_1__1__55_chanx_right_out ;
wire [0:0] cbx_1__1__56_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__56_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__56_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__56_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__56_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__56_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__56_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__56_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__56_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__56_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__56_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__56_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__56_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__56_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__56_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__56_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__56_ccff_tail ;
wire [0:19] cbx_1__1__56_chanx_left_out ;
wire [0:19] cbx_1__1__56_chanx_right_out ;
wire [0:0] cbx_1__1__57_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__57_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__57_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__57_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__57_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__57_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__57_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__57_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__57_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__57_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__57_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__57_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__57_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__57_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__57_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__57_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__57_ccff_tail ;
wire [0:19] cbx_1__1__57_chanx_left_out ;
wire [0:19] cbx_1__1__57_chanx_right_out ;
wire [0:0] cbx_1__1__58_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__58_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__58_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__58_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__58_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__58_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__58_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__58_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__58_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__58_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__58_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__58_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__58_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__58_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__58_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__58_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__58_ccff_tail ;
wire [0:19] cbx_1__1__58_chanx_left_out ;
wire [0:19] cbx_1__1__58_chanx_right_out ;
wire [0:0] cbx_1__1__59_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__59_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__59_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__59_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__59_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__59_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__59_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__59_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__59_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__59_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__59_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__59_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__59_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__59_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__59_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__59_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__59_ccff_tail ;
wire [0:19] cbx_1__1__59_chanx_left_out ;
wire [0:19] cbx_1__1__59_chanx_right_out ;
wire [0:0] cbx_1__1__5_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__5_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__5_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__5_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__5_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__5_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__5_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__5_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__5_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__5_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__5_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__5_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__5_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__5_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__5_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__5_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__5_ccff_tail ;
wire [0:19] cbx_1__1__5_chanx_left_out ;
wire [0:19] cbx_1__1__5_chanx_right_out ;
wire [0:0] cbx_1__1__60_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__60_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__60_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__60_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__60_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__60_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__60_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__60_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__60_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__60_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__60_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__60_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__60_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__60_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__60_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__60_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__60_ccff_tail ;
wire [0:19] cbx_1__1__60_chanx_left_out ;
wire [0:19] cbx_1__1__60_chanx_right_out ;
wire [0:0] cbx_1__1__61_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__61_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__61_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__61_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__61_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__61_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__61_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__61_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__61_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__61_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__61_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__61_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__61_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__61_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__61_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__61_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__61_ccff_tail ;
wire [0:19] cbx_1__1__61_chanx_left_out ;
wire [0:19] cbx_1__1__61_chanx_right_out ;
wire [0:0] cbx_1__1__62_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__62_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__62_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__62_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__62_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__62_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__62_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__62_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__62_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__62_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__62_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__62_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__62_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__62_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__62_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__62_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__62_ccff_tail ;
wire [0:19] cbx_1__1__62_chanx_left_out ;
wire [0:19] cbx_1__1__62_chanx_right_out ;
wire [0:0] cbx_1__1__63_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__63_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__63_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__63_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__63_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__63_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__63_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__63_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__63_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__63_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__63_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__63_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__63_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__63_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__63_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__63_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__63_ccff_tail ;
wire [0:19] cbx_1__1__63_chanx_left_out ;
wire [0:19] cbx_1__1__63_chanx_right_out ;
wire [0:0] cbx_1__1__64_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__64_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__64_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__64_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__64_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__64_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__64_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__64_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__64_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__64_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__64_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__64_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__64_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__64_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__64_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__64_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__64_ccff_tail ;
wire [0:19] cbx_1__1__64_chanx_left_out ;
wire [0:19] cbx_1__1__64_chanx_right_out ;
wire [0:0] cbx_1__1__65_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__65_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__65_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__65_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__65_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__65_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__65_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__65_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__65_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__65_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__65_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__65_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__65_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__65_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__65_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__65_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__65_ccff_tail ;
wire [0:19] cbx_1__1__65_chanx_left_out ;
wire [0:19] cbx_1__1__65_chanx_right_out ;
wire [0:0] cbx_1__1__66_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__66_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__66_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__66_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__66_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__66_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__66_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__66_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__66_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__66_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__66_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__66_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__66_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__66_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__66_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__66_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__66_ccff_tail ;
wire [0:19] cbx_1__1__66_chanx_left_out ;
wire [0:19] cbx_1__1__66_chanx_right_out ;
wire [0:0] cbx_1__1__67_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__67_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__67_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__67_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__67_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__67_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__67_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__67_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__67_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__67_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__67_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__67_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__67_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__67_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__67_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__67_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__67_ccff_tail ;
wire [0:19] cbx_1__1__67_chanx_left_out ;
wire [0:19] cbx_1__1__67_chanx_right_out ;
wire [0:0] cbx_1__1__68_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__68_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__68_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__68_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__68_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__68_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__68_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__68_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__68_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__68_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__68_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__68_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__68_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__68_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__68_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__68_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__68_ccff_tail ;
wire [0:19] cbx_1__1__68_chanx_left_out ;
wire [0:19] cbx_1__1__68_chanx_right_out ;
wire [0:0] cbx_1__1__69_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__69_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__69_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__69_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__69_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__69_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__69_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__69_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__69_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__69_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__69_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__69_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__69_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__69_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__69_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__69_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__69_ccff_tail ;
wire [0:19] cbx_1__1__69_chanx_left_out ;
wire [0:19] cbx_1__1__69_chanx_right_out ;
wire [0:0] cbx_1__1__6_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__6_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__6_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__6_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__6_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__6_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__6_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__6_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__6_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__6_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__6_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__6_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__6_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__6_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__6_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__6_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__6_ccff_tail ;
wire [0:19] cbx_1__1__6_chanx_left_out ;
wire [0:19] cbx_1__1__6_chanx_right_out ;
wire [0:0] cbx_1__1__70_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__70_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__70_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__70_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__70_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__70_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__70_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__70_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__70_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__70_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__70_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__70_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__70_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__70_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__70_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__70_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__70_ccff_tail ;
wire [0:19] cbx_1__1__70_chanx_left_out ;
wire [0:19] cbx_1__1__70_chanx_right_out ;
wire [0:0] cbx_1__1__71_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__71_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__71_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__71_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__71_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__71_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__71_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__71_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__71_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__71_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__71_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__71_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__71_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__71_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__71_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__71_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__71_ccff_tail ;
wire [0:19] cbx_1__1__71_chanx_left_out ;
wire [0:19] cbx_1__1__71_chanx_right_out ;
wire [0:0] cbx_1__1__72_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__72_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__72_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__72_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__72_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__72_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__72_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__72_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__72_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__72_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__72_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__72_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__72_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__72_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__72_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__72_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__72_ccff_tail ;
wire [0:19] cbx_1__1__72_chanx_left_out ;
wire [0:19] cbx_1__1__72_chanx_right_out ;
wire [0:0] cbx_1__1__73_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__73_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__73_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__73_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__73_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__73_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__73_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__73_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__73_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__73_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__73_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__73_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__73_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__73_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__73_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__73_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__73_ccff_tail ;
wire [0:19] cbx_1__1__73_chanx_left_out ;
wire [0:19] cbx_1__1__73_chanx_right_out ;
wire [0:0] cbx_1__1__74_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__74_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__74_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__74_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__74_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__74_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__74_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__74_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__74_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__74_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__74_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__74_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__74_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__74_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__74_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__74_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__74_ccff_tail ;
wire [0:19] cbx_1__1__74_chanx_left_out ;
wire [0:19] cbx_1__1__74_chanx_right_out ;
wire [0:0] cbx_1__1__75_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__75_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__75_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__75_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__75_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__75_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__75_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__75_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__75_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__75_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__75_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__75_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__75_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__75_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__75_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__75_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__75_ccff_tail ;
wire [0:19] cbx_1__1__75_chanx_left_out ;
wire [0:19] cbx_1__1__75_chanx_right_out ;
wire [0:0] cbx_1__1__76_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__76_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__76_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__76_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__76_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__76_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__76_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__76_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__76_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__76_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__76_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__76_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__76_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__76_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__76_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__76_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__76_ccff_tail ;
wire [0:19] cbx_1__1__76_chanx_left_out ;
wire [0:19] cbx_1__1__76_chanx_right_out ;
wire [0:0] cbx_1__1__77_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__77_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__77_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__77_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__77_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__77_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__77_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__77_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__77_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__77_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__77_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__77_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__77_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__77_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__77_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__77_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__77_ccff_tail ;
wire [0:19] cbx_1__1__77_chanx_left_out ;
wire [0:19] cbx_1__1__77_chanx_right_out ;
wire [0:0] cbx_1__1__78_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__78_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__78_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__78_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__78_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__78_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__78_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__78_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__78_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__78_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__78_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__78_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__78_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__78_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__78_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__78_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__78_ccff_tail ;
wire [0:19] cbx_1__1__78_chanx_left_out ;
wire [0:19] cbx_1__1__78_chanx_right_out ;
wire [0:0] cbx_1__1__79_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__79_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__79_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__79_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__79_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__79_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__79_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__79_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__79_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__79_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__79_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__79_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__79_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__79_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__79_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__79_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__79_ccff_tail ;
wire [0:19] cbx_1__1__79_chanx_left_out ;
wire [0:19] cbx_1__1__79_chanx_right_out ;
wire [0:0] cbx_1__1__7_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__7_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__7_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__7_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__7_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__7_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__7_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__7_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__7_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__7_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__7_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__7_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__7_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__7_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__7_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__7_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__7_ccff_tail ;
wire [0:19] cbx_1__1__7_chanx_left_out ;
wire [0:19] cbx_1__1__7_chanx_right_out ;
wire [0:0] cbx_1__1__80_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__80_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__80_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__80_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__80_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__80_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__80_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__80_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__80_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__80_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__80_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__80_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__80_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__80_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__80_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__80_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__80_ccff_tail ;
wire [0:19] cbx_1__1__80_chanx_left_out ;
wire [0:19] cbx_1__1__80_chanx_right_out ;
wire [0:0] cbx_1__1__81_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__81_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__81_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__81_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__81_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__81_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__81_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__81_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__81_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__81_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__81_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__81_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__81_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__81_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__81_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__81_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__81_ccff_tail ;
wire [0:19] cbx_1__1__81_chanx_left_out ;
wire [0:19] cbx_1__1__81_chanx_right_out ;
wire [0:0] cbx_1__1__82_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__82_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__82_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__82_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__82_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__82_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__82_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__82_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__82_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__82_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__82_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__82_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__82_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__82_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__82_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__82_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__82_ccff_tail ;
wire [0:19] cbx_1__1__82_chanx_left_out ;
wire [0:19] cbx_1__1__82_chanx_right_out ;
wire [0:0] cbx_1__1__83_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__83_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__83_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__83_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__83_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__83_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__83_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__83_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__83_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__83_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__83_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__83_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__83_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__83_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__83_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__83_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__83_ccff_tail ;
wire [0:19] cbx_1__1__83_chanx_left_out ;
wire [0:19] cbx_1__1__83_chanx_right_out ;
wire [0:0] cbx_1__1__84_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__84_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__84_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__84_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__84_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__84_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__84_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__84_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__84_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__84_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__84_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__84_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__84_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__84_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__84_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__84_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__84_ccff_tail ;
wire [0:19] cbx_1__1__84_chanx_left_out ;
wire [0:19] cbx_1__1__84_chanx_right_out ;
wire [0:0] cbx_1__1__85_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__85_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__85_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__85_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__85_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__85_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__85_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__85_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__85_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__85_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__85_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__85_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__85_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__85_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__85_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__85_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__85_ccff_tail ;
wire [0:19] cbx_1__1__85_chanx_left_out ;
wire [0:19] cbx_1__1__85_chanx_right_out ;
wire [0:0] cbx_1__1__86_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__86_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__86_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__86_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__86_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__86_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__86_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__86_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__86_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__86_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__86_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__86_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__86_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__86_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__86_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__86_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__86_ccff_tail ;
wire [0:19] cbx_1__1__86_chanx_left_out ;
wire [0:19] cbx_1__1__86_chanx_right_out ;
wire [0:0] cbx_1__1__87_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__87_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__87_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__87_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__87_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__87_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__87_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__87_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__87_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__87_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__87_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__87_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__87_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__87_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__87_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__87_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__87_ccff_tail ;
wire [0:19] cbx_1__1__87_chanx_left_out ;
wire [0:19] cbx_1__1__87_chanx_right_out ;
wire [0:0] cbx_1__1__88_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__88_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__88_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__88_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__88_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__88_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__88_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__88_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__88_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__88_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__88_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__88_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__88_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__88_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__88_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__88_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__88_ccff_tail ;
wire [0:19] cbx_1__1__88_chanx_left_out ;
wire [0:19] cbx_1__1__88_chanx_right_out ;
wire [0:0] cbx_1__1__89_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__89_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__89_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__89_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__89_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__89_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__89_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__89_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__89_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__89_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__89_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__89_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__89_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__89_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__89_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__89_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__89_ccff_tail ;
wire [0:19] cbx_1__1__89_chanx_left_out ;
wire [0:19] cbx_1__1__89_chanx_right_out ;
wire [0:0] cbx_1__1__8_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__8_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__8_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__8_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__8_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__8_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__8_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__8_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__8_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__8_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__8_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__8_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__8_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__8_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__8_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__8_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__8_ccff_tail ;
wire [0:19] cbx_1__1__8_chanx_left_out ;
wire [0:19] cbx_1__1__8_chanx_right_out ;
wire [0:0] cbx_1__1__90_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__90_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__90_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__90_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__90_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__90_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__90_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__90_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__90_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__90_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__90_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__90_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__90_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__90_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__90_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__90_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__90_ccff_tail ;
wire [0:19] cbx_1__1__90_chanx_left_out ;
wire [0:19] cbx_1__1__90_chanx_right_out ;
wire [0:0] cbx_1__1__91_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__91_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__91_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__91_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__91_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__91_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__91_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__91_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__91_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__91_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__91_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__91_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__91_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__91_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__91_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__91_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__91_ccff_tail ;
wire [0:19] cbx_1__1__91_chanx_left_out ;
wire [0:19] cbx_1__1__91_chanx_right_out ;
wire [0:0] cbx_1__1__92_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__92_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__92_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__92_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__92_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__92_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__92_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__92_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__92_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__92_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__92_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__92_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__92_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__92_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__92_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__92_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__92_ccff_tail ;
wire [0:19] cbx_1__1__92_chanx_left_out ;
wire [0:19] cbx_1__1__92_chanx_right_out ;
wire [0:0] cbx_1__1__93_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__93_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__93_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__93_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__93_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__93_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__93_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__93_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__93_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__93_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__93_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__93_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__93_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__93_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__93_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__93_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__93_ccff_tail ;
wire [0:19] cbx_1__1__93_chanx_left_out ;
wire [0:19] cbx_1__1__93_chanx_right_out ;
wire [0:0] cbx_1__1__94_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__94_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__94_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__94_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__94_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__94_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__94_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__94_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__94_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__94_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__94_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__94_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__94_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__94_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__94_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__94_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__94_ccff_tail ;
wire [0:19] cbx_1__1__94_chanx_left_out ;
wire [0:19] cbx_1__1__94_chanx_right_out ;
wire [0:0] cbx_1__1__95_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__95_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__95_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__95_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__95_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__95_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__95_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__95_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__95_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__95_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__95_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__95_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__95_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__95_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__95_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__95_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__95_ccff_tail ;
wire [0:19] cbx_1__1__95_chanx_left_out ;
wire [0:19] cbx_1__1__95_chanx_right_out ;
wire [0:0] cbx_1__1__96_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__96_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__96_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__96_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__96_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__96_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__96_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__96_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__96_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__96_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__96_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__96_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__96_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__96_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__96_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__96_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__96_ccff_tail ;
wire [0:19] cbx_1__1__96_chanx_left_out ;
wire [0:19] cbx_1__1__96_chanx_right_out ;
wire [0:0] cbx_1__1__97_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__97_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__97_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__97_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__97_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__97_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__97_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__97_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__97_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__97_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__97_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__97_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__97_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__97_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__97_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__97_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__97_ccff_tail ;
wire [0:19] cbx_1__1__97_chanx_left_out ;
wire [0:19] cbx_1__1__97_chanx_right_out ;
wire [0:0] cbx_1__1__98_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__98_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__98_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__98_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__98_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__98_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__98_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__98_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__98_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__98_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__98_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__98_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__98_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__98_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__98_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__98_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__98_ccff_tail ;
wire [0:19] cbx_1__1__98_chanx_left_out ;
wire [0:19] cbx_1__1__98_chanx_right_out ;
wire [0:0] cbx_1__1__99_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__99_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__99_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__99_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__99_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__99_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__99_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__99_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__99_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__99_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__99_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__99_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__99_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__99_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__99_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__99_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__99_ccff_tail ;
wire [0:19] cbx_1__1__99_chanx_left_out ;
wire [0:19] cbx_1__1__99_chanx_right_out ;
wire [0:0] cbx_1__1__9_bottom_grid_pin_0_ ;
wire [0:0] cbx_1__1__9_bottom_grid_pin_10_ ;
wire [0:0] cbx_1__1__9_bottom_grid_pin_11_ ;
wire [0:0] cbx_1__1__9_bottom_grid_pin_12_ ;
wire [0:0] cbx_1__1__9_bottom_grid_pin_13_ ;
wire [0:0] cbx_1__1__9_bottom_grid_pin_14_ ;
wire [0:0] cbx_1__1__9_bottom_grid_pin_15_ ;
wire [0:0] cbx_1__1__9_bottom_grid_pin_1_ ;
wire [0:0] cbx_1__1__9_bottom_grid_pin_2_ ;
wire [0:0] cbx_1__1__9_bottom_grid_pin_3_ ;
wire [0:0] cbx_1__1__9_bottom_grid_pin_4_ ;
wire [0:0] cbx_1__1__9_bottom_grid_pin_5_ ;
wire [0:0] cbx_1__1__9_bottom_grid_pin_6_ ;
wire [0:0] cbx_1__1__9_bottom_grid_pin_7_ ;
wire [0:0] cbx_1__1__9_bottom_grid_pin_8_ ;
wire [0:0] cbx_1__1__9_bottom_grid_pin_9_ ;
wire [0:0] cbx_1__1__9_ccff_tail ;
wire [0:19] cbx_1__1__9_chanx_left_out ;
wire [0:19] cbx_1__1__9_chanx_right_out ;
wire [0:19] cby_0__1__0_chany_bottom_out ;
wire [0:19] cby_0__1__0_chany_top_out ;
wire [0:0] cby_0__1__0_left_grid_pin_0_ ;
wire [0:19] cby_0__1__10_chany_bottom_out ;
wire [0:19] cby_0__1__10_chany_top_out ;
wire [0:0] cby_0__1__10_left_grid_pin_0_ ;
wire [0:19] cby_0__1__11_chany_bottom_out ;
wire [0:19] cby_0__1__11_chany_top_out ;
wire [0:0] cby_0__1__11_left_grid_pin_0_ ;
wire [0:19] cby_0__1__1_chany_bottom_out ;
wire [0:19] cby_0__1__1_chany_top_out ;
wire [0:0] cby_0__1__1_left_grid_pin_0_ ;
wire [0:19] cby_0__1__2_chany_bottom_out ;
wire [0:19] cby_0__1__2_chany_top_out ;
wire [0:0] cby_0__1__2_left_grid_pin_0_ ;
wire [0:19] cby_0__1__3_chany_bottom_out ;
wire [0:19] cby_0__1__3_chany_top_out ;
wire [0:0] cby_0__1__3_left_grid_pin_0_ ;
wire [0:19] cby_0__1__4_chany_bottom_out ;
wire [0:19] cby_0__1__4_chany_top_out ;
wire [0:0] cby_0__1__4_left_grid_pin_0_ ;
wire [0:19] cby_0__1__5_chany_bottom_out ;
wire [0:19] cby_0__1__5_chany_top_out ;
wire [0:0] cby_0__1__5_left_grid_pin_0_ ;
wire [0:19] cby_0__1__6_chany_bottom_out ;
wire [0:19] cby_0__1__6_chany_top_out ;
wire [0:0] cby_0__1__6_left_grid_pin_0_ ;
wire [0:19] cby_0__1__7_chany_bottom_out ;
wire [0:19] cby_0__1__7_chany_top_out ;
wire [0:0] cby_0__1__7_left_grid_pin_0_ ;
wire [0:19] cby_0__1__8_chany_bottom_out ;
wire [0:19] cby_0__1__8_chany_top_out ;
wire [0:0] cby_0__1__8_left_grid_pin_0_ ;
wire [0:19] cby_0__1__9_chany_bottom_out ;
wire [0:19] cby_0__1__9_chany_top_out ;
wire [0:0] cby_0__1__9_left_grid_pin_0_ ;
wire [0:19] cby_12__1__0_chany_bottom_out ;
wire [0:19] cby_12__1__0_chany_top_out ;
wire [0:0] cby_12__1__0_left_grid_pin_16_ ;
wire [0:0] cby_12__1__0_left_grid_pin_17_ ;
wire [0:0] cby_12__1__0_left_grid_pin_18_ ;
wire [0:0] cby_12__1__0_left_grid_pin_19_ ;
wire [0:0] cby_12__1__0_left_grid_pin_20_ ;
wire [0:0] cby_12__1__0_left_grid_pin_21_ ;
wire [0:0] cby_12__1__0_left_grid_pin_22_ ;
wire [0:0] cby_12__1__0_left_grid_pin_23_ ;
wire [0:0] cby_12__1__0_left_grid_pin_24_ ;
wire [0:0] cby_12__1__0_left_grid_pin_25_ ;
wire [0:0] cby_12__1__0_left_grid_pin_26_ ;
wire [0:0] cby_12__1__0_left_grid_pin_27_ ;
wire [0:0] cby_12__1__0_left_grid_pin_28_ ;
wire [0:0] cby_12__1__0_left_grid_pin_29_ ;
wire [0:0] cby_12__1__0_left_grid_pin_30_ ;
wire [0:0] cby_12__1__0_left_grid_pin_31_ ;
wire [0:0] cby_12__1__0_right_grid_pin_0_ ;
wire [0:19] cby_12__1__10_chany_bottom_out ;
wire [0:19] cby_12__1__10_chany_top_out ;
wire [0:0] cby_12__1__10_left_grid_pin_16_ ;
wire [0:0] cby_12__1__10_left_grid_pin_17_ ;
wire [0:0] cby_12__1__10_left_grid_pin_18_ ;
wire [0:0] cby_12__1__10_left_grid_pin_19_ ;
wire [0:0] cby_12__1__10_left_grid_pin_20_ ;
wire [0:0] cby_12__1__10_left_grid_pin_21_ ;
wire [0:0] cby_12__1__10_left_grid_pin_22_ ;
wire [0:0] cby_12__1__10_left_grid_pin_23_ ;
wire [0:0] cby_12__1__10_left_grid_pin_24_ ;
wire [0:0] cby_12__1__10_left_grid_pin_25_ ;
wire [0:0] cby_12__1__10_left_grid_pin_26_ ;
wire [0:0] cby_12__1__10_left_grid_pin_27_ ;
wire [0:0] cby_12__1__10_left_grid_pin_28_ ;
wire [0:0] cby_12__1__10_left_grid_pin_29_ ;
wire [0:0] cby_12__1__10_left_grid_pin_30_ ;
wire [0:0] cby_12__1__10_left_grid_pin_31_ ;
wire [0:0] cby_12__1__10_right_grid_pin_0_ ;
wire [0:19] cby_12__1__11_chany_bottom_out ;
wire [0:19] cby_12__1__11_chany_top_out ;
wire [0:0] cby_12__1__11_left_grid_pin_16_ ;
wire [0:0] cby_12__1__11_left_grid_pin_17_ ;
wire [0:0] cby_12__1__11_left_grid_pin_18_ ;
wire [0:0] cby_12__1__11_left_grid_pin_19_ ;
wire [0:0] cby_12__1__11_left_grid_pin_20_ ;
wire [0:0] cby_12__1__11_left_grid_pin_21_ ;
wire [0:0] cby_12__1__11_left_grid_pin_22_ ;
wire [0:0] cby_12__1__11_left_grid_pin_23_ ;
wire [0:0] cby_12__1__11_left_grid_pin_24_ ;
wire [0:0] cby_12__1__11_left_grid_pin_25_ ;
wire [0:0] cby_12__1__11_left_grid_pin_26_ ;
wire [0:0] cby_12__1__11_left_grid_pin_27_ ;
wire [0:0] cby_12__1__11_left_grid_pin_28_ ;
wire [0:0] cby_12__1__11_left_grid_pin_29_ ;
wire [0:0] cby_12__1__11_left_grid_pin_30_ ;
wire [0:0] cby_12__1__11_left_grid_pin_31_ ;
wire [0:0] cby_12__1__11_right_grid_pin_0_ ;
wire [0:19] cby_12__1__1_chany_bottom_out ;
wire [0:19] cby_12__1__1_chany_top_out ;
wire [0:0] cby_12__1__1_left_grid_pin_16_ ;
wire [0:0] cby_12__1__1_left_grid_pin_17_ ;
wire [0:0] cby_12__1__1_left_grid_pin_18_ ;
wire [0:0] cby_12__1__1_left_grid_pin_19_ ;
wire [0:0] cby_12__1__1_left_grid_pin_20_ ;
wire [0:0] cby_12__1__1_left_grid_pin_21_ ;
wire [0:0] cby_12__1__1_left_grid_pin_22_ ;
wire [0:0] cby_12__1__1_left_grid_pin_23_ ;
wire [0:0] cby_12__1__1_left_grid_pin_24_ ;
wire [0:0] cby_12__1__1_left_grid_pin_25_ ;
wire [0:0] cby_12__1__1_left_grid_pin_26_ ;
wire [0:0] cby_12__1__1_left_grid_pin_27_ ;
wire [0:0] cby_12__1__1_left_grid_pin_28_ ;
wire [0:0] cby_12__1__1_left_grid_pin_29_ ;
wire [0:0] cby_12__1__1_left_grid_pin_30_ ;
wire [0:0] cby_12__1__1_left_grid_pin_31_ ;
wire [0:0] cby_12__1__1_right_grid_pin_0_ ;
wire [0:19] cby_12__1__2_chany_bottom_out ;
wire [0:19] cby_12__1__2_chany_top_out ;
wire [0:0] cby_12__1__2_left_grid_pin_16_ ;
wire [0:0] cby_12__1__2_left_grid_pin_17_ ;
wire [0:0] cby_12__1__2_left_grid_pin_18_ ;
wire [0:0] cby_12__1__2_left_grid_pin_19_ ;
wire [0:0] cby_12__1__2_left_grid_pin_20_ ;
wire [0:0] cby_12__1__2_left_grid_pin_21_ ;
wire [0:0] cby_12__1__2_left_grid_pin_22_ ;
wire [0:0] cby_12__1__2_left_grid_pin_23_ ;
wire [0:0] cby_12__1__2_left_grid_pin_24_ ;
wire [0:0] cby_12__1__2_left_grid_pin_25_ ;
wire [0:0] cby_12__1__2_left_grid_pin_26_ ;
wire [0:0] cby_12__1__2_left_grid_pin_27_ ;
wire [0:0] cby_12__1__2_left_grid_pin_28_ ;
wire [0:0] cby_12__1__2_left_grid_pin_29_ ;
wire [0:0] cby_12__1__2_left_grid_pin_30_ ;
wire [0:0] cby_12__1__2_left_grid_pin_31_ ;
wire [0:0] cby_12__1__2_right_grid_pin_0_ ;
wire [0:19] cby_12__1__3_chany_bottom_out ;
wire [0:19] cby_12__1__3_chany_top_out ;
wire [0:0] cby_12__1__3_left_grid_pin_16_ ;
wire [0:0] cby_12__1__3_left_grid_pin_17_ ;
wire [0:0] cby_12__1__3_left_grid_pin_18_ ;
wire [0:0] cby_12__1__3_left_grid_pin_19_ ;
wire [0:0] cby_12__1__3_left_grid_pin_20_ ;
wire [0:0] cby_12__1__3_left_grid_pin_21_ ;
wire [0:0] cby_12__1__3_left_grid_pin_22_ ;
wire [0:0] cby_12__1__3_left_grid_pin_23_ ;
wire [0:0] cby_12__1__3_left_grid_pin_24_ ;
wire [0:0] cby_12__1__3_left_grid_pin_25_ ;
wire [0:0] cby_12__1__3_left_grid_pin_26_ ;
wire [0:0] cby_12__1__3_left_grid_pin_27_ ;
wire [0:0] cby_12__1__3_left_grid_pin_28_ ;
wire [0:0] cby_12__1__3_left_grid_pin_29_ ;
wire [0:0] cby_12__1__3_left_grid_pin_30_ ;
wire [0:0] cby_12__1__3_left_grid_pin_31_ ;
wire [0:0] cby_12__1__3_right_grid_pin_0_ ;
wire [0:19] cby_12__1__4_chany_bottom_out ;
wire [0:19] cby_12__1__4_chany_top_out ;
wire [0:0] cby_12__1__4_left_grid_pin_16_ ;
wire [0:0] cby_12__1__4_left_grid_pin_17_ ;
wire [0:0] cby_12__1__4_left_grid_pin_18_ ;
wire [0:0] cby_12__1__4_left_grid_pin_19_ ;
wire [0:0] cby_12__1__4_left_grid_pin_20_ ;
wire [0:0] cby_12__1__4_left_grid_pin_21_ ;
wire [0:0] cby_12__1__4_left_grid_pin_22_ ;
wire [0:0] cby_12__1__4_left_grid_pin_23_ ;
wire [0:0] cby_12__1__4_left_grid_pin_24_ ;
wire [0:0] cby_12__1__4_left_grid_pin_25_ ;
wire [0:0] cby_12__1__4_left_grid_pin_26_ ;
wire [0:0] cby_12__1__4_left_grid_pin_27_ ;
wire [0:0] cby_12__1__4_left_grid_pin_28_ ;
wire [0:0] cby_12__1__4_left_grid_pin_29_ ;
wire [0:0] cby_12__1__4_left_grid_pin_30_ ;
wire [0:0] cby_12__1__4_left_grid_pin_31_ ;
wire [0:0] cby_12__1__4_right_grid_pin_0_ ;
wire [0:19] cby_12__1__5_chany_bottom_out ;
wire [0:19] cby_12__1__5_chany_top_out ;
wire [0:0] cby_12__1__5_left_grid_pin_16_ ;
wire [0:0] cby_12__1__5_left_grid_pin_17_ ;
wire [0:0] cby_12__1__5_left_grid_pin_18_ ;
wire [0:0] cby_12__1__5_left_grid_pin_19_ ;
wire [0:0] cby_12__1__5_left_grid_pin_20_ ;
wire [0:0] cby_12__1__5_left_grid_pin_21_ ;
wire [0:0] cby_12__1__5_left_grid_pin_22_ ;
wire [0:0] cby_12__1__5_left_grid_pin_23_ ;
wire [0:0] cby_12__1__5_left_grid_pin_24_ ;
wire [0:0] cby_12__1__5_left_grid_pin_25_ ;
wire [0:0] cby_12__1__5_left_grid_pin_26_ ;
wire [0:0] cby_12__1__5_left_grid_pin_27_ ;
wire [0:0] cby_12__1__5_left_grid_pin_28_ ;
wire [0:0] cby_12__1__5_left_grid_pin_29_ ;
wire [0:0] cby_12__1__5_left_grid_pin_30_ ;
wire [0:0] cby_12__1__5_left_grid_pin_31_ ;
wire [0:0] cby_12__1__5_right_grid_pin_0_ ;
wire [0:19] cby_12__1__6_chany_bottom_out ;
wire [0:19] cby_12__1__6_chany_top_out ;
wire [0:0] cby_12__1__6_left_grid_pin_16_ ;
wire [0:0] cby_12__1__6_left_grid_pin_17_ ;
wire [0:0] cby_12__1__6_left_grid_pin_18_ ;
wire [0:0] cby_12__1__6_left_grid_pin_19_ ;
wire [0:0] cby_12__1__6_left_grid_pin_20_ ;
wire [0:0] cby_12__1__6_left_grid_pin_21_ ;
wire [0:0] cby_12__1__6_left_grid_pin_22_ ;
wire [0:0] cby_12__1__6_left_grid_pin_23_ ;
wire [0:0] cby_12__1__6_left_grid_pin_24_ ;
wire [0:0] cby_12__1__6_left_grid_pin_25_ ;
wire [0:0] cby_12__1__6_left_grid_pin_26_ ;
wire [0:0] cby_12__1__6_left_grid_pin_27_ ;
wire [0:0] cby_12__1__6_left_grid_pin_28_ ;
wire [0:0] cby_12__1__6_left_grid_pin_29_ ;
wire [0:0] cby_12__1__6_left_grid_pin_30_ ;
wire [0:0] cby_12__1__6_left_grid_pin_31_ ;
wire [0:0] cby_12__1__6_right_grid_pin_0_ ;
wire [0:19] cby_12__1__7_chany_bottom_out ;
wire [0:19] cby_12__1__7_chany_top_out ;
wire [0:0] cby_12__1__7_left_grid_pin_16_ ;
wire [0:0] cby_12__1__7_left_grid_pin_17_ ;
wire [0:0] cby_12__1__7_left_grid_pin_18_ ;
wire [0:0] cby_12__1__7_left_grid_pin_19_ ;
wire [0:0] cby_12__1__7_left_grid_pin_20_ ;
wire [0:0] cby_12__1__7_left_grid_pin_21_ ;
wire [0:0] cby_12__1__7_left_grid_pin_22_ ;
wire [0:0] cby_12__1__7_left_grid_pin_23_ ;
wire [0:0] cby_12__1__7_left_grid_pin_24_ ;
wire [0:0] cby_12__1__7_left_grid_pin_25_ ;
wire [0:0] cby_12__1__7_left_grid_pin_26_ ;
wire [0:0] cby_12__1__7_left_grid_pin_27_ ;
wire [0:0] cby_12__1__7_left_grid_pin_28_ ;
wire [0:0] cby_12__1__7_left_grid_pin_29_ ;
wire [0:0] cby_12__1__7_left_grid_pin_30_ ;
wire [0:0] cby_12__1__7_left_grid_pin_31_ ;
wire [0:0] cby_12__1__7_right_grid_pin_0_ ;
wire [0:19] cby_12__1__8_chany_bottom_out ;
wire [0:19] cby_12__1__8_chany_top_out ;
wire [0:0] cby_12__1__8_left_grid_pin_16_ ;
wire [0:0] cby_12__1__8_left_grid_pin_17_ ;
wire [0:0] cby_12__1__8_left_grid_pin_18_ ;
wire [0:0] cby_12__1__8_left_grid_pin_19_ ;
wire [0:0] cby_12__1__8_left_grid_pin_20_ ;
wire [0:0] cby_12__1__8_left_grid_pin_21_ ;
wire [0:0] cby_12__1__8_left_grid_pin_22_ ;
wire [0:0] cby_12__1__8_left_grid_pin_23_ ;
wire [0:0] cby_12__1__8_left_grid_pin_24_ ;
wire [0:0] cby_12__1__8_left_grid_pin_25_ ;
wire [0:0] cby_12__1__8_left_grid_pin_26_ ;
wire [0:0] cby_12__1__8_left_grid_pin_27_ ;
wire [0:0] cby_12__1__8_left_grid_pin_28_ ;
wire [0:0] cby_12__1__8_left_grid_pin_29_ ;
wire [0:0] cby_12__1__8_left_grid_pin_30_ ;
wire [0:0] cby_12__1__8_left_grid_pin_31_ ;
wire [0:0] cby_12__1__8_right_grid_pin_0_ ;
wire [0:19] cby_12__1__9_chany_bottom_out ;
wire [0:19] cby_12__1__9_chany_top_out ;
wire [0:0] cby_12__1__9_left_grid_pin_16_ ;
wire [0:0] cby_12__1__9_left_grid_pin_17_ ;
wire [0:0] cby_12__1__9_left_grid_pin_18_ ;
wire [0:0] cby_12__1__9_left_grid_pin_19_ ;
wire [0:0] cby_12__1__9_left_grid_pin_20_ ;
wire [0:0] cby_12__1__9_left_grid_pin_21_ ;
wire [0:0] cby_12__1__9_left_grid_pin_22_ ;
wire [0:0] cby_12__1__9_left_grid_pin_23_ ;
wire [0:0] cby_12__1__9_left_grid_pin_24_ ;
wire [0:0] cby_12__1__9_left_grid_pin_25_ ;
wire [0:0] cby_12__1__9_left_grid_pin_26_ ;
wire [0:0] cby_12__1__9_left_grid_pin_27_ ;
wire [0:0] cby_12__1__9_left_grid_pin_28_ ;
wire [0:0] cby_12__1__9_left_grid_pin_29_ ;
wire [0:0] cby_12__1__9_left_grid_pin_30_ ;
wire [0:0] cby_12__1__9_left_grid_pin_31_ ;
wire [0:0] cby_12__1__9_right_grid_pin_0_ ;
wire [0:0] cby_1__1__0_ccff_tail ;
wire [0:19] cby_1__1__0_chany_bottom_out ;
wire [0:19] cby_1__1__0_chany_top_out ;
wire [0:0] cby_1__1__0_left_grid_pin_16_ ;
wire [0:0] cby_1__1__0_left_grid_pin_17_ ;
wire [0:0] cby_1__1__0_left_grid_pin_18_ ;
wire [0:0] cby_1__1__0_left_grid_pin_19_ ;
wire [0:0] cby_1__1__0_left_grid_pin_20_ ;
wire [0:0] cby_1__1__0_left_grid_pin_21_ ;
wire [0:0] cby_1__1__0_left_grid_pin_22_ ;
wire [0:0] cby_1__1__0_left_grid_pin_23_ ;
wire [0:0] cby_1__1__0_left_grid_pin_24_ ;
wire [0:0] cby_1__1__0_left_grid_pin_25_ ;
wire [0:0] cby_1__1__0_left_grid_pin_26_ ;
wire [0:0] cby_1__1__0_left_grid_pin_27_ ;
wire [0:0] cby_1__1__0_left_grid_pin_28_ ;
wire [0:0] cby_1__1__0_left_grid_pin_29_ ;
wire [0:0] cby_1__1__0_left_grid_pin_30_ ;
wire [0:0] cby_1__1__0_left_grid_pin_31_ ;
wire [0:0] cby_1__1__100_ccff_tail ;
wire [0:19] cby_1__1__100_chany_bottom_out ;
wire [0:19] cby_1__1__100_chany_top_out ;
wire [0:0] cby_1__1__100_left_grid_pin_16_ ;
wire [0:0] cby_1__1__100_left_grid_pin_17_ ;
wire [0:0] cby_1__1__100_left_grid_pin_18_ ;
wire [0:0] cby_1__1__100_left_grid_pin_19_ ;
wire [0:0] cby_1__1__100_left_grid_pin_20_ ;
wire [0:0] cby_1__1__100_left_grid_pin_21_ ;
wire [0:0] cby_1__1__100_left_grid_pin_22_ ;
wire [0:0] cby_1__1__100_left_grid_pin_23_ ;
wire [0:0] cby_1__1__100_left_grid_pin_24_ ;
wire [0:0] cby_1__1__100_left_grid_pin_25_ ;
wire [0:0] cby_1__1__100_left_grid_pin_26_ ;
wire [0:0] cby_1__1__100_left_grid_pin_27_ ;
wire [0:0] cby_1__1__100_left_grid_pin_28_ ;
wire [0:0] cby_1__1__100_left_grid_pin_29_ ;
wire [0:0] cby_1__1__100_left_grid_pin_30_ ;
wire [0:0] cby_1__1__100_left_grid_pin_31_ ;
wire [0:0] cby_1__1__101_ccff_tail ;
wire [0:19] cby_1__1__101_chany_bottom_out ;
wire [0:19] cby_1__1__101_chany_top_out ;
wire [0:0] cby_1__1__101_left_grid_pin_16_ ;
wire [0:0] cby_1__1__101_left_grid_pin_17_ ;
wire [0:0] cby_1__1__101_left_grid_pin_18_ ;
wire [0:0] cby_1__1__101_left_grid_pin_19_ ;
wire [0:0] cby_1__1__101_left_grid_pin_20_ ;
wire [0:0] cby_1__1__101_left_grid_pin_21_ ;
wire [0:0] cby_1__1__101_left_grid_pin_22_ ;
wire [0:0] cby_1__1__101_left_grid_pin_23_ ;
wire [0:0] cby_1__1__101_left_grid_pin_24_ ;
wire [0:0] cby_1__1__101_left_grid_pin_25_ ;
wire [0:0] cby_1__1__101_left_grid_pin_26_ ;
wire [0:0] cby_1__1__101_left_grid_pin_27_ ;
wire [0:0] cby_1__1__101_left_grid_pin_28_ ;
wire [0:0] cby_1__1__101_left_grid_pin_29_ ;
wire [0:0] cby_1__1__101_left_grid_pin_30_ ;
wire [0:0] cby_1__1__101_left_grid_pin_31_ ;
wire [0:0] cby_1__1__102_ccff_tail ;
wire [0:19] cby_1__1__102_chany_bottom_out ;
wire [0:19] cby_1__1__102_chany_top_out ;
wire [0:0] cby_1__1__102_left_grid_pin_16_ ;
wire [0:0] cby_1__1__102_left_grid_pin_17_ ;
wire [0:0] cby_1__1__102_left_grid_pin_18_ ;
wire [0:0] cby_1__1__102_left_grid_pin_19_ ;
wire [0:0] cby_1__1__102_left_grid_pin_20_ ;
wire [0:0] cby_1__1__102_left_grid_pin_21_ ;
wire [0:0] cby_1__1__102_left_grid_pin_22_ ;
wire [0:0] cby_1__1__102_left_grid_pin_23_ ;
wire [0:0] cby_1__1__102_left_grid_pin_24_ ;
wire [0:0] cby_1__1__102_left_grid_pin_25_ ;
wire [0:0] cby_1__1__102_left_grid_pin_26_ ;
wire [0:0] cby_1__1__102_left_grid_pin_27_ ;
wire [0:0] cby_1__1__102_left_grid_pin_28_ ;
wire [0:0] cby_1__1__102_left_grid_pin_29_ ;
wire [0:0] cby_1__1__102_left_grid_pin_30_ ;
wire [0:0] cby_1__1__102_left_grid_pin_31_ ;
wire [0:0] cby_1__1__103_ccff_tail ;
wire [0:19] cby_1__1__103_chany_bottom_out ;
wire [0:19] cby_1__1__103_chany_top_out ;
wire [0:0] cby_1__1__103_left_grid_pin_16_ ;
wire [0:0] cby_1__1__103_left_grid_pin_17_ ;
wire [0:0] cby_1__1__103_left_grid_pin_18_ ;
wire [0:0] cby_1__1__103_left_grid_pin_19_ ;
wire [0:0] cby_1__1__103_left_grid_pin_20_ ;
wire [0:0] cby_1__1__103_left_grid_pin_21_ ;
wire [0:0] cby_1__1__103_left_grid_pin_22_ ;
wire [0:0] cby_1__1__103_left_grid_pin_23_ ;
wire [0:0] cby_1__1__103_left_grid_pin_24_ ;
wire [0:0] cby_1__1__103_left_grid_pin_25_ ;
wire [0:0] cby_1__1__103_left_grid_pin_26_ ;
wire [0:0] cby_1__1__103_left_grid_pin_27_ ;
wire [0:0] cby_1__1__103_left_grid_pin_28_ ;
wire [0:0] cby_1__1__103_left_grid_pin_29_ ;
wire [0:0] cby_1__1__103_left_grid_pin_30_ ;
wire [0:0] cby_1__1__103_left_grid_pin_31_ ;
wire [0:0] cby_1__1__104_ccff_tail ;
wire [0:19] cby_1__1__104_chany_bottom_out ;
wire [0:19] cby_1__1__104_chany_top_out ;
wire [0:0] cby_1__1__104_left_grid_pin_16_ ;
wire [0:0] cby_1__1__104_left_grid_pin_17_ ;
wire [0:0] cby_1__1__104_left_grid_pin_18_ ;
wire [0:0] cby_1__1__104_left_grid_pin_19_ ;
wire [0:0] cby_1__1__104_left_grid_pin_20_ ;
wire [0:0] cby_1__1__104_left_grid_pin_21_ ;
wire [0:0] cby_1__1__104_left_grid_pin_22_ ;
wire [0:0] cby_1__1__104_left_grid_pin_23_ ;
wire [0:0] cby_1__1__104_left_grid_pin_24_ ;
wire [0:0] cby_1__1__104_left_grid_pin_25_ ;
wire [0:0] cby_1__1__104_left_grid_pin_26_ ;
wire [0:0] cby_1__1__104_left_grid_pin_27_ ;
wire [0:0] cby_1__1__104_left_grid_pin_28_ ;
wire [0:0] cby_1__1__104_left_grid_pin_29_ ;
wire [0:0] cby_1__1__104_left_grid_pin_30_ ;
wire [0:0] cby_1__1__104_left_grid_pin_31_ ;
wire [0:0] cby_1__1__105_ccff_tail ;
wire [0:19] cby_1__1__105_chany_bottom_out ;
wire [0:19] cby_1__1__105_chany_top_out ;
wire [0:0] cby_1__1__105_left_grid_pin_16_ ;
wire [0:0] cby_1__1__105_left_grid_pin_17_ ;
wire [0:0] cby_1__1__105_left_grid_pin_18_ ;
wire [0:0] cby_1__1__105_left_grid_pin_19_ ;
wire [0:0] cby_1__1__105_left_grid_pin_20_ ;
wire [0:0] cby_1__1__105_left_grid_pin_21_ ;
wire [0:0] cby_1__1__105_left_grid_pin_22_ ;
wire [0:0] cby_1__1__105_left_grid_pin_23_ ;
wire [0:0] cby_1__1__105_left_grid_pin_24_ ;
wire [0:0] cby_1__1__105_left_grid_pin_25_ ;
wire [0:0] cby_1__1__105_left_grid_pin_26_ ;
wire [0:0] cby_1__1__105_left_grid_pin_27_ ;
wire [0:0] cby_1__1__105_left_grid_pin_28_ ;
wire [0:0] cby_1__1__105_left_grid_pin_29_ ;
wire [0:0] cby_1__1__105_left_grid_pin_30_ ;
wire [0:0] cby_1__1__105_left_grid_pin_31_ ;
wire [0:0] cby_1__1__106_ccff_tail ;
wire [0:19] cby_1__1__106_chany_bottom_out ;
wire [0:19] cby_1__1__106_chany_top_out ;
wire [0:0] cby_1__1__106_left_grid_pin_16_ ;
wire [0:0] cby_1__1__106_left_grid_pin_17_ ;
wire [0:0] cby_1__1__106_left_grid_pin_18_ ;
wire [0:0] cby_1__1__106_left_grid_pin_19_ ;
wire [0:0] cby_1__1__106_left_grid_pin_20_ ;
wire [0:0] cby_1__1__106_left_grid_pin_21_ ;
wire [0:0] cby_1__1__106_left_grid_pin_22_ ;
wire [0:0] cby_1__1__106_left_grid_pin_23_ ;
wire [0:0] cby_1__1__106_left_grid_pin_24_ ;
wire [0:0] cby_1__1__106_left_grid_pin_25_ ;
wire [0:0] cby_1__1__106_left_grid_pin_26_ ;
wire [0:0] cby_1__1__106_left_grid_pin_27_ ;
wire [0:0] cby_1__1__106_left_grid_pin_28_ ;
wire [0:0] cby_1__1__106_left_grid_pin_29_ ;
wire [0:0] cby_1__1__106_left_grid_pin_30_ ;
wire [0:0] cby_1__1__106_left_grid_pin_31_ ;
wire [0:0] cby_1__1__107_ccff_tail ;
wire [0:19] cby_1__1__107_chany_bottom_out ;
wire [0:19] cby_1__1__107_chany_top_out ;
wire [0:0] cby_1__1__107_left_grid_pin_16_ ;
wire [0:0] cby_1__1__107_left_grid_pin_17_ ;
wire [0:0] cby_1__1__107_left_grid_pin_18_ ;
wire [0:0] cby_1__1__107_left_grid_pin_19_ ;
wire [0:0] cby_1__1__107_left_grid_pin_20_ ;
wire [0:0] cby_1__1__107_left_grid_pin_21_ ;
wire [0:0] cby_1__1__107_left_grid_pin_22_ ;
wire [0:0] cby_1__1__107_left_grid_pin_23_ ;
wire [0:0] cby_1__1__107_left_grid_pin_24_ ;
wire [0:0] cby_1__1__107_left_grid_pin_25_ ;
wire [0:0] cby_1__1__107_left_grid_pin_26_ ;
wire [0:0] cby_1__1__107_left_grid_pin_27_ ;
wire [0:0] cby_1__1__107_left_grid_pin_28_ ;
wire [0:0] cby_1__1__107_left_grid_pin_29_ ;
wire [0:0] cby_1__1__107_left_grid_pin_30_ ;
wire [0:0] cby_1__1__107_left_grid_pin_31_ ;
wire [0:0] cby_1__1__108_ccff_tail ;
wire [0:19] cby_1__1__108_chany_bottom_out ;
wire [0:19] cby_1__1__108_chany_top_out ;
wire [0:0] cby_1__1__108_left_grid_pin_16_ ;
wire [0:0] cby_1__1__108_left_grid_pin_17_ ;
wire [0:0] cby_1__1__108_left_grid_pin_18_ ;
wire [0:0] cby_1__1__108_left_grid_pin_19_ ;
wire [0:0] cby_1__1__108_left_grid_pin_20_ ;
wire [0:0] cby_1__1__108_left_grid_pin_21_ ;
wire [0:0] cby_1__1__108_left_grid_pin_22_ ;
wire [0:0] cby_1__1__108_left_grid_pin_23_ ;
wire [0:0] cby_1__1__108_left_grid_pin_24_ ;
wire [0:0] cby_1__1__108_left_grid_pin_25_ ;
wire [0:0] cby_1__1__108_left_grid_pin_26_ ;
wire [0:0] cby_1__1__108_left_grid_pin_27_ ;
wire [0:0] cby_1__1__108_left_grid_pin_28_ ;
wire [0:0] cby_1__1__108_left_grid_pin_29_ ;
wire [0:0] cby_1__1__108_left_grid_pin_30_ ;
wire [0:0] cby_1__1__108_left_grid_pin_31_ ;
wire [0:0] cby_1__1__109_ccff_tail ;
wire [0:19] cby_1__1__109_chany_bottom_out ;
wire [0:19] cby_1__1__109_chany_top_out ;
wire [0:0] cby_1__1__109_left_grid_pin_16_ ;
wire [0:0] cby_1__1__109_left_grid_pin_17_ ;
wire [0:0] cby_1__1__109_left_grid_pin_18_ ;
wire [0:0] cby_1__1__109_left_grid_pin_19_ ;
wire [0:0] cby_1__1__109_left_grid_pin_20_ ;
wire [0:0] cby_1__1__109_left_grid_pin_21_ ;
wire [0:0] cby_1__1__109_left_grid_pin_22_ ;
wire [0:0] cby_1__1__109_left_grid_pin_23_ ;
wire [0:0] cby_1__1__109_left_grid_pin_24_ ;
wire [0:0] cby_1__1__109_left_grid_pin_25_ ;
wire [0:0] cby_1__1__109_left_grid_pin_26_ ;
wire [0:0] cby_1__1__109_left_grid_pin_27_ ;
wire [0:0] cby_1__1__109_left_grid_pin_28_ ;
wire [0:0] cby_1__1__109_left_grid_pin_29_ ;
wire [0:0] cby_1__1__109_left_grid_pin_30_ ;
wire [0:0] cby_1__1__109_left_grid_pin_31_ ;
wire [0:0] cby_1__1__10_ccff_tail ;
wire [0:19] cby_1__1__10_chany_bottom_out ;
wire [0:19] cby_1__1__10_chany_top_out ;
wire [0:0] cby_1__1__10_left_grid_pin_16_ ;
wire [0:0] cby_1__1__10_left_grid_pin_17_ ;
wire [0:0] cby_1__1__10_left_grid_pin_18_ ;
wire [0:0] cby_1__1__10_left_grid_pin_19_ ;
wire [0:0] cby_1__1__10_left_grid_pin_20_ ;
wire [0:0] cby_1__1__10_left_grid_pin_21_ ;
wire [0:0] cby_1__1__10_left_grid_pin_22_ ;
wire [0:0] cby_1__1__10_left_grid_pin_23_ ;
wire [0:0] cby_1__1__10_left_grid_pin_24_ ;
wire [0:0] cby_1__1__10_left_grid_pin_25_ ;
wire [0:0] cby_1__1__10_left_grid_pin_26_ ;
wire [0:0] cby_1__1__10_left_grid_pin_27_ ;
wire [0:0] cby_1__1__10_left_grid_pin_28_ ;
wire [0:0] cby_1__1__10_left_grid_pin_29_ ;
wire [0:0] cby_1__1__10_left_grid_pin_30_ ;
wire [0:0] cby_1__1__10_left_grid_pin_31_ ;
wire [0:0] cby_1__1__110_ccff_tail ;
wire [0:19] cby_1__1__110_chany_bottom_out ;
wire [0:19] cby_1__1__110_chany_top_out ;
wire [0:0] cby_1__1__110_left_grid_pin_16_ ;
wire [0:0] cby_1__1__110_left_grid_pin_17_ ;
wire [0:0] cby_1__1__110_left_grid_pin_18_ ;
wire [0:0] cby_1__1__110_left_grid_pin_19_ ;
wire [0:0] cby_1__1__110_left_grid_pin_20_ ;
wire [0:0] cby_1__1__110_left_grid_pin_21_ ;
wire [0:0] cby_1__1__110_left_grid_pin_22_ ;
wire [0:0] cby_1__1__110_left_grid_pin_23_ ;
wire [0:0] cby_1__1__110_left_grid_pin_24_ ;
wire [0:0] cby_1__1__110_left_grid_pin_25_ ;
wire [0:0] cby_1__1__110_left_grid_pin_26_ ;
wire [0:0] cby_1__1__110_left_grid_pin_27_ ;
wire [0:0] cby_1__1__110_left_grid_pin_28_ ;
wire [0:0] cby_1__1__110_left_grid_pin_29_ ;
wire [0:0] cby_1__1__110_left_grid_pin_30_ ;
wire [0:0] cby_1__1__110_left_grid_pin_31_ ;
wire [0:0] cby_1__1__111_ccff_tail ;
wire [0:19] cby_1__1__111_chany_bottom_out ;
wire [0:19] cby_1__1__111_chany_top_out ;
wire [0:0] cby_1__1__111_left_grid_pin_16_ ;
wire [0:0] cby_1__1__111_left_grid_pin_17_ ;
wire [0:0] cby_1__1__111_left_grid_pin_18_ ;
wire [0:0] cby_1__1__111_left_grid_pin_19_ ;
wire [0:0] cby_1__1__111_left_grid_pin_20_ ;
wire [0:0] cby_1__1__111_left_grid_pin_21_ ;
wire [0:0] cby_1__1__111_left_grid_pin_22_ ;
wire [0:0] cby_1__1__111_left_grid_pin_23_ ;
wire [0:0] cby_1__1__111_left_grid_pin_24_ ;
wire [0:0] cby_1__1__111_left_grid_pin_25_ ;
wire [0:0] cby_1__1__111_left_grid_pin_26_ ;
wire [0:0] cby_1__1__111_left_grid_pin_27_ ;
wire [0:0] cby_1__1__111_left_grid_pin_28_ ;
wire [0:0] cby_1__1__111_left_grid_pin_29_ ;
wire [0:0] cby_1__1__111_left_grid_pin_30_ ;
wire [0:0] cby_1__1__111_left_grid_pin_31_ ;
wire [0:0] cby_1__1__112_ccff_tail ;
wire [0:19] cby_1__1__112_chany_bottom_out ;
wire [0:19] cby_1__1__112_chany_top_out ;
wire [0:0] cby_1__1__112_left_grid_pin_16_ ;
wire [0:0] cby_1__1__112_left_grid_pin_17_ ;
wire [0:0] cby_1__1__112_left_grid_pin_18_ ;
wire [0:0] cby_1__1__112_left_grid_pin_19_ ;
wire [0:0] cby_1__1__112_left_grid_pin_20_ ;
wire [0:0] cby_1__1__112_left_grid_pin_21_ ;
wire [0:0] cby_1__1__112_left_grid_pin_22_ ;
wire [0:0] cby_1__1__112_left_grid_pin_23_ ;
wire [0:0] cby_1__1__112_left_grid_pin_24_ ;
wire [0:0] cby_1__1__112_left_grid_pin_25_ ;
wire [0:0] cby_1__1__112_left_grid_pin_26_ ;
wire [0:0] cby_1__1__112_left_grid_pin_27_ ;
wire [0:0] cby_1__1__112_left_grid_pin_28_ ;
wire [0:0] cby_1__1__112_left_grid_pin_29_ ;
wire [0:0] cby_1__1__112_left_grid_pin_30_ ;
wire [0:0] cby_1__1__112_left_grid_pin_31_ ;
wire [0:0] cby_1__1__113_ccff_tail ;
wire [0:19] cby_1__1__113_chany_bottom_out ;
wire [0:19] cby_1__1__113_chany_top_out ;
wire [0:0] cby_1__1__113_left_grid_pin_16_ ;
wire [0:0] cby_1__1__113_left_grid_pin_17_ ;
wire [0:0] cby_1__1__113_left_grid_pin_18_ ;
wire [0:0] cby_1__1__113_left_grid_pin_19_ ;
wire [0:0] cby_1__1__113_left_grid_pin_20_ ;
wire [0:0] cby_1__1__113_left_grid_pin_21_ ;
wire [0:0] cby_1__1__113_left_grid_pin_22_ ;
wire [0:0] cby_1__1__113_left_grid_pin_23_ ;
wire [0:0] cby_1__1__113_left_grid_pin_24_ ;
wire [0:0] cby_1__1__113_left_grid_pin_25_ ;
wire [0:0] cby_1__1__113_left_grid_pin_26_ ;
wire [0:0] cby_1__1__113_left_grid_pin_27_ ;
wire [0:0] cby_1__1__113_left_grid_pin_28_ ;
wire [0:0] cby_1__1__113_left_grid_pin_29_ ;
wire [0:0] cby_1__1__113_left_grid_pin_30_ ;
wire [0:0] cby_1__1__113_left_grid_pin_31_ ;
wire [0:0] cby_1__1__114_ccff_tail ;
wire [0:19] cby_1__1__114_chany_bottom_out ;
wire [0:19] cby_1__1__114_chany_top_out ;
wire [0:0] cby_1__1__114_left_grid_pin_16_ ;
wire [0:0] cby_1__1__114_left_grid_pin_17_ ;
wire [0:0] cby_1__1__114_left_grid_pin_18_ ;
wire [0:0] cby_1__1__114_left_grid_pin_19_ ;
wire [0:0] cby_1__1__114_left_grid_pin_20_ ;
wire [0:0] cby_1__1__114_left_grid_pin_21_ ;
wire [0:0] cby_1__1__114_left_grid_pin_22_ ;
wire [0:0] cby_1__1__114_left_grid_pin_23_ ;
wire [0:0] cby_1__1__114_left_grid_pin_24_ ;
wire [0:0] cby_1__1__114_left_grid_pin_25_ ;
wire [0:0] cby_1__1__114_left_grid_pin_26_ ;
wire [0:0] cby_1__1__114_left_grid_pin_27_ ;
wire [0:0] cby_1__1__114_left_grid_pin_28_ ;
wire [0:0] cby_1__1__114_left_grid_pin_29_ ;
wire [0:0] cby_1__1__114_left_grid_pin_30_ ;
wire [0:0] cby_1__1__114_left_grid_pin_31_ ;
wire [0:0] cby_1__1__115_ccff_tail ;
wire [0:19] cby_1__1__115_chany_bottom_out ;
wire [0:19] cby_1__1__115_chany_top_out ;
wire [0:0] cby_1__1__115_left_grid_pin_16_ ;
wire [0:0] cby_1__1__115_left_grid_pin_17_ ;
wire [0:0] cby_1__1__115_left_grid_pin_18_ ;
wire [0:0] cby_1__1__115_left_grid_pin_19_ ;
wire [0:0] cby_1__1__115_left_grid_pin_20_ ;
wire [0:0] cby_1__1__115_left_grid_pin_21_ ;
wire [0:0] cby_1__1__115_left_grid_pin_22_ ;
wire [0:0] cby_1__1__115_left_grid_pin_23_ ;
wire [0:0] cby_1__1__115_left_grid_pin_24_ ;
wire [0:0] cby_1__1__115_left_grid_pin_25_ ;
wire [0:0] cby_1__1__115_left_grid_pin_26_ ;
wire [0:0] cby_1__1__115_left_grid_pin_27_ ;
wire [0:0] cby_1__1__115_left_grid_pin_28_ ;
wire [0:0] cby_1__1__115_left_grid_pin_29_ ;
wire [0:0] cby_1__1__115_left_grid_pin_30_ ;
wire [0:0] cby_1__1__115_left_grid_pin_31_ ;
wire [0:0] cby_1__1__116_ccff_tail ;
wire [0:19] cby_1__1__116_chany_bottom_out ;
wire [0:19] cby_1__1__116_chany_top_out ;
wire [0:0] cby_1__1__116_left_grid_pin_16_ ;
wire [0:0] cby_1__1__116_left_grid_pin_17_ ;
wire [0:0] cby_1__1__116_left_grid_pin_18_ ;
wire [0:0] cby_1__1__116_left_grid_pin_19_ ;
wire [0:0] cby_1__1__116_left_grid_pin_20_ ;
wire [0:0] cby_1__1__116_left_grid_pin_21_ ;
wire [0:0] cby_1__1__116_left_grid_pin_22_ ;
wire [0:0] cby_1__1__116_left_grid_pin_23_ ;
wire [0:0] cby_1__1__116_left_grid_pin_24_ ;
wire [0:0] cby_1__1__116_left_grid_pin_25_ ;
wire [0:0] cby_1__1__116_left_grid_pin_26_ ;
wire [0:0] cby_1__1__116_left_grid_pin_27_ ;
wire [0:0] cby_1__1__116_left_grid_pin_28_ ;
wire [0:0] cby_1__1__116_left_grid_pin_29_ ;
wire [0:0] cby_1__1__116_left_grid_pin_30_ ;
wire [0:0] cby_1__1__116_left_grid_pin_31_ ;
wire [0:0] cby_1__1__117_ccff_tail ;
wire [0:19] cby_1__1__117_chany_bottom_out ;
wire [0:19] cby_1__1__117_chany_top_out ;
wire [0:0] cby_1__1__117_left_grid_pin_16_ ;
wire [0:0] cby_1__1__117_left_grid_pin_17_ ;
wire [0:0] cby_1__1__117_left_grid_pin_18_ ;
wire [0:0] cby_1__1__117_left_grid_pin_19_ ;
wire [0:0] cby_1__1__117_left_grid_pin_20_ ;
wire [0:0] cby_1__1__117_left_grid_pin_21_ ;
wire [0:0] cby_1__1__117_left_grid_pin_22_ ;
wire [0:0] cby_1__1__117_left_grid_pin_23_ ;
wire [0:0] cby_1__1__117_left_grid_pin_24_ ;
wire [0:0] cby_1__1__117_left_grid_pin_25_ ;
wire [0:0] cby_1__1__117_left_grid_pin_26_ ;
wire [0:0] cby_1__1__117_left_grid_pin_27_ ;
wire [0:0] cby_1__1__117_left_grid_pin_28_ ;
wire [0:0] cby_1__1__117_left_grid_pin_29_ ;
wire [0:0] cby_1__1__117_left_grid_pin_30_ ;
wire [0:0] cby_1__1__117_left_grid_pin_31_ ;
wire [0:0] cby_1__1__118_ccff_tail ;
wire [0:19] cby_1__1__118_chany_bottom_out ;
wire [0:19] cby_1__1__118_chany_top_out ;
wire [0:0] cby_1__1__118_left_grid_pin_16_ ;
wire [0:0] cby_1__1__118_left_grid_pin_17_ ;
wire [0:0] cby_1__1__118_left_grid_pin_18_ ;
wire [0:0] cby_1__1__118_left_grid_pin_19_ ;
wire [0:0] cby_1__1__118_left_grid_pin_20_ ;
wire [0:0] cby_1__1__118_left_grid_pin_21_ ;
wire [0:0] cby_1__1__118_left_grid_pin_22_ ;
wire [0:0] cby_1__1__118_left_grid_pin_23_ ;
wire [0:0] cby_1__1__118_left_grid_pin_24_ ;
wire [0:0] cby_1__1__118_left_grid_pin_25_ ;
wire [0:0] cby_1__1__118_left_grid_pin_26_ ;
wire [0:0] cby_1__1__118_left_grid_pin_27_ ;
wire [0:0] cby_1__1__118_left_grid_pin_28_ ;
wire [0:0] cby_1__1__118_left_grid_pin_29_ ;
wire [0:0] cby_1__1__118_left_grid_pin_30_ ;
wire [0:0] cby_1__1__118_left_grid_pin_31_ ;
wire [0:0] cby_1__1__119_ccff_tail ;
wire [0:19] cby_1__1__119_chany_bottom_out ;
wire [0:19] cby_1__1__119_chany_top_out ;
wire [0:0] cby_1__1__119_left_grid_pin_16_ ;
wire [0:0] cby_1__1__119_left_grid_pin_17_ ;
wire [0:0] cby_1__1__119_left_grid_pin_18_ ;
wire [0:0] cby_1__1__119_left_grid_pin_19_ ;
wire [0:0] cby_1__1__119_left_grid_pin_20_ ;
wire [0:0] cby_1__1__119_left_grid_pin_21_ ;
wire [0:0] cby_1__1__119_left_grid_pin_22_ ;
wire [0:0] cby_1__1__119_left_grid_pin_23_ ;
wire [0:0] cby_1__1__119_left_grid_pin_24_ ;
wire [0:0] cby_1__1__119_left_grid_pin_25_ ;
wire [0:0] cby_1__1__119_left_grid_pin_26_ ;
wire [0:0] cby_1__1__119_left_grid_pin_27_ ;
wire [0:0] cby_1__1__119_left_grid_pin_28_ ;
wire [0:0] cby_1__1__119_left_grid_pin_29_ ;
wire [0:0] cby_1__1__119_left_grid_pin_30_ ;
wire [0:0] cby_1__1__119_left_grid_pin_31_ ;
wire [0:0] cby_1__1__11_ccff_tail ;
wire [0:19] cby_1__1__11_chany_bottom_out ;
wire [0:19] cby_1__1__11_chany_top_out ;
wire [0:0] cby_1__1__11_left_grid_pin_16_ ;
wire [0:0] cby_1__1__11_left_grid_pin_17_ ;
wire [0:0] cby_1__1__11_left_grid_pin_18_ ;
wire [0:0] cby_1__1__11_left_grid_pin_19_ ;
wire [0:0] cby_1__1__11_left_grid_pin_20_ ;
wire [0:0] cby_1__1__11_left_grid_pin_21_ ;
wire [0:0] cby_1__1__11_left_grid_pin_22_ ;
wire [0:0] cby_1__1__11_left_grid_pin_23_ ;
wire [0:0] cby_1__1__11_left_grid_pin_24_ ;
wire [0:0] cby_1__1__11_left_grid_pin_25_ ;
wire [0:0] cby_1__1__11_left_grid_pin_26_ ;
wire [0:0] cby_1__1__11_left_grid_pin_27_ ;
wire [0:0] cby_1__1__11_left_grid_pin_28_ ;
wire [0:0] cby_1__1__11_left_grid_pin_29_ ;
wire [0:0] cby_1__1__11_left_grid_pin_30_ ;
wire [0:0] cby_1__1__11_left_grid_pin_31_ ;
wire [0:0] cby_1__1__120_ccff_tail ;
wire [0:19] cby_1__1__120_chany_bottom_out ;
wire [0:19] cby_1__1__120_chany_top_out ;
wire [0:0] cby_1__1__120_left_grid_pin_16_ ;
wire [0:0] cby_1__1__120_left_grid_pin_17_ ;
wire [0:0] cby_1__1__120_left_grid_pin_18_ ;
wire [0:0] cby_1__1__120_left_grid_pin_19_ ;
wire [0:0] cby_1__1__120_left_grid_pin_20_ ;
wire [0:0] cby_1__1__120_left_grid_pin_21_ ;
wire [0:0] cby_1__1__120_left_grid_pin_22_ ;
wire [0:0] cby_1__1__120_left_grid_pin_23_ ;
wire [0:0] cby_1__1__120_left_grid_pin_24_ ;
wire [0:0] cby_1__1__120_left_grid_pin_25_ ;
wire [0:0] cby_1__1__120_left_grid_pin_26_ ;
wire [0:0] cby_1__1__120_left_grid_pin_27_ ;
wire [0:0] cby_1__1__120_left_grid_pin_28_ ;
wire [0:0] cby_1__1__120_left_grid_pin_29_ ;
wire [0:0] cby_1__1__120_left_grid_pin_30_ ;
wire [0:0] cby_1__1__120_left_grid_pin_31_ ;
wire [0:0] cby_1__1__121_ccff_tail ;
wire [0:19] cby_1__1__121_chany_bottom_out ;
wire [0:19] cby_1__1__121_chany_top_out ;
wire [0:0] cby_1__1__121_left_grid_pin_16_ ;
wire [0:0] cby_1__1__121_left_grid_pin_17_ ;
wire [0:0] cby_1__1__121_left_grid_pin_18_ ;
wire [0:0] cby_1__1__121_left_grid_pin_19_ ;
wire [0:0] cby_1__1__121_left_grid_pin_20_ ;
wire [0:0] cby_1__1__121_left_grid_pin_21_ ;
wire [0:0] cby_1__1__121_left_grid_pin_22_ ;
wire [0:0] cby_1__1__121_left_grid_pin_23_ ;
wire [0:0] cby_1__1__121_left_grid_pin_24_ ;
wire [0:0] cby_1__1__121_left_grid_pin_25_ ;
wire [0:0] cby_1__1__121_left_grid_pin_26_ ;
wire [0:0] cby_1__1__121_left_grid_pin_27_ ;
wire [0:0] cby_1__1__121_left_grid_pin_28_ ;
wire [0:0] cby_1__1__121_left_grid_pin_29_ ;
wire [0:0] cby_1__1__121_left_grid_pin_30_ ;
wire [0:0] cby_1__1__121_left_grid_pin_31_ ;
wire [0:0] cby_1__1__122_ccff_tail ;
wire [0:19] cby_1__1__122_chany_bottom_out ;
wire [0:19] cby_1__1__122_chany_top_out ;
wire [0:0] cby_1__1__122_left_grid_pin_16_ ;
wire [0:0] cby_1__1__122_left_grid_pin_17_ ;
wire [0:0] cby_1__1__122_left_grid_pin_18_ ;
wire [0:0] cby_1__1__122_left_grid_pin_19_ ;
wire [0:0] cby_1__1__122_left_grid_pin_20_ ;
wire [0:0] cby_1__1__122_left_grid_pin_21_ ;
wire [0:0] cby_1__1__122_left_grid_pin_22_ ;
wire [0:0] cby_1__1__122_left_grid_pin_23_ ;
wire [0:0] cby_1__1__122_left_grid_pin_24_ ;
wire [0:0] cby_1__1__122_left_grid_pin_25_ ;
wire [0:0] cby_1__1__122_left_grid_pin_26_ ;
wire [0:0] cby_1__1__122_left_grid_pin_27_ ;
wire [0:0] cby_1__1__122_left_grid_pin_28_ ;
wire [0:0] cby_1__1__122_left_grid_pin_29_ ;
wire [0:0] cby_1__1__122_left_grid_pin_30_ ;
wire [0:0] cby_1__1__122_left_grid_pin_31_ ;
wire [0:0] cby_1__1__123_ccff_tail ;
wire [0:19] cby_1__1__123_chany_bottom_out ;
wire [0:19] cby_1__1__123_chany_top_out ;
wire [0:0] cby_1__1__123_left_grid_pin_16_ ;
wire [0:0] cby_1__1__123_left_grid_pin_17_ ;
wire [0:0] cby_1__1__123_left_grid_pin_18_ ;
wire [0:0] cby_1__1__123_left_grid_pin_19_ ;
wire [0:0] cby_1__1__123_left_grid_pin_20_ ;
wire [0:0] cby_1__1__123_left_grid_pin_21_ ;
wire [0:0] cby_1__1__123_left_grid_pin_22_ ;
wire [0:0] cby_1__1__123_left_grid_pin_23_ ;
wire [0:0] cby_1__1__123_left_grid_pin_24_ ;
wire [0:0] cby_1__1__123_left_grid_pin_25_ ;
wire [0:0] cby_1__1__123_left_grid_pin_26_ ;
wire [0:0] cby_1__1__123_left_grid_pin_27_ ;
wire [0:0] cby_1__1__123_left_grid_pin_28_ ;
wire [0:0] cby_1__1__123_left_grid_pin_29_ ;
wire [0:0] cby_1__1__123_left_grid_pin_30_ ;
wire [0:0] cby_1__1__123_left_grid_pin_31_ ;
wire [0:0] cby_1__1__124_ccff_tail ;
wire [0:19] cby_1__1__124_chany_bottom_out ;
wire [0:19] cby_1__1__124_chany_top_out ;
wire [0:0] cby_1__1__124_left_grid_pin_16_ ;
wire [0:0] cby_1__1__124_left_grid_pin_17_ ;
wire [0:0] cby_1__1__124_left_grid_pin_18_ ;
wire [0:0] cby_1__1__124_left_grid_pin_19_ ;
wire [0:0] cby_1__1__124_left_grid_pin_20_ ;
wire [0:0] cby_1__1__124_left_grid_pin_21_ ;
wire [0:0] cby_1__1__124_left_grid_pin_22_ ;
wire [0:0] cby_1__1__124_left_grid_pin_23_ ;
wire [0:0] cby_1__1__124_left_grid_pin_24_ ;
wire [0:0] cby_1__1__124_left_grid_pin_25_ ;
wire [0:0] cby_1__1__124_left_grid_pin_26_ ;
wire [0:0] cby_1__1__124_left_grid_pin_27_ ;
wire [0:0] cby_1__1__124_left_grid_pin_28_ ;
wire [0:0] cby_1__1__124_left_grid_pin_29_ ;
wire [0:0] cby_1__1__124_left_grid_pin_30_ ;
wire [0:0] cby_1__1__124_left_grid_pin_31_ ;
wire [0:0] cby_1__1__125_ccff_tail ;
wire [0:19] cby_1__1__125_chany_bottom_out ;
wire [0:19] cby_1__1__125_chany_top_out ;
wire [0:0] cby_1__1__125_left_grid_pin_16_ ;
wire [0:0] cby_1__1__125_left_grid_pin_17_ ;
wire [0:0] cby_1__1__125_left_grid_pin_18_ ;
wire [0:0] cby_1__1__125_left_grid_pin_19_ ;
wire [0:0] cby_1__1__125_left_grid_pin_20_ ;
wire [0:0] cby_1__1__125_left_grid_pin_21_ ;
wire [0:0] cby_1__1__125_left_grid_pin_22_ ;
wire [0:0] cby_1__1__125_left_grid_pin_23_ ;
wire [0:0] cby_1__1__125_left_grid_pin_24_ ;
wire [0:0] cby_1__1__125_left_grid_pin_25_ ;
wire [0:0] cby_1__1__125_left_grid_pin_26_ ;
wire [0:0] cby_1__1__125_left_grid_pin_27_ ;
wire [0:0] cby_1__1__125_left_grid_pin_28_ ;
wire [0:0] cby_1__1__125_left_grid_pin_29_ ;
wire [0:0] cby_1__1__125_left_grid_pin_30_ ;
wire [0:0] cby_1__1__125_left_grid_pin_31_ ;
wire [0:0] cby_1__1__126_ccff_tail ;
wire [0:19] cby_1__1__126_chany_bottom_out ;
wire [0:19] cby_1__1__126_chany_top_out ;
wire [0:0] cby_1__1__126_left_grid_pin_16_ ;
wire [0:0] cby_1__1__126_left_grid_pin_17_ ;
wire [0:0] cby_1__1__126_left_grid_pin_18_ ;
wire [0:0] cby_1__1__126_left_grid_pin_19_ ;
wire [0:0] cby_1__1__126_left_grid_pin_20_ ;
wire [0:0] cby_1__1__126_left_grid_pin_21_ ;
wire [0:0] cby_1__1__126_left_grid_pin_22_ ;
wire [0:0] cby_1__1__126_left_grid_pin_23_ ;
wire [0:0] cby_1__1__126_left_grid_pin_24_ ;
wire [0:0] cby_1__1__126_left_grid_pin_25_ ;
wire [0:0] cby_1__1__126_left_grid_pin_26_ ;
wire [0:0] cby_1__1__126_left_grid_pin_27_ ;
wire [0:0] cby_1__1__126_left_grid_pin_28_ ;
wire [0:0] cby_1__1__126_left_grid_pin_29_ ;
wire [0:0] cby_1__1__126_left_grid_pin_30_ ;
wire [0:0] cby_1__1__126_left_grid_pin_31_ ;
wire [0:0] cby_1__1__127_ccff_tail ;
wire [0:19] cby_1__1__127_chany_bottom_out ;
wire [0:19] cby_1__1__127_chany_top_out ;
wire [0:0] cby_1__1__127_left_grid_pin_16_ ;
wire [0:0] cby_1__1__127_left_grid_pin_17_ ;
wire [0:0] cby_1__1__127_left_grid_pin_18_ ;
wire [0:0] cby_1__1__127_left_grid_pin_19_ ;
wire [0:0] cby_1__1__127_left_grid_pin_20_ ;
wire [0:0] cby_1__1__127_left_grid_pin_21_ ;
wire [0:0] cby_1__1__127_left_grid_pin_22_ ;
wire [0:0] cby_1__1__127_left_grid_pin_23_ ;
wire [0:0] cby_1__1__127_left_grid_pin_24_ ;
wire [0:0] cby_1__1__127_left_grid_pin_25_ ;
wire [0:0] cby_1__1__127_left_grid_pin_26_ ;
wire [0:0] cby_1__1__127_left_grid_pin_27_ ;
wire [0:0] cby_1__1__127_left_grid_pin_28_ ;
wire [0:0] cby_1__1__127_left_grid_pin_29_ ;
wire [0:0] cby_1__1__127_left_grid_pin_30_ ;
wire [0:0] cby_1__1__127_left_grid_pin_31_ ;
wire [0:0] cby_1__1__128_ccff_tail ;
wire [0:19] cby_1__1__128_chany_bottom_out ;
wire [0:19] cby_1__1__128_chany_top_out ;
wire [0:0] cby_1__1__128_left_grid_pin_16_ ;
wire [0:0] cby_1__1__128_left_grid_pin_17_ ;
wire [0:0] cby_1__1__128_left_grid_pin_18_ ;
wire [0:0] cby_1__1__128_left_grid_pin_19_ ;
wire [0:0] cby_1__1__128_left_grid_pin_20_ ;
wire [0:0] cby_1__1__128_left_grid_pin_21_ ;
wire [0:0] cby_1__1__128_left_grid_pin_22_ ;
wire [0:0] cby_1__1__128_left_grid_pin_23_ ;
wire [0:0] cby_1__1__128_left_grid_pin_24_ ;
wire [0:0] cby_1__1__128_left_grid_pin_25_ ;
wire [0:0] cby_1__1__128_left_grid_pin_26_ ;
wire [0:0] cby_1__1__128_left_grid_pin_27_ ;
wire [0:0] cby_1__1__128_left_grid_pin_28_ ;
wire [0:0] cby_1__1__128_left_grid_pin_29_ ;
wire [0:0] cby_1__1__128_left_grid_pin_30_ ;
wire [0:0] cby_1__1__128_left_grid_pin_31_ ;
wire [0:0] cby_1__1__129_ccff_tail ;
wire [0:19] cby_1__1__129_chany_bottom_out ;
wire [0:19] cby_1__1__129_chany_top_out ;
wire [0:0] cby_1__1__129_left_grid_pin_16_ ;
wire [0:0] cby_1__1__129_left_grid_pin_17_ ;
wire [0:0] cby_1__1__129_left_grid_pin_18_ ;
wire [0:0] cby_1__1__129_left_grid_pin_19_ ;
wire [0:0] cby_1__1__129_left_grid_pin_20_ ;
wire [0:0] cby_1__1__129_left_grid_pin_21_ ;
wire [0:0] cby_1__1__129_left_grid_pin_22_ ;
wire [0:0] cby_1__1__129_left_grid_pin_23_ ;
wire [0:0] cby_1__1__129_left_grid_pin_24_ ;
wire [0:0] cby_1__1__129_left_grid_pin_25_ ;
wire [0:0] cby_1__1__129_left_grid_pin_26_ ;
wire [0:0] cby_1__1__129_left_grid_pin_27_ ;
wire [0:0] cby_1__1__129_left_grid_pin_28_ ;
wire [0:0] cby_1__1__129_left_grid_pin_29_ ;
wire [0:0] cby_1__1__129_left_grid_pin_30_ ;
wire [0:0] cby_1__1__129_left_grid_pin_31_ ;
wire [0:0] cby_1__1__12_ccff_tail ;
wire [0:19] cby_1__1__12_chany_bottom_out ;
wire [0:19] cby_1__1__12_chany_top_out ;
wire [0:0] cby_1__1__12_left_grid_pin_16_ ;
wire [0:0] cby_1__1__12_left_grid_pin_17_ ;
wire [0:0] cby_1__1__12_left_grid_pin_18_ ;
wire [0:0] cby_1__1__12_left_grid_pin_19_ ;
wire [0:0] cby_1__1__12_left_grid_pin_20_ ;
wire [0:0] cby_1__1__12_left_grid_pin_21_ ;
wire [0:0] cby_1__1__12_left_grid_pin_22_ ;
wire [0:0] cby_1__1__12_left_grid_pin_23_ ;
wire [0:0] cby_1__1__12_left_grid_pin_24_ ;
wire [0:0] cby_1__1__12_left_grid_pin_25_ ;
wire [0:0] cby_1__1__12_left_grid_pin_26_ ;
wire [0:0] cby_1__1__12_left_grid_pin_27_ ;
wire [0:0] cby_1__1__12_left_grid_pin_28_ ;
wire [0:0] cby_1__1__12_left_grid_pin_29_ ;
wire [0:0] cby_1__1__12_left_grid_pin_30_ ;
wire [0:0] cby_1__1__12_left_grid_pin_31_ ;
wire [0:0] cby_1__1__130_ccff_tail ;
wire [0:19] cby_1__1__130_chany_bottom_out ;
wire [0:19] cby_1__1__130_chany_top_out ;
wire [0:0] cby_1__1__130_left_grid_pin_16_ ;
wire [0:0] cby_1__1__130_left_grid_pin_17_ ;
wire [0:0] cby_1__1__130_left_grid_pin_18_ ;
wire [0:0] cby_1__1__130_left_grid_pin_19_ ;
wire [0:0] cby_1__1__130_left_grid_pin_20_ ;
wire [0:0] cby_1__1__130_left_grid_pin_21_ ;
wire [0:0] cby_1__1__130_left_grid_pin_22_ ;
wire [0:0] cby_1__1__130_left_grid_pin_23_ ;
wire [0:0] cby_1__1__130_left_grid_pin_24_ ;
wire [0:0] cby_1__1__130_left_grid_pin_25_ ;
wire [0:0] cby_1__1__130_left_grid_pin_26_ ;
wire [0:0] cby_1__1__130_left_grid_pin_27_ ;
wire [0:0] cby_1__1__130_left_grid_pin_28_ ;
wire [0:0] cby_1__1__130_left_grid_pin_29_ ;
wire [0:0] cby_1__1__130_left_grid_pin_30_ ;
wire [0:0] cby_1__1__130_left_grid_pin_31_ ;
wire [0:0] cby_1__1__131_ccff_tail ;
wire [0:19] cby_1__1__131_chany_bottom_out ;
wire [0:19] cby_1__1__131_chany_top_out ;
wire [0:0] cby_1__1__131_left_grid_pin_16_ ;
wire [0:0] cby_1__1__131_left_grid_pin_17_ ;
wire [0:0] cby_1__1__131_left_grid_pin_18_ ;
wire [0:0] cby_1__1__131_left_grid_pin_19_ ;
wire [0:0] cby_1__1__131_left_grid_pin_20_ ;
wire [0:0] cby_1__1__131_left_grid_pin_21_ ;
wire [0:0] cby_1__1__131_left_grid_pin_22_ ;
wire [0:0] cby_1__1__131_left_grid_pin_23_ ;
wire [0:0] cby_1__1__131_left_grid_pin_24_ ;
wire [0:0] cby_1__1__131_left_grid_pin_25_ ;
wire [0:0] cby_1__1__131_left_grid_pin_26_ ;
wire [0:0] cby_1__1__131_left_grid_pin_27_ ;
wire [0:0] cby_1__1__131_left_grid_pin_28_ ;
wire [0:0] cby_1__1__131_left_grid_pin_29_ ;
wire [0:0] cby_1__1__131_left_grid_pin_30_ ;
wire [0:0] cby_1__1__131_left_grid_pin_31_ ;
wire [0:0] cby_1__1__13_ccff_tail ;
wire [0:19] cby_1__1__13_chany_bottom_out ;
wire [0:19] cby_1__1__13_chany_top_out ;
wire [0:0] cby_1__1__13_left_grid_pin_16_ ;
wire [0:0] cby_1__1__13_left_grid_pin_17_ ;
wire [0:0] cby_1__1__13_left_grid_pin_18_ ;
wire [0:0] cby_1__1__13_left_grid_pin_19_ ;
wire [0:0] cby_1__1__13_left_grid_pin_20_ ;
wire [0:0] cby_1__1__13_left_grid_pin_21_ ;
wire [0:0] cby_1__1__13_left_grid_pin_22_ ;
wire [0:0] cby_1__1__13_left_grid_pin_23_ ;
wire [0:0] cby_1__1__13_left_grid_pin_24_ ;
wire [0:0] cby_1__1__13_left_grid_pin_25_ ;
wire [0:0] cby_1__1__13_left_grid_pin_26_ ;
wire [0:0] cby_1__1__13_left_grid_pin_27_ ;
wire [0:0] cby_1__1__13_left_grid_pin_28_ ;
wire [0:0] cby_1__1__13_left_grid_pin_29_ ;
wire [0:0] cby_1__1__13_left_grid_pin_30_ ;
wire [0:0] cby_1__1__13_left_grid_pin_31_ ;
wire [0:0] cby_1__1__14_ccff_tail ;
wire [0:19] cby_1__1__14_chany_bottom_out ;
wire [0:19] cby_1__1__14_chany_top_out ;
wire [0:0] cby_1__1__14_left_grid_pin_16_ ;
wire [0:0] cby_1__1__14_left_grid_pin_17_ ;
wire [0:0] cby_1__1__14_left_grid_pin_18_ ;
wire [0:0] cby_1__1__14_left_grid_pin_19_ ;
wire [0:0] cby_1__1__14_left_grid_pin_20_ ;
wire [0:0] cby_1__1__14_left_grid_pin_21_ ;
wire [0:0] cby_1__1__14_left_grid_pin_22_ ;
wire [0:0] cby_1__1__14_left_grid_pin_23_ ;
wire [0:0] cby_1__1__14_left_grid_pin_24_ ;
wire [0:0] cby_1__1__14_left_grid_pin_25_ ;
wire [0:0] cby_1__1__14_left_grid_pin_26_ ;
wire [0:0] cby_1__1__14_left_grid_pin_27_ ;
wire [0:0] cby_1__1__14_left_grid_pin_28_ ;
wire [0:0] cby_1__1__14_left_grid_pin_29_ ;
wire [0:0] cby_1__1__14_left_grid_pin_30_ ;
wire [0:0] cby_1__1__14_left_grid_pin_31_ ;
wire [0:0] cby_1__1__15_ccff_tail ;
wire [0:19] cby_1__1__15_chany_bottom_out ;
wire [0:19] cby_1__1__15_chany_top_out ;
wire [0:0] cby_1__1__15_left_grid_pin_16_ ;
wire [0:0] cby_1__1__15_left_grid_pin_17_ ;
wire [0:0] cby_1__1__15_left_grid_pin_18_ ;
wire [0:0] cby_1__1__15_left_grid_pin_19_ ;
wire [0:0] cby_1__1__15_left_grid_pin_20_ ;
wire [0:0] cby_1__1__15_left_grid_pin_21_ ;
wire [0:0] cby_1__1__15_left_grid_pin_22_ ;
wire [0:0] cby_1__1__15_left_grid_pin_23_ ;
wire [0:0] cby_1__1__15_left_grid_pin_24_ ;
wire [0:0] cby_1__1__15_left_grid_pin_25_ ;
wire [0:0] cby_1__1__15_left_grid_pin_26_ ;
wire [0:0] cby_1__1__15_left_grid_pin_27_ ;
wire [0:0] cby_1__1__15_left_grid_pin_28_ ;
wire [0:0] cby_1__1__15_left_grid_pin_29_ ;
wire [0:0] cby_1__1__15_left_grid_pin_30_ ;
wire [0:0] cby_1__1__15_left_grid_pin_31_ ;
wire [0:0] cby_1__1__16_ccff_tail ;
wire [0:19] cby_1__1__16_chany_bottom_out ;
wire [0:19] cby_1__1__16_chany_top_out ;
wire [0:0] cby_1__1__16_left_grid_pin_16_ ;
wire [0:0] cby_1__1__16_left_grid_pin_17_ ;
wire [0:0] cby_1__1__16_left_grid_pin_18_ ;
wire [0:0] cby_1__1__16_left_grid_pin_19_ ;
wire [0:0] cby_1__1__16_left_grid_pin_20_ ;
wire [0:0] cby_1__1__16_left_grid_pin_21_ ;
wire [0:0] cby_1__1__16_left_grid_pin_22_ ;
wire [0:0] cby_1__1__16_left_grid_pin_23_ ;
wire [0:0] cby_1__1__16_left_grid_pin_24_ ;
wire [0:0] cby_1__1__16_left_grid_pin_25_ ;
wire [0:0] cby_1__1__16_left_grid_pin_26_ ;
wire [0:0] cby_1__1__16_left_grid_pin_27_ ;
wire [0:0] cby_1__1__16_left_grid_pin_28_ ;
wire [0:0] cby_1__1__16_left_grid_pin_29_ ;
wire [0:0] cby_1__1__16_left_grid_pin_30_ ;
wire [0:0] cby_1__1__16_left_grid_pin_31_ ;
wire [0:0] cby_1__1__17_ccff_tail ;
wire [0:19] cby_1__1__17_chany_bottom_out ;
wire [0:19] cby_1__1__17_chany_top_out ;
wire [0:0] cby_1__1__17_left_grid_pin_16_ ;
wire [0:0] cby_1__1__17_left_grid_pin_17_ ;
wire [0:0] cby_1__1__17_left_grid_pin_18_ ;
wire [0:0] cby_1__1__17_left_grid_pin_19_ ;
wire [0:0] cby_1__1__17_left_grid_pin_20_ ;
wire [0:0] cby_1__1__17_left_grid_pin_21_ ;
wire [0:0] cby_1__1__17_left_grid_pin_22_ ;
wire [0:0] cby_1__1__17_left_grid_pin_23_ ;
wire [0:0] cby_1__1__17_left_grid_pin_24_ ;
wire [0:0] cby_1__1__17_left_grid_pin_25_ ;
wire [0:0] cby_1__1__17_left_grid_pin_26_ ;
wire [0:0] cby_1__1__17_left_grid_pin_27_ ;
wire [0:0] cby_1__1__17_left_grid_pin_28_ ;
wire [0:0] cby_1__1__17_left_grid_pin_29_ ;
wire [0:0] cby_1__1__17_left_grid_pin_30_ ;
wire [0:0] cby_1__1__17_left_grid_pin_31_ ;
wire [0:0] cby_1__1__18_ccff_tail ;
wire [0:19] cby_1__1__18_chany_bottom_out ;
wire [0:19] cby_1__1__18_chany_top_out ;
wire [0:0] cby_1__1__18_left_grid_pin_16_ ;
wire [0:0] cby_1__1__18_left_grid_pin_17_ ;
wire [0:0] cby_1__1__18_left_grid_pin_18_ ;
wire [0:0] cby_1__1__18_left_grid_pin_19_ ;
wire [0:0] cby_1__1__18_left_grid_pin_20_ ;
wire [0:0] cby_1__1__18_left_grid_pin_21_ ;
wire [0:0] cby_1__1__18_left_grid_pin_22_ ;
wire [0:0] cby_1__1__18_left_grid_pin_23_ ;
wire [0:0] cby_1__1__18_left_grid_pin_24_ ;
wire [0:0] cby_1__1__18_left_grid_pin_25_ ;
wire [0:0] cby_1__1__18_left_grid_pin_26_ ;
wire [0:0] cby_1__1__18_left_grid_pin_27_ ;
wire [0:0] cby_1__1__18_left_grid_pin_28_ ;
wire [0:0] cby_1__1__18_left_grid_pin_29_ ;
wire [0:0] cby_1__1__18_left_grid_pin_30_ ;
wire [0:0] cby_1__1__18_left_grid_pin_31_ ;
wire [0:0] cby_1__1__19_ccff_tail ;
wire [0:19] cby_1__1__19_chany_bottom_out ;
wire [0:19] cby_1__1__19_chany_top_out ;
wire [0:0] cby_1__1__19_left_grid_pin_16_ ;
wire [0:0] cby_1__1__19_left_grid_pin_17_ ;
wire [0:0] cby_1__1__19_left_grid_pin_18_ ;
wire [0:0] cby_1__1__19_left_grid_pin_19_ ;
wire [0:0] cby_1__1__19_left_grid_pin_20_ ;
wire [0:0] cby_1__1__19_left_grid_pin_21_ ;
wire [0:0] cby_1__1__19_left_grid_pin_22_ ;
wire [0:0] cby_1__1__19_left_grid_pin_23_ ;
wire [0:0] cby_1__1__19_left_grid_pin_24_ ;
wire [0:0] cby_1__1__19_left_grid_pin_25_ ;
wire [0:0] cby_1__1__19_left_grid_pin_26_ ;
wire [0:0] cby_1__1__19_left_grid_pin_27_ ;
wire [0:0] cby_1__1__19_left_grid_pin_28_ ;
wire [0:0] cby_1__1__19_left_grid_pin_29_ ;
wire [0:0] cby_1__1__19_left_grid_pin_30_ ;
wire [0:0] cby_1__1__19_left_grid_pin_31_ ;
wire [0:0] cby_1__1__1_ccff_tail ;
wire [0:19] cby_1__1__1_chany_bottom_out ;
wire [0:19] cby_1__1__1_chany_top_out ;
wire [0:0] cby_1__1__1_left_grid_pin_16_ ;
wire [0:0] cby_1__1__1_left_grid_pin_17_ ;
wire [0:0] cby_1__1__1_left_grid_pin_18_ ;
wire [0:0] cby_1__1__1_left_grid_pin_19_ ;
wire [0:0] cby_1__1__1_left_grid_pin_20_ ;
wire [0:0] cby_1__1__1_left_grid_pin_21_ ;
wire [0:0] cby_1__1__1_left_grid_pin_22_ ;
wire [0:0] cby_1__1__1_left_grid_pin_23_ ;
wire [0:0] cby_1__1__1_left_grid_pin_24_ ;
wire [0:0] cby_1__1__1_left_grid_pin_25_ ;
wire [0:0] cby_1__1__1_left_grid_pin_26_ ;
wire [0:0] cby_1__1__1_left_grid_pin_27_ ;
wire [0:0] cby_1__1__1_left_grid_pin_28_ ;
wire [0:0] cby_1__1__1_left_grid_pin_29_ ;
wire [0:0] cby_1__1__1_left_grid_pin_30_ ;
wire [0:0] cby_1__1__1_left_grid_pin_31_ ;
wire [0:0] cby_1__1__20_ccff_tail ;
wire [0:19] cby_1__1__20_chany_bottom_out ;
wire [0:19] cby_1__1__20_chany_top_out ;
wire [0:0] cby_1__1__20_left_grid_pin_16_ ;
wire [0:0] cby_1__1__20_left_grid_pin_17_ ;
wire [0:0] cby_1__1__20_left_grid_pin_18_ ;
wire [0:0] cby_1__1__20_left_grid_pin_19_ ;
wire [0:0] cby_1__1__20_left_grid_pin_20_ ;
wire [0:0] cby_1__1__20_left_grid_pin_21_ ;
wire [0:0] cby_1__1__20_left_grid_pin_22_ ;
wire [0:0] cby_1__1__20_left_grid_pin_23_ ;
wire [0:0] cby_1__1__20_left_grid_pin_24_ ;
wire [0:0] cby_1__1__20_left_grid_pin_25_ ;
wire [0:0] cby_1__1__20_left_grid_pin_26_ ;
wire [0:0] cby_1__1__20_left_grid_pin_27_ ;
wire [0:0] cby_1__1__20_left_grid_pin_28_ ;
wire [0:0] cby_1__1__20_left_grid_pin_29_ ;
wire [0:0] cby_1__1__20_left_grid_pin_30_ ;
wire [0:0] cby_1__1__20_left_grid_pin_31_ ;
wire [0:0] cby_1__1__21_ccff_tail ;
wire [0:19] cby_1__1__21_chany_bottom_out ;
wire [0:19] cby_1__1__21_chany_top_out ;
wire [0:0] cby_1__1__21_left_grid_pin_16_ ;
wire [0:0] cby_1__1__21_left_grid_pin_17_ ;
wire [0:0] cby_1__1__21_left_grid_pin_18_ ;
wire [0:0] cby_1__1__21_left_grid_pin_19_ ;
wire [0:0] cby_1__1__21_left_grid_pin_20_ ;
wire [0:0] cby_1__1__21_left_grid_pin_21_ ;
wire [0:0] cby_1__1__21_left_grid_pin_22_ ;
wire [0:0] cby_1__1__21_left_grid_pin_23_ ;
wire [0:0] cby_1__1__21_left_grid_pin_24_ ;
wire [0:0] cby_1__1__21_left_grid_pin_25_ ;
wire [0:0] cby_1__1__21_left_grid_pin_26_ ;
wire [0:0] cby_1__1__21_left_grid_pin_27_ ;
wire [0:0] cby_1__1__21_left_grid_pin_28_ ;
wire [0:0] cby_1__1__21_left_grid_pin_29_ ;
wire [0:0] cby_1__1__21_left_grid_pin_30_ ;
wire [0:0] cby_1__1__21_left_grid_pin_31_ ;
wire [0:0] cby_1__1__22_ccff_tail ;
wire [0:19] cby_1__1__22_chany_bottom_out ;
wire [0:19] cby_1__1__22_chany_top_out ;
wire [0:0] cby_1__1__22_left_grid_pin_16_ ;
wire [0:0] cby_1__1__22_left_grid_pin_17_ ;
wire [0:0] cby_1__1__22_left_grid_pin_18_ ;
wire [0:0] cby_1__1__22_left_grid_pin_19_ ;
wire [0:0] cby_1__1__22_left_grid_pin_20_ ;
wire [0:0] cby_1__1__22_left_grid_pin_21_ ;
wire [0:0] cby_1__1__22_left_grid_pin_22_ ;
wire [0:0] cby_1__1__22_left_grid_pin_23_ ;
wire [0:0] cby_1__1__22_left_grid_pin_24_ ;
wire [0:0] cby_1__1__22_left_grid_pin_25_ ;
wire [0:0] cby_1__1__22_left_grid_pin_26_ ;
wire [0:0] cby_1__1__22_left_grid_pin_27_ ;
wire [0:0] cby_1__1__22_left_grid_pin_28_ ;
wire [0:0] cby_1__1__22_left_grid_pin_29_ ;
wire [0:0] cby_1__1__22_left_grid_pin_30_ ;
wire [0:0] cby_1__1__22_left_grid_pin_31_ ;
wire [0:0] cby_1__1__23_ccff_tail ;
wire [0:19] cby_1__1__23_chany_bottom_out ;
wire [0:19] cby_1__1__23_chany_top_out ;
wire [0:0] cby_1__1__23_left_grid_pin_16_ ;
wire [0:0] cby_1__1__23_left_grid_pin_17_ ;
wire [0:0] cby_1__1__23_left_grid_pin_18_ ;
wire [0:0] cby_1__1__23_left_grid_pin_19_ ;
wire [0:0] cby_1__1__23_left_grid_pin_20_ ;
wire [0:0] cby_1__1__23_left_grid_pin_21_ ;
wire [0:0] cby_1__1__23_left_grid_pin_22_ ;
wire [0:0] cby_1__1__23_left_grid_pin_23_ ;
wire [0:0] cby_1__1__23_left_grid_pin_24_ ;
wire [0:0] cby_1__1__23_left_grid_pin_25_ ;
wire [0:0] cby_1__1__23_left_grid_pin_26_ ;
wire [0:0] cby_1__1__23_left_grid_pin_27_ ;
wire [0:0] cby_1__1__23_left_grid_pin_28_ ;
wire [0:0] cby_1__1__23_left_grid_pin_29_ ;
wire [0:0] cby_1__1__23_left_grid_pin_30_ ;
wire [0:0] cby_1__1__23_left_grid_pin_31_ ;
wire [0:0] cby_1__1__24_ccff_tail ;
wire [0:19] cby_1__1__24_chany_bottom_out ;
wire [0:19] cby_1__1__24_chany_top_out ;
wire [0:0] cby_1__1__24_left_grid_pin_16_ ;
wire [0:0] cby_1__1__24_left_grid_pin_17_ ;
wire [0:0] cby_1__1__24_left_grid_pin_18_ ;
wire [0:0] cby_1__1__24_left_grid_pin_19_ ;
wire [0:0] cby_1__1__24_left_grid_pin_20_ ;
wire [0:0] cby_1__1__24_left_grid_pin_21_ ;
wire [0:0] cby_1__1__24_left_grid_pin_22_ ;
wire [0:0] cby_1__1__24_left_grid_pin_23_ ;
wire [0:0] cby_1__1__24_left_grid_pin_24_ ;
wire [0:0] cby_1__1__24_left_grid_pin_25_ ;
wire [0:0] cby_1__1__24_left_grid_pin_26_ ;
wire [0:0] cby_1__1__24_left_grid_pin_27_ ;
wire [0:0] cby_1__1__24_left_grid_pin_28_ ;
wire [0:0] cby_1__1__24_left_grid_pin_29_ ;
wire [0:0] cby_1__1__24_left_grid_pin_30_ ;
wire [0:0] cby_1__1__24_left_grid_pin_31_ ;
wire [0:0] cby_1__1__25_ccff_tail ;
wire [0:19] cby_1__1__25_chany_bottom_out ;
wire [0:19] cby_1__1__25_chany_top_out ;
wire [0:0] cby_1__1__25_left_grid_pin_16_ ;
wire [0:0] cby_1__1__25_left_grid_pin_17_ ;
wire [0:0] cby_1__1__25_left_grid_pin_18_ ;
wire [0:0] cby_1__1__25_left_grid_pin_19_ ;
wire [0:0] cby_1__1__25_left_grid_pin_20_ ;
wire [0:0] cby_1__1__25_left_grid_pin_21_ ;
wire [0:0] cby_1__1__25_left_grid_pin_22_ ;
wire [0:0] cby_1__1__25_left_grid_pin_23_ ;
wire [0:0] cby_1__1__25_left_grid_pin_24_ ;
wire [0:0] cby_1__1__25_left_grid_pin_25_ ;
wire [0:0] cby_1__1__25_left_grid_pin_26_ ;
wire [0:0] cby_1__1__25_left_grid_pin_27_ ;
wire [0:0] cby_1__1__25_left_grid_pin_28_ ;
wire [0:0] cby_1__1__25_left_grid_pin_29_ ;
wire [0:0] cby_1__1__25_left_grid_pin_30_ ;
wire [0:0] cby_1__1__25_left_grid_pin_31_ ;
wire [0:0] cby_1__1__26_ccff_tail ;
wire [0:19] cby_1__1__26_chany_bottom_out ;
wire [0:19] cby_1__1__26_chany_top_out ;
wire [0:0] cby_1__1__26_left_grid_pin_16_ ;
wire [0:0] cby_1__1__26_left_grid_pin_17_ ;
wire [0:0] cby_1__1__26_left_grid_pin_18_ ;
wire [0:0] cby_1__1__26_left_grid_pin_19_ ;
wire [0:0] cby_1__1__26_left_grid_pin_20_ ;
wire [0:0] cby_1__1__26_left_grid_pin_21_ ;
wire [0:0] cby_1__1__26_left_grid_pin_22_ ;
wire [0:0] cby_1__1__26_left_grid_pin_23_ ;
wire [0:0] cby_1__1__26_left_grid_pin_24_ ;
wire [0:0] cby_1__1__26_left_grid_pin_25_ ;
wire [0:0] cby_1__1__26_left_grid_pin_26_ ;
wire [0:0] cby_1__1__26_left_grid_pin_27_ ;
wire [0:0] cby_1__1__26_left_grid_pin_28_ ;
wire [0:0] cby_1__1__26_left_grid_pin_29_ ;
wire [0:0] cby_1__1__26_left_grid_pin_30_ ;
wire [0:0] cby_1__1__26_left_grid_pin_31_ ;
wire [0:0] cby_1__1__27_ccff_tail ;
wire [0:19] cby_1__1__27_chany_bottom_out ;
wire [0:19] cby_1__1__27_chany_top_out ;
wire [0:0] cby_1__1__27_left_grid_pin_16_ ;
wire [0:0] cby_1__1__27_left_grid_pin_17_ ;
wire [0:0] cby_1__1__27_left_grid_pin_18_ ;
wire [0:0] cby_1__1__27_left_grid_pin_19_ ;
wire [0:0] cby_1__1__27_left_grid_pin_20_ ;
wire [0:0] cby_1__1__27_left_grid_pin_21_ ;
wire [0:0] cby_1__1__27_left_grid_pin_22_ ;
wire [0:0] cby_1__1__27_left_grid_pin_23_ ;
wire [0:0] cby_1__1__27_left_grid_pin_24_ ;
wire [0:0] cby_1__1__27_left_grid_pin_25_ ;
wire [0:0] cby_1__1__27_left_grid_pin_26_ ;
wire [0:0] cby_1__1__27_left_grid_pin_27_ ;
wire [0:0] cby_1__1__27_left_grid_pin_28_ ;
wire [0:0] cby_1__1__27_left_grid_pin_29_ ;
wire [0:0] cby_1__1__27_left_grid_pin_30_ ;
wire [0:0] cby_1__1__27_left_grid_pin_31_ ;
wire [0:0] cby_1__1__28_ccff_tail ;
wire [0:19] cby_1__1__28_chany_bottom_out ;
wire [0:19] cby_1__1__28_chany_top_out ;
wire [0:0] cby_1__1__28_left_grid_pin_16_ ;
wire [0:0] cby_1__1__28_left_grid_pin_17_ ;
wire [0:0] cby_1__1__28_left_grid_pin_18_ ;
wire [0:0] cby_1__1__28_left_grid_pin_19_ ;
wire [0:0] cby_1__1__28_left_grid_pin_20_ ;
wire [0:0] cby_1__1__28_left_grid_pin_21_ ;
wire [0:0] cby_1__1__28_left_grid_pin_22_ ;
wire [0:0] cby_1__1__28_left_grid_pin_23_ ;
wire [0:0] cby_1__1__28_left_grid_pin_24_ ;
wire [0:0] cby_1__1__28_left_grid_pin_25_ ;
wire [0:0] cby_1__1__28_left_grid_pin_26_ ;
wire [0:0] cby_1__1__28_left_grid_pin_27_ ;
wire [0:0] cby_1__1__28_left_grid_pin_28_ ;
wire [0:0] cby_1__1__28_left_grid_pin_29_ ;
wire [0:0] cby_1__1__28_left_grid_pin_30_ ;
wire [0:0] cby_1__1__28_left_grid_pin_31_ ;
wire [0:0] cby_1__1__29_ccff_tail ;
wire [0:19] cby_1__1__29_chany_bottom_out ;
wire [0:19] cby_1__1__29_chany_top_out ;
wire [0:0] cby_1__1__29_left_grid_pin_16_ ;
wire [0:0] cby_1__1__29_left_grid_pin_17_ ;
wire [0:0] cby_1__1__29_left_grid_pin_18_ ;
wire [0:0] cby_1__1__29_left_grid_pin_19_ ;
wire [0:0] cby_1__1__29_left_grid_pin_20_ ;
wire [0:0] cby_1__1__29_left_grid_pin_21_ ;
wire [0:0] cby_1__1__29_left_grid_pin_22_ ;
wire [0:0] cby_1__1__29_left_grid_pin_23_ ;
wire [0:0] cby_1__1__29_left_grid_pin_24_ ;
wire [0:0] cby_1__1__29_left_grid_pin_25_ ;
wire [0:0] cby_1__1__29_left_grid_pin_26_ ;
wire [0:0] cby_1__1__29_left_grid_pin_27_ ;
wire [0:0] cby_1__1__29_left_grid_pin_28_ ;
wire [0:0] cby_1__1__29_left_grid_pin_29_ ;
wire [0:0] cby_1__1__29_left_grid_pin_30_ ;
wire [0:0] cby_1__1__29_left_grid_pin_31_ ;
wire [0:0] cby_1__1__2_ccff_tail ;
wire [0:19] cby_1__1__2_chany_bottom_out ;
wire [0:19] cby_1__1__2_chany_top_out ;
wire [0:0] cby_1__1__2_left_grid_pin_16_ ;
wire [0:0] cby_1__1__2_left_grid_pin_17_ ;
wire [0:0] cby_1__1__2_left_grid_pin_18_ ;
wire [0:0] cby_1__1__2_left_grid_pin_19_ ;
wire [0:0] cby_1__1__2_left_grid_pin_20_ ;
wire [0:0] cby_1__1__2_left_grid_pin_21_ ;
wire [0:0] cby_1__1__2_left_grid_pin_22_ ;
wire [0:0] cby_1__1__2_left_grid_pin_23_ ;
wire [0:0] cby_1__1__2_left_grid_pin_24_ ;
wire [0:0] cby_1__1__2_left_grid_pin_25_ ;
wire [0:0] cby_1__1__2_left_grid_pin_26_ ;
wire [0:0] cby_1__1__2_left_grid_pin_27_ ;
wire [0:0] cby_1__1__2_left_grid_pin_28_ ;
wire [0:0] cby_1__1__2_left_grid_pin_29_ ;
wire [0:0] cby_1__1__2_left_grid_pin_30_ ;
wire [0:0] cby_1__1__2_left_grid_pin_31_ ;
wire [0:0] cby_1__1__30_ccff_tail ;
wire [0:19] cby_1__1__30_chany_bottom_out ;
wire [0:19] cby_1__1__30_chany_top_out ;
wire [0:0] cby_1__1__30_left_grid_pin_16_ ;
wire [0:0] cby_1__1__30_left_grid_pin_17_ ;
wire [0:0] cby_1__1__30_left_grid_pin_18_ ;
wire [0:0] cby_1__1__30_left_grid_pin_19_ ;
wire [0:0] cby_1__1__30_left_grid_pin_20_ ;
wire [0:0] cby_1__1__30_left_grid_pin_21_ ;
wire [0:0] cby_1__1__30_left_grid_pin_22_ ;
wire [0:0] cby_1__1__30_left_grid_pin_23_ ;
wire [0:0] cby_1__1__30_left_grid_pin_24_ ;
wire [0:0] cby_1__1__30_left_grid_pin_25_ ;
wire [0:0] cby_1__1__30_left_grid_pin_26_ ;
wire [0:0] cby_1__1__30_left_grid_pin_27_ ;
wire [0:0] cby_1__1__30_left_grid_pin_28_ ;
wire [0:0] cby_1__1__30_left_grid_pin_29_ ;
wire [0:0] cby_1__1__30_left_grid_pin_30_ ;
wire [0:0] cby_1__1__30_left_grid_pin_31_ ;
wire [0:0] cby_1__1__31_ccff_tail ;
wire [0:19] cby_1__1__31_chany_bottom_out ;
wire [0:19] cby_1__1__31_chany_top_out ;
wire [0:0] cby_1__1__31_left_grid_pin_16_ ;
wire [0:0] cby_1__1__31_left_grid_pin_17_ ;
wire [0:0] cby_1__1__31_left_grid_pin_18_ ;
wire [0:0] cby_1__1__31_left_grid_pin_19_ ;
wire [0:0] cby_1__1__31_left_grid_pin_20_ ;
wire [0:0] cby_1__1__31_left_grid_pin_21_ ;
wire [0:0] cby_1__1__31_left_grid_pin_22_ ;
wire [0:0] cby_1__1__31_left_grid_pin_23_ ;
wire [0:0] cby_1__1__31_left_grid_pin_24_ ;
wire [0:0] cby_1__1__31_left_grid_pin_25_ ;
wire [0:0] cby_1__1__31_left_grid_pin_26_ ;
wire [0:0] cby_1__1__31_left_grid_pin_27_ ;
wire [0:0] cby_1__1__31_left_grid_pin_28_ ;
wire [0:0] cby_1__1__31_left_grid_pin_29_ ;
wire [0:0] cby_1__1__31_left_grid_pin_30_ ;
wire [0:0] cby_1__1__31_left_grid_pin_31_ ;
wire [0:0] cby_1__1__32_ccff_tail ;
wire [0:19] cby_1__1__32_chany_bottom_out ;
wire [0:19] cby_1__1__32_chany_top_out ;
wire [0:0] cby_1__1__32_left_grid_pin_16_ ;
wire [0:0] cby_1__1__32_left_grid_pin_17_ ;
wire [0:0] cby_1__1__32_left_grid_pin_18_ ;
wire [0:0] cby_1__1__32_left_grid_pin_19_ ;
wire [0:0] cby_1__1__32_left_grid_pin_20_ ;
wire [0:0] cby_1__1__32_left_grid_pin_21_ ;
wire [0:0] cby_1__1__32_left_grid_pin_22_ ;
wire [0:0] cby_1__1__32_left_grid_pin_23_ ;
wire [0:0] cby_1__1__32_left_grid_pin_24_ ;
wire [0:0] cby_1__1__32_left_grid_pin_25_ ;
wire [0:0] cby_1__1__32_left_grid_pin_26_ ;
wire [0:0] cby_1__1__32_left_grid_pin_27_ ;
wire [0:0] cby_1__1__32_left_grid_pin_28_ ;
wire [0:0] cby_1__1__32_left_grid_pin_29_ ;
wire [0:0] cby_1__1__32_left_grid_pin_30_ ;
wire [0:0] cby_1__1__32_left_grid_pin_31_ ;
wire [0:0] cby_1__1__33_ccff_tail ;
wire [0:19] cby_1__1__33_chany_bottom_out ;
wire [0:19] cby_1__1__33_chany_top_out ;
wire [0:0] cby_1__1__33_left_grid_pin_16_ ;
wire [0:0] cby_1__1__33_left_grid_pin_17_ ;
wire [0:0] cby_1__1__33_left_grid_pin_18_ ;
wire [0:0] cby_1__1__33_left_grid_pin_19_ ;
wire [0:0] cby_1__1__33_left_grid_pin_20_ ;
wire [0:0] cby_1__1__33_left_grid_pin_21_ ;
wire [0:0] cby_1__1__33_left_grid_pin_22_ ;
wire [0:0] cby_1__1__33_left_grid_pin_23_ ;
wire [0:0] cby_1__1__33_left_grid_pin_24_ ;
wire [0:0] cby_1__1__33_left_grid_pin_25_ ;
wire [0:0] cby_1__1__33_left_grid_pin_26_ ;
wire [0:0] cby_1__1__33_left_grid_pin_27_ ;
wire [0:0] cby_1__1__33_left_grid_pin_28_ ;
wire [0:0] cby_1__1__33_left_grid_pin_29_ ;
wire [0:0] cby_1__1__33_left_grid_pin_30_ ;
wire [0:0] cby_1__1__33_left_grid_pin_31_ ;
wire [0:0] cby_1__1__34_ccff_tail ;
wire [0:19] cby_1__1__34_chany_bottom_out ;
wire [0:19] cby_1__1__34_chany_top_out ;
wire [0:0] cby_1__1__34_left_grid_pin_16_ ;
wire [0:0] cby_1__1__34_left_grid_pin_17_ ;
wire [0:0] cby_1__1__34_left_grid_pin_18_ ;
wire [0:0] cby_1__1__34_left_grid_pin_19_ ;
wire [0:0] cby_1__1__34_left_grid_pin_20_ ;
wire [0:0] cby_1__1__34_left_grid_pin_21_ ;
wire [0:0] cby_1__1__34_left_grid_pin_22_ ;
wire [0:0] cby_1__1__34_left_grid_pin_23_ ;
wire [0:0] cby_1__1__34_left_grid_pin_24_ ;
wire [0:0] cby_1__1__34_left_grid_pin_25_ ;
wire [0:0] cby_1__1__34_left_grid_pin_26_ ;
wire [0:0] cby_1__1__34_left_grid_pin_27_ ;
wire [0:0] cby_1__1__34_left_grid_pin_28_ ;
wire [0:0] cby_1__1__34_left_grid_pin_29_ ;
wire [0:0] cby_1__1__34_left_grid_pin_30_ ;
wire [0:0] cby_1__1__34_left_grid_pin_31_ ;
wire [0:0] cby_1__1__35_ccff_tail ;
wire [0:19] cby_1__1__35_chany_bottom_out ;
wire [0:19] cby_1__1__35_chany_top_out ;
wire [0:0] cby_1__1__35_left_grid_pin_16_ ;
wire [0:0] cby_1__1__35_left_grid_pin_17_ ;
wire [0:0] cby_1__1__35_left_grid_pin_18_ ;
wire [0:0] cby_1__1__35_left_grid_pin_19_ ;
wire [0:0] cby_1__1__35_left_grid_pin_20_ ;
wire [0:0] cby_1__1__35_left_grid_pin_21_ ;
wire [0:0] cby_1__1__35_left_grid_pin_22_ ;
wire [0:0] cby_1__1__35_left_grid_pin_23_ ;
wire [0:0] cby_1__1__35_left_grid_pin_24_ ;
wire [0:0] cby_1__1__35_left_grid_pin_25_ ;
wire [0:0] cby_1__1__35_left_grid_pin_26_ ;
wire [0:0] cby_1__1__35_left_grid_pin_27_ ;
wire [0:0] cby_1__1__35_left_grid_pin_28_ ;
wire [0:0] cby_1__1__35_left_grid_pin_29_ ;
wire [0:0] cby_1__1__35_left_grid_pin_30_ ;
wire [0:0] cby_1__1__35_left_grid_pin_31_ ;
wire [0:0] cby_1__1__36_ccff_tail ;
wire [0:19] cby_1__1__36_chany_bottom_out ;
wire [0:19] cby_1__1__36_chany_top_out ;
wire [0:0] cby_1__1__36_left_grid_pin_16_ ;
wire [0:0] cby_1__1__36_left_grid_pin_17_ ;
wire [0:0] cby_1__1__36_left_grid_pin_18_ ;
wire [0:0] cby_1__1__36_left_grid_pin_19_ ;
wire [0:0] cby_1__1__36_left_grid_pin_20_ ;
wire [0:0] cby_1__1__36_left_grid_pin_21_ ;
wire [0:0] cby_1__1__36_left_grid_pin_22_ ;
wire [0:0] cby_1__1__36_left_grid_pin_23_ ;
wire [0:0] cby_1__1__36_left_grid_pin_24_ ;
wire [0:0] cby_1__1__36_left_grid_pin_25_ ;
wire [0:0] cby_1__1__36_left_grid_pin_26_ ;
wire [0:0] cby_1__1__36_left_grid_pin_27_ ;
wire [0:0] cby_1__1__36_left_grid_pin_28_ ;
wire [0:0] cby_1__1__36_left_grid_pin_29_ ;
wire [0:0] cby_1__1__36_left_grid_pin_30_ ;
wire [0:0] cby_1__1__36_left_grid_pin_31_ ;
wire [0:0] cby_1__1__37_ccff_tail ;
wire [0:19] cby_1__1__37_chany_bottom_out ;
wire [0:19] cby_1__1__37_chany_top_out ;
wire [0:0] cby_1__1__37_left_grid_pin_16_ ;
wire [0:0] cby_1__1__37_left_grid_pin_17_ ;
wire [0:0] cby_1__1__37_left_grid_pin_18_ ;
wire [0:0] cby_1__1__37_left_grid_pin_19_ ;
wire [0:0] cby_1__1__37_left_grid_pin_20_ ;
wire [0:0] cby_1__1__37_left_grid_pin_21_ ;
wire [0:0] cby_1__1__37_left_grid_pin_22_ ;
wire [0:0] cby_1__1__37_left_grid_pin_23_ ;
wire [0:0] cby_1__1__37_left_grid_pin_24_ ;
wire [0:0] cby_1__1__37_left_grid_pin_25_ ;
wire [0:0] cby_1__1__37_left_grid_pin_26_ ;
wire [0:0] cby_1__1__37_left_grid_pin_27_ ;
wire [0:0] cby_1__1__37_left_grid_pin_28_ ;
wire [0:0] cby_1__1__37_left_grid_pin_29_ ;
wire [0:0] cby_1__1__37_left_grid_pin_30_ ;
wire [0:0] cby_1__1__37_left_grid_pin_31_ ;
wire [0:0] cby_1__1__38_ccff_tail ;
wire [0:19] cby_1__1__38_chany_bottom_out ;
wire [0:19] cby_1__1__38_chany_top_out ;
wire [0:0] cby_1__1__38_left_grid_pin_16_ ;
wire [0:0] cby_1__1__38_left_grid_pin_17_ ;
wire [0:0] cby_1__1__38_left_grid_pin_18_ ;
wire [0:0] cby_1__1__38_left_grid_pin_19_ ;
wire [0:0] cby_1__1__38_left_grid_pin_20_ ;
wire [0:0] cby_1__1__38_left_grid_pin_21_ ;
wire [0:0] cby_1__1__38_left_grid_pin_22_ ;
wire [0:0] cby_1__1__38_left_grid_pin_23_ ;
wire [0:0] cby_1__1__38_left_grid_pin_24_ ;
wire [0:0] cby_1__1__38_left_grid_pin_25_ ;
wire [0:0] cby_1__1__38_left_grid_pin_26_ ;
wire [0:0] cby_1__1__38_left_grid_pin_27_ ;
wire [0:0] cby_1__1__38_left_grid_pin_28_ ;
wire [0:0] cby_1__1__38_left_grid_pin_29_ ;
wire [0:0] cby_1__1__38_left_grid_pin_30_ ;
wire [0:0] cby_1__1__38_left_grid_pin_31_ ;
wire [0:0] cby_1__1__39_ccff_tail ;
wire [0:19] cby_1__1__39_chany_bottom_out ;
wire [0:19] cby_1__1__39_chany_top_out ;
wire [0:0] cby_1__1__39_left_grid_pin_16_ ;
wire [0:0] cby_1__1__39_left_grid_pin_17_ ;
wire [0:0] cby_1__1__39_left_grid_pin_18_ ;
wire [0:0] cby_1__1__39_left_grid_pin_19_ ;
wire [0:0] cby_1__1__39_left_grid_pin_20_ ;
wire [0:0] cby_1__1__39_left_grid_pin_21_ ;
wire [0:0] cby_1__1__39_left_grid_pin_22_ ;
wire [0:0] cby_1__1__39_left_grid_pin_23_ ;
wire [0:0] cby_1__1__39_left_grid_pin_24_ ;
wire [0:0] cby_1__1__39_left_grid_pin_25_ ;
wire [0:0] cby_1__1__39_left_grid_pin_26_ ;
wire [0:0] cby_1__1__39_left_grid_pin_27_ ;
wire [0:0] cby_1__1__39_left_grid_pin_28_ ;
wire [0:0] cby_1__1__39_left_grid_pin_29_ ;
wire [0:0] cby_1__1__39_left_grid_pin_30_ ;
wire [0:0] cby_1__1__39_left_grid_pin_31_ ;
wire [0:0] cby_1__1__3_ccff_tail ;
wire [0:19] cby_1__1__3_chany_bottom_out ;
wire [0:19] cby_1__1__3_chany_top_out ;
wire [0:0] cby_1__1__3_left_grid_pin_16_ ;
wire [0:0] cby_1__1__3_left_grid_pin_17_ ;
wire [0:0] cby_1__1__3_left_grid_pin_18_ ;
wire [0:0] cby_1__1__3_left_grid_pin_19_ ;
wire [0:0] cby_1__1__3_left_grid_pin_20_ ;
wire [0:0] cby_1__1__3_left_grid_pin_21_ ;
wire [0:0] cby_1__1__3_left_grid_pin_22_ ;
wire [0:0] cby_1__1__3_left_grid_pin_23_ ;
wire [0:0] cby_1__1__3_left_grid_pin_24_ ;
wire [0:0] cby_1__1__3_left_grid_pin_25_ ;
wire [0:0] cby_1__1__3_left_grid_pin_26_ ;
wire [0:0] cby_1__1__3_left_grid_pin_27_ ;
wire [0:0] cby_1__1__3_left_grid_pin_28_ ;
wire [0:0] cby_1__1__3_left_grid_pin_29_ ;
wire [0:0] cby_1__1__3_left_grid_pin_30_ ;
wire [0:0] cby_1__1__3_left_grid_pin_31_ ;
wire [0:0] cby_1__1__40_ccff_tail ;
wire [0:19] cby_1__1__40_chany_bottom_out ;
wire [0:19] cby_1__1__40_chany_top_out ;
wire [0:0] cby_1__1__40_left_grid_pin_16_ ;
wire [0:0] cby_1__1__40_left_grid_pin_17_ ;
wire [0:0] cby_1__1__40_left_grid_pin_18_ ;
wire [0:0] cby_1__1__40_left_grid_pin_19_ ;
wire [0:0] cby_1__1__40_left_grid_pin_20_ ;
wire [0:0] cby_1__1__40_left_grid_pin_21_ ;
wire [0:0] cby_1__1__40_left_grid_pin_22_ ;
wire [0:0] cby_1__1__40_left_grid_pin_23_ ;
wire [0:0] cby_1__1__40_left_grid_pin_24_ ;
wire [0:0] cby_1__1__40_left_grid_pin_25_ ;
wire [0:0] cby_1__1__40_left_grid_pin_26_ ;
wire [0:0] cby_1__1__40_left_grid_pin_27_ ;
wire [0:0] cby_1__1__40_left_grid_pin_28_ ;
wire [0:0] cby_1__1__40_left_grid_pin_29_ ;
wire [0:0] cby_1__1__40_left_grid_pin_30_ ;
wire [0:0] cby_1__1__40_left_grid_pin_31_ ;
wire [0:0] cby_1__1__41_ccff_tail ;
wire [0:19] cby_1__1__41_chany_bottom_out ;
wire [0:19] cby_1__1__41_chany_top_out ;
wire [0:0] cby_1__1__41_left_grid_pin_16_ ;
wire [0:0] cby_1__1__41_left_grid_pin_17_ ;
wire [0:0] cby_1__1__41_left_grid_pin_18_ ;
wire [0:0] cby_1__1__41_left_grid_pin_19_ ;
wire [0:0] cby_1__1__41_left_grid_pin_20_ ;
wire [0:0] cby_1__1__41_left_grid_pin_21_ ;
wire [0:0] cby_1__1__41_left_grid_pin_22_ ;
wire [0:0] cby_1__1__41_left_grid_pin_23_ ;
wire [0:0] cby_1__1__41_left_grid_pin_24_ ;
wire [0:0] cby_1__1__41_left_grid_pin_25_ ;
wire [0:0] cby_1__1__41_left_grid_pin_26_ ;
wire [0:0] cby_1__1__41_left_grid_pin_27_ ;
wire [0:0] cby_1__1__41_left_grid_pin_28_ ;
wire [0:0] cby_1__1__41_left_grid_pin_29_ ;
wire [0:0] cby_1__1__41_left_grid_pin_30_ ;
wire [0:0] cby_1__1__41_left_grid_pin_31_ ;
wire [0:0] cby_1__1__42_ccff_tail ;
wire [0:19] cby_1__1__42_chany_bottom_out ;
wire [0:19] cby_1__1__42_chany_top_out ;
wire [0:0] cby_1__1__42_left_grid_pin_16_ ;
wire [0:0] cby_1__1__42_left_grid_pin_17_ ;
wire [0:0] cby_1__1__42_left_grid_pin_18_ ;
wire [0:0] cby_1__1__42_left_grid_pin_19_ ;
wire [0:0] cby_1__1__42_left_grid_pin_20_ ;
wire [0:0] cby_1__1__42_left_grid_pin_21_ ;
wire [0:0] cby_1__1__42_left_grid_pin_22_ ;
wire [0:0] cby_1__1__42_left_grid_pin_23_ ;
wire [0:0] cby_1__1__42_left_grid_pin_24_ ;
wire [0:0] cby_1__1__42_left_grid_pin_25_ ;
wire [0:0] cby_1__1__42_left_grid_pin_26_ ;
wire [0:0] cby_1__1__42_left_grid_pin_27_ ;
wire [0:0] cby_1__1__42_left_grid_pin_28_ ;
wire [0:0] cby_1__1__42_left_grid_pin_29_ ;
wire [0:0] cby_1__1__42_left_grid_pin_30_ ;
wire [0:0] cby_1__1__42_left_grid_pin_31_ ;
wire [0:0] cby_1__1__43_ccff_tail ;
wire [0:19] cby_1__1__43_chany_bottom_out ;
wire [0:19] cby_1__1__43_chany_top_out ;
wire [0:0] cby_1__1__43_left_grid_pin_16_ ;
wire [0:0] cby_1__1__43_left_grid_pin_17_ ;
wire [0:0] cby_1__1__43_left_grid_pin_18_ ;
wire [0:0] cby_1__1__43_left_grid_pin_19_ ;
wire [0:0] cby_1__1__43_left_grid_pin_20_ ;
wire [0:0] cby_1__1__43_left_grid_pin_21_ ;
wire [0:0] cby_1__1__43_left_grid_pin_22_ ;
wire [0:0] cby_1__1__43_left_grid_pin_23_ ;
wire [0:0] cby_1__1__43_left_grid_pin_24_ ;
wire [0:0] cby_1__1__43_left_grid_pin_25_ ;
wire [0:0] cby_1__1__43_left_grid_pin_26_ ;
wire [0:0] cby_1__1__43_left_grid_pin_27_ ;
wire [0:0] cby_1__1__43_left_grid_pin_28_ ;
wire [0:0] cby_1__1__43_left_grid_pin_29_ ;
wire [0:0] cby_1__1__43_left_grid_pin_30_ ;
wire [0:0] cby_1__1__43_left_grid_pin_31_ ;
wire [0:0] cby_1__1__44_ccff_tail ;
wire [0:19] cby_1__1__44_chany_bottom_out ;
wire [0:19] cby_1__1__44_chany_top_out ;
wire [0:0] cby_1__1__44_left_grid_pin_16_ ;
wire [0:0] cby_1__1__44_left_grid_pin_17_ ;
wire [0:0] cby_1__1__44_left_grid_pin_18_ ;
wire [0:0] cby_1__1__44_left_grid_pin_19_ ;
wire [0:0] cby_1__1__44_left_grid_pin_20_ ;
wire [0:0] cby_1__1__44_left_grid_pin_21_ ;
wire [0:0] cby_1__1__44_left_grid_pin_22_ ;
wire [0:0] cby_1__1__44_left_grid_pin_23_ ;
wire [0:0] cby_1__1__44_left_grid_pin_24_ ;
wire [0:0] cby_1__1__44_left_grid_pin_25_ ;
wire [0:0] cby_1__1__44_left_grid_pin_26_ ;
wire [0:0] cby_1__1__44_left_grid_pin_27_ ;
wire [0:0] cby_1__1__44_left_grid_pin_28_ ;
wire [0:0] cby_1__1__44_left_grid_pin_29_ ;
wire [0:0] cby_1__1__44_left_grid_pin_30_ ;
wire [0:0] cby_1__1__44_left_grid_pin_31_ ;
wire [0:0] cby_1__1__45_ccff_tail ;
wire [0:19] cby_1__1__45_chany_bottom_out ;
wire [0:19] cby_1__1__45_chany_top_out ;
wire [0:0] cby_1__1__45_left_grid_pin_16_ ;
wire [0:0] cby_1__1__45_left_grid_pin_17_ ;
wire [0:0] cby_1__1__45_left_grid_pin_18_ ;
wire [0:0] cby_1__1__45_left_grid_pin_19_ ;
wire [0:0] cby_1__1__45_left_grid_pin_20_ ;
wire [0:0] cby_1__1__45_left_grid_pin_21_ ;
wire [0:0] cby_1__1__45_left_grid_pin_22_ ;
wire [0:0] cby_1__1__45_left_grid_pin_23_ ;
wire [0:0] cby_1__1__45_left_grid_pin_24_ ;
wire [0:0] cby_1__1__45_left_grid_pin_25_ ;
wire [0:0] cby_1__1__45_left_grid_pin_26_ ;
wire [0:0] cby_1__1__45_left_grid_pin_27_ ;
wire [0:0] cby_1__1__45_left_grid_pin_28_ ;
wire [0:0] cby_1__1__45_left_grid_pin_29_ ;
wire [0:0] cby_1__1__45_left_grid_pin_30_ ;
wire [0:0] cby_1__1__45_left_grid_pin_31_ ;
wire [0:0] cby_1__1__46_ccff_tail ;
wire [0:19] cby_1__1__46_chany_bottom_out ;
wire [0:19] cby_1__1__46_chany_top_out ;
wire [0:0] cby_1__1__46_left_grid_pin_16_ ;
wire [0:0] cby_1__1__46_left_grid_pin_17_ ;
wire [0:0] cby_1__1__46_left_grid_pin_18_ ;
wire [0:0] cby_1__1__46_left_grid_pin_19_ ;
wire [0:0] cby_1__1__46_left_grid_pin_20_ ;
wire [0:0] cby_1__1__46_left_grid_pin_21_ ;
wire [0:0] cby_1__1__46_left_grid_pin_22_ ;
wire [0:0] cby_1__1__46_left_grid_pin_23_ ;
wire [0:0] cby_1__1__46_left_grid_pin_24_ ;
wire [0:0] cby_1__1__46_left_grid_pin_25_ ;
wire [0:0] cby_1__1__46_left_grid_pin_26_ ;
wire [0:0] cby_1__1__46_left_grid_pin_27_ ;
wire [0:0] cby_1__1__46_left_grid_pin_28_ ;
wire [0:0] cby_1__1__46_left_grid_pin_29_ ;
wire [0:0] cby_1__1__46_left_grid_pin_30_ ;
wire [0:0] cby_1__1__46_left_grid_pin_31_ ;
wire [0:0] cby_1__1__47_ccff_tail ;
wire [0:19] cby_1__1__47_chany_bottom_out ;
wire [0:19] cby_1__1__47_chany_top_out ;
wire [0:0] cby_1__1__47_left_grid_pin_16_ ;
wire [0:0] cby_1__1__47_left_grid_pin_17_ ;
wire [0:0] cby_1__1__47_left_grid_pin_18_ ;
wire [0:0] cby_1__1__47_left_grid_pin_19_ ;
wire [0:0] cby_1__1__47_left_grid_pin_20_ ;
wire [0:0] cby_1__1__47_left_grid_pin_21_ ;
wire [0:0] cby_1__1__47_left_grid_pin_22_ ;
wire [0:0] cby_1__1__47_left_grid_pin_23_ ;
wire [0:0] cby_1__1__47_left_grid_pin_24_ ;
wire [0:0] cby_1__1__47_left_grid_pin_25_ ;
wire [0:0] cby_1__1__47_left_grid_pin_26_ ;
wire [0:0] cby_1__1__47_left_grid_pin_27_ ;
wire [0:0] cby_1__1__47_left_grid_pin_28_ ;
wire [0:0] cby_1__1__47_left_grid_pin_29_ ;
wire [0:0] cby_1__1__47_left_grid_pin_30_ ;
wire [0:0] cby_1__1__47_left_grid_pin_31_ ;
wire [0:0] cby_1__1__48_ccff_tail ;
wire [0:19] cby_1__1__48_chany_bottom_out ;
wire [0:19] cby_1__1__48_chany_top_out ;
wire [0:0] cby_1__1__48_left_grid_pin_16_ ;
wire [0:0] cby_1__1__48_left_grid_pin_17_ ;
wire [0:0] cby_1__1__48_left_grid_pin_18_ ;
wire [0:0] cby_1__1__48_left_grid_pin_19_ ;
wire [0:0] cby_1__1__48_left_grid_pin_20_ ;
wire [0:0] cby_1__1__48_left_grid_pin_21_ ;
wire [0:0] cby_1__1__48_left_grid_pin_22_ ;
wire [0:0] cby_1__1__48_left_grid_pin_23_ ;
wire [0:0] cby_1__1__48_left_grid_pin_24_ ;
wire [0:0] cby_1__1__48_left_grid_pin_25_ ;
wire [0:0] cby_1__1__48_left_grid_pin_26_ ;
wire [0:0] cby_1__1__48_left_grid_pin_27_ ;
wire [0:0] cby_1__1__48_left_grid_pin_28_ ;
wire [0:0] cby_1__1__48_left_grid_pin_29_ ;
wire [0:0] cby_1__1__48_left_grid_pin_30_ ;
wire [0:0] cby_1__1__48_left_grid_pin_31_ ;
wire [0:0] cby_1__1__49_ccff_tail ;
wire [0:19] cby_1__1__49_chany_bottom_out ;
wire [0:19] cby_1__1__49_chany_top_out ;
wire [0:0] cby_1__1__49_left_grid_pin_16_ ;
wire [0:0] cby_1__1__49_left_grid_pin_17_ ;
wire [0:0] cby_1__1__49_left_grid_pin_18_ ;
wire [0:0] cby_1__1__49_left_grid_pin_19_ ;
wire [0:0] cby_1__1__49_left_grid_pin_20_ ;
wire [0:0] cby_1__1__49_left_grid_pin_21_ ;
wire [0:0] cby_1__1__49_left_grid_pin_22_ ;
wire [0:0] cby_1__1__49_left_grid_pin_23_ ;
wire [0:0] cby_1__1__49_left_grid_pin_24_ ;
wire [0:0] cby_1__1__49_left_grid_pin_25_ ;
wire [0:0] cby_1__1__49_left_grid_pin_26_ ;
wire [0:0] cby_1__1__49_left_grid_pin_27_ ;
wire [0:0] cby_1__1__49_left_grid_pin_28_ ;
wire [0:0] cby_1__1__49_left_grid_pin_29_ ;
wire [0:0] cby_1__1__49_left_grid_pin_30_ ;
wire [0:0] cby_1__1__49_left_grid_pin_31_ ;
wire [0:0] cby_1__1__4_ccff_tail ;
wire [0:19] cby_1__1__4_chany_bottom_out ;
wire [0:19] cby_1__1__4_chany_top_out ;
wire [0:0] cby_1__1__4_left_grid_pin_16_ ;
wire [0:0] cby_1__1__4_left_grid_pin_17_ ;
wire [0:0] cby_1__1__4_left_grid_pin_18_ ;
wire [0:0] cby_1__1__4_left_grid_pin_19_ ;
wire [0:0] cby_1__1__4_left_grid_pin_20_ ;
wire [0:0] cby_1__1__4_left_grid_pin_21_ ;
wire [0:0] cby_1__1__4_left_grid_pin_22_ ;
wire [0:0] cby_1__1__4_left_grid_pin_23_ ;
wire [0:0] cby_1__1__4_left_grid_pin_24_ ;
wire [0:0] cby_1__1__4_left_grid_pin_25_ ;
wire [0:0] cby_1__1__4_left_grid_pin_26_ ;
wire [0:0] cby_1__1__4_left_grid_pin_27_ ;
wire [0:0] cby_1__1__4_left_grid_pin_28_ ;
wire [0:0] cby_1__1__4_left_grid_pin_29_ ;
wire [0:0] cby_1__1__4_left_grid_pin_30_ ;
wire [0:0] cby_1__1__4_left_grid_pin_31_ ;
wire [0:0] cby_1__1__50_ccff_tail ;
wire [0:19] cby_1__1__50_chany_bottom_out ;
wire [0:19] cby_1__1__50_chany_top_out ;
wire [0:0] cby_1__1__50_left_grid_pin_16_ ;
wire [0:0] cby_1__1__50_left_grid_pin_17_ ;
wire [0:0] cby_1__1__50_left_grid_pin_18_ ;
wire [0:0] cby_1__1__50_left_grid_pin_19_ ;
wire [0:0] cby_1__1__50_left_grid_pin_20_ ;
wire [0:0] cby_1__1__50_left_grid_pin_21_ ;
wire [0:0] cby_1__1__50_left_grid_pin_22_ ;
wire [0:0] cby_1__1__50_left_grid_pin_23_ ;
wire [0:0] cby_1__1__50_left_grid_pin_24_ ;
wire [0:0] cby_1__1__50_left_grid_pin_25_ ;
wire [0:0] cby_1__1__50_left_grid_pin_26_ ;
wire [0:0] cby_1__1__50_left_grid_pin_27_ ;
wire [0:0] cby_1__1__50_left_grid_pin_28_ ;
wire [0:0] cby_1__1__50_left_grid_pin_29_ ;
wire [0:0] cby_1__1__50_left_grid_pin_30_ ;
wire [0:0] cby_1__1__50_left_grid_pin_31_ ;
wire [0:0] cby_1__1__51_ccff_tail ;
wire [0:19] cby_1__1__51_chany_bottom_out ;
wire [0:19] cby_1__1__51_chany_top_out ;
wire [0:0] cby_1__1__51_left_grid_pin_16_ ;
wire [0:0] cby_1__1__51_left_grid_pin_17_ ;
wire [0:0] cby_1__1__51_left_grid_pin_18_ ;
wire [0:0] cby_1__1__51_left_grid_pin_19_ ;
wire [0:0] cby_1__1__51_left_grid_pin_20_ ;
wire [0:0] cby_1__1__51_left_grid_pin_21_ ;
wire [0:0] cby_1__1__51_left_grid_pin_22_ ;
wire [0:0] cby_1__1__51_left_grid_pin_23_ ;
wire [0:0] cby_1__1__51_left_grid_pin_24_ ;
wire [0:0] cby_1__1__51_left_grid_pin_25_ ;
wire [0:0] cby_1__1__51_left_grid_pin_26_ ;
wire [0:0] cby_1__1__51_left_grid_pin_27_ ;
wire [0:0] cby_1__1__51_left_grid_pin_28_ ;
wire [0:0] cby_1__1__51_left_grid_pin_29_ ;
wire [0:0] cby_1__1__51_left_grid_pin_30_ ;
wire [0:0] cby_1__1__51_left_grid_pin_31_ ;
wire [0:0] cby_1__1__52_ccff_tail ;
wire [0:19] cby_1__1__52_chany_bottom_out ;
wire [0:19] cby_1__1__52_chany_top_out ;
wire [0:0] cby_1__1__52_left_grid_pin_16_ ;
wire [0:0] cby_1__1__52_left_grid_pin_17_ ;
wire [0:0] cby_1__1__52_left_grid_pin_18_ ;
wire [0:0] cby_1__1__52_left_grid_pin_19_ ;
wire [0:0] cby_1__1__52_left_grid_pin_20_ ;
wire [0:0] cby_1__1__52_left_grid_pin_21_ ;
wire [0:0] cby_1__1__52_left_grid_pin_22_ ;
wire [0:0] cby_1__1__52_left_grid_pin_23_ ;
wire [0:0] cby_1__1__52_left_grid_pin_24_ ;
wire [0:0] cby_1__1__52_left_grid_pin_25_ ;
wire [0:0] cby_1__1__52_left_grid_pin_26_ ;
wire [0:0] cby_1__1__52_left_grid_pin_27_ ;
wire [0:0] cby_1__1__52_left_grid_pin_28_ ;
wire [0:0] cby_1__1__52_left_grid_pin_29_ ;
wire [0:0] cby_1__1__52_left_grid_pin_30_ ;
wire [0:0] cby_1__1__52_left_grid_pin_31_ ;
wire [0:0] cby_1__1__53_ccff_tail ;
wire [0:19] cby_1__1__53_chany_bottom_out ;
wire [0:19] cby_1__1__53_chany_top_out ;
wire [0:0] cby_1__1__53_left_grid_pin_16_ ;
wire [0:0] cby_1__1__53_left_grid_pin_17_ ;
wire [0:0] cby_1__1__53_left_grid_pin_18_ ;
wire [0:0] cby_1__1__53_left_grid_pin_19_ ;
wire [0:0] cby_1__1__53_left_grid_pin_20_ ;
wire [0:0] cby_1__1__53_left_grid_pin_21_ ;
wire [0:0] cby_1__1__53_left_grid_pin_22_ ;
wire [0:0] cby_1__1__53_left_grid_pin_23_ ;
wire [0:0] cby_1__1__53_left_grid_pin_24_ ;
wire [0:0] cby_1__1__53_left_grid_pin_25_ ;
wire [0:0] cby_1__1__53_left_grid_pin_26_ ;
wire [0:0] cby_1__1__53_left_grid_pin_27_ ;
wire [0:0] cby_1__1__53_left_grid_pin_28_ ;
wire [0:0] cby_1__1__53_left_grid_pin_29_ ;
wire [0:0] cby_1__1__53_left_grid_pin_30_ ;
wire [0:0] cby_1__1__53_left_grid_pin_31_ ;
wire [0:0] cby_1__1__54_ccff_tail ;
wire [0:19] cby_1__1__54_chany_bottom_out ;
wire [0:19] cby_1__1__54_chany_top_out ;
wire [0:0] cby_1__1__54_left_grid_pin_16_ ;
wire [0:0] cby_1__1__54_left_grid_pin_17_ ;
wire [0:0] cby_1__1__54_left_grid_pin_18_ ;
wire [0:0] cby_1__1__54_left_grid_pin_19_ ;
wire [0:0] cby_1__1__54_left_grid_pin_20_ ;
wire [0:0] cby_1__1__54_left_grid_pin_21_ ;
wire [0:0] cby_1__1__54_left_grid_pin_22_ ;
wire [0:0] cby_1__1__54_left_grid_pin_23_ ;
wire [0:0] cby_1__1__54_left_grid_pin_24_ ;
wire [0:0] cby_1__1__54_left_grid_pin_25_ ;
wire [0:0] cby_1__1__54_left_grid_pin_26_ ;
wire [0:0] cby_1__1__54_left_grid_pin_27_ ;
wire [0:0] cby_1__1__54_left_grid_pin_28_ ;
wire [0:0] cby_1__1__54_left_grid_pin_29_ ;
wire [0:0] cby_1__1__54_left_grid_pin_30_ ;
wire [0:0] cby_1__1__54_left_grid_pin_31_ ;
wire [0:0] cby_1__1__55_ccff_tail ;
wire [0:19] cby_1__1__55_chany_bottom_out ;
wire [0:19] cby_1__1__55_chany_top_out ;
wire [0:0] cby_1__1__55_left_grid_pin_16_ ;
wire [0:0] cby_1__1__55_left_grid_pin_17_ ;
wire [0:0] cby_1__1__55_left_grid_pin_18_ ;
wire [0:0] cby_1__1__55_left_grid_pin_19_ ;
wire [0:0] cby_1__1__55_left_grid_pin_20_ ;
wire [0:0] cby_1__1__55_left_grid_pin_21_ ;
wire [0:0] cby_1__1__55_left_grid_pin_22_ ;
wire [0:0] cby_1__1__55_left_grid_pin_23_ ;
wire [0:0] cby_1__1__55_left_grid_pin_24_ ;
wire [0:0] cby_1__1__55_left_grid_pin_25_ ;
wire [0:0] cby_1__1__55_left_grid_pin_26_ ;
wire [0:0] cby_1__1__55_left_grid_pin_27_ ;
wire [0:0] cby_1__1__55_left_grid_pin_28_ ;
wire [0:0] cby_1__1__55_left_grid_pin_29_ ;
wire [0:0] cby_1__1__55_left_grid_pin_30_ ;
wire [0:0] cby_1__1__55_left_grid_pin_31_ ;
wire [0:0] cby_1__1__56_ccff_tail ;
wire [0:19] cby_1__1__56_chany_bottom_out ;
wire [0:19] cby_1__1__56_chany_top_out ;
wire [0:0] cby_1__1__56_left_grid_pin_16_ ;
wire [0:0] cby_1__1__56_left_grid_pin_17_ ;
wire [0:0] cby_1__1__56_left_grid_pin_18_ ;
wire [0:0] cby_1__1__56_left_grid_pin_19_ ;
wire [0:0] cby_1__1__56_left_grid_pin_20_ ;
wire [0:0] cby_1__1__56_left_grid_pin_21_ ;
wire [0:0] cby_1__1__56_left_grid_pin_22_ ;
wire [0:0] cby_1__1__56_left_grid_pin_23_ ;
wire [0:0] cby_1__1__56_left_grid_pin_24_ ;
wire [0:0] cby_1__1__56_left_grid_pin_25_ ;
wire [0:0] cby_1__1__56_left_grid_pin_26_ ;
wire [0:0] cby_1__1__56_left_grid_pin_27_ ;
wire [0:0] cby_1__1__56_left_grid_pin_28_ ;
wire [0:0] cby_1__1__56_left_grid_pin_29_ ;
wire [0:0] cby_1__1__56_left_grid_pin_30_ ;
wire [0:0] cby_1__1__56_left_grid_pin_31_ ;
wire [0:0] cby_1__1__57_ccff_tail ;
wire [0:19] cby_1__1__57_chany_bottom_out ;
wire [0:19] cby_1__1__57_chany_top_out ;
wire [0:0] cby_1__1__57_left_grid_pin_16_ ;
wire [0:0] cby_1__1__57_left_grid_pin_17_ ;
wire [0:0] cby_1__1__57_left_grid_pin_18_ ;
wire [0:0] cby_1__1__57_left_grid_pin_19_ ;
wire [0:0] cby_1__1__57_left_grid_pin_20_ ;
wire [0:0] cby_1__1__57_left_grid_pin_21_ ;
wire [0:0] cby_1__1__57_left_grid_pin_22_ ;
wire [0:0] cby_1__1__57_left_grid_pin_23_ ;
wire [0:0] cby_1__1__57_left_grid_pin_24_ ;
wire [0:0] cby_1__1__57_left_grid_pin_25_ ;
wire [0:0] cby_1__1__57_left_grid_pin_26_ ;
wire [0:0] cby_1__1__57_left_grid_pin_27_ ;
wire [0:0] cby_1__1__57_left_grid_pin_28_ ;
wire [0:0] cby_1__1__57_left_grid_pin_29_ ;
wire [0:0] cby_1__1__57_left_grid_pin_30_ ;
wire [0:0] cby_1__1__57_left_grid_pin_31_ ;
wire [0:0] cby_1__1__58_ccff_tail ;
wire [0:19] cby_1__1__58_chany_bottom_out ;
wire [0:19] cby_1__1__58_chany_top_out ;
wire [0:0] cby_1__1__58_left_grid_pin_16_ ;
wire [0:0] cby_1__1__58_left_grid_pin_17_ ;
wire [0:0] cby_1__1__58_left_grid_pin_18_ ;
wire [0:0] cby_1__1__58_left_grid_pin_19_ ;
wire [0:0] cby_1__1__58_left_grid_pin_20_ ;
wire [0:0] cby_1__1__58_left_grid_pin_21_ ;
wire [0:0] cby_1__1__58_left_grid_pin_22_ ;
wire [0:0] cby_1__1__58_left_grid_pin_23_ ;
wire [0:0] cby_1__1__58_left_grid_pin_24_ ;
wire [0:0] cby_1__1__58_left_grid_pin_25_ ;
wire [0:0] cby_1__1__58_left_grid_pin_26_ ;
wire [0:0] cby_1__1__58_left_grid_pin_27_ ;
wire [0:0] cby_1__1__58_left_grid_pin_28_ ;
wire [0:0] cby_1__1__58_left_grid_pin_29_ ;
wire [0:0] cby_1__1__58_left_grid_pin_30_ ;
wire [0:0] cby_1__1__58_left_grid_pin_31_ ;
wire [0:0] cby_1__1__59_ccff_tail ;
wire [0:19] cby_1__1__59_chany_bottom_out ;
wire [0:19] cby_1__1__59_chany_top_out ;
wire [0:0] cby_1__1__59_left_grid_pin_16_ ;
wire [0:0] cby_1__1__59_left_grid_pin_17_ ;
wire [0:0] cby_1__1__59_left_grid_pin_18_ ;
wire [0:0] cby_1__1__59_left_grid_pin_19_ ;
wire [0:0] cby_1__1__59_left_grid_pin_20_ ;
wire [0:0] cby_1__1__59_left_grid_pin_21_ ;
wire [0:0] cby_1__1__59_left_grid_pin_22_ ;
wire [0:0] cby_1__1__59_left_grid_pin_23_ ;
wire [0:0] cby_1__1__59_left_grid_pin_24_ ;
wire [0:0] cby_1__1__59_left_grid_pin_25_ ;
wire [0:0] cby_1__1__59_left_grid_pin_26_ ;
wire [0:0] cby_1__1__59_left_grid_pin_27_ ;
wire [0:0] cby_1__1__59_left_grid_pin_28_ ;
wire [0:0] cby_1__1__59_left_grid_pin_29_ ;
wire [0:0] cby_1__1__59_left_grid_pin_30_ ;
wire [0:0] cby_1__1__59_left_grid_pin_31_ ;
wire [0:0] cby_1__1__5_ccff_tail ;
wire [0:19] cby_1__1__5_chany_bottom_out ;
wire [0:19] cby_1__1__5_chany_top_out ;
wire [0:0] cby_1__1__5_left_grid_pin_16_ ;
wire [0:0] cby_1__1__5_left_grid_pin_17_ ;
wire [0:0] cby_1__1__5_left_grid_pin_18_ ;
wire [0:0] cby_1__1__5_left_grid_pin_19_ ;
wire [0:0] cby_1__1__5_left_grid_pin_20_ ;
wire [0:0] cby_1__1__5_left_grid_pin_21_ ;
wire [0:0] cby_1__1__5_left_grid_pin_22_ ;
wire [0:0] cby_1__1__5_left_grid_pin_23_ ;
wire [0:0] cby_1__1__5_left_grid_pin_24_ ;
wire [0:0] cby_1__1__5_left_grid_pin_25_ ;
wire [0:0] cby_1__1__5_left_grid_pin_26_ ;
wire [0:0] cby_1__1__5_left_grid_pin_27_ ;
wire [0:0] cby_1__1__5_left_grid_pin_28_ ;
wire [0:0] cby_1__1__5_left_grid_pin_29_ ;
wire [0:0] cby_1__1__5_left_grid_pin_30_ ;
wire [0:0] cby_1__1__5_left_grid_pin_31_ ;
wire [0:0] cby_1__1__60_ccff_tail ;
wire [0:19] cby_1__1__60_chany_bottom_out ;
wire [0:19] cby_1__1__60_chany_top_out ;
wire [0:0] cby_1__1__60_left_grid_pin_16_ ;
wire [0:0] cby_1__1__60_left_grid_pin_17_ ;
wire [0:0] cby_1__1__60_left_grid_pin_18_ ;
wire [0:0] cby_1__1__60_left_grid_pin_19_ ;
wire [0:0] cby_1__1__60_left_grid_pin_20_ ;
wire [0:0] cby_1__1__60_left_grid_pin_21_ ;
wire [0:0] cby_1__1__60_left_grid_pin_22_ ;
wire [0:0] cby_1__1__60_left_grid_pin_23_ ;
wire [0:0] cby_1__1__60_left_grid_pin_24_ ;
wire [0:0] cby_1__1__60_left_grid_pin_25_ ;
wire [0:0] cby_1__1__60_left_grid_pin_26_ ;
wire [0:0] cby_1__1__60_left_grid_pin_27_ ;
wire [0:0] cby_1__1__60_left_grid_pin_28_ ;
wire [0:0] cby_1__1__60_left_grid_pin_29_ ;
wire [0:0] cby_1__1__60_left_grid_pin_30_ ;
wire [0:0] cby_1__1__60_left_grid_pin_31_ ;
wire [0:0] cby_1__1__61_ccff_tail ;
wire [0:19] cby_1__1__61_chany_bottom_out ;
wire [0:19] cby_1__1__61_chany_top_out ;
wire [0:0] cby_1__1__61_left_grid_pin_16_ ;
wire [0:0] cby_1__1__61_left_grid_pin_17_ ;
wire [0:0] cby_1__1__61_left_grid_pin_18_ ;
wire [0:0] cby_1__1__61_left_grid_pin_19_ ;
wire [0:0] cby_1__1__61_left_grid_pin_20_ ;
wire [0:0] cby_1__1__61_left_grid_pin_21_ ;
wire [0:0] cby_1__1__61_left_grid_pin_22_ ;
wire [0:0] cby_1__1__61_left_grid_pin_23_ ;
wire [0:0] cby_1__1__61_left_grid_pin_24_ ;
wire [0:0] cby_1__1__61_left_grid_pin_25_ ;
wire [0:0] cby_1__1__61_left_grid_pin_26_ ;
wire [0:0] cby_1__1__61_left_grid_pin_27_ ;
wire [0:0] cby_1__1__61_left_grid_pin_28_ ;
wire [0:0] cby_1__1__61_left_grid_pin_29_ ;
wire [0:0] cby_1__1__61_left_grid_pin_30_ ;
wire [0:0] cby_1__1__61_left_grid_pin_31_ ;
wire [0:0] cby_1__1__62_ccff_tail ;
wire [0:19] cby_1__1__62_chany_bottom_out ;
wire [0:19] cby_1__1__62_chany_top_out ;
wire [0:0] cby_1__1__62_left_grid_pin_16_ ;
wire [0:0] cby_1__1__62_left_grid_pin_17_ ;
wire [0:0] cby_1__1__62_left_grid_pin_18_ ;
wire [0:0] cby_1__1__62_left_grid_pin_19_ ;
wire [0:0] cby_1__1__62_left_grid_pin_20_ ;
wire [0:0] cby_1__1__62_left_grid_pin_21_ ;
wire [0:0] cby_1__1__62_left_grid_pin_22_ ;
wire [0:0] cby_1__1__62_left_grid_pin_23_ ;
wire [0:0] cby_1__1__62_left_grid_pin_24_ ;
wire [0:0] cby_1__1__62_left_grid_pin_25_ ;
wire [0:0] cby_1__1__62_left_grid_pin_26_ ;
wire [0:0] cby_1__1__62_left_grid_pin_27_ ;
wire [0:0] cby_1__1__62_left_grid_pin_28_ ;
wire [0:0] cby_1__1__62_left_grid_pin_29_ ;
wire [0:0] cby_1__1__62_left_grid_pin_30_ ;
wire [0:0] cby_1__1__62_left_grid_pin_31_ ;
wire [0:0] cby_1__1__63_ccff_tail ;
wire [0:19] cby_1__1__63_chany_bottom_out ;
wire [0:19] cby_1__1__63_chany_top_out ;
wire [0:0] cby_1__1__63_left_grid_pin_16_ ;
wire [0:0] cby_1__1__63_left_grid_pin_17_ ;
wire [0:0] cby_1__1__63_left_grid_pin_18_ ;
wire [0:0] cby_1__1__63_left_grid_pin_19_ ;
wire [0:0] cby_1__1__63_left_grid_pin_20_ ;
wire [0:0] cby_1__1__63_left_grid_pin_21_ ;
wire [0:0] cby_1__1__63_left_grid_pin_22_ ;
wire [0:0] cby_1__1__63_left_grid_pin_23_ ;
wire [0:0] cby_1__1__63_left_grid_pin_24_ ;
wire [0:0] cby_1__1__63_left_grid_pin_25_ ;
wire [0:0] cby_1__1__63_left_grid_pin_26_ ;
wire [0:0] cby_1__1__63_left_grid_pin_27_ ;
wire [0:0] cby_1__1__63_left_grid_pin_28_ ;
wire [0:0] cby_1__1__63_left_grid_pin_29_ ;
wire [0:0] cby_1__1__63_left_grid_pin_30_ ;
wire [0:0] cby_1__1__63_left_grid_pin_31_ ;
wire [0:0] cby_1__1__64_ccff_tail ;
wire [0:19] cby_1__1__64_chany_bottom_out ;
wire [0:19] cby_1__1__64_chany_top_out ;
wire [0:0] cby_1__1__64_left_grid_pin_16_ ;
wire [0:0] cby_1__1__64_left_grid_pin_17_ ;
wire [0:0] cby_1__1__64_left_grid_pin_18_ ;
wire [0:0] cby_1__1__64_left_grid_pin_19_ ;
wire [0:0] cby_1__1__64_left_grid_pin_20_ ;
wire [0:0] cby_1__1__64_left_grid_pin_21_ ;
wire [0:0] cby_1__1__64_left_grid_pin_22_ ;
wire [0:0] cby_1__1__64_left_grid_pin_23_ ;
wire [0:0] cby_1__1__64_left_grid_pin_24_ ;
wire [0:0] cby_1__1__64_left_grid_pin_25_ ;
wire [0:0] cby_1__1__64_left_grid_pin_26_ ;
wire [0:0] cby_1__1__64_left_grid_pin_27_ ;
wire [0:0] cby_1__1__64_left_grid_pin_28_ ;
wire [0:0] cby_1__1__64_left_grid_pin_29_ ;
wire [0:0] cby_1__1__64_left_grid_pin_30_ ;
wire [0:0] cby_1__1__64_left_grid_pin_31_ ;
wire [0:0] cby_1__1__65_ccff_tail ;
wire [0:19] cby_1__1__65_chany_bottom_out ;
wire [0:19] cby_1__1__65_chany_top_out ;
wire [0:0] cby_1__1__65_left_grid_pin_16_ ;
wire [0:0] cby_1__1__65_left_grid_pin_17_ ;
wire [0:0] cby_1__1__65_left_grid_pin_18_ ;
wire [0:0] cby_1__1__65_left_grid_pin_19_ ;
wire [0:0] cby_1__1__65_left_grid_pin_20_ ;
wire [0:0] cby_1__1__65_left_grid_pin_21_ ;
wire [0:0] cby_1__1__65_left_grid_pin_22_ ;
wire [0:0] cby_1__1__65_left_grid_pin_23_ ;
wire [0:0] cby_1__1__65_left_grid_pin_24_ ;
wire [0:0] cby_1__1__65_left_grid_pin_25_ ;
wire [0:0] cby_1__1__65_left_grid_pin_26_ ;
wire [0:0] cby_1__1__65_left_grid_pin_27_ ;
wire [0:0] cby_1__1__65_left_grid_pin_28_ ;
wire [0:0] cby_1__1__65_left_grid_pin_29_ ;
wire [0:0] cby_1__1__65_left_grid_pin_30_ ;
wire [0:0] cby_1__1__65_left_grid_pin_31_ ;
wire [0:0] cby_1__1__66_ccff_tail ;
wire [0:19] cby_1__1__66_chany_bottom_out ;
wire [0:19] cby_1__1__66_chany_top_out ;
wire [0:0] cby_1__1__66_left_grid_pin_16_ ;
wire [0:0] cby_1__1__66_left_grid_pin_17_ ;
wire [0:0] cby_1__1__66_left_grid_pin_18_ ;
wire [0:0] cby_1__1__66_left_grid_pin_19_ ;
wire [0:0] cby_1__1__66_left_grid_pin_20_ ;
wire [0:0] cby_1__1__66_left_grid_pin_21_ ;
wire [0:0] cby_1__1__66_left_grid_pin_22_ ;
wire [0:0] cby_1__1__66_left_grid_pin_23_ ;
wire [0:0] cby_1__1__66_left_grid_pin_24_ ;
wire [0:0] cby_1__1__66_left_grid_pin_25_ ;
wire [0:0] cby_1__1__66_left_grid_pin_26_ ;
wire [0:0] cby_1__1__66_left_grid_pin_27_ ;
wire [0:0] cby_1__1__66_left_grid_pin_28_ ;
wire [0:0] cby_1__1__66_left_grid_pin_29_ ;
wire [0:0] cby_1__1__66_left_grid_pin_30_ ;
wire [0:0] cby_1__1__66_left_grid_pin_31_ ;
wire [0:0] cby_1__1__67_ccff_tail ;
wire [0:19] cby_1__1__67_chany_bottom_out ;
wire [0:19] cby_1__1__67_chany_top_out ;
wire [0:0] cby_1__1__67_left_grid_pin_16_ ;
wire [0:0] cby_1__1__67_left_grid_pin_17_ ;
wire [0:0] cby_1__1__67_left_grid_pin_18_ ;
wire [0:0] cby_1__1__67_left_grid_pin_19_ ;
wire [0:0] cby_1__1__67_left_grid_pin_20_ ;
wire [0:0] cby_1__1__67_left_grid_pin_21_ ;
wire [0:0] cby_1__1__67_left_grid_pin_22_ ;
wire [0:0] cby_1__1__67_left_grid_pin_23_ ;
wire [0:0] cby_1__1__67_left_grid_pin_24_ ;
wire [0:0] cby_1__1__67_left_grid_pin_25_ ;
wire [0:0] cby_1__1__67_left_grid_pin_26_ ;
wire [0:0] cby_1__1__67_left_grid_pin_27_ ;
wire [0:0] cby_1__1__67_left_grid_pin_28_ ;
wire [0:0] cby_1__1__67_left_grid_pin_29_ ;
wire [0:0] cby_1__1__67_left_grid_pin_30_ ;
wire [0:0] cby_1__1__67_left_grid_pin_31_ ;
wire [0:0] cby_1__1__68_ccff_tail ;
wire [0:19] cby_1__1__68_chany_bottom_out ;
wire [0:19] cby_1__1__68_chany_top_out ;
wire [0:0] cby_1__1__68_left_grid_pin_16_ ;
wire [0:0] cby_1__1__68_left_grid_pin_17_ ;
wire [0:0] cby_1__1__68_left_grid_pin_18_ ;
wire [0:0] cby_1__1__68_left_grid_pin_19_ ;
wire [0:0] cby_1__1__68_left_grid_pin_20_ ;
wire [0:0] cby_1__1__68_left_grid_pin_21_ ;
wire [0:0] cby_1__1__68_left_grid_pin_22_ ;
wire [0:0] cby_1__1__68_left_grid_pin_23_ ;
wire [0:0] cby_1__1__68_left_grid_pin_24_ ;
wire [0:0] cby_1__1__68_left_grid_pin_25_ ;
wire [0:0] cby_1__1__68_left_grid_pin_26_ ;
wire [0:0] cby_1__1__68_left_grid_pin_27_ ;
wire [0:0] cby_1__1__68_left_grid_pin_28_ ;
wire [0:0] cby_1__1__68_left_grid_pin_29_ ;
wire [0:0] cby_1__1__68_left_grid_pin_30_ ;
wire [0:0] cby_1__1__68_left_grid_pin_31_ ;
wire [0:0] cby_1__1__69_ccff_tail ;
wire [0:19] cby_1__1__69_chany_bottom_out ;
wire [0:19] cby_1__1__69_chany_top_out ;
wire [0:0] cby_1__1__69_left_grid_pin_16_ ;
wire [0:0] cby_1__1__69_left_grid_pin_17_ ;
wire [0:0] cby_1__1__69_left_grid_pin_18_ ;
wire [0:0] cby_1__1__69_left_grid_pin_19_ ;
wire [0:0] cby_1__1__69_left_grid_pin_20_ ;
wire [0:0] cby_1__1__69_left_grid_pin_21_ ;
wire [0:0] cby_1__1__69_left_grid_pin_22_ ;
wire [0:0] cby_1__1__69_left_grid_pin_23_ ;
wire [0:0] cby_1__1__69_left_grid_pin_24_ ;
wire [0:0] cby_1__1__69_left_grid_pin_25_ ;
wire [0:0] cby_1__1__69_left_grid_pin_26_ ;
wire [0:0] cby_1__1__69_left_grid_pin_27_ ;
wire [0:0] cby_1__1__69_left_grid_pin_28_ ;
wire [0:0] cby_1__1__69_left_grid_pin_29_ ;
wire [0:0] cby_1__1__69_left_grid_pin_30_ ;
wire [0:0] cby_1__1__69_left_grid_pin_31_ ;
wire [0:0] cby_1__1__6_ccff_tail ;
wire [0:19] cby_1__1__6_chany_bottom_out ;
wire [0:19] cby_1__1__6_chany_top_out ;
wire [0:0] cby_1__1__6_left_grid_pin_16_ ;
wire [0:0] cby_1__1__6_left_grid_pin_17_ ;
wire [0:0] cby_1__1__6_left_grid_pin_18_ ;
wire [0:0] cby_1__1__6_left_grid_pin_19_ ;
wire [0:0] cby_1__1__6_left_grid_pin_20_ ;
wire [0:0] cby_1__1__6_left_grid_pin_21_ ;
wire [0:0] cby_1__1__6_left_grid_pin_22_ ;
wire [0:0] cby_1__1__6_left_grid_pin_23_ ;
wire [0:0] cby_1__1__6_left_grid_pin_24_ ;
wire [0:0] cby_1__1__6_left_grid_pin_25_ ;
wire [0:0] cby_1__1__6_left_grid_pin_26_ ;
wire [0:0] cby_1__1__6_left_grid_pin_27_ ;
wire [0:0] cby_1__1__6_left_grid_pin_28_ ;
wire [0:0] cby_1__1__6_left_grid_pin_29_ ;
wire [0:0] cby_1__1__6_left_grid_pin_30_ ;
wire [0:0] cby_1__1__6_left_grid_pin_31_ ;
wire [0:0] cby_1__1__70_ccff_tail ;
wire [0:19] cby_1__1__70_chany_bottom_out ;
wire [0:19] cby_1__1__70_chany_top_out ;
wire [0:0] cby_1__1__70_left_grid_pin_16_ ;
wire [0:0] cby_1__1__70_left_grid_pin_17_ ;
wire [0:0] cby_1__1__70_left_grid_pin_18_ ;
wire [0:0] cby_1__1__70_left_grid_pin_19_ ;
wire [0:0] cby_1__1__70_left_grid_pin_20_ ;
wire [0:0] cby_1__1__70_left_grid_pin_21_ ;
wire [0:0] cby_1__1__70_left_grid_pin_22_ ;
wire [0:0] cby_1__1__70_left_grid_pin_23_ ;
wire [0:0] cby_1__1__70_left_grid_pin_24_ ;
wire [0:0] cby_1__1__70_left_grid_pin_25_ ;
wire [0:0] cby_1__1__70_left_grid_pin_26_ ;
wire [0:0] cby_1__1__70_left_grid_pin_27_ ;
wire [0:0] cby_1__1__70_left_grid_pin_28_ ;
wire [0:0] cby_1__1__70_left_grid_pin_29_ ;
wire [0:0] cby_1__1__70_left_grid_pin_30_ ;
wire [0:0] cby_1__1__70_left_grid_pin_31_ ;
wire [0:0] cby_1__1__71_ccff_tail ;
wire [0:19] cby_1__1__71_chany_bottom_out ;
wire [0:19] cby_1__1__71_chany_top_out ;
wire [0:0] cby_1__1__71_left_grid_pin_16_ ;
wire [0:0] cby_1__1__71_left_grid_pin_17_ ;
wire [0:0] cby_1__1__71_left_grid_pin_18_ ;
wire [0:0] cby_1__1__71_left_grid_pin_19_ ;
wire [0:0] cby_1__1__71_left_grid_pin_20_ ;
wire [0:0] cby_1__1__71_left_grid_pin_21_ ;
wire [0:0] cby_1__1__71_left_grid_pin_22_ ;
wire [0:0] cby_1__1__71_left_grid_pin_23_ ;
wire [0:0] cby_1__1__71_left_grid_pin_24_ ;
wire [0:0] cby_1__1__71_left_grid_pin_25_ ;
wire [0:0] cby_1__1__71_left_grid_pin_26_ ;
wire [0:0] cby_1__1__71_left_grid_pin_27_ ;
wire [0:0] cby_1__1__71_left_grid_pin_28_ ;
wire [0:0] cby_1__1__71_left_grid_pin_29_ ;
wire [0:0] cby_1__1__71_left_grid_pin_30_ ;
wire [0:0] cby_1__1__71_left_grid_pin_31_ ;
wire [0:0] cby_1__1__72_ccff_tail ;
wire [0:19] cby_1__1__72_chany_bottom_out ;
wire [0:19] cby_1__1__72_chany_top_out ;
wire [0:0] cby_1__1__72_left_grid_pin_16_ ;
wire [0:0] cby_1__1__72_left_grid_pin_17_ ;
wire [0:0] cby_1__1__72_left_grid_pin_18_ ;
wire [0:0] cby_1__1__72_left_grid_pin_19_ ;
wire [0:0] cby_1__1__72_left_grid_pin_20_ ;
wire [0:0] cby_1__1__72_left_grid_pin_21_ ;
wire [0:0] cby_1__1__72_left_grid_pin_22_ ;
wire [0:0] cby_1__1__72_left_grid_pin_23_ ;
wire [0:0] cby_1__1__72_left_grid_pin_24_ ;
wire [0:0] cby_1__1__72_left_grid_pin_25_ ;
wire [0:0] cby_1__1__72_left_grid_pin_26_ ;
wire [0:0] cby_1__1__72_left_grid_pin_27_ ;
wire [0:0] cby_1__1__72_left_grid_pin_28_ ;
wire [0:0] cby_1__1__72_left_grid_pin_29_ ;
wire [0:0] cby_1__1__72_left_grid_pin_30_ ;
wire [0:0] cby_1__1__72_left_grid_pin_31_ ;
wire [0:0] cby_1__1__73_ccff_tail ;
wire [0:19] cby_1__1__73_chany_bottom_out ;
wire [0:19] cby_1__1__73_chany_top_out ;
wire [0:0] cby_1__1__73_left_grid_pin_16_ ;
wire [0:0] cby_1__1__73_left_grid_pin_17_ ;
wire [0:0] cby_1__1__73_left_grid_pin_18_ ;
wire [0:0] cby_1__1__73_left_grid_pin_19_ ;
wire [0:0] cby_1__1__73_left_grid_pin_20_ ;
wire [0:0] cby_1__1__73_left_grid_pin_21_ ;
wire [0:0] cby_1__1__73_left_grid_pin_22_ ;
wire [0:0] cby_1__1__73_left_grid_pin_23_ ;
wire [0:0] cby_1__1__73_left_grid_pin_24_ ;
wire [0:0] cby_1__1__73_left_grid_pin_25_ ;
wire [0:0] cby_1__1__73_left_grid_pin_26_ ;
wire [0:0] cby_1__1__73_left_grid_pin_27_ ;
wire [0:0] cby_1__1__73_left_grid_pin_28_ ;
wire [0:0] cby_1__1__73_left_grid_pin_29_ ;
wire [0:0] cby_1__1__73_left_grid_pin_30_ ;
wire [0:0] cby_1__1__73_left_grid_pin_31_ ;
wire [0:0] cby_1__1__74_ccff_tail ;
wire [0:19] cby_1__1__74_chany_bottom_out ;
wire [0:19] cby_1__1__74_chany_top_out ;
wire [0:0] cby_1__1__74_left_grid_pin_16_ ;
wire [0:0] cby_1__1__74_left_grid_pin_17_ ;
wire [0:0] cby_1__1__74_left_grid_pin_18_ ;
wire [0:0] cby_1__1__74_left_grid_pin_19_ ;
wire [0:0] cby_1__1__74_left_grid_pin_20_ ;
wire [0:0] cby_1__1__74_left_grid_pin_21_ ;
wire [0:0] cby_1__1__74_left_grid_pin_22_ ;
wire [0:0] cby_1__1__74_left_grid_pin_23_ ;
wire [0:0] cby_1__1__74_left_grid_pin_24_ ;
wire [0:0] cby_1__1__74_left_grid_pin_25_ ;
wire [0:0] cby_1__1__74_left_grid_pin_26_ ;
wire [0:0] cby_1__1__74_left_grid_pin_27_ ;
wire [0:0] cby_1__1__74_left_grid_pin_28_ ;
wire [0:0] cby_1__1__74_left_grid_pin_29_ ;
wire [0:0] cby_1__1__74_left_grid_pin_30_ ;
wire [0:0] cby_1__1__74_left_grid_pin_31_ ;
wire [0:0] cby_1__1__75_ccff_tail ;
wire [0:19] cby_1__1__75_chany_bottom_out ;
wire [0:19] cby_1__1__75_chany_top_out ;
wire [0:0] cby_1__1__75_left_grid_pin_16_ ;
wire [0:0] cby_1__1__75_left_grid_pin_17_ ;
wire [0:0] cby_1__1__75_left_grid_pin_18_ ;
wire [0:0] cby_1__1__75_left_grid_pin_19_ ;
wire [0:0] cby_1__1__75_left_grid_pin_20_ ;
wire [0:0] cby_1__1__75_left_grid_pin_21_ ;
wire [0:0] cby_1__1__75_left_grid_pin_22_ ;
wire [0:0] cby_1__1__75_left_grid_pin_23_ ;
wire [0:0] cby_1__1__75_left_grid_pin_24_ ;
wire [0:0] cby_1__1__75_left_grid_pin_25_ ;
wire [0:0] cby_1__1__75_left_grid_pin_26_ ;
wire [0:0] cby_1__1__75_left_grid_pin_27_ ;
wire [0:0] cby_1__1__75_left_grid_pin_28_ ;
wire [0:0] cby_1__1__75_left_grid_pin_29_ ;
wire [0:0] cby_1__1__75_left_grid_pin_30_ ;
wire [0:0] cby_1__1__75_left_grid_pin_31_ ;
wire [0:0] cby_1__1__76_ccff_tail ;
wire [0:19] cby_1__1__76_chany_bottom_out ;
wire [0:19] cby_1__1__76_chany_top_out ;
wire [0:0] cby_1__1__76_left_grid_pin_16_ ;
wire [0:0] cby_1__1__76_left_grid_pin_17_ ;
wire [0:0] cby_1__1__76_left_grid_pin_18_ ;
wire [0:0] cby_1__1__76_left_grid_pin_19_ ;
wire [0:0] cby_1__1__76_left_grid_pin_20_ ;
wire [0:0] cby_1__1__76_left_grid_pin_21_ ;
wire [0:0] cby_1__1__76_left_grid_pin_22_ ;
wire [0:0] cby_1__1__76_left_grid_pin_23_ ;
wire [0:0] cby_1__1__76_left_grid_pin_24_ ;
wire [0:0] cby_1__1__76_left_grid_pin_25_ ;
wire [0:0] cby_1__1__76_left_grid_pin_26_ ;
wire [0:0] cby_1__1__76_left_grid_pin_27_ ;
wire [0:0] cby_1__1__76_left_grid_pin_28_ ;
wire [0:0] cby_1__1__76_left_grid_pin_29_ ;
wire [0:0] cby_1__1__76_left_grid_pin_30_ ;
wire [0:0] cby_1__1__76_left_grid_pin_31_ ;
wire [0:0] cby_1__1__77_ccff_tail ;
wire [0:19] cby_1__1__77_chany_bottom_out ;
wire [0:19] cby_1__1__77_chany_top_out ;
wire [0:0] cby_1__1__77_left_grid_pin_16_ ;
wire [0:0] cby_1__1__77_left_grid_pin_17_ ;
wire [0:0] cby_1__1__77_left_grid_pin_18_ ;
wire [0:0] cby_1__1__77_left_grid_pin_19_ ;
wire [0:0] cby_1__1__77_left_grid_pin_20_ ;
wire [0:0] cby_1__1__77_left_grid_pin_21_ ;
wire [0:0] cby_1__1__77_left_grid_pin_22_ ;
wire [0:0] cby_1__1__77_left_grid_pin_23_ ;
wire [0:0] cby_1__1__77_left_grid_pin_24_ ;
wire [0:0] cby_1__1__77_left_grid_pin_25_ ;
wire [0:0] cby_1__1__77_left_grid_pin_26_ ;
wire [0:0] cby_1__1__77_left_grid_pin_27_ ;
wire [0:0] cby_1__1__77_left_grid_pin_28_ ;
wire [0:0] cby_1__1__77_left_grid_pin_29_ ;
wire [0:0] cby_1__1__77_left_grid_pin_30_ ;
wire [0:0] cby_1__1__77_left_grid_pin_31_ ;
wire [0:0] cby_1__1__78_ccff_tail ;
wire [0:19] cby_1__1__78_chany_bottom_out ;
wire [0:19] cby_1__1__78_chany_top_out ;
wire [0:0] cby_1__1__78_left_grid_pin_16_ ;
wire [0:0] cby_1__1__78_left_grid_pin_17_ ;
wire [0:0] cby_1__1__78_left_grid_pin_18_ ;
wire [0:0] cby_1__1__78_left_grid_pin_19_ ;
wire [0:0] cby_1__1__78_left_grid_pin_20_ ;
wire [0:0] cby_1__1__78_left_grid_pin_21_ ;
wire [0:0] cby_1__1__78_left_grid_pin_22_ ;
wire [0:0] cby_1__1__78_left_grid_pin_23_ ;
wire [0:0] cby_1__1__78_left_grid_pin_24_ ;
wire [0:0] cby_1__1__78_left_grid_pin_25_ ;
wire [0:0] cby_1__1__78_left_grid_pin_26_ ;
wire [0:0] cby_1__1__78_left_grid_pin_27_ ;
wire [0:0] cby_1__1__78_left_grid_pin_28_ ;
wire [0:0] cby_1__1__78_left_grid_pin_29_ ;
wire [0:0] cby_1__1__78_left_grid_pin_30_ ;
wire [0:0] cby_1__1__78_left_grid_pin_31_ ;
wire [0:0] cby_1__1__79_ccff_tail ;
wire [0:19] cby_1__1__79_chany_bottom_out ;
wire [0:19] cby_1__1__79_chany_top_out ;
wire [0:0] cby_1__1__79_left_grid_pin_16_ ;
wire [0:0] cby_1__1__79_left_grid_pin_17_ ;
wire [0:0] cby_1__1__79_left_grid_pin_18_ ;
wire [0:0] cby_1__1__79_left_grid_pin_19_ ;
wire [0:0] cby_1__1__79_left_grid_pin_20_ ;
wire [0:0] cby_1__1__79_left_grid_pin_21_ ;
wire [0:0] cby_1__1__79_left_grid_pin_22_ ;
wire [0:0] cby_1__1__79_left_grid_pin_23_ ;
wire [0:0] cby_1__1__79_left_grid_pin_24_ ;
wire [0:0] cby_1__1__79_left_grid_pin_25_ ;
wire [0:0] cby_1__1__79_left_grid_pin_26_ ;
wire [0:0] cby_1__1__79_left_grid_pin_27_ ;
wire [0:0] cby_1__1__79_left_grid_pin_28_ ;
wire [0:0] cby_1__1__79_left_grid_pin_29_ ;
wire [0:0] cby_1__1__79_left_grid_pin_30_ ;
wire [0:0] cby_1__1__79_left_grid_pin_31_ ;
wire [0:0] cby_1__1__7_ccff_tail ;
wire [0:19] cby_1__1__7_chany_bottom_out ;
wire [0:19] cby_1__1__7_chany_top_out ;
wire [0:0] cby_1__1__7_left_grid_pin_16_ ;
wire [0:0] cby_1__1__7_left_grid_pin_17_ ;
wire [0:0] cby_1__1__7_left_grid_pin_18_ ;
wire [0:0] cby_1__1__7_left_grid_pin_19_ ;
wire [0:0] cby_1__1__7_left_grid_pin_20_ ;
wire [0:0] cby_1__1__7_left_grid_pin_21_ ;
wire [0:0] cby_1__1__7_left_grid_pin_22_ ;
wire [0:0] cby_1__1__7_left_grid_pin_23_ ;
wire [0:0] cby_1__1__7_left_grid_pin_24_ ;
wire [0:0] cby_1__1__7_left_grid_pin_25_ ;
wire [0:0] cby_1__1__7_left_grid_pin_26_ ;
wire [0:0] cby_1__1__7_left_grid_pin_27_ ;
wire [0:0] cby_1__1__7_left_grid_pin_28_ ;
wire [0:0] cby_1__1__7_left_grid_pin_29_ ;
wire [0:0] cby_1__1__7_left_grid_pin_30_ ;
wire [0:0] cby_1__1__7_left_grid_pin_31_ ;
wire [0:0] cby_1__1__80_ccff_tail ;
wire [0:19] cby_1__1__80_chany_bottom_out ;
wire [0:19] cby_1__1__80_chany_top_out ;
wire [0:0] cby_1__1__80_left_grid_pin_16_ ;
wire [0:0] cby_1__1__80_left_grid_pin_17_ ;
wire [0:0] cby_1__1__80_left_grid_pin_18_ ;
wire [0:0] cby_1__1__80_left_grid_pin_19_ ;
wire [0:0] cby_1__1__80_left_grid_pin_20_ ;
wire [0:0] cby_1__1__80_left_grid_pin_21_ ;
wire [0:0] cby_1__1__80_left_grid_pin_22_ ;
wire [0:0] cby_1__1__80_left_grid_pin_23_ ;
wire [0:0] cby_1__1__80_left_grid_pin_24_ ;
wire [0:0] cby_1__1__80_left_grid_pin_25_ ;
wire [0:0] cby_1__1__80_left_grid_pin_26_ ;
wire [0:0] cby_1__1__80_left_grid_pin_27_ ;
wire [0:0] cby_1__1__80_left_grid_pin_28_ ;
wire [0:0] cby_1__1__80_left_grid_pin_29_ ;
wire [0:0] cby_1__1__80_left_grid_pin_30_ ;
wire [0:0] cby_1__1__80_left_grid_pin_31_ ;
wire [0:0] cby_1__1__81_ccff_tail ;
wire [0:19] cby_1__1__81_chany_bottom_out ;
wire [0:19] cby_1__1__81_chany_top_out ;
wire [0:0] cby_1__1__81_left_grid_pin_16_ ;
wire [0:0] cby_1__1__81_left_grid_pin_17_ ;
wire [0:0] cby_1__1__81_left_grid_pin_18_ ;
wire [0:0] cby_1__1__81_left_grid_pin_19_ ;
wire [0:0] cby_1__1__81_left_grid_pin_20_ ;
wire [0:0] cby_1__1__81_left_grid_pin_21_ ;
wire [0:0] cby_1__1__81_left_grid_pin_22_ ;
wire [0:0] cby_1__1__81_left_grid_pin_23_ ;
wire [0:0] cby_1__1__81_left_grid_pin_24_ ;
wire [0:0] cby_1__1__81_left_grid_pin_25_ ;
wire [0:0] cby_1__1__81_left_grid_pin_26_ ;
wire [0:0] cby_1__1__81_left_grid_pin_27_ ;
wire [0:0] cby_1__1__81_left_grid_pin_28_ ;
wire [0:0] cby_1__1__81_left_grid_pin_29_ ;
wire [0:0] cby_1__1__81_left_grid_pin_30_ ;
wire [0:0] cby_1__1__81_left_grid_pin_31_ ;
wire [0:0] cby_1__1__82_ccff_tail ;
wire [0:19] cby_1__1__82_chany_bottom_out ;
wire [0:19] cby_1__1__82_chany_top_out ;
wire [0:0] cby_1__1__82_left_grid_pin_16_ ;
wire [0:0] cby_1__1__82_left_grid_pin_17_ ;
wire [0:0] cby_1__1__82_left_grid_pin_18_ ;
wire [0:0] cby_1__1__82_left_grid_pin_19_ ;
wire [0:0] cby_1__1__82_left_grid_pin_20_ ;
wire [0:0] cby_1__1__82_left_grid_pin_21_ ;
wire [0:0] cby_1__1__82_left_grid_pin_22_ ;
wire [0:0] cby_1__1__82_left_grid_pin_23_ ;
wire [0:0] cby_1__1__82_left_grid_pin_24_ ;
wire [0:0] cby_1__1__82_left_grid_pin_25_ ;
wire [0:0] cby_1__1__82_left_grid_pin_26_ ;
wire [0:0] cby_1__1__82_left_grid_pin_27_ ;
wire [0:0] cby_1__1__82_left_grid_pin_28_ ;
wire [0:0] cby_1__1__82_left_grid_pin_29_ ;
wire [0:0] cby_1__1__82_left_grid_pin_30_ ;
wire [0:0] cby_1__1__82_left_grid_pin_31_ ;
wire [0:0] cby_1__1__83_ccff_tail ;
wire [0:19] cby_1__1__83_chany_bottom_out ;
wire [0:19] cby_1__1__83_chany_top_out ;
wire [0:0] cby_1__1__83_left_grid_pin_16_ ;
wire [0:0] cby_1__1__83_left_grid_pin_17_ ;
wire [0:0] cby_1__1__83_left_grid_pin_18_ ;
wire [0:0] cby_1__1__83_left_grid_pin_19_ ;
wire [0:0] cby_1__1__83_left_grid_pin_20_ ;
wire [0:0] cby_1__1__83_left_grid_pin_21_ ;
wire [0:0] cby_1__1__83_left_grid_pin_22_ ;
wire [0:0] cby_1__1__83_left_grid_pin_23_ ;
wire [0:0] cby_1__1__83_left_grid_pin_24_ ;
wire [0:0] cby_1__1__83_left_grid_pin_25_ ;
wire [0:0] cby_1__1__83_left_grid_pin_26_ ;
wire [0:0] cby_1__1__83_left_grid_pin_27_ ;
wire [0:0] cby_1__1__83_left_grid_pin_28_ ;
wire [0:0] cby_1__1__83_left_grid_pin_29_ ;
wire [0:0] cby_1__1__83_left_grid_pin_30_ ;
wire [0:0] cby_1__1__83_left_grid_pin_31_ ;
wire [0:0] cby_1__1__84_ccff_tail ;
wire [0:19] cby_1__1__84_chany_bottom_out ;
wire [0:19] cby_1__1__84_chany_top_out ;
wire [0:0] cby_1__1__84_left_grid_pin_16_ ;
wire [0:0] cby_1__1__84_left_grid_pin_17_ ;
wire [0:0] cby_1__1__84_left_grid_pin_18_ ;
wire [0:0] cby_1__1__84_left_grid_pin_19_ ;
wire [0:0] cby_1__1__84_left_grid_pin_20_ ;
wire [0:0] cby_1__1__84_left_grid_pin_21_ ;
wire [0:0] cby_1__1__84_left_grid_pin_22_ ;
wire [0:0] cby_1__1__84_left_grid_pin_23_ ;
wire [0:0] cby_1__1__84_left_grid_pin_24_ ;
wire [0:0] cby_1__1__84_left_grid_pin_25_ ;
wire [0:0] cby_1__1__84_left_grid_pin_26_ ;
wire [0:0] cby_1__1__84_left_grid_pin_27_ ;
wire [0:0] cby_1__1__84_left_grid_pin_28_ ;
wire [0:0] cby_1__1__84_left_grid_pin_29_ ;
wire [0:0] cby_1__1__84_left_grid_pin_30_ ;
wire [0:0] cby_1__1__84_left_grid_pin_31_ ;
wire [0:0] cby_1__1__85_ccff_tail ;
wire [0:19] cby_1__1__85_chany_bottom_out ;
wire [0:19] cby_1__1__85_chany_top_out ;
wire [0:0] cby_1__1__85_left_grid_pin_16_ ;
wire [0:0] cby_1__1__85_left_grid_pin_17_ ;
wire [0:0] cby_1__1__85_left_grid_pin_18_ ;
wire [0:0] cby_1__1__85_left_grid_pin_19_ ;
wire [0:0] cby_1__1__85_left_grid_pin_20_ ;
wire [0:0] cby_1__1__85_left_grid_pin_21_ ;
wire [0:0] cby_1__1__85_left_grid_pin_22_ ;
wire [0:0] cby_1__1__85_left_grid_pin_23_ ;
wire [0:0] cby_1__1__85_left_grid_pin_24_ ;
wire [0:0] cby_1__1__85_left_grid_pin_25_ ;
wire [0:0] cby_1__1__85_left_grid_pin_26_ ;
wire [0:0] cby_1__1__85_left_grid_pin_27_ ;
wire [0:0] cby_1__1__85_left_grid_pin_28_ ;
wire [0:0] cby_1__1__85_left_grid_pin_29_ ;
wire [0:0] cby_1__1__85_left_grid_pin_30_ ;
wire [0:0] cby_1__1__85_left_grid_pin_31_ ;
wire [0:0] cby_1__1__86_ccff_tail ;
wire [0:19] cby_1__1__86_chany_bottom_out ;
wire [0:19] cby_1__1__86_chany_top_out ;
wire [0:0] cby_1__1__86_left_grid_pin_16_ ;
wire [0:0] cby_1__1__86_left_grid_pin_17_ ;
wire [0:0] cby_1__1__86_left_grid_pin_18_ ;
wire [0:0] cby_1__1__86_left_grid_pin_19_ ;
wire [0:0] cby_1__1__86_left_grid_pin_20_ ;
wire [0:0] cby_1__1__86_left_grid_pin_21_ ;
wire [0:0] cby_1__1__86_left_grid_pin_22_ ;
wire [0:0] cby_1__1__86_left_grid_pin_23_ ;
wire [0:0] cby_1__1__86_left_grid_pin_24_ ;
wire [0:0] cby_1__1__86_left_grid_pin_25_ ;
wire [0:0] cby_1__1__86_left_grid_pin_26_ ;
wire [0:0] cby_1__1__86_left_grid_pin_27_ ;
wire [0:0] cby_1__1__86_left_grid_pin_28_ ;
wire [0:0] cby_1__1__86_left_grid_pin_29_ ;
wire [0:0] cby_1__1__86_left_grid_pin_30_ ;
wire [0:0] cby_1__1__86_left_grid_pin_31_ ;
wire [0:0] cby_1__1__87_ccff_tail ;
wire [0:19] cby_1__1__87_chany_bottom_out ;
wire [0:19] cby_1__1__87_chany_top_out ;
wire [0:0] cby_1__1__87_left_grid_pin_16_ ;
wire [0:0] cby_1__1__87_left_grid_pin_17_ ;
wire [0:0] cby_1__1__87_left_grid_pin_18_ ;
wire [0:0] cby_1__1__87_left_grid_pin_19_ ;
wire [0:0] cby_1__1__87_left_grid_pin_20_ ;
wire [0:0] cby_1__1__87_left_grid_pin_21_ ;
wire [0:0] cby_1__1__87_left_grid_pin_22_ ;
wire [0:0] cby_1__1__87_left_grid_pin_23_ ;
wire [0:0] cby_1__1__87_left_grid_pin_24_ ;
wire [0:0] cby_1__1__87_left_grid_pin_25_ ;
wire [0:0] cby_1__1__87_left_grid_pin_26_ ;
wire [0:0] cby_1__1__87_left_grid_pin_27_ ;
wire [0:0] cby_1__1__87_left_grid_pin_28_ ;
wire [0:0] cby_1__1__87_left_grid_pin_29_ ;
wire [0:0] cby_1__1__87_left_grid_pin_30_ ;
wire [0:0] cby_1__1__87_left_grid_pin_31_ ;
wire [0:0] cby_1__1__88_ccff_tail ;
wire [0:19] cby_1__1__88_chany_bottom_out ;
wire [0:19] cby_1__1__88_chany_top_out ;
wire [0:0] cby_1__1__88_left_grid_pin_16_ ;
wire [0:0] cby_1__1__88_left_grid_pin_17_ ;
wire [0:0] cby_1__1__88_left_grid_pin_18_ ;
wire [0:0] cby_1__1__88_left_grid_pin_19_ ;
wire [0:0] cby_1__1__88_left_grid_pin_20_ ;
wire [0:0] cby_1__1__88_left_grid_pin_21_ ;
wire [0:0] cby_1__1__88_left_grid_pin_22_ ;
wire [0:0] cby_1__1__88_left_grid_pin_23_ ;
wire [0:0] cby_1__1__88_left_grid_pin_24_ ;
wire [0:0] cby_1__1__88_left_grid_pin_25_ ;
wire [0:0] cby_1__1__88_left_grid_pin_26_ ;
wire [0:0] cby_1__1__88_left_grid_pin_27_ ;
wire [0:0] cby_1__1__88_left_grid_pin_28_ ;
wire [0:0] cby_1__1__88_left_grid_pin_29_ ;
wire [0:0] cby_1__1__88_left_grid_pin_30_ ;
wire [0:0] cby_1__1__88_left_grid_pin_31_ ;
wire [0:0] cby_1__1__89_ccff_tail ;
wire [0:19] cby_1__1__89_chany_bottom_out ;
wire [0:19] cby_1__1__89_chany_top_out ;
wire [0:0] cby_1__1__89_left_grid_pin_16_ ;
wire [0:0] cby_1__1__89_left_grid_pin_17_ ;
wire [0:0] cby_1__1__89_left_grid_pin_18_ ;
wire [0:0] cby_1__1__89_left_grid_pin_19_ ;
wire [0:0] cby_1__1__89_left_grid_pin_20_ ;
wire [0:0] cby_1__1__89_left_grid_pin_21_ ;
wire [0:0] cby_1__1__89_left_grid_pin_22_ ;
wire [0:0] cby_1__1__89_left_grid_pin_23_ ;
wire [0:0] cby_1__1__89_left_grid_pin_24_ ;
wire [0:0] cby_1__1__89_left_grid_pin_25_ ;
wire [0:0] cby_1__1__89_left_grid_pin_26_ ;
wire [0:0] cby_1__1__89_left_grid_pin_27_ ;
wire [0:0] cby_1__1__89_left_grid_pin_28_ ;
wire [0:0] cby_1__1__89_left_grid_pin_29_ ;
wire [0:0] cby_1__1__89_left_grid_pin_30_ ;
wire [0:0] cby_1__1__89_left_grid_pin_31_ ;
wire [0:0] cby_1__1__8_ccff_tail ;
wire [0:19] cby_1__1__8_chany_bottom_out ;
wire [0:19] cby_1__1__8_chany_top_out ;
wire [0:0] cby_1__1__8_left_grid_pin_16_ ;
wire [0:0] cby_1__1__8_left_grid_pin_17_ ;
wire [0:0] cby_1__1__8_left_grid_pin_18_ ;
wire [0:0] cby_1__1__8_left_grid_pin_19_ ;
wire [0:0] cby_1__1__8_left_grid_pin_20_ ;
wire [0:0] cby_1__1__8_left_grid_pin_21_ ;
wire [0:0] cby_1__1__8_left_grid_pin_22_ ;
wire [0:0] cby_1__1__8_left_grid_pin_23_ ;
wire [0:0] cby_1__1__8_left_grid_pin_24_ ;
wire [0:0] cby_1__1__8_left_grid_pin_25_ ;
wire [0:0] cby_1__1__8_left_grid_pin_26_ ;
wire [0:0] cby_1__1__8_left_grid_pin_27_ ;
wire [0:0] cby_1__1__8_left_grid_pin_28_ ;
wire [0:0] cby_1__1__8_left_grid_pin_29_ ;
wire [0:0] cby_1__1__8_left_grid_pin_30_ ;
wire [0:0] cby_1__1__8_left_grid_pin_31_ ;
wire [0:0] cby_1__1__90_ccff_tail ;
wire [0:19] cby_1__1__90_chany_bottom_out ;
wire [0:19] cby_1__1__90_chany_top_out ;
wire [0:0] cby_1__1__90_left_grid_pin_16_ ;
wire [0:0] cby_1__1__90_left_grid_pin_17_ ;
wire [0:0] cby_1__1__90_left_grid_pin_18_ ;
wire [0:0] cby_1__1__90_left_grid_pin_19_ ;
wire [0:0] cby_1__1__90_left_grid_pin_20_ ;
wire [0:0] cby_1__1__90_left_grid_pin_21_ ;
wire [0:0] cby_1__1__90_left_grid_pin_22_ ;
wire [0:0] cby_1__1__90_left_grid_pin_23_ ;
wire [0:0] cby_1__1__90_left_grid_pin_24_ ;
wire [0:0] cby_1__1__90_left_grid_pin_25_ ;
wire [0:0] cby_1__1__90_left_grid_pin_26_ ;
wire [0:0] cby_1__1__90_left_grid_pin_27_ ;
wire [0:0] cby_1__1__90_left_grid_pin_28_ ;
wire [0:0] cby_1__1__90_left_grid_pin_29_ ;
wire [0:0] cby_1__1__90_left_grid_pin_30_ ;
wire [0:0] cby_1__1__90_left_grid_pin_31_ ;
wire [0:0] cby_1__1__91_ccff_tail ;
wire [0:19] cby_1__1__91_chany_bottom_out ;
wire [0:19] cby_1__1__91_chany_top_out ;
wire [0:0] cby_1__1__91_left_grid_pin_16_ ;
wire [0:0] cby_1__1__91_left_grid_pin_17_ ;
wire [0:0] cby_1__1__91_left_grid_pin_18_ ;
wire [0:0] cby_1__1__91_left_grid_pin_19_ ;
wire [0:0] cby_1__1__91_left_grid_pin_20_ ;
wire [0:0] cby_1__1__91_left_grid_pin_21_ ;
wire [0:0] cby_1__1__91_left_grid_pin_22_ ;
wire [0:0] cby_1__1__91_left_grid_pin_23_ ;
wire [0:0] cby_1__1__91_left_grid_pin_24_ ;
wire [0:0] cby_1__1__91_left_grid_pin_25_ ;
wire [0:0] cby_1__1__91_left_grid_pin_26_ ;
wire [0:0] cby_1__1__91_left_grid_pin_27_ ;
wire [0:0] cby_1__1__91_left_grid_pin_28_ ;
wire [0:0] cby_1__1__91_left_grid_pin_29_ ;
wire [0:0] cby_1__1__91_left_grid_pin_30_ ;
wire [0:0] cby_1__1__91_left_grid_pin_31_ ;
wire [0:0] cby_1__1__92_ccff_tail ;
wire [0:19] cby_1__1__92_chany_bottom_out ;
wire [0:19] cby_1__1__92_chany_top_out ;
wire [0:0] cby_1__1__92_left_grid_pin_16_ ;
wire [0:0] cby_1__1__92_left_grid_pin_17_ ;
wire [0:0] cby_1__1__92_left_grid_pin_18_ ;
wire [0:0] cby_1__1__92_left_grid_pin_19_ ;
wire [0:0] cby_1__1__92_left_grid_pin_20_ ;
wire [0:0] cby_1__1__92_left_grid_pin_21_ ;
wire [0:0] cby_1__1__92_left_grid_pin_22_ ;
wire [0:0] cby_1__1__92_left_grid_pin_23_ ;
wire [0:0] cby_1__1__92_left_grid_pin_24_ ;
wire [0:0] cby_1__1__92_left_grid_pin_25_ ;
wire [0:0] cby_1__1__92_left_grid_pin_26_ ;
wire [0:0] cby_1__1__92_left_grid_pin_27_ ;
wire [0:0] cby_1__1__92_left_grid_pin_28_ ;
wire [0:0] cby_1__1__92_left_grid_pin_29_ ;
wire [0:0] cby_1__1__92_left_grid_pin_30_ ;
wire [0:0] cby_1__1__92_left_grid_pin_31_ ;
wire [0:0] cby_1__1__93_ccff_tail ;
wire [0:19] cby_1__1__93_chany_bottom_out ;
wire [0:19] cby_1__1__93_chany_top_out ;
wire [0:0] cby_1__1__93_left_grid_pin_16_ ;
wire [0:0] cby_1__1__93_left_grid_pin_17_ ;
wire [0:0] cby_1__1__93_left_grid_pin_18_ ;
wire [0:0] cby_1__1__93_left_grid_pin_19_ ;
wire [0:0] cby_1__1__93_left_grid_pin_20_ ;
wire [0:0] cby_1__1__93_left_grid_pin_21_ ;
wire [0:0] cby_1__1__93_left_grid_pin_22_ ;
wire [0:0] cby_1__1__93_left_grid_pin_23_ ;
wire [0:0] cby_1__1__93_left_grid_pin_24_ ;
wire [0:0] cby_1__1__93_left_grid_pin_25_ ;
wire [0:0] cby_1__1__93_left_grid_pin_26_ ;
wire [0:0] cby_1__1__93_left_grid_pin_27_ ;
wire [0:0] cby_1__1__93_left_grid_pin_28_ ;
wire [0:0] cby_1__1__93_left_grid_pin_29_ ;
wire [0:0] cby_1__1__93_left_grid_pin_30_ ;
wire [0:0] cby_1__1__93_left_grid_pin_31_ ;
wire [0:0] cby_1__1__94_ccff_tail ;
wire [0:19] cby_1__1__94_chany_bottom_out ;
wire [0:19] cby_1__1__94_chany_top_out ;
wire [0:0] cby_1__1__94_left_grid_pin_16_ ;
wire [0:0] cby_1__1__94_left_grid_pin_17_ ;
wire [0:0] cby_1__1__94_left_grid_pin_18_ ;
wire [0:0] cby_1__1__94_left_grid_pin_19_ ;
wire [0:0] cby_1__1__94_left_grid_pin_20_ ;
wire [0:0] cby_1__1__94_left_grid_pin_21_ ;
wire [0:0] cby_1__1__94_left_grid_pin_22_ ;
wire [0:0] cby_1__1__94_left_grid_pin_23_ ;
wire [0:0] cby_1__1__94_left_grid_pin_24_ ;
wire [0:0] cby_1__1__94_left_grid_pin_25_ ;
wire [0:0] cby_1__1__94_left_grid_pin_26_ ;
wire [0:0] cby_1__1__94_left_grid_pin_27_ ;
wire [0:0] cby_1__1__94_left_grid_pin_28_ ;
wire [0:0] cby_1__1__94_left_grid_pin_29_ ;
wire [0:0] cby_1__1__94_left_grid_pin_30_ ;
wire [0:0] cby_1__1__94_left_grid_pin_31_ ;
wire [0:0] cby_1__1__95_ccff_tail ;
wire [0:19] cby_1__1__95_chany_bottom_out ;
wire [0:19] cby_1__1__95_chany_top_out ;
wire [0:0] cby_1__1__95_left_grid_pin_16_ ;
wire [0:0] cby_1__1__95_left_grid_pin_17_ ;
wire [0:0] cby_1__1__95_left_grid_pin_18_ ;
wire [0:0] cby_1__1__95_left_grid_pin_19_ ;
wire [0:0] cby_1__1__95_left_grid_pin_20_ ;
wire [0:0] cby_1__1__95_left_grid_pin_21_ ;
wire [0:0] cby_1__1__95_left_grid_pin_22_ ;
wire [0:0] cby_1__1__95_left_grid_pin_23_ ;
wire [0:0] cby_1__1__95_left_grid_pin_24_ ;
wire [0:0] cby_1__1__95_left_grid_pin_25_ ;
wire [0:0] cby_1__1__95_left_grid_pin_26_ ;
wire [0:0] cby_1__1__95_left_grid_pin_27_ ;
wire [0:0] cby_1__1__95_left_grid_pin_28_ ;
wire [0:0] cby_1__1__95_left_grid_pin_29_ ;
wire [0:0] cby_1__1__95_left_grid_pin_30_ ;
wire [0:0] cby_1__1__95_left_grid_pin_31_ ;
wire [0:0] cby_1__1__96_ccff_tail ;
wire [0:19] cby_1__1__96_chany_bottom_out ;
wire [0:19] cby_1__1__96_chany_top_out ;
wire [0:0] cby_1__1__96_left_grid_pin_16_ ;
wire [0:0] cby_1__1__96_left_grid_pin_17_ ;
wire [0:0] cby_1__1__96_left_grid_pin_18_ ;
wire [0:0] cby_1__1__96_left_grid_pin_19_ ;
wire [0:0] cby_1__1__96_left_grid_pin_20_ ;
wire [0:0] cby_1__1__96_left_grid_pin_21_ ;
wire [0:0] cby_1__1__96_left_grid_pin_22_ ;
wire [0:0] cby_1__1__96_left_grid_pin_23_ ;
wire [0:0] cby_1__1__96_left_grid_pin_24_ ;
wire [0:0] cby_1__1__96_left_grid_pin_25_ ;
wire [0:0] cby_1__1__96_left_grid_pin_26_ ;
wire [0:0] cby_1__1__96_left_grid_pin_27_ ;
wire [0:0] cby_1__1__96_left_grid_pin_28_ ;
wire [0:0] cby_1__1__96_left_grid_pin_29_ ;
wire [0:0] cby_1__1__96_left_grid_pin_30_ ;
wire [0:0] cby_1__1__96_left_grid_pin_31_ ;
wire [0:0] cby_1__1__97_ccff_tail ;
wire [0:19] cby_1__1__97_chany_bottom_out ;
wire [0:19] cby_1__1__97_chany_top_out ;
wire [0:0] cby_1__1__97_left_grid_pin_16_ ;
wire [0:0] cby_1__1__97_left_grid_pin_17_ ;
wire [0:0] cby_1__1__97_left_grid_pin_18_ ;
wire [0:0] cby_1__1__97_left_grid_pin_19_ ;
wire [0:0] cby_1__1__97_left_grid_pin_20_ ;
wire [0:0] cby_1__1__97_left_grid_pin_21_ ;
wire [0:0] cby_1__1__97_left_grid_pin_22_ ;
wire [0:0] cby_1__1__97_left_grid_pin_23_ ;
wire [0:0] cby_1__1__97_left_grid_pin_24_ ;
wire [0:0] cby_1__1__97_left_grid_pin_25_ ;
wire [0:0] cby_1__1__97_left_grid_pin_26_ ;
wire [0:0] cby_1__1__97_left_grid_pin_27_ ;
wire [0:0] cby_1__1__97_left_grid_pin_28_ ;
wire [0:0] cby_1__1__97_left_grid_pin_29_ ;
wire [0:0] cby_1__1__97_left_grid_pin_30_ ;
wire [0:0] cby_1__1__97_left_grid_pin_31_ ;
wire [0:0] cby_1__1__98_ccff_tail ;
wire [0:19] cby_1__1__98_chany_bottom_out ;
wire [0:19] cby_1__1__98_chany_top_out ;
wire [0:0] cby_1__1__98_left_grid_pin_16_ ;
wire [0:0] cby_1__1__98_left_grid_pin_17_ ;
wire [0:0] cby_1__1__98_left_grid_pin_18_ ;
wire [0:0] cby_1__1__98_left_grid_pin_19_ ;
wire [0:0] cby_1__1__98_left_grid_pin_20_ ;
wire [0:0] cby_1__1__98_left_grid_pin_21_ ;
wire [0:0] cby_1__1__98_left_grid_pin_22_ ;
wire [0:0] cby_1__1__98_left_grid_pin_23_ ;
wire [0:0] cby_1__1__98_left_grid_pin_24_ ;
wire [0:0] cby_1__1__98_left_grid_pin_25_ ;
wire [0:0] cby_1__1__98_left_grid_pin_26_ ;
wire [0:0] cby_1__1__98_left_grid_pin_27_ ;
wire [0:0] cby_1__1__98_left_grid_pin_28_ ;
wire [0:0] cby_1__1__98_left_grid_pin_29_ ;
wire [0:0] cby_1__1__98_left_grid_pin_30_ ;
wire [0:0] cby_1__1__98_left_grid_pin_31_ ;
wire [0:0] cby_1__1__99_ccff_tail ;
wire [0:19] cby_1__1__99_chany_bottom_out ;
wire [0:19] cby_1__1__99_chany_top_out ;
wire [0:0] cby_1__1__99_left_grid_pin_16_ ;
wire [0:0] cby_1__1__99_left_grid_pin_17_ ;
wire [0:0] cby_1__1__99_left_grid_pin_18_ ;
wire [0:0] cby_1__1__99_left_grid_pin_19_ ;
wire [0:0] cby_1__1__99_left_grid_pin_20_ ;
wire [0:0] cby_1__1__99_left_grid_pin_21_ ;
wire [0:0] cby_1__1__99_left_grid_pin_22_ ;
wire [0:0] cby_1__1__99_left_grid_pin_23_ ;
wire [0:0] cby_1__1__99_left_grid_pin_24_ ;
wire [0:0] cby_1__1__99_left_grid_pin_25_ ;
wire [0:0] cby_1__1__99_left_grid_pin_26_ ;
wire [0:0] cby_1__1__99_left_grid_pin_27_ ;
wire [0:0] cby_1__1__99_left_grid_pin_28_ ;
wire [0:0] cby_1__1__99_left_grid_pin_29_ ;
wire [0:0] cby_1__1__99_left_grid_pin_30_ ;
wire [0:0] cby_1__1__99_left_grid_pin_31_ ;
wire [0:0] cby_1__1__9_ccff_tail ;
wire [0:19] cby_1__1__9_chany_bottom_out ;
wire [0:19] cby_1__1__9_chany_top_out ;
wire [0:0] cby_1__1__9_left_grid_pin_16_ ;
wire [0:0] cby_1__1__9_left_grid_pin_17_ ;
wire [0:0] cby_1__1__9_left_grid_pin_18_ ;
wire [0:0] cby_1__1__9_left_grid_pin_19_ ;
wire [0:0] cby_1__1__9_left_grid_pin_20_ ;
wire [0:0] cby_1__1__9_left_grid_pin_21_ ;
wire [0:0] cby_1__1__9_left_grid_pin_22_ ;
wire [0:0] cby_1__1__9_left_grid_pin_23_ ;
wire [0:0] cby_1__1__9_left_grid_pin_24_ ;
wire [0:0] cby_1__1__9_left_grid_pin_25_ ;
wire [0:0] cby_1__1__9_left_grid_pin_26_ ;
wire [0:0] cby_1__1__9_left_grid_pin_27_ ;
wire [0:0] cby_1__1__9_left_grid_pin_28_ ;
wire [0:0] cby_1__1__9_left_grid_pin_29_ ;
wire [0:0] cby_1__1__9_left_grid_pin_30_ ;
wire [0:0] cby_1__1__9_left_grid_pin_31_ ;
wire [0:0] direct_interc_0_out ;
wire [0:0] direct_interc_100_out ;
wire [0:0] direct_interc_101_out ;
wire [0:0] direct_interc_102_out ;
wire [0:0] direct_interc_103_out ;
wire [0:0] direct_interc_104_out ;
wire [0:0] direct_interc_105_out ;
wire [0:0] direct_interc_106_out ;
wire [0:0] direct_interc_107_out ;
wire [0:0] direct_interc_108_out ;
wire [0:0] direct_interc_109_out ;
wire [0:0] direct_interc_10_out ;
wire [0:0] direct_interc_110_out ;
wire [0:0] direct_interc_111_out ;
wire [0:0] direct_interc_112_out ;
wire [0:0] direct_interc_113_out ;
wire [0:0] direct_interc_114_out ;
wire [0:0] direct_interc_115_out ;
wire [0:0] direct_interc_116_out ;
wire [0:0] direct_interc_117_out ;
wire [0:0] direct_interc_118_out ;
wire [0:0] direct_interc_119_out ;
wire [0:0] direct_interc_11_out ;
wire [0:0] direct_interc_120_out ;
wire [0:0] direct_interc_121_out ;
wire [0:0] direct_interc_122_out ;
wire [0:0] direct_interc_123_out ;
wire [0:0] direct_interc_124_out ;
wire [0:0] direct_interc_125_out ;
wire [0:0] direct_interc_126_out ;
wire [0:0] direct_interc_127_out ;
wire [0:0] direct_interc_128_out ;
wire [0:0] direct_interc_129_out ;
wire [0:0] direct_interc_12_out ;
wire [0:0] direct_interc_130_out ;
wire [0:0] direct_interc_131_out ;
wire [0:0] direct_interc_132_out ;
wire [0:0] direct_interc_133_out ;
wire [0:0] direct_interc_134_out ;
wire [0:0] direct_interc_135_out ;
wire [0:0] direct_interc_136_out ;
wire [0:0] direct_interc_137_out ;
wire [0:0] direct_interc_138_out ;
wire [0:0] direct_interc_139_out ;
wire [0:0] direct_interc_13_out ;
wire [0:0] direct_interc_140_out ;
wire [0:0] direct_interc_141_out ;
wire [0:0] direct_interc_142_out ;
wire [0:0] direct_interc_14_out ;
wire [0:0] direct_interc_15_out ;
wire [0:0] direct_interc_16_out ;
wire [0:0] direct_interc_17_out ;
wire [0:0] direct_interc_18_out ;
wire [0:0] direct_interc_19_out ;
wire [0:0] direct_interc_1_out ;
wire [0:0] direct_interc_20_out ;
wire [0:0] direct_interc_21_out ;
wire [0:0] direct_interc_22_out ;
wire [0:0] direct_interc_23_out ;
wire [0:0] direct_interc_24_out ;
wire [0:0] direct_interc_25_out ;
wire [0:0] direct_interc_26_out ;
wire [0:0] direct_interc_27_out ;
wire [0:0] direct_interc_28_out ;
wire [0:0] direct_interc_29_out ;
wire [0:0] direct_interc_2_out ;
wire [0:0] direct_interc_30_out ;
wire [0:0] direct_interc_31_out ;
wire [0:0] direct_interc_32_out ;
wire [0:0] direct_interc_33_out ;
wire [0:0] direct_interc_34_out ;
wire [0:0] direct_interc_35_out ;
wire [0:0] direct_interc_36_out ;
wire [0:0] direct_interc_37_out ;
wire [0:0] direct_interc_38_out ;
wire [0:0] direct_interc_39_out ;
wire [0:0] direct_interc_3_out ;
wire [0:0] direct_interc_40_out ;
wire [0:0] direct_interc_41_out ;
wire [0:0] direct_interc_42_out ;
wire [0:0] direct_interc_43_out ;
wire [0:0] direct_interc_44_out ;
wire [0:0] direct_interc_45_out ;
wire [0:0] direct_interc_46_out ;
wire [0:0] direct_interc_47_out ;
wire [0:0] direct_interc_48_out ;
wire [0:0] direct_interc_49_out ;
wire [0:0] direct_interc_4_out ;
wire [0:0] direct_interc_50_out ;
wire [0:0] direct_interc_51_out ;
wire [0:0] direct_interc_52_out ;
wire [0:0] direct_interc_53_out ;
wire [0:0] direct_interc_54_out ;
wire [0:0] direct_interc_55_out ;
wire [0:0] direct_interc_56_out ;
wire [0:0] direct_interc_57_out ;
wire [0:0] direct_interc_58_out ;
wire [0:0] direct_interc_59_out ;
wire [0:0] direct_interc_5_out ;
wire [0:0] direct_interc_60_out ;
wire [0:0] direct_interc_61_out ;
wire [0:0] direct_interc_62_out ;
wire [0:0] direct_interc_63_out ;
wire [0:0] direct_interc_64_out ;
wire [0:0] direct_interc_65_out ;
wire [0:0] direct_interc_66_out ;
wire [0:0] direct_interc_67_out ;
wire [0:0] direct_interc_68_out ;
wire [0:0] direct_interc_69_out ;
wire [0:0] direct_interc_6_out ;
wire [0:0] direct_interc_70_out ;
wire [0:0] direct_interc_71_out ;
wire [0:0] direct_interc_72_out ;
wire [0:0] direct_interc_73_out ;
wire [0:0] direct_interc_74_out ;
wire [0:0] direct_interc_75_out ;
wire [0:0] direct_interc_76_out ;
wire [0:0] direct_interc_77_out ;
wire [0:0] direct_interc_78_out ;
wire [0:0] direct_interc_79_out ;
wire [0:0] direct_interc_7_out ;
wire [0:0] direct_interc_80_out ;
wire [0:0] direct_interc_81_out ;
wire [0:0] direct_interc_82_out ;
wire [0:0] direct_interc_83_out ;
wire [0:0] direct_interc_84_out ;
wire [0:0] direct_interc_85_out ;
wire [0:0] direct_interc_86_out ;
wire [0:0] direct_interc_87_out ;
wire [0:0] direct_interc_88_out ;
wire [0:0] direct_interc_89_out ;
wire [0:0] direct_interc_8_out ;
wire [0:0] direct_interc_90_out ;
wire [0:0] direct_interc_91_out ;
wire [0:0] direct_interc_92_out ;
wire [0:0] direct_interc_93_out ;
wire [0:0] direct_interc_94_out ;
wire [0:0] direct_interc_95_out ;
wire [0:0] direct_interc_96_out ;
wire [0:0] direct_interc_97_out ;
wire [0:0] direct_interc_98_out ;
wire [0:0] direct_interc_99_out ;
wire [0:0] direct_interc_9_out ;
wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_0_ccff_tail ;
wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_100_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_100_ccff_tail ;
wire [0:0] grid_clb_100_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_100_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_100_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_100_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_100_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_100_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_100_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_100_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_100_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_100_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_100_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_100_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_100_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_100_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_100_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_100_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_100_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_100_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_100_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_100_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_100_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_100_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_100_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_100_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_100_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_100_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_100_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_100_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_100_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_100_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_100_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_100_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_101_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_101_ccff_tail ;
wire [0:0] grid_clb_101_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_101_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_101_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_101_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_101_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_101_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_101_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_101_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_101_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_101_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_101_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_101_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_101_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_101_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_101_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_101_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_101_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_101_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_101_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_101_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_101_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_101_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_101_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_101_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_101_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_101_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_101_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_101_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_101_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_101_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_101_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_101_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_102_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_102_ccff_tail ;
wire [0:0] grid_clb_102_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_102_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_102_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_102_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_102_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_102_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_102_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_102_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_102_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_102_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_102_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_102_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_102_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_102_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_102_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_102_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_102_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_102_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_102_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_102_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_102_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_102_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_102_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_102_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_102_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_102_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_102_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_102_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_102_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_102_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_102_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_102_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_103_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_103_ccff_tail ;
wire [0:0] grid_clb_103_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_103_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_103_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_103_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_103_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_103_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_103_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_103_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_103_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_103_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_103_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_103_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_103_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_103_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_103_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_103_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_103_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_103_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_103_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_103_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_103_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_103_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_103_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_103_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_103_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_103_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_103_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_103_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_103_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_103_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_103_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_103_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_104_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_104_ccff_tail ;
wire [0:0] grid_clb_104_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_104_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_104_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_104_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_104_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_104_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_104_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_104_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_104_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_104_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_104_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_104_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_104_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_104_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_104_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_104_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_104_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_104_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_104_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_104_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_104_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_104_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_104_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_104_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_104_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_104_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_104_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_104_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_104_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_104_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_104_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_104_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_105_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_105_ccff_tail ;
wire [0:0] grid_clb_105_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_105_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_105_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_105_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_105_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_105_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_105_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_105_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_105_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_105_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_105_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_105_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_105_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_105_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_105_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_105_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_105_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_105_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_105_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_105_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_105_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_105_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_105_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_105_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_105_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_105_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_105_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_105_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_105_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_105_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_105_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_105_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_106_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_106_ccff_tail ;
wire [0:0] grid_clb_106_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_106_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_106_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_106_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_106_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_106_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_106_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_106_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_106_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_106_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_106_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_106_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_106_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_106_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_106_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_106_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_106_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_106_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_106_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_106_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_106_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_106_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_106_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_106_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_106_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_106_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_106_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_106_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_106_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_106_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_106_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_106_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_107_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_107_ccff_tail ;
wire [0:0] grid_clb_107_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_107_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_107_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_107_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_107_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_107_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_107_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_107_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_107_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_107_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_107_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_107_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_107_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_107_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_107_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_107_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_107_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_107_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_107_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_107_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_107_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_107_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_107_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_107_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_107_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_107_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_107_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_107_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_107_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_107_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_107_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_107_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_108_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_108_ccff_tail ;
wire [0:0] grid_clb_108_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_108_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_108_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_108_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_108_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_108_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_108_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_108_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_108_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_108_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_108_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_108_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_108_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_108_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_108_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_108_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_108_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_108_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_108_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_108_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_108_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_108_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_108_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_108_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_108_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_108_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_108_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_108_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_108_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_108_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_108_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_108_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_109_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_109_ccff_tail ;
wire [0:0] grid_clb_109_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_109_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_109_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_109_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_109_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_109_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_109_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_109_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_109_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_109_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_109_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_109_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_109_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_109_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_109_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_109_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_109_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_109_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_109_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_109_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_109_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_109_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_109_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_109_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_109_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_109_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_109_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_109_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_109_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_109_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_109_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_109_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_10__10__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_10__11__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_10__12__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_10__1__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_10__2__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_10__3__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_10__4__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_10__5__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_10__6__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_10__7__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_10__8__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_10__9__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_10_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_10_ccff_tail ;
wire [0:0] grid_clb_10_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_10_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_10_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_10_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_10_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_10_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_10_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_10_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_10_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_10_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_10_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_10_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_10_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_10_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_10_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_10_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_10_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_10_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_10_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_10_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_10_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_10_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_10_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_10_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_10_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_10_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_10_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_10_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_10_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_10_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_10_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_10_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_110_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_110_ccff_tail ;
wire [0:0] grid_clb_110_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_110_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_110_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_110_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_110_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_110_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_110_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_110_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_110_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_110_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_110_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_110_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_110_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_110_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_110_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_110_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_110_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_110_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_110_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_110_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_110_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_110_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_110_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_110_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_110_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_110_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_110_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_110_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_110_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_110_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_110_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_110_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_111_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_111_ccff_tail ;
wire [0:0] grid_clb_111_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_111_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_111_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_111_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_111_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_111_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_111_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_111_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_111_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_111_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_111_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_111_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_111_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_111_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_111_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_111_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_111_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_111_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_111_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_111_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_111_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_111_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_111_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_111_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_111_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_111_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_111_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_111_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_111_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_111_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_111_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_111_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_112_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_112_ccff_tail ;
wire [0:0] grid_clb_112_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_112_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_112_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_112_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_112_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_112_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_112_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_112_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_112_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_112_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_112_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_112_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_112_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_112_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_112_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_112_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_112_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_112_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_112_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_112_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_112_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_112_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_112_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_112_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_112_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_112_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_112_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_112_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_112_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_112_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_112_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_112_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_113_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_113_ccff_tail ;
wire [0:0] grid_clb_113_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_113_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_113_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_113_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_113_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_113_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_113_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_113_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_113_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_113_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_113_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_113_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_113_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_113_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_113_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_113_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_113_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_113_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_113_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_113_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_113_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_113_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_113_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_113_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_113_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_113_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_113_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_113_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_113_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_113_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_113_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_113_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_114_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_114_ccff_tail ;
wire [0:0] grid_clb_114_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_114_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_114_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_114_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_114_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_114_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_114_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_114_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_114_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_114_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_114_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_114_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_114_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_114_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_114_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_114_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_114_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_114_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_114_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_114_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_114_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_114_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_114_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_114_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_114_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_114_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_114_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_114_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_114_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_114_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_114_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_114_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_115_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_115_ccff_tail ;
wire [0:0] grid_clb_115_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_115_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_115_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_115_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_115_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_115_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_115_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_115_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_115_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_115_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_115_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_115_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_115_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_115_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_115_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_115_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_115_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_115_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_115_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_115_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_115_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_115_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_115_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_115_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_115_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_115_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_115_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_115_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_115_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_115_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_115_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_115_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_116_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_116_ccff_tail ;
wire [0:0] grid_clb_116_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_116_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_116_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_116_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_116_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_116_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_116_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_116_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_116_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_116_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_116_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_116_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_116_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_116_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_116_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_116_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_116_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_116_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_116_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_116_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_116_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_116_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_116_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_116_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_116_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_116_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_116_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_116_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_116_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_116_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_116_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_116_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_117_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_117_ccff_tail ;
wire [0:0] grid_clb_117_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_117_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_117_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_117_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_117_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_117_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_117_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_117_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_117_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_117_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_117_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_117_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_117_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_117_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_117_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_117_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_117_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_117_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_117_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_117_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_117_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_117_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_117_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_117_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_117_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_117_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_117_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_117_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_117_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_117_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_117_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_117_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_118_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_118_ccff_tail ;
wire [0:0] grid_clb_118_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_118_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_118_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_118_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_118_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_118_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_118_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_118_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_118_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_118_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_118_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_118_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_118_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_118_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_118_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_118_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_118_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_118_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_118_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_118_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_118_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_118_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_118_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_118_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_118_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_118_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_118_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_118_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_118_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_118_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_118_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_118_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_119_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_119_ccff_tail ;
wire [0:0] grid_clb_119_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_119_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_119_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_119_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_119_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_119_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_119_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_119_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_119_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_119_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_119_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_119_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_119_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_119_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_119_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_119_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_119_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_119_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_119_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_119_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_119_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_119_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_119_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_119_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_119_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_119_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_119_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_119_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_119_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_119_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_119_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_119_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_11__10__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_11__11__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_11__12__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_11__1__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_11__2__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_11__3__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_11__4__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_11__5__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_11__6__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_11__7__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_11__8__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_11__9__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_11_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_11_ccff_tail ;
wire [0:0] grid_clb_11_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_11_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_11_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_11_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_11_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_11_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_11_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_11_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_11_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_11_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_11_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_11_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_11_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_11_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_11_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_11_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_11_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_11_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_11_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_11_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_11_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_11_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_11_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_11_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_11_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_11_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_11_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_11_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_11_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_11_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_11_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_11_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_120_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_120_bottom_width_0_height_0__pin_51_ ;
wire [0:0] grid_clb_120_ccff_tail ;
wire [0:0] grid_clb_120_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_120_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_120_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_120_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_120_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_120_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_120_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_120_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_120_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_120_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_120_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_120_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_120_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_120_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_120_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_120_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_120_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_120_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_120_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_120_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_120_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_120_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_120_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_120_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_120_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_120_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_120_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_120_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_120_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_120_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_120_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_120_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_121_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_121_ccff_tail ;
wire [0:0] grid_clb_121_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_121_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_121_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_121_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_121_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_121_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_121_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_121_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_121_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_121_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_121_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_121_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_121_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_121_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_121_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_121_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_121_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_121_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_121_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_121_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_121_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_121_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_121_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_121_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_121_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_121_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_121_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_121_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_121_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_121_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_121_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_121_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_122_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_122_ccff_tail ;
wire [0:0] grid_clb_122_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_122_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_122_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_122_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_122_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_122_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_122_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_122_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_122_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_122_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_122_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_122_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_122_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_122_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_122_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_122_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_122_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_122_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_122_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_122_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_122_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_122_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_122_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_122_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_122_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_122_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_122_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_122_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_122_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_122_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_122_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_122_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_123_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_123_ccff_tail ;
wire [0:0] grid_clb_123_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_123_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_123_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_123_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_123_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_123_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_123_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_123_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_123_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_123_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_123_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_123_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_123_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_123_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_123_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_123_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_123_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_123_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_123_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_123_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_123_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_123_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_123_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_123_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_123_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_123_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_123_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_123_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_123_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_123_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_123_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_123_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_124_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_124_ccff_tail ;
wire [0:0] grid_clb_124_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_124_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_124_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_124_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_124_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_124_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_124_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_124_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_124_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_124_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_124_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_124_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_124_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_124_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_124_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_124_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_124_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_124_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_124_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_124_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_124_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_124_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_124_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_124_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_124_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_124_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_124_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_124_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_124_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_124_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_124_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_124_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_125_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_125_ccff_tail ;
wire [0:0] grid_clb_125_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_125_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_125_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_125_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_125_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_125_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_125_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_125_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_125_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_125_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_125_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_125_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_125_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_125_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_125_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_125_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_125_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_125_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_125_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_125_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_125_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_125_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_125_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_125_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_125_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_125_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_125_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_125_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_125_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_125_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_125_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_125_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_126_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_126_ccff_tail ;
wire [0:0] grid_clb_126_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_126_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_126_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_126_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_126_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_126_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_126_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_126_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_126_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_126_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_126_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_126_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_126_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_126_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_126_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_126_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_126_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_126_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_126_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_126_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_126_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_126_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_126_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_126_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_126_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_126_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_126_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_126_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_126_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_126_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_126_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_126_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_127_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_127_ccff_tail ;
wire [0:0] grid_clb_127_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_127_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_127_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_127_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_127_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_127_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_127_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_127_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_127_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_127_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_127_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_127_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_127_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_127_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_127_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_127_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_127_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_127_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_127_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_127_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_127_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_127_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_127_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_127_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_127_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_127_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_127_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_127_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_127_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_127_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_127_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_127_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_128_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_128_ccff_tail ;
wire [0:0] grid_clb_128_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_128_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_128_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_128_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_128_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_128_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_128_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_128_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_128_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_128_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_128_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_128_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_128_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_128_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_128_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_128_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_128_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_128_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_128_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_128_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_128_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_128_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_128_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_128_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_128_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_128_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_128_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_128_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_128_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_128_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_128_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_128_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_129_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_129_ccff_tail ;
wire [0:0] grid_clb_129_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_129_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_129_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_129_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_129_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_129_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_129_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_129_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_129_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_129_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_129_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_129_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_129_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_129_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_129_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_129_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_129_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_129_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_129_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_129_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_129_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_129_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_129_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_129_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_129_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_129_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_129_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_129_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_129_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_129_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_129_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_129_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_12__10__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_12__11__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_12__12__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_12__1__undriven_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_12__1__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_12__2__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_12__3__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_12__4__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_12__5__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_12__6__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_12__7__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_12__8__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_12__9__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_12_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_12_ccff_tail ;
wire [0:0] grid_clb_12_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_12_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_12_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_12_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_12_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_12_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_12_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_12_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_12_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_12_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_12_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_12_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_12_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_12_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_12_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_12_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_12_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_12_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_12_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_12_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_12_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_12_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_12_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_12_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_12_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_12_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_12_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_12_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_12_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_12_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_12_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_12_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_130_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_130_ccff_tail ;
wire [0:0] grid_clb_130_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_130_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_130_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_130_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_130_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_130_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_130_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_130_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_130_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_130_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_130_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_130_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_130_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_130_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_130_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_130_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_130_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_130_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_130_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_130_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_130_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_130_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_130_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_130_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_130_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_130_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_130_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_130_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_130_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_130_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_130_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_130_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_131_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_131_ccff_tail ;
wire [0:0] grid_clb_131_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_131_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_131_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_131_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_131_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_131_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_131_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_131_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_131_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_131_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_131_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_131_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_131_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_131_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_131_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_131_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_131_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_131_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_131_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_131_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_131_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_131_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_131_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_131_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_131_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_131_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_131_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_131_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_131_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_131_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_131_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_131_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_132_ccff_tail ;
wire [0:0] grid_clb_132_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_132_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_132_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_132_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_132_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_132_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_132_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_132_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_132_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_132_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_132_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_132_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_132_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_132_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_132_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_132_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_132_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_132_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_132_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_132_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_132_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_132_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_132_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_132_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_132_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_132_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_132_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_132_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_132_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_132_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_132_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_132_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_133_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_133_ccff_tail ;
wire [0:0] grid_clb_133_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_133_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_133_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_133_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_133_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_133_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_133_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_133_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_133_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_133_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_133_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_133_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_133_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_133_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_133_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_133_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_133_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_133_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_133_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_133_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_133_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_133_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_133_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_133_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_133_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_133_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_133_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_133_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_133_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_133_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_133_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_133_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_134_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_134_ccff_tail ;
wire [0:0] grid_clb_134_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_134_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_134_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_134_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_134_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_134_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_134_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_134_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_134_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_134_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_134_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_134_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_134_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_134_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_134_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_134_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_134_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_134_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_134_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_134_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_134_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_134_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_134_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_134_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_134_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_134_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_134_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_134_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_134_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_134_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_134_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_134_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_135_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_135_ccff_tail ;
wire [0:0] grid_clb_135_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_135_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_135_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_135_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_135_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_135_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_135_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_135_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_135_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_135_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_135_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_135_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_135_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_135_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_135_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_135_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_135_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_135_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_135_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_135_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_135_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_135_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_135_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_135_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_135_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_135_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_135_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_135_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_135_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_135_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_135_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_135_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_136_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_136_ccff_tail ;
wire [0:0] grid_clb_136_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_136_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_136_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_136_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_136_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_136_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_136_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_136_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_136_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_136_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_136_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_136_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_136_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_136_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_136_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_136_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_136_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_136_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_136_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_136_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_136_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_136_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_136_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_136_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_136_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_136_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_136_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_136_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_136_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_136_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_136_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_136_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_137_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_137_ccff_tail ;
wire [0:0] grid_clb_137_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_137_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_137_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_137_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_137_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_137_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_137_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_137_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_137_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_137_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_137_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_137_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_137_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_137_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_137_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_137_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_137_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_137_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_137_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_137_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_137_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_137_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_137_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_137_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_137_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_137_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_137_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_137_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_137_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_137_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_137_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_137_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_138_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_138_ccff_tail ;
wire [0:0] grid_clb_138_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_138_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_138_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_138_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_138_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_138_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_138_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_138_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_138_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_138_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_138_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_138_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_138_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_138_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_138_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_138_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_138_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_138_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_138_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_138_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_138_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_138_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_138_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_138_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_138_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_138_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_138_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_138_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_138_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_138_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_138_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_138_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_139_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_139_ccff_tail ;
wire [0:0] grid_clb_139_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_139_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_139_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_139_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_139_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_139_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_139_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_139_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_139_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_139_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_139_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_139_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_139_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_139_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_139_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_139_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_139_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_139_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_139_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_139_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_139_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_139_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_139_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_139_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_139_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_139_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_139_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_139_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_139_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_139_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_139_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_139_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_13_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_13_ccff_tail ;
wire [0:0] grid_clb_13_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_13_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_13_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_13_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_13_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_13_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_13_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_13_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_13_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_13_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_13_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_13_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_13_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_13_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_13_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_13_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_13_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_13_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_13_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_13_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_13_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_13_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_13_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_13_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_13_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_13_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_13_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_13_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_13_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_13_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_13_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_13_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_140_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_140_ccff_tail ;
wire [0:0] grid_clb_140_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_140_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_140_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_140_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_140_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_140_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_140_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_140_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_140_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_140_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_140_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_140_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_140_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_140_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_140_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_140_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_140_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_140_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_140_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_140_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_140_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_140_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_140_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_140_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_140_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_140_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_140_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_140_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_140_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_140_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_140_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_140_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_141_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_141_ccff_tail ;
wire [0:0] grid_clb_141_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_141_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_141_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_141_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_141_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_141_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_141_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_141_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_141_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_141_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_141_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_141_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_141_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_141_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_141_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_141_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_141_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_141_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_141_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_141_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_141_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_141_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_141_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_141_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_141_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_141_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_141_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_141_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_141_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_141_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_141_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_141_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_142_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_142_ccff_tail ;
wire [0:0] grid_clb_142_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_142_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_142_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_142_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_142_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_142_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_142_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_142_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_142_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_142_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_142_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_142_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_142_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_142_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_142_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_142_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_142_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_142_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_142_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_142_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_142_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_142_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_142_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_142_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_142_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_142_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_142_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_142_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_142_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_142_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_142_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_142_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_143_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_143_ccff_tail ;
wire [0:0] grid_clb_143_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_143_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_143_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_143_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_143_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_143_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_143_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_143_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_143_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_143_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_143_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_143_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_143_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_143_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_143_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_143_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_143_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_143_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_143_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_143_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_143_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_143_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_143_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_143_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_143_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_143_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_143_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_143_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_143_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_143_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_143_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_143_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_14_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_14_ccff_tail ;
wire [0:0] grid_clb_14_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_14_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_14_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_14_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_14_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_14_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_14_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_14_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_14_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_14_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_14_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_14_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_14_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_14_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_14_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_14_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_14_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_14_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_14_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_14_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_14_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_14_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_14_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_14_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_14_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_14_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_14_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_14_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_14_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_14_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_14_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_14_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_15_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_15_ccff_tail ;
wire [0:0] grid_clb_15_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_15_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_15_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_15_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_15_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_15_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_15_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_15_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_15_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_15_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_15_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_15_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_15_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_15_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_15_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_15_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_15_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_15_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_15_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_15_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_15_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_15_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_15_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_15_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_15_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_15_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_15_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_15_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_15_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_15_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_15_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_15_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_16_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_16_ccff_tail ;
wire [0:0] grid_clb_16_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_16_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_16_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_16_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_16_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_16_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_16_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_16_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_16_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_16_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_16_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_16_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_16_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_16_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_16_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_16_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_16_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_16_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_16_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_16_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_16_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_16_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_16_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_16_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_16_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_16_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_16_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_16_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_16_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_16_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_16_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_16_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_17_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_17_ccff_tail ;
wire [0:0] grid_clb_17_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_17_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_17_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_17_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_17_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_17_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_17_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_17_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_17_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_17_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_17_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_17_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_17_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_17_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_17_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_17_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_17_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_17_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_17_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_17_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_17_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_17_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_17_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_17_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_17_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_17_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_17_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_17_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_17_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_17_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_17_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_17_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_18_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_18_ccff_tail ;
wire [0:0] grid_clb_18_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_18_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_18_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_18_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_18_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_18_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_18_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_18_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_18_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_18_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_18_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_18_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_18_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_18_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_18_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_18_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_18_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_18_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_18_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_18_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_18_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_18_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_18_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_18_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_18_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_18_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_18_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_18_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_18_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_18_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_18_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_18_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_19_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_19_ccff_tail ;
wire [0:0] grid_clb_19_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_19_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_19_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_19_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_19_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_19_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_19_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_19_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_19_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_19_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_19_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_19_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_19_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_19_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_19_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_19_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_19_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_19_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_19_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_19_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_19_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_19_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_19_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_19_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_19_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_19_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_19_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_19_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_19_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_19_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_19_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_19_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_1__10__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_1__11__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_1__12__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_1__12__undriven_top_width_0_height_0__pin_32_ ;
wire [0:0] grid_clb_1__1__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_1__2__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_1__3__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_1__4__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_1__5__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_1__6__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_1__7__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_1__8__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_1__9__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_1_ccff_tail ;
wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_20_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_20_ccff_tail ;
wire [0:0] grid_clb_20_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_20_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_20_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_20_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_20_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_20_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_20_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_20_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_20_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_20_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_20_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_20_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_20_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_20_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_20_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_20_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_20_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_20_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_20_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_20_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_20_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_20_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_20_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_20_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_20_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_20_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_20_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_20_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_20_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_20_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_20_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_20_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_21_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_21_ccff_tail ;
wire [0:0] grid_clb_21_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_21_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_21_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_21_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_21_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_21_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_21_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_21_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_21_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_21_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_21_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_21_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_21_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_21_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_21_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_21_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_21_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_21_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_21_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_21_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_21_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_21_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_21_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_21_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_21_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_21_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_21_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_21_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_21_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_21_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_21_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_21_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_22_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_22_ccff_tail ;
wire [0:0] grid_clb_22_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_22_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_22_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_22_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_22_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_22_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_22_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_22_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_22_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_22_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_22_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_22_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_22_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_22_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_22_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_22_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_22_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_22_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_22_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_22_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_22_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_22_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_22_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_22_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_22_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_22_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_22_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_22_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_22_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_22_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_22_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_22_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_23_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_23_ccff_tail ;
wire [0:0] grid_clb_23_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_23_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_23_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_23_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_23_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_23_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_23_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_23_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_23_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_23_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_23_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_23_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_23_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_23_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_23_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_23_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_23_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_23_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_23_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_23_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_23_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_23_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_23_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_23_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_23_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_23_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_23_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_23_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_23_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_23_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_23_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_23_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_24_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_24_ccff_tail ;
wire [0:0] grid_clb_24_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_24_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_24_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_24_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_24_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_24_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_24_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_24_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_24_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_24_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_24_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_24_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_24_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_24_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_24_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_24_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_24_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_24_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_24_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_24_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_24_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_24_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_24_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_24_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_24_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_24_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_24_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_24_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_24_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_24_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_24_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_24_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_25_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_25_ccff_tail ;
wire [0:0] grid_clb_25_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_25_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_25_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_25_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_25_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_25_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_25_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_25_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_25_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_25_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_25_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_25_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_25_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_25_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_25_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_25_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_25_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_25_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_25_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_25_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_25_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_25_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_25_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_25_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_25_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_25_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_25_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_25_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_25_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_25_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_25_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_25_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_26_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_26_ccff_tail ;
wire [0:0] grid_clb_26_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_26_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_26_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_26_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_26_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_26_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_26_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_26_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_26_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_26_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_26_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_26_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_26_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_26_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_26_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_26_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_26_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_26_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_26_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_26_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_26_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_26_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_26_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_26_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_26_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_26_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_26_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_26_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_26_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_26_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_26_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_26_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_27_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_27_ccff_tail ;
wire [0:0] grid_clb_27_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_27_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_27_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_27_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_27_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_27_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_27_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_27_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_27_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_27_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_27_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_27_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_27_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_27_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_27_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_27_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_27_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_27_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_27_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_27_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_27_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_27_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_27_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_27_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_27_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_27_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_27_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_27_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_27_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_27_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_27_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_27_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_28_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_28_ccff_tail ;
wire [0:0] grid_clb_28_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_28_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_28_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_28_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_28_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_28_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_28_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_28_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_28_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_28_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_28_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_28_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_28_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_28_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_28_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_28_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_28_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_28_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_28_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_28_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_28_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_28_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_28_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_28_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_28_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_28_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_28_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_28_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_28_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_28_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_28_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_28_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_29_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_29_ccff_tail ;
wire [0:0] grid_clb_29_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_29_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_29_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_29_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_29_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_29_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_29_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_29_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_29_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_29_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_29_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_29_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_29_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_29_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_29_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_29_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_29_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_29_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_29_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_29_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_29_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_29_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_29_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_29_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_29_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_29_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_29_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_29_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_29_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_29_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_29_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_29_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_2__10__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_2__11__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_2__12__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_2__1__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_2__2__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_2__3__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_2__4__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_2__5__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_2__6__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_2__7__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_2__8__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_2__9__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_2_ccff_tail ;
wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_30_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_30_ccff_tail ;
wire [0:0] grid_clb_30_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_30_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_30_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_30_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_30_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_30_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_30_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_30_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_30_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_30_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_30_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_30_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_30_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_30_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_30_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_30_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_30_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_30_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_30_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_30_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_30_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_30_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_30_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_30_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_30_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_30_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_30_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_30_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_30_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_30_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_30_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_30_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_31_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_31_ccff_tail ;
wire [0:0] grid_clb_31_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_31_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_31_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_31_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_31_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_31_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_31_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_31_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_31_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_31_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_31_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_31_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_31_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_31_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_31_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_31_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_31_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_31_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_31_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_31_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_31_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_31_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_31_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_31_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_31_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_31_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_31_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_31_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_31_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_31_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_31_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_31_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_32_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_32_ccff_tail ;
wire [0:0] grid_clb_32_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_32_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_32_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_32_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_32_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_32_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_32_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_32_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_32_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_32_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_32_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_32_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_32_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_32_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_32_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_32_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_32_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_32_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_32_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_32_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_32_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_32_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_32_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_32_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_32_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_32_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_32_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_32_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_32_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_32_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_32_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_32_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_33_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_33_ccff_tail ;
wire [0:0] grid_clb_33_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_33_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_33_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_33_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_33_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_33_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_33_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_33_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_33_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_33_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_33_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_33_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_33_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_33_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_33_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_33_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_33_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_33_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_33_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_33_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_33_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_33_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_33_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_33_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_33_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_33_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_33_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_33_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_33_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_33_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_33_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_33_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_34_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_34_ccff_tail ;
wire [0:0] grid_clb_34_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_34_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_34_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_34_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_34_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_34_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_34_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_34_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_34_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_34_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_34_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_34_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_34_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_34_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_34_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_34_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_34_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_34_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_34_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_34_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_34_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_34_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_34_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_34_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_34_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_34_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_34_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_34_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_34_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_34_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_34_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_34_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_35_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_35_ccff_tail ;
wire [0:0] grid_clb_35_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_35_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_35_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_35_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_35_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_35_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_35_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_35_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_35_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_35_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_35_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_35_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_35_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_35_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_35_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_35_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_35_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_35_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_35_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_35_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_35_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_35_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_35_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_35_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_35_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_35_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_35_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_35_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_35_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_35_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_35_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_35_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_36_ccff_tail ;
wire [0:0] grid_clb_36_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_36_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_36_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_36_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_36_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_36_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_36_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_36_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_36_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_36_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_36_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_36_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_36_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_36_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_36_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_36_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_36_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_36_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_36_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_36_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_36_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_36_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_36_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_36_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_36_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_36_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_36_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_36_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_36_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_36_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_36_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_36_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_37_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_37_ccff_tail ;
wire [0:0] grid_clb_37_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_37_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_37_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_37_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_37_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_37_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_37_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_37_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_37_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_37_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_37_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_37_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_37_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_37_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_37_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_37_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_37_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_37_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_37_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_37_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_37_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_37_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_37_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_37_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_37_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_37_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_37_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_37_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_37_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_37_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_37_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_37_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_38_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_38_ccff_tail ;
wire [0:0] grid_clb_38_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_38_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_38_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_38_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_38_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_38_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_38_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_38_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_38_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_38_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_38_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_38_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_38_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_38_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_38_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_38_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_38_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_38_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_38_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_38_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_38_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_38_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_38_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_38_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_38_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_38_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_38_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_38_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_38_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_38_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_38_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_38_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_39_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_39_ccff_tail ;
wire [0:0] grid_clb_39_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_39_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_39_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_39_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_39_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_39_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_39_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_39_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_39_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_39_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_39_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_39_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_39_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_39_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_39_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_39_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_39_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_39_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_39_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_39_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_39_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_39_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_39_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_39_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_39_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_39_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_39_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_39_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_39_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_39_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_39_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_39_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_3__10__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_3__11__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_3__12__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_3__1__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_3__2__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_3__3__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_3__4__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_3__5__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_3__6__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_3__7__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_3__8__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_3__9__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_3_ccff_tail ;
wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_40_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_40_ccff_tail ;
wire [0:0] grid_clb_40_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_40_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_40_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_40_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_40_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_40_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_40_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_40_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_40_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_40_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_40_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_40_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_40_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_40_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_40_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_40_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_40_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_40_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_40_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_40_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_40_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_40_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_40_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_40_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_40_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_40_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_40_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_40_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_40_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_40_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_40_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_40_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_41_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_41_ccff_tail ;
wire [0:0] grid_clb_41_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_41_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_41_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_41_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_41_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_41_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_41_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_41_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_41_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_41_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_41_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_41_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_41_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_41_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_41_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_41_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_41_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_41_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_41_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_41_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_41_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_41_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_41_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_41_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_41_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_41_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_41_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_41_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_41_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_41_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_41_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_41_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_42_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_42_ccff_tail ;
wire [0:0] grid_clb_42_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_42_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_42_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_42_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_42_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_42_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_42_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_42_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_42_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_42_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_42_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_42_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_42_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_42_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_42_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_42_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_42_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_42_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_42_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_42_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_42_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_42_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_42_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_42_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_42_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_42_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_42_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_42_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_42_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_42_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_42_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_42_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_43_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_43_ccff_tail ;
wire [0:0] grid_clb_43_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_43_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_43_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_43_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_43_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_43_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_43_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_43_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_43_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_43_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_43_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_43_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_43_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_43_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_43_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_43_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_43_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_43_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_43_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_43_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_43_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_43_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_43_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_43_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_43_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_43_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_43_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_43_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_43_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_43_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_43_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_43_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_44_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_44_ccff_tail ;
wire [0:0] grid_clb_44_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_44_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_44_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_44_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_44_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_44_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_44_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_44_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_44_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_44_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_44_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_44_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_44_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_44_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_44_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_44_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_44_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_44_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_44_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_44_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_44_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_44_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_44_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_44_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_44_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_44_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_44_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_44_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_44_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_44_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_44_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_44_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_45_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_45_ccff_tail ;
wire [0:0] grid_clb_45_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_45_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_45_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_45_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_45_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_45_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_45_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_45_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_45_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_45_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_45_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_45_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_45_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_45_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_45_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_45_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_45_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_45_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_45_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_45_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_45_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_45_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_45_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_45_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_45_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_45_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_45_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_45_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_45_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_45_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_45_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_45_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_46_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_46_ccff_tail ;
wire [0:0] grid_clb_46_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_46_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_46_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_46_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_46_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_46_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_46_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_46_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_46_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_46_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_46_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_46_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_46_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_46_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_46_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_46_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_46_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_46_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_46_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_46_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_46_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_46_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_46_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_46_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_46_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_46_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_46_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_46_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_46_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_46_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_46_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_46_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_47_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_47_ccff_tail ;
wire [0:0] grid_clb_47_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_47_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_47_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_47_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_47_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_47_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_47_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_47_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_47_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_47_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_47_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_47_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_47_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_47_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_47_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_47_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_47_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_47_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_47_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_47_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_47_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_47_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_47_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_47_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_47_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_47_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_47_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_47_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_47_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_47_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_47_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_47_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_48_ccff_tail ;
wire [0:0] grid_clb_48_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_48_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_48_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_48_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_48_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_48_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_48_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_48_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_48_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_48_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_48_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_48_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_48_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_48_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_48_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_48_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_48_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_48_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_48_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_48_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_48_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_48_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_48_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_48_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_48_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_48_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_48_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_48_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_48_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_48_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_48_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_48_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_49_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_49_ccff_tail ;
wire [0:0] grid_clb_49_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_49_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_49_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_49_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_49_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_49_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_49_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_49_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_49_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_49_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_49_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_49_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_49_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_49_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_49_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_49_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_49_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_49_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_49_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_49_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_49_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_49_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_49_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_49_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_49_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_49_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_49_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_49_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_49_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_49_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_49_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_49_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_4__10__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_4__11__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_4__12__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_4__1__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_4__2__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_4__3__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_4__4__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_4__5__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_4__6__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_4__7__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_4__8__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_4__9__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_4_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_4_ccff_tail ;
wire [0:0] grid_clb_4_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_4_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_4_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_4_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_4_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_4_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_4_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_4_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_4_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_4_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_4_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_4_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_4_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_4_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_4_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_4_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_4_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_4_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_4_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_4_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_4_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_4_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_4_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_4_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_4_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_4_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_4_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_4_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_4_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_4_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_4_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_4_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_50_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_50_ccff_tail ;
wire [0:0] grid_clb_50_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_50_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_50_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_50_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_50_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_50_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_50_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_50_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_50_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_50_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_50_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_50_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_50_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_50_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_50_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_50_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_50_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_50_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_50_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_50_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_50_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_50_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_50_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_50_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_50_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_50_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_50_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_50_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_50_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_50_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_50_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_50_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_51_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_51_ccff_tail ;
wire [0:0] grid_clb_51_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_51_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_51_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_51_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_51_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_51_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_51_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_51_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_51_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_51_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_51_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_51_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_51_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_51_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_51_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_51_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_51_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_51_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_51_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_51_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_51_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_51_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_51_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_51_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_51_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_51_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_51_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_51_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_51_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_51_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_51_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_51_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_52_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_52_ccff_tail ;
wire [0:0] grid_clb_52_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_52_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_52_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_52_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_52_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_52_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_52_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_52_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_52_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_52_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_52_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_52_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_52_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_52_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_52_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_52_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_52_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_52_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_52_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_52_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_52_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_52_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_52_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_52_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_52_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_52_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_52_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_52_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_52_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_52_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_52_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_52_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_53_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_53_ccff_tail ;
wire [0:0] grid_clb_53_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_53_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_53_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_53_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_53_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_53_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_53_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_53_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_53_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_53_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_53_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_53_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_53_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_53_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_53_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_53_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_53_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_53_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_53_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_53_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_53_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_53_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_53_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_53_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_53_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_53_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_53_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_53_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_53_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_53_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_53_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_53_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_54_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_54_ccff_tail ;
wire [0:0] grid_clb_54_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_54_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_54_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_54_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_54_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_54_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_54_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_54_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_54_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_54_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_54_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_54_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_54_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_54_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_54_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_54_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_54_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_54_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_54_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_54_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_54_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_54_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_54_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_54_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_54_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_54_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_54_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_54_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_54_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_54_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_54_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_54_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_55_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_55_ccff_tail ;
wire [0:0] grid_clb_55_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_55_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_55_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_55_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_55_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_55_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_55_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_55_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_55_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_55_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_55_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_55_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_55_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_55_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_55_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_55_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_55_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_55_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_55_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_55_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_55_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_55_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_55_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_55_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_55_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_55_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_55_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_55_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_55_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_55_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_55_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_55_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_56_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_56_ccff_tail ;
wire [0:0] grid_clb_56_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_56_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_56_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_56_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_56_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_56_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_56_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_56_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_56_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_56_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_56_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_56_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_56_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_56_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_56_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_56_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_56_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_56_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_56_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_56_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_56_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_56_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_56_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_56_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_56_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_56_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_56_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_56_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_56_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_56_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_56_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_56_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_57_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_57_ccff_tail ;
wire [0:0] grid_clb_57_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_57_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_57_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_57_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_57_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_57_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_57_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_57_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_57_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_57_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_57_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_57_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_57_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_57_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_57_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_57_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_57_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_57_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_57_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_57_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_57_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_57_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_57_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_57_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_57_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_57_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_57_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_57_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_57_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_57_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_57_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_57_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_58_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_58_ccff_tail ;
wire [0:0] grid_clb_58_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_58_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_58_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_58_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_58_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_58_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_58_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_58_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_58_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_58_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_58_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_58_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_58_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_58_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_58_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_58_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_58_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_58_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_58_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_58_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_58_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_58_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_58_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_58_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_58_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_58_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_58_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_58_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_58_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_58_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_58_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_58_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_59_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_59_ccff_tail ;
wire [0:0] grid_clb_59_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_59_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_59_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_59_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_59_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_59_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_59_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_59_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_59_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_59_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_59_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_59_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_59_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_59_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_59_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_59_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_59_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_59_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_59_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_59_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_59_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_59_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_59_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_59_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_59_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_59_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_59_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_59_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_59_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_59_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_59_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_59_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_5__10__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_5__11__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_5__12__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_5__1__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_5__2__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_5__3__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_5__4__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_5__5__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_5__6__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_5__7__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_5__8__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_5__9__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_5_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_5_ccff_tail ;
wire [0:0] grid_clb_5_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_5_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_5_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_5_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_5_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_5_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_5_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_5_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_5_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_5_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_5_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_5_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_5_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_5_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_5_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_5_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_5_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_5_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_5_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_5_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_5_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_5_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_5_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_5_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_5_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_5_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_5_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_5_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_5_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_5_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_5_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_5_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_60_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_60_ccff_tail ;
wire [0:0] grid_clb_60_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_60_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_60_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_60_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_60_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_60_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_60_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_60_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_60_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_60_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_60_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_60_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_60_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_60_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_60_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_60_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_60_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_60_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_60_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_60_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_60_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_60_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_60_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_60_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_60_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_60_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_60_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_60_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_60_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_60_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_60_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_60_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_61_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_61_ccff_tail ;
wire [0:0] grid_clb_61_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_61_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_61_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_61_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_61_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_61_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_61_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_61_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_61_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_61_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_61_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_61_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_61_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_61_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_61_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_61_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_61_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_61_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_61_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_61_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_61_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_61_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_61_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_61_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_61_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_61_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_61_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_61_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_61_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_61_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_61_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_61_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_62_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_62_ccff_tail ;
wire [0:0] grid_clb_62_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_62_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_62_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_62_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_62_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_62_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_62_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_62_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_62_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_62_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_62_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_62_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_62_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_62_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_62_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_62_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_62_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_62_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_62_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_62_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_62_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_62_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_62_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_62_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_62_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_62_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_62_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_62_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_62_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_62_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_62_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_62_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_63_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_63_ccff_tail ;
wire [0:0] grid_clb_63_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_63_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_63_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_63_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_63_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_63_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_63_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_63_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_63_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_63_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_63_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_63_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_63_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_63_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_63_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_63_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_63_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_63_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_63_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_63_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_63_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_63_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_63_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_63_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_63_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_63_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_63_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_63_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_63_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_63_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_63_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_63_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_64_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_64_ccff_tail ;
wire [0:0] grid_clb_64_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_64_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_64_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_64_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_64_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_64_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_64_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_64_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_64_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_64_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_64_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_64_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_64_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_64_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_64_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_64_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_64_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_64_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_64_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_64_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_64_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_64_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_64_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_64_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_64_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_64_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_64_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_64_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_64_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_64_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_64_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_64_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_65_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_65_ccff_tail ;
wire [0:0] grid_clb_65_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_65_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_65_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_65_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_65_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_65_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_65_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_65_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_65_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_65_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_65_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_65_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_65_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_65_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_65_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_65_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_65_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_65_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_65_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_65_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_65_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_65_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_65_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_65_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_65_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_65_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_65_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_65_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_65_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_65_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_65_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_65_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_66_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_66_ccff_tail ;
wire [0:0] grid_clb_66_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_66_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_66_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_66_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_66_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_66_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_66_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_66_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_66_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_66_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_66_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_66_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_66_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_66_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_66_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_66_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_66_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_66_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_66_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_66_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_66_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_66_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_66_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_66_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_66_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_66_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_66_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_66_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_66_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_66_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_66_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_66_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_67_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_67_ccff_tail ;
wire [0:0] grid_clb_67_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_67_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_67_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_67_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_67_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_67_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_67_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_67_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_67_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_67_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_67_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_67_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_67_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_67_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_67_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_67_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_67_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_67_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_67_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_67_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_67_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_67_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_67_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_67_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_67_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_67_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_67_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_67_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_67_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_67_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_67_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_67_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_68_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_68_ccff_tail ;
wire [0:0] grid_clb_68_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_68_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_68_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_68_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_68_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_68_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_68_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_68_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_68_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_68_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_68_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_68_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_68_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_68_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_68_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_68_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_68_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_68_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_68_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_68_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_68_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_68_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_68_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_68_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_68_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_68_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_68_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_68_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_68_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_68_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_68_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_68_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_69_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_69_ccff_tail ;
wire [0:0] grid_clb_69_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_69_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_69_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_69_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_69_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_69_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_69_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_69_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_69_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_69_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_69_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_69_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_69_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_69_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_69_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_69_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_69_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_69_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_69_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_69_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_69_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_69_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_69_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_69_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_69_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_69_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_69_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_69_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_69_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_69_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_69_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_69_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_6__10__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_6__11__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_6__12__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_6__1__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_6__2__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_6__3__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_6__4__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_6__5__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_6__6__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_6__7__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_6__8__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_6__9__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_6_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_6_ccff_tail ;
wire [0:0] grid_clb_6_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_6_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_6_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_6_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_6_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_6_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_6_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_6_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_6_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_6_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_6_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_6_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_6_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_6_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_6_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_6_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_6_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_6_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_6_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_6_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_6_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_6_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_6_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_6_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_6_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_6_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_6_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_6_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_6_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_6_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_6_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_6_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_70_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_70_ccff_tail ;
wire [0:0] grid_clb_70_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_70_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_70_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_70_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_70_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_70_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_70_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_70_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_70_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_70_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_70_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_70_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_70_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_70_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_70_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_70_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_70_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_70_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_70_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_70_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_70_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_70_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_70_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_70_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_70_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_70_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_70_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_70_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_70_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_70_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_70_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_70_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_71_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_71_ccff_tail ;
wire [0:0] grid_clb_71_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_71_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_71_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_71_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_71_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_71_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_71_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_71_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_71_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_71_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_71_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_71_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_71_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_71_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_71_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_71_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_71_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_71_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_71_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_71_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_71_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_71_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_71_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_71_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_71_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_71_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_71_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_71_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_71_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_71_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_71_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_71_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_72_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_72_ccff_tail ;
wire [0:0] grid_clb_72_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_72_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_72_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_72_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_72_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_72_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_72_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_72_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_72_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_72_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_72_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_72_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_72_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_72_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_72_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_72_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_72_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_72_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_72_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_72_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_72_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_72_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_72_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_72_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_72_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_72_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_72_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_72_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_72_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_72_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_72_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_72_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_73_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_73_ccff_tail ;
wire [0:0] grid_clb_73_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_73_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_73_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_73_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_73_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_73_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_73_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_73_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_73_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_73_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_73_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_73_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_73_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_73_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_73_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_73_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_73_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_73_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_73_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_73_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_73_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_73_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_73_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_73_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_73_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_73_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_73_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_73_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_73_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_73_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_73_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_73_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_74_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_74_ccff_tail ;
wire [0:0] grid_clb_74_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_74_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_74_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_74_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_74_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_74_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_74_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_74_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_74_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_74_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_74_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_74_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_74_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_74_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_74_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_74_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_74_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_74_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_74_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_74_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_74_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_74_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_74_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_74_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_74_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_74_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_74_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_74_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_74_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_74_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_74_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_74_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_75_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_75_ccff_tail ;
wire [0:0] grid_clb_75_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_75_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_75_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_75_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_75_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_75_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_75_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_75_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_75_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_75_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_75_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_75_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_75_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_75_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_75_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_75_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_75_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_75_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_75_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_75_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_75_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_75_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_75_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_75_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_75_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_75_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_75_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_75_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_75_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_75_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_75_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_75_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_76_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_76_ccff_tail ;
wire [0:0] grid_clb_76_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_76_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_76_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_76_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_76_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_76_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_76_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_76_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_76_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_76_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_76_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_76_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_76_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_76_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_76_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_76_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_76_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_76_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_76_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_76_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_76_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_76_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_76_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_76_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_76_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_76_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_76_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_76_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_76_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_76_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_76_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_76_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_77_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_77_ccff_tail ;
wire [0:0] grid_clb_77_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_77_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_77_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_77_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_77_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_77_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_77_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_77_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_77_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_77_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_77_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_77_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_77_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_77_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_77_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_77_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_77_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_77_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_77_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_77_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_77_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_77_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_77_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_77_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_77_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_77_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_77_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_77_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_77_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_77_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_77_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_77_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_78_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_78_ccff_tail ;
wire [0:0] grid_clb_78_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_78_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_78_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_78_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_78_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_78_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_78_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_78_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_78_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_78_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_78_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_78_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_78_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_78_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_78_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_78_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_78_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_78_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_78_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_78_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_78_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_78_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_78_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_78_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_78_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_78_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_78_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_78_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_78_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_78_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_78_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_78_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_79_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_79_ccff_tail ;
wire [0:0] grid_clb_79_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_79_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_79_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_79_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_79_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_79_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_79_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_79_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_79_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_79_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_79_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_79_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_79_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_79_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_79_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_79_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_79_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_79_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_79_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_79_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_79_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_79_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_79_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_79_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_79_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_79_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_79_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_79_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_79_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_79_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_79_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_79_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_7__10__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_7__11__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_7__12__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_7__1__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_7__2__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_7__3__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_7__4__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_7__5__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_7__6__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_7__7__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_7__8__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_7__9__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_7_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_7_ccff_tail ;
wire [0:0] grid_clb_7_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_7_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_7_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_7_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_7_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_7_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_7_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_7_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_7_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_7_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_7_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_7_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_7_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_7_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_7_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_7_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_7_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_7_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_7_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_7_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_7_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_7_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_7_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_7_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_7_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_7_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_7_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_7_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_7_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_7_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_7_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_7_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_80_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_80_ccff_tail ;
wire [0:0] grid_clb_80_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_80_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_80_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_80_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_80_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_80_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_80_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_80_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_80_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_80_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_80_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_80_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_80_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_80_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_80_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_80_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_80_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_80_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_80_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_80_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_80_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_80_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_80_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_80_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_80_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_80_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_80_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_80_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_80_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_80_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_80_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_80_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_81_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_81_ccff_tail ;
wire [0:0] grid_clb_81_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_81_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_81_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_81_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_81_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_81_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_81_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_81_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_81_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_81_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_81_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_81_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_81_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_81_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_81_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_81_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_81_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_81_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_81_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_81_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_81_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_81_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_81_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_81_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_81_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_81_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_81_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_81_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_81_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_81_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_81_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_81_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_82_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_82_ccff_tail ;
wire [0:0] grid_clb_82_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_82_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_82_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_82_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_82_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_82_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_82_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_82_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_82_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_82_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_82_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_82_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_82_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_82_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_82_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_82_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_82_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_82_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_82_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_82_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_82_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_82_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_82_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_82_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_82_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_82_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_82_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_82_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_82_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_82_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_82_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_82_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_83_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_83_ccff_tail ;
wire [0:0] grid_clb_83_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_83_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_83_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_83_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_83_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_83_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_83_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_83_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_83_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_83_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_83_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_83_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_83_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_83_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_83_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_83_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_83_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_83_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_83_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_83_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_83_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_83_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_83_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_83_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_83_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_83_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_83_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_83_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_83_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_83_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_83_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_83_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_84_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_84_ccff_tail ;
wire [0:0] grid_clb_84_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_84_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_84_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_84_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_84_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_84_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_84_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_84_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_84_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_84_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_84_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_84_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_84_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_84_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_84_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_84_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_84_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_84_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_84_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_84_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_84_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_84_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_84_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_84_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_84_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_84_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_84_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_84_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_84_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_84_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_84_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_84_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_85_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_85_ccff_tail ;
wire [0:0] grid_clb_85_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_85_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_85_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_85_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_85_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_85_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_85_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_85_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_85_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_85_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_85_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_85_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_85_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_85_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_85_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_85_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_85_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_85_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_85_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_85_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_85_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_85_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_85_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_85_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_85_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_85_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_85_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_85_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_85_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_85_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_85_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_85_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_86_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_86_ccff_tail ;
wire [0:0] grid_clb_86_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_86_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_86_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_86_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_86_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_86_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_86_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_86_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_86_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_86_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_86_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_86_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_86_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_86_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_86_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_86_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_86_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_86_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_86_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_86_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_86_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_86_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_86_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_86_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_86_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_86_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_86_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_86_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_86_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_86_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_86_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_86_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_87_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_87_ccff_tail ;
wire [0:0] grid_clb_87_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_87_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_87_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_87_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_87_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_87_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_87_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_87_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_87_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_87_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_87_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_87_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_87_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_87_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_87_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_87_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_87_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_87_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_87_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_87_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_87_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_87_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_87_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_87_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_87_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_87_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_87_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_87_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_87_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_87_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_87_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_87_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_88_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_88_ccff_tail ;
wire [0:0] grid_clb_88_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_88_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_88_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_88_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_88_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_88_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_88_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_88_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_88_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_88_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_88_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_88_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_88_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_88_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_88_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_88_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_88_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_88_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_88_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_88_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_88_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_88_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_88_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_88_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_88_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_88_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_88_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_88_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_88_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_88_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_88_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_88_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_89_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_89_ccff_tail ;
wire [0:0] grid_clb_89_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_89_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_89_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_89_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_89_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_89_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_89_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_89_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_89_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_89_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_89_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_89_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_89_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_89_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_89_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_89_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_89_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_89_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_89_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_89_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_89_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_89_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_89_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_89_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_89_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_89_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_89_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_89_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_89_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_89_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_89_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_89_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_8__10__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_8__11__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_8__12__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_8__1__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_8__2__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_8__3__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_8__4__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_8__5__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_8__6__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_8__7__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_8__8__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_8__9__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_8_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_8_ccff_tail ;
wire [0:0] grid_clb_8_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_8_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_8_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_8_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_8_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_8_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_8_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_8_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_8_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_8_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_8_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_8_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_8_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_8_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_8_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_8_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_8_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_8_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_8_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_8_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_8_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_8_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_8_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_8_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_8_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_8_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_8_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_8_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_8_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_8_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_8_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_8_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_90_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_90_ccff_tail ;
wire [0:0] grid_clb_90_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_90_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_90_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_90_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_90_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_90_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_90_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_90_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_90_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_90_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_90_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_90_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_90_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_90_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_90_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_90_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_90_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_90_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_90_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_90_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_90_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_90_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_90_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_90_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_90_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_90_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_90_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_90_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_90_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_90_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_90_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_90_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_91_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_91_ccff_tail ;
wire [0:0] grid_clb_91_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_91_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_91_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_91_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_91_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_91_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_91_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_91_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_91_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_91_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_91_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_91_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_91_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_91_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_91_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_91_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_91_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_91_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_91_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_91_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_91_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_91_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_91_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_91_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_91_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_91_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_91_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_91_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_91_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_91_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_91_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_91_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_92_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_92_ccff_tail ;
wire [0:0] grid_clb_92_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_92_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_92_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_92_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_92_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_92_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_92_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_92_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_92_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_92_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_92_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_92_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_92_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_92_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_92_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_92_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_92_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_92_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_92_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_92_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_92_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_92_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_92_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_92_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_92_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_92_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_92_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_92_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_92_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_92_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_92_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_92_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_93_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_93_ccff_tail ;
wire [0:0] grid_clb_93_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_93_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_93_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_93_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_93_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_93_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_93_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_93_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_93_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_93_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_93_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_93_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_93_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_93_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_93_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_93_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_93_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_93_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_93_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_93_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_93_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_93_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_93_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_93_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_93_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_93_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_93_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_93_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_93_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_93_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_93_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_93_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_94_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_94_ccff_tail ;
wire [0:0] grid_clb_94_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_94_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_94_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_94_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_94_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_94_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_94_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_94_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_94_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_94_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_94_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_94_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_94_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_94_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_94_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_94_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_94_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_94_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_94_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_94_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_94_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_94_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_94_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_94_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_94_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_94_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_94_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_94_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_94_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_94_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_94_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_94_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_95_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_95_ccff_tail ;
wire [0:0] grid_clb_95_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_95_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_95_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_95_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_95_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_95_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_95_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_95_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_95_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_95_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_95_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_95_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_95_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_95_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_95_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_95_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_95_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_95_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_95_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_95_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_95_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_95_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_95_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_95_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_95_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_95_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_95_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_95_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_95_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_95_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_95_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_95_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_96_ccff_tail ;
wire [0:0] grid_clb_96_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_96_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_96_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_96_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_96_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_96_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_96_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_96_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_96_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_96_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_96_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_96_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_96_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_96_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_96_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_96_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_96_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_96_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_96_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_96_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_96_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_96_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_96_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_96_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_96_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_96_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_96_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_96_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_96_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_96_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_96_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_96_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_97_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_97_ccff_tail ;
wire [0:0] grid_clb_97_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_97_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_97_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_97_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_97_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_97_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_97_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_97_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_97_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_97_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_97_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_97_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_97_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_97_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_97_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_97_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_97_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_97_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_97_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_97_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_97_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_97_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_97_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_97_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_97_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_97_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_97_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_97_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_97_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_97_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_97_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_97_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_98_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_98_ccff_tail ;
wire [0:0] grid_clb_98_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_98_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_98_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_98_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_98_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_98_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_98_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_98_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_98_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_98_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_98_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_98_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_98_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_98_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_98_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_98_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_98_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_98_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_98_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_98_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_98_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_98_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_98_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_98_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_98_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_98_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_98_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_98_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_98_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_98_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_98_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_98_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_99_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_99_ccff_tail ;
wire [0:0] grid_clb_99_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_99_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_99_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_99_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_99_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_99_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_99_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_99_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_99_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_99_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_99_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_99_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_99_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_99_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_99_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_99_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_99_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_99_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_99_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_99_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_99_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_99_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_99_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_99_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_99_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_99_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_99_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_99_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_99_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_99_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_99_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_99_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_clb_9__10__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_9__11__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_9__12__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_9__1__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_9__2__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_9__3__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_9__4__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_9__5__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_9__6__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_9__7__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_9__8__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_9__9__undriven_left_width_0_height_0__pin_52_ ;
wire [0:0] grid_clb_9_bottom_width_0_height_0__pin_50_ ;
wire [0:0] grid_clb_9_ccff_tail ;
wire [0:0] grid_clb_9_right_width_0_height_0__pin_42_lower ;
wire [0:0] grid_clb_9_right_width_0_height_0__pin_42_upper ;
wire [0:0] grid_clb_9_right_width_0_height_0__pin_43_lower ;
wire [0:0] grid_clb_9_right_width_0_height_0__pin_43_upper ;
wire [0:0] grid_clb_9_right_width_0_height_0__pin_44_lower ;
wire [0:0] grid_clb_9_right_width_0_height_0__pin_44_upper ;
wire [0:0] grid_clb_9_right_width_0_height_0__pin_45_lower ;
wire [0:0] grid_clb_9_right_width_0_height_0__pin_45_upper ;
wire [0:0] grid_clb_9_right_width_0_height_0__pin_46_lower ;
wire [0:0] grid_clb_9_right_width_0_height_0__pin_46_upper ;
wire [0:0] grid_clb_9_right_width_0_height_0__pin_47_lower ;
wire [0:0] grid_clb_9_right_width_0_height_0__pin_47_upper ;
wire [0:0] grid_clb_9_right_width_0_height_0__pin_48_lower ;
wire [0:0] grid_clb_9_right_width_0_height_0__pin_48_upper ;
wire [0:0] grid_clb_9_right_width_0_height_0__pin_49_lower ;
wire [0:0] grid_clb_9_right_width_0_height_0__pin_49_upper ;
wire [0:0] grid_clb_9_top_width_0_height_0__pin_34_lower ;
wire [0:0] grid_clb_9_top_width_0_height_0__pin_34_upper ;
wire [0:0] grid_clb_9_top_width_0_height_0__pin_35_lower ;
wire [0:0] grid_clb_9_top_width_0_height_0__pin_35_upper ;
wire [0:0] grid_clb_9_top_width_0_height_0__pin_36_lower ;
wire [0:0] grid_clb_9_top_width_0_height_0__pin_36_upper ;
wire [0:0] grid_clb_9_top_width_0_height_0__pin_37_lower ;
wire [0:0] grid_clb_9_top_width_0_height_0__pin_37_upper ;
wire [0:0] grid_clb_9_top_width_0_height_0__pin_38_lower ;
wire [0:0] grid_clb_9_top_width_0_height_0__pin_38_upper ;
wire [0:0] grid_clb_9_top_width_0_height_0__pin_39_lower ;
wire [0:0] grid_clb_9_top_width_0_height_0__pin_39_upper ;
wire [0:0] grid_clb_9_top_width_0_height_0__pin_40_lower ;
wire [0:0] grid_clb_9_top_width_0_height_0__pin_40_upper ;
wire [0:0] grid_clb_9_top_width_0_height_0__pin_41_lower ;
wire [0:0] grid_clb_9_top_width_0_height_0__pin_41_upper ;
wire [0:0] grid_io_bottom_0_ccff_tail ;
wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_lower ;
wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_upper ;
wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_lower ;
wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_upper ;
wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_lower ;
wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_upper ;
wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_lower ;
wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_upper ;
wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_lower ;
wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_upper ;
wire [0:0] grid_io_bottom_10_ccff_tail ;
wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_11_lower ;
wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_11_upper ;
wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_3_lower ;
wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_3_upper ;
wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_5_lower ;
wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_5_upper ;
wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_7_lower ;
wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_7_upper ;
wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_9_lower ;
wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_9_upper ;
wire [0:0] grid_io_bottom_11_ccff_tail ;
wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_11_lower ;
wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_11_upper ;
wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_3_lower ;
wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_3_upper ;
wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_5_lower ;
wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_5_upper ;
wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_7_lower ;
wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_7_upper ;
wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_9_lower ;
wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_9_upper ;
wire [0:0] grid_io_bottom_1_ccff_tail ;
wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_lower ;
wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_upper ;
wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_lower ;
wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_upper ;
wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_lower ;
wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_upper ;
wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_lower ;
wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_upper ;
wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_lower ;
wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_upper ;
wire [0:0] grid_io_bottom_2_ccff_tail ;
wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_11_lower ;
wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_11_upper ;
wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_3_lower ;
wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_3_upper ;
wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_5_lower ;
wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_5_upper ;
wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_7_lower ;
wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_7_upper ;
wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_9_lower ;
wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_9_upper ;
wire [0:0] grid_io_bottom_3_ccff_tail ;
wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_11_lower ;
wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_11_upper ;
wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_3_lower ;
wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_3_upper ;
wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_5_lower ;
wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_5_upper ;
wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_7_lower ;
wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_7_upper ;
wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_9_lower ;
wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_9_upper ;
wire [0:0] grid_io_bottom_4_ccff_tail ;
wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_11_lower ;
wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_11_upper ;
wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_3_lower ;
wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_3_upper ;
wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_5_lower ;
wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_5_upper ;
wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_7_lower ;
wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_7_upper ;
wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_9_lower ;
wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_9_upper ;
wire [0:0] grid_io_bottom_5_ccff_tail ;
wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_11_lower ;
wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_11_upper ;
wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_3_lower ;
wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_3_upper ;
wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_5_lower ;
wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_5_upper ;
wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_7_lower ;
wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_7_upper ;
wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_9_lower ;
wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_9_upper ;
wire [0:0] grid_io_bottom_6_ccff_tail ;
wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_11_lower ;
wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_11_upper ;
wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_3_lower ;
wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_3_upper ;
wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_5_lower ;
wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_5_upper ;
wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_7_lower ;
wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_7_upper ;
wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_9_lower ;
wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_9_upper ;
wire [0:0] grid_io_bottom_7_ccff_tail ;
wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_11_lower ;
wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_11_upper ;
wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_3_lower ;
wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_3_upper ;
wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_5_lower ;
wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_5_upper ;
wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_7_lower ;
wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_7_upper ;
wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_9_lower ;
wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_9_upper ;
wire [0:0] grid_io_bottom_8_ccff_tail ;
wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_11_lower ;
wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_11_upper ;
wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_3_lower ;
wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_3_upper ;
wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_5_lower ;
wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_5_upper ;
wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_7_lower ;
wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_7_upper ;
wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_9_lower ;
wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_9_upper ;
wire [0:0] grid_io_bottom_9_ccff_tail ;
wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_11_lower ;
wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_11_upper ;
wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_3_lower ;
wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_3_upper ;
wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_5_lower ;
wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_5_upper ;
wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_7_lower ;
wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_7_upper ;
wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_9_lower ;
wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_9_upper ;
wire [0:0] grid_io_left_0_ccff_tail ;
wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_left_10_ccff_tail ;
wire [0:0] grid_io_left_10_right_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_left_10_right_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_left_11_ccff_tail ;
wire [0:0] grid_io_left_11_right_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_left_11_right_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_left_1_ccff_tail ;
wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_left_2_ccff_tail ;
wire [0:0] grid_io_left_2_right_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_left_2_right_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_left_3_ccff_tail ;
wire [0:0] grid_io_left_3_right_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_left_3_right_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_left_4_ccff_tail ;
wire [0:0] grid_io_left_4_right_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_left_4_right_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_left_5_ccff_tail ;
wire [0:0] grid_io_left_5_right_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_left_5_right_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_left_6_ccff_tail ;
wire [0:0] grid_io_left_6_right_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_left_6_right_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_left_7_ccff_tail ;
wire [0:0] grid_io_left_7_right_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_left_7_right_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_left_8_ccff_tail ;
wire [0:0] grid_io_left_8_right_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_left_8_right_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_left_9_ccff_tail ;
wire [0:0] grid_io_left_9_right_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_left_9_right_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_right_0_ccff_tail ;
wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_right_10_ccff_tail ;
wire [0:0] grid_io_right_10_left_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_right_10_left_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_right_11_ccff_tail ;
wire [0:0] grid_io_right_11_left_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_right_11_left_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_right_1_ccff_tail ;
wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_right_2_ccff_tail ;
wire [0:0] grid_io_right_2_left_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_right_2_left_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_right_3_ccff_tail ;
wire [0:0] grid_io_right_3_left_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_right_3_left_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_right_4_ccff_tail ;
wire [0:0] grid_io_right_4_left_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_right_4_left_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_right_5_ccff_tail ;
wire [0:0] grid_io_right_5_left_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_right_5_left_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_right_6_ccff_tail ;
wire [0:0] grid_io_right_6_left_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_right_6_left_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_right_7_ccff_tail ;
wire [0:0] grid_io_right_7_left_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_right_7_left_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_right_8_ccff_tail ;
wire [0:0] grid_io_right_8_left_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_right_8_left_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_right_9_ccff_tail ;
wire [0:0] grid_io_right_9_left_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_right_9_left_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_top_0_ccff_tail ;
wire [0:0] grid_io_top_10_bottom_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_top_10_bottom_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_top_10_ccff_tail ;
wire [0:0] grid_io_top_11_bottom_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_top_11_bottom_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_top_11_ccff_tail ;
wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_top_1_ccff_tail ;
wire [0:0] grid_io_top_2_bottom_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_top_2_bottom_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_top_2_ccff_tail ;
wire [0:0] grid_io_top_3_bottom_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_top_3_bottom_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_top_3_ccff_tail ;
wire [0:0] grid_io_top_4_bottom_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_top_4_bottom_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_top_4_ccff_tail ;
wire [0:0] grid_io_top_5_bottom_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_top_5_bottom_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_top_5_ccff_tail ;
wire [0:0] grid_io_top_6_bottom_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_top_6_bottom_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_top_6_ccff_tail ;
wire [0:0] grid_io_top_7_bottom_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_top_7_bottom_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_top_7_ccff_tail ;
wire [0:0] grid_io_top_8_bottom_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_top_8_bottom_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_top_8_ccff_tail ;
wire [0:0] grid_io_top_9_bottom_width_0_height_0__pin_1_lower ;
wire [0:0] grid_io_top_9_bottom_width_0_height_0__pin_1_upper ;
wire [0:0] grid_io_top_9_ccff_tail ;
wire [0:19] sb_0__0__0_chanx_right_out ;
wire [0:19] sb_0__0__0_chany_top_out ;
wire [0:0] sb_0__12__0_ccff_tail ;
wire [0:19] sb_0__12__0_chanx_right_out ;
wire [0:19] sb_0__12__0_chany_bottom_out ;
wire [0:0] sb_0__1__0_ccff_tail ;
wire [0:19] sb_0__1__0_chanx_right_out ;
wire [0:19] sb_0__1__0_chany_bottom_out ;
wire [0:19] sb_0__1__0_chany_top_out ;
wire [0:0] sb_0__1__10_ccff_tail ;
wire [0:19] sb_0__1__10_chanx_right_out ;
wire [0:19] sb_0__1__10_chany_bottom_out ;
wire [0:19] sb_0__1__10_chany_top_out ;
wire [0:0] sb_0__1__1_ccff_tail ;
wire [0:19] sb_0__1__1_chanx_right_out ;
wire [0:19] sb_0__1__1_chany_bottom_out ;
wire [0:19] sb_0__1__1_chany_top_out ;
wire [0:0] sb_0__1__2_ccff_tail ;
wire [0:19] sb_0__1__2_chanx_right_out ;
wire [0:19] sb_0__1__2_chany_bottom_out ;
wire [0:19] sb_0__1__2_chany_top_out ;
wire [0:0] sb_0__1__3_ccff_tail ;
wire [0:19] sb_0__1__3_chanx_right_out ;
wire [0:19] sb_0__1__3_chany_bottom_out ;
wire [0:19] sb_0__1__3_chany_top_out ;
wire [0:0] sb_0__1__4_ccff_tail ;
wire [0:19] sb_0__1__4_chanx_right_out ;
wire [0:19] sb_0__1__4_chany_bottom_out ;
wire [0:19] sb_0__1__4_chany_top_out ;
wire [0:0] sb_0__1__5_ccff_tail ;
wire [0:19] sb_0__1__5_chanx_right_out ;
wire [0:19] sb_0__1__5_chany_bottom_out ;
wire [0:19] sb_0__1__5_chany_top_out ;
wire [0:0] sb_0__1__6_ccff_tail ;
wire [0:19] sb_0__1__6_chanx_right_out ;
wire [0:19] sb_0__1__6_chany_bottom_out ;
wire [0:19] sb_0__1__6_chany_top_out ;
wire [0:0] sb_0__1__7_ccff_tail ;
wire [0:19] sb_0__1__7_chanx_right_out ;
wire [0:19] sb_0__1__7_chany_bottom_out ;
wire [0:19] sb_0__1__7_chany_top_out ;
wire [0:0] sb_0__1__8_ccff_tail ;
wire [0:19] sb_0__1__8_chanx_right_out ;
wire [0:19] sb_0__1__8_chany_bottom_out ;
wire [0:19] sb_0__1__8_chany_top_out ;
wire [0:0] sb_0__1__9_ccff_tail ;
wire [0:19] sb_0__1__9_chanx_right_out ;
wire [0:19] sb_0__1__9_chany_bottom_out ;
wire [0:19] sb_0__1__9_chany_top_out ;
wire [0:0] sb_12__0__0_ccff_tail ;
wire [0:19] sb_12__0__0_chanx_left_out ;
wire [0:19] sb_12__0__0_chany_top_out ;
wire [0:0] sb_12__12__0_ccff_tail ;
wire [0:19] sb_12__12__0_chanx_left_out ;
wire [0:19] sb_12__12__0_chany_bottom_out ;
wire [0:0] sb_12__1__0_ccff_tail ;
wire [0:19] sb_12__1__0_chanx_left_out ;
wire [0:19] sb_12__1__0_chany_bottom_out ;
wire [0:19] sb_12__1__0_chany_top_out ;
wire [0:0] sb_12__1__10_ccff_tail ;
wire [0:19] sb_12__1__10_chanx_left_out ;
wire [0:19] sb_12__1__10_chany_bottom_out ;
wire [0:19] sb_12__1__10_chany_top_out ;
wire [0:0] sb_12__1__1_ccff_tail ;
wire [0:19] sb_12__1__1_chanx_left_out ;
wire [0:19] sb_12__1__1_chany_bottom_out ;
wire [0:19] sb_12__1__1_chany_top_out ;
wire [0:0] sb_12__1__2_ccff_tail ;
wire [0:19] sb_12__1__2_chanx_left_out ;
wire [0:19] sb_12__1__2_chany_bottom_out ;
wire [0:19] sb_12__1__2_chany_top_out ;
wire [0:0] sb_12__1__3_ccff_tail ;
wire [0:19] sb_12__1__3_chanx_left_out ;
wire [0:19] sb_12__1__3_chany_bottom_out ;
wire [0:19] sb_12__1__3_chany_top_out ;
wire [0:0] sb_12__1__4_ccff_tail ;
wire [0:19] sb_12__1__4_chanx_left_out ;
wire [0:19] sb_12__1__4_chany_bottom_out ;
wire [0:19] sb_12__1__4_chany_top_out ;
wire [0:0] sb_12__1__5_ccff_tail ;
wire [0:19] sb_12__1__5_chanx_left_out ;
wire [0:19] sb_12__1__5_chany_bottom_out ;
wire [0:19] sb_12__1__5_chany_top_out ;
wire [0:0] sb_12__1__6_ccff_tail ;
wire [0:19] sb_12__1__6_chanx_left_out ;
wire [0:19] sb_12__1__6_chany_bottom_out ;
wire [0:19] sb_12__1__6_chany_top_out ;
wire [0:0] sb_12__1__7_ccff_tail ;
wire [0:19] sb_12__1__7_chanx_left_out ;
wire [0:19] sb_12__1__7_chany_bottom_out ;
wire [0:19] sb_12__1__7_chany_top_out ;
wire [0:0] sb_12__1__8_ccff_tail ;
wire [0:19] sb_12__1__8_chanx_left_out ;
wire [0:19] sb_12__1__8_chany_bottom_out ;
wire [0:19] sb_12__1__8_chany_top_out ;
wire [0:0] sb_12__1__9_ccff_tail ;
wire [0:19] sb_12__1__9_chanx_left_out ;
wire [0:19] sb_12__1__9_chany_bottom_out ;
wire [0:19] sb_12__1__9_chany_top_out ;
wire [0:0] sb_1__0__0_ccff_tail ;
wire [0:19] sb_1__0__0_chanx_left_out ;
wire [0:19] sb_1__0__0_chanx_right_out ;
wire [0:19] sb_1__0__0_chany_top_out ;
wire [0:0] sb_1__0__10_ccff_tail ;
wire [0:19] sb_1__0__10_chanx_left_out ;
wire [0:19] sb_1__0__10_chanx_right_out ;
wire [0:19] sb_1__0__10_chany_top_out ;
wire [0:0] sb_1__0__1_ccff_tail ;
wire [0:19] sb_1__0__1_chanx_left_out ;
wire [0:19] sb_1__0__1_chanx_right_out ;
wire [0:19] sb_1__0__1_chany_top_out ;
wire [0:0] sb_1__0__2_ccff_tail ;
wire [0:19] sb_1__0__2_chanx_left_out ;
wire [0:19] sb_1__0__2_chanx_right_out ;
wire [0:19] sb_1__0__2_chany_top_out ;
wire [0:0] sb_1__0__3_ccff_tail ;
wire [0:19] sb_1__0__3_chanx_left_out ;
wire [0:19] sb_1__0__3_chanx_right_out ;
wire [0:19] sb_1__0__3_chany_top_out ;
wire [0:0] sb_1__0__4_ccff_tail ;
wire [0:19] sb_1__0__4_chanx_left_out ;
wire [0:19] sb_1__0__4_chanx_right_out ;
wire [0:19] sb_1__0__4_chany_top_out ;
wire [0:0] sb_1__0__5_ccff_tail ;
wire [0:19] sb_1__0__5_chanx_left_out ;
wire [0:19] sb_1__0__5_chanx_right_out ;
wire [0:19] sb_1__0__5_chany_top_out ;
wire [0:0] sb_1__0__6_ccff_tail ;
wire [0:19] sb_1__0__6_chanx_left_out ;
wire [0:19] sb_1__0__6_chanx_right_out ;
wire [0:19] sb_1__0__6_chany_top_out ;
wire [0:0] sb_1__0__7_ccff_tail ;
wire [0:19] sb_1__0__7_chanx_left_out ;
wire [0:19] sb_1__0__7_chanx_right_out ;
wire [0:19] sb_1__0__7_chany_top_out ;
wire [0:0] sb_1__0__8_ccff_tail ;
wire [0:19] sb_1__0__8_chanx_left_out ;
wire [0:19] sb_1__0__8_chanx_right_out ;
wire [0:19] sb_1__0__8_chany_top_out ;
wire [0:0] sb_1__0__9_ccff_tail ;
wire [0:19] sb_1__0__9_chanx_left_out ;
wire [0:19] sb_1__0__9_chanx_right_out ;
wire [0:19] sb_1__0__9_chany_top_out ;
wire [0:0] sb_1__12__0_ccff_tail ;
wire [0:19] sb_1__12__0_chanx_left_out ;
wire [0:19] sb_1__12__0_chanx_right_out ;
wire [0:19] sb_1__12__0_chany_bottom_out ;
wire [0:0] sb_1__12__10_ccff_tail ;
wire [0:19] sb_1__12__10_chanx_left_out ;
wire [0:19] sb_1__12__10_chanx_right_out ;
wire [0:19] sb_1__12__10_chany_bottom_out ;
wire [0:0] sb_1__12__1_ccff_tail ;
wire [0:19] sb_1__12__1_chanx_left_out ;
wire [0:19] sb_1__12__1_chanx_right_out ;
wire [0:19] sb_1__12__1_chany_bottom_out ;
wire [0:0] sb_1__12__2_ccff_tail ;
wire [0:19] sb_1__12__2_chanx_left_out ;
wire [0:19] sb_1__12__2_chanx_right_out ;
wire [0:19] sb_1__12__2_chany_bottom_out ;
wire [0:0] sb_1__12__3_ccff_tail ;
wire [0:19] sb_1__12__3_chanx_left_out ;
wire [0:19] sb_1__12__3_chanx_right_out ;
wire [0:19] sb_1__12__3_chany_bottom_out ;
wire [0:0] sb_1__12__4_ccff_tail ;
wire [0:19] sb_1__12__4_chanx_left_out ;
wire [0:19] sb_1__12__4_chanx_right_out ;
wire [0:19] sb_1__12__4_chany_bottom_out ;
wire [0:0] sb_1__12__5_ccff_tail ;
wire [0:19] sb_1__12__5_chanx_left_out ;
wire [0:19] sb_1__12__5_chanx_right_out ;
wire [0:19] sb_1__12__5_chany_bottom_out ;
wire [0:0] sb_1__12__6_ccff_tail ;
wire [0:19] sb_1__12__6_chanx_left_out ;
wire [0:19] sb_1__12__6_chanx_right_out ;
wire [0:19] sb_1__12__6_chany_bottom_out ;
wire [0:0] sb_1__12__7_ccff_tail ;
wire [0:19] sb_1__12__7_chanx_left_out ;
wire [0:19] sb_1__12__7_chanx_right_out ;
wire [0:19] sb_1__12__7_chany_bottom_out ;
wire [0:0] sb_1__12__8_ccff_tail ;
wire [0:19] sb_1__12__8_chanx_left_out ;
wire [0:19] sb_1__12__8_chanx_right_out ;
wire [0:19] sb_1__12__8_chany_bottom_out ;
wire [0:0] sb_1__12__9_ccff_tail ;
wire [0:19] sb_1__12__9_chanx_left_out ;
wire [0:19] sb_1__12__9_chanx_right_out ;
wire [0:19] sb_1__12__9_chany_bottom_out ;
wire [0:0] sb_1__1__0_ccff_tail ;
wire [0:19] sb_1__1__0_chanx_left_out ;
wire [0:19] sb_1__1__0_chanx_right_out ;
wire [0:19] sb_1__1__0_chany_bottom_out ;
wire [0:19] sb_1__1__0_chany_top_out ;
wire [0:0] sb_1__1__100_ccff_tail ;
wire [0:19] sb_1__1__100_chanx_left_out ;
wire [0:19] sb_1__1__100_chanx_right_out ;
wire [0:19] sb_1__1__100_chany_bottom_out ;
wire [0:19] sb_1__1__100_chany_top_out ;
wire [0:0] sb_1__1__101_ccff_tail ;
wire [0:19] sb_1__1__101_chanx_left_out ;
wire [0:19] sb_1__1__101_chanx_right_out ;
wire [0:19] sb_1__1__101_chany_bottom_out ;
wire [0:19] sb_1__1__101_chany_top_out ;
wire [0:0] sb_1__1__102_ccff_tail ;
wire [0:19] sb_1__1__102_chanx_left_out ;
wire [0:19] sb_1__1__102_chanx_right_out ;
wire [0:19] sb_1__1__102_chany_bottom_out ;
wire [0:19] sb_1__1__102_chany_top_out ;
wire [0:0] sb_1__1__103_ccff_tail ;
wire [0:19] sb_1__1__103_chanx_left_out ;
wire [0:19] sb_1__1__103_chanx_right_out ;
wire [0:19] sb_1__1__103_chany_bottom_out ;
wire [0:19] sb_1__1__103_chany_top_out ;
wire [0:0] sb_1__1__104_ccff_tail ;
wire [0:19] sb_1__1__104_chanx_left_out ;
wire [0:19] sb_1__1__104_chanx_right_out ;
wire [0:19] sb_1__1__104_chany_bottom_out ;
wire [0:19] sb_1__1__104_chany_top_out ;
wire [0:0] sb_1__1__105_ccff_tail ;
wire [0:19] sb_1__1__105_chanx_left_out ;
wire [0:19] sb_1__1__105_chanx_right_out ;
wire [0:19] sb_1__1__105_chany_bottom_out ;
wire [0:19] sb_1__1__105_chany_top_out ;
wire [0:0] sb_1__1__106_ccff_tail ;
wire [0:19] sb_1__1__106_chanx_left_out ;
wire [0:19] sb_1__1__106_chanx_right_out ;
wire [0:19] sb_1__1__106_chany_bottom_out ;
wire [0:19] sb_1__1__106_chany_top_out ;
wire [0:0] sb_1__1__107_ccff_tail ;
wire [0:19] sb_1__1__107_chanx_left_out ;
wire [0:19] sb_1__1__107_chanx_right_out ;
wire [0:19] sb_1__1__107_chany_bottom_out ;
wire [0:19] sb_1__1__107_chany_top_out ;
wire [0:0] sb_1__1__108_ccff_tail ;
wire [0:19] sb_1__1__108_chanx_left_out ;
wire [0:19] sb_1__1__108_chanx_right_out ;
wire [0:19] sb_1__1__108_chany_bottom_out ;
wire [0:19] sb_1__1__108_chany_top_out ;
wire [0:0] sb_1__1__109_ccff_tail ;
wire [0:19] sb_1__1__109_chanx_left_out ;
wire [0:19] sb_1__1__109_chanx_right_out ;
wire [0:19] sb_1__1__109_chany_bottom_out ;
wire [0:19] sb_1__1__109_chany_top_out ;
wire [0:0] sb_1__1__10_ccff_tail ;
wire [0:19] sb_1__1__10_chanx_left_out ;
wire [0:19] sb_1__1__10_chanx_right_out ;
wire [0:19] sb_1__1__10_chany_bottom_out ;
wire [0:19] sb_1__1__10_chany_top_out ;
wire [0:0] sb_1__1__110_ccff_tail ;
wire [0:19] sb_1__1__110_chanx_left_out ;
wire [0:19] sb_1__1__110_chanx_right_out ;
wire [0:19] sb_1__1__110_chany_bottom_out ;
wire [0:19] sb_1__1__110_chany_top_out ;
wire [0:0] sb_1__1__111_ccff_tail ;
wire [0:19] sb_1__1__111_chanx_left_out ;
wire [0:19] sb_1__1__111_chanx_right_out ;
wire [0:19] sb_1__1__111_chany_bottom_out ;
wire [0:19] sb_1__1__111_chany_top_out ;
wire [0:0] sb_1__1__112_ccff_tail ;
wire [0:19] sb_1__1__112_chanx_left_out ;
wire [0:19] sb_1__1__112_chanx_right_out ;
wire [0:19] sb_1__1__112_chany_bottom_out ;
wire [0:19] sb_1__1__112_chany_top_out ;
wire [0:0] sb_1__1__113_ccff_tail ;
wire [0:19] sb_1__1__113_chanx_left_out ;
wire [0:19] sb_1__1__113_chanx_right_out ;
wire [0:19] sb_1__1__113_chany_bottom_out ;
wire [0:19] sb_1__1__113_chany_top_out ;
wire [0:0] sb_1__1__114_ccff_tail ;
wire [0:19] sb_1__1__114_chanx_left_out ;
wire [0:19] sb_1__1__114_chanx_right_out ;
wire [0:19] sb_1__1__114_chany_bottom_out ;
wire [0:19] sb_1__1__114_chany_top_out ;
wire [0:0] sb_1__1__115_ccff_tail ;
wire [0:19] sb_1__1__115_chanx_left_out ;
wire [0:19] sb_1__1__115_chanx_right_out ;
wire [0:19] sb_1__1__115_chany_bottom_out ;
wire [0:19] sb_1__1__115_chany_top_out ;
wire [0:0] sb_1__1__116_ccff_tail ;
wire [0:19] sb_1__1__116_chanx_left_out ;
wire [0:19] sb_1__1__116_chanx_right_out ;
wire [0:19] sb_1__1__116_chany_bottom_out ;
wire [0:19] sb_1__1__116_chany_top_out ;
wire [0:0] sb_1__1__117_ccff_tail ;
wire [0:19] sb_1__1__117_chanx_left_out ;
wire [0:19] sb_1__1__117_chanx_right_out ;
wire [0:19] sb_1__1__117_chany_bottom_out ;
wire [0:19] sb_1__1__117_chany_top_out ;
wire [0:0] sb_1__1__118_ccff_tail ;
wire [0:19] sb_1__1__118_chanx_left_out ;
wire [0:19] sb_1__1__118_chanx_right_out ;
wire [0:19] sb_1__1__118_chany_bottom_out ;
wire [0:19] sb_1__1__118_chany_top_out ;
wire [0:0] sb_1__1__119_ccff_tail ;
wire [0:19] sb_1__1__119_chanx_left_out ;
wire [0:19] sb_1__1__119_chanx_right_out ;
wire [0:19] sb_1__1__119_chany_bottom_out ;
wire [0:19] sb_1__1__119_chany_top_out ;
wire [0:0] sb_1__1__11_ccff_tail ;
wire [0:19] sb_1__1__11_chanx_left_out ;
wire [0:19] sb_1__1__11_chanx_right_out ;
wire [0:19] sb_1__1__11_chany_bottom_out ;
wire [0:19] sb_1__1__11_chany_top_out ;
wire [0:0] sb_1__1__120_ccff_tail ;
wire [0:19] sb_1__1__120_chanx_left_out ;
wire [0:19] sb_1__1__120_chanx_right_out ;
wire [0:19] sb_1__1__120_chany_bottom_out ;
wire [0:19] sb_1__1__120_chany_top_out ;
wire [0:0] sb_1__1__12_ccff_tail ;
wire [0:19] sb_1__1__12_chanx_left_out ;
wire [0:19] sb_1__1__12_chanx_right_out ;
wire [0:19] sb_1__1__12_chany_bottom_out ;
wire [0:19] sb_1__1__12_chany_top_out ;
wire [0:0] sb_1__1__13_ccff_tail ;
wire [0:19] sb_1__1__13_chanx_left_out ;
wire [0:19] sb_1__1__13_chanx_right_out ;
wire [0:19] sb_1__1__13_chany_bottom_out ;
wire [0:19] sb_1__1__13_chany_top_out ;
wire [0:0] sb_1__1__14_ccff_tail ;
wire [0:19] sb_1__1__14_chanx_left_out ;
wire [0:19] sb_1__1__14_chanx_right_out ;
wire [0:19] sb_1__1__14_chany_bottom_out ;
wire [0:19] sb_1__1__14_chany_top_out ;
wire [0:0] sb_1__1__15_ccff_tail ;
wire [0:19] sb_1__1__15_chanx_left_out ;
wire [0:19] sb_1__1__15_chanx_right_out ;
wire [0:19] sb_1__1__15_chany_bottom_out ;
wire [0:19] sb_1__1__15_chany_top_out ;
wire [0:0] sb_1__1__16_ccff_tail ;
wire [0:19] sb_1__1__16_chanx_left_out ;
wire [0:19] sb_1__1__16_chanx_right_out ;
wire [0:19] sb_1__1__16_chany_bottom_out ;
wire [0:19] sb_1__1__16_chany_top_out ;
wire [0:0] sb_1__1__17_ccff_tail ;
wire [0:19] sb_1__1__17_chanx_left_out ;
wire [0:19] sb_1__1__17_chanx_right_out ;
wire [0:19] sb_1__1__17_chany_bottom_out ;
wire [0:19] sb_1__1__17_chany_top_out ;
wire [0:0] sb_1__1__18_ccff_tail ;
wire [0:19] sb_1__1__18_chanx_left_out ;
wire [0:19] sb_1__1__18_chanx_right_out ;
wire [0:19] sb_1__1__18_chany_bottom_out ;
wire [0:19] sb_1__1__18_chany_top_out ;
wire [0:0] sb_1__1__19_ccff_tail ;
wire [0:19] sb_1__1__19_chanx_left_out ;
wire [0:19] sb_1__1__19_chanx_right_out ;
wire [0:19] sb_1__1__19_chany_bottom_out ;
wire [0:19] sb_1__1__19_chany_top_out ;
wire [0:0] sb_1__1__1_ccff_tail ;
wire [0:19] sb_1__1__1_chanx_left_out ;
wire [0:19] sb_1__1__1_chanx_right_out ;
wire [0:19] sb_1__1__1_chany_bottom_out ;
wire [0:19] sb_1__1__1_chany_top_out ;
wire [0:0] sb_1__1__20_ccff_tail ;
wire [0:19] sb_1__1__20_chanx_left_out ;
wire [0:19] sb_1__1__20_chanx_right_out ;
wire [0:19] sb_1__1__20_chany_bottom_out ;
wire [0:19] sb_1__1__20_chany_top_out ;
wire [0:0] sb_1__1__21_ccff_tail ;
wire [0:19] sb_1__1__21_chanx_left_out ;
wire [0:19] sb_1__1__21_chanx_right_out ;
wire [0:19] sb_1__1__21_chany_bottom_out ;
wire [0:19] sb_1__1__21_chany_top_out ;
wire [0:0] sb_1__1__22_ccff_tail ;
wire [0:19] sb_1__1__22_chanx_left_out ;
wire [0:19] sb_1__1__22_chanx_right_out ;
wire [0:19] sb_1__1__22_chany_bottom_out ;
wire [0:19] sb_1__1__22_chany_top_out ;
wire [0:0] sb_1__1__23_ccff_tail ;
wire [0:19] sb_1__1__23_chanx_left_out ;
wire [0:19] sb_1__1__23_chanx_right_out ;
wire [0:19] sb_1__1__23_chany_bottom_out ;
wire [0:19] sb_1__1__23_chany_top_out ;
wire [0:0] sb_1__1__24_ccff_tail ;
wire [0:19] sb_1__1__24_chanx_left_out ;
wire [0:19] sb_1__1__24_chanx_right_out ;
wire [0:19] sb_1__1__24_chany_bottom_out ;
wire [0:19] sb_1__1__24_chany_top_out ;
wire [0:0] sb_1__1__25_ccff_tail ;
wire [0:19] sb_1__1__25_chanx_left_out ;
wire [0:19] sb_1__1__25_chanx_right_out ;
wire [0:19] sb_1__1__25_chany_bottom_out ;
wire [0:19] sb_1__1__25_chany_top_out ;
wire [0:0] sb_1__1__26_ccff_tail ;
wire [0:19] sb_1__1__26_chanx_left_out ;
wire [0:19] sb_1__1__26_chanx_right_out ;
wire [0:19] sb_1__1__26_chany_bottom_out ;
wire [0:19] sb_1__1__26_chany_top_out ;
wire [0:0] sb_1__1__27_ccff_tail ;
wire [0:19] sb_1__1__27_chanx_left_out ;
wire [0:19] sb_1__1__27_chanx_right_out ;
wire [0:19] sb_1__1__27_chany_bottom_out ;
wire [0:19] sb_1__1__27_chany_top_out ;
wire [0:0] sb_1__1__28_ccff_tail ;
wire [0:19] sb_1__1__28_chanx_left_out ;
wire [0:19] sb_1__1__28_chanx_right_out ;
wire [0:19] sb_1__1__28_chany_bottom_out ;
wire [0:19] sb_1__1__28_chany_top_out ;
wire [0:0] sb_1__1__29_ccff_tail ;
wire [0:19] sb_1__1__29_chanx_left_out ;
wire [0:19] sb_1__1__29_chanx_right_out ;
wire [0:19] sb_1__1__29_chany_bottom_out ;
wire [0:19] sb_1__1__29_chany_top_out ;
wire [0:0] sb_1__1__2_ccff_tail ;
wire [0:19] sb_1__1__2_chanx_left_out ;
wire [0:19] sb_1__1__2_chanx_right_out ;
wire [0:19] sb_1__1__2_chany_bottom_out ;
wire [0:19] sb_1__1__2_chany_top_out ;
wire [0:0] sb_1__1__30_ccff_tail ;
wire [0:19] sb_1__1__30_chanx_left_out ;
wire [0:19] sb_1__1__30_chanx_right_out ;
wire [0:19] sb_1__1__30_chany_bottom_out ;
wire [0:19] sb_1__1__30_chany_top_out ;
wire [0:0] sb_1__1__31_ccff_tail ;
wire [0:19] sb_1__1__31_chanx_left_out ;
wire [0:19] sb_1__1__31_chanx_right_out ;
wire [0:19] sb_1__1__31_chany_bottom_out ;
wire [0:19] sb_1__1__31_chany_top_out ;
wire [0:0] sb_1__1__32_ccff_tail ;
wire [0:19] sb_1__1__32_chanx_left_out ;
wire [0:19] sb_1__1__32_chanx_right_out ;
wire [0:19] sb_1__1__32_chany_bottom_out ;
wire [0:19] sb_1__1__32_chany_top_out ;
wire [0:0] sb_1__1__33_ccff_tail ;
wire [0:19] sb_1__1__33_chanx_left_out ;
wire [0:19] sb_1__1__33_chanx_right_out ;
wire [0:19] sb_1__1__33_chany_bottom_out ;
wire [0:19] sb_1__1__33_chany_top_out ;
wire [0:0] sb_1__1__34_ccff_tail ;
wire [0:19] sb_1__1__34_chanx_left_out ;
wire [0:19] sb_1__1__34_chanx_right_out ;
wire [0:19] sb_1__1__34_chany_bottom_out ;
wire [0:19] sb_1__1__34_chany_top_out ;
wire [0:0] sb_1__1__35_ccff_tail ;
wire [0:19] sb_1__1__35_chanx_left_out ;
wire [0:19] sb_1__1__35_chanx_right_out ;
wire [0:19] sb_1__1__35_chany_bottom_out ;
wire [0:19] sb_1__1__35_chany_top_out ;
wire [0:0] sb_1__1__36_ccff_tail ;
wire [0:19] sb_1__1__36_chanx_left_out ;
wire [0:19] sb_1__1__36_chanx_right_out ;
wire [0:19] sb_1__1__36_chany_bottom_out ;
wire [0:19] sb_1__1__36_chany_top_out ;
wire [0:0] sb_1__1__37_ccff_tail ;
wire [0:19] sb_1__1__37_chanx_left_out ;
wire [0:19] sb_1__1__37_chanx_right_out ;
wire [0:19] sb_1__1__37_chany_bottom_out ;
wire [0:19] sb_1__1__37_chany_top_out ;
wire [0:0] sb_1__1__38_ccff_tail ;
wire [0:19] sb_1__1__38_chanx_left_out ;
wire [0:19] sb_1__1__38_chanx_right_out ;
wire [0:19] sb_1__1__38_chany_bottom_out ;
wire [0:19] sb_1__1__38_chany_top_out ;
wire [0:0] sb_1__1__39_ccff_tail ;
wire [0:19] sb_1__1__39_chanx_left_out ;
wire [0:19] sb_1__1__39_chanx_right_out ;
wire [0:19] sb_1__1__39_chany_bottom_out ;
wire [0:19] sb_1__1__39_chany_top_out ;
wire [0:0] sb_1__1__3_ccff_tail ;
wire [0:19] sb_1__1__3_chanx_left_out ;
wire [0:19] sb_1__1__3_chanx_right_out ;
wire [0:19] sb_1__1__3_chany_bottom_out ;
wire [0:19] sb_1__1__3_chany_top_out ;
wire [0:0] sb_1__1__40_ccff_tail ;
wire [0:19] sb_1__1__40_chanx_left_out ;
wire [0:19] sb_1__1__40_chanx_right_out ;
wire [0:19] sb_1__1__40_chany_bottom_out ;
wire [0:19] sb_1__1__40_chany_top_out ;
wire [0:0] sb_1__1__41_ccff_tail ;
wire [0:19] sb_1__1__41_chanx_left_out ;
wire [0:19] sb_1__1__41_chanx_right_out ;
wire [0:19] sb_1__1__41_chany_bottom_out ;
wire [0:19] sb_1__1__41_chany_top_out ;
wire [0:0] sb_1__1__42_ccff_tail ;
wire [0:19] sb_1__1__42_chanx_left_out ;
wire [0:19] sb_1__1__42_chanx_right_out ;
wire [0:19] sb_1__1__42_chany_bottom_out ;
wire [0:19] sb_1__1__42_chany_top_out ;
wire [0:0] sb_1__1__43_ccff_tail ;
wire [0:19] sb_1__1__43_chanx_left_out ;
wire [0:19] sb_1__1__43_chanx_right_out ;
wire [0:19] sb_1__1__43_chany_bottom_out ;
wire [0:19] sb_1__1__43_chany_top_out ;
wire [0:0] sb_1__1__44_ccff_tail ;
wire [0:19] sb_1__1__44_chanx_left_out ;
wire [0:19] sb_1__1__44_chanx_right_out ;
wire [0:19] sb_1__1__44_chany_bottom_out ;
wire [0:19] sb_1__1__44_chany_top_out ;
wire [0:0] sb_1__1__45_ccff_tail ;
wire [0:19] sb_1__1__45_chanx_left_out ;
wire [0:19] sb_1__1__45_chanx_right_out ;
wire [0:19] sb_1__1__45_chany_bottom_out ;
wire [0:19] sb_1__1__45_chany_top_out ;
wire [0:0] sb_1__1__46_ccff_tail ;
wire [0:19] sb_1__1__46_chanx_left_out ;
wire [0:19] sb_1__1__46_chanx_right_out ;
wire [0:19] sb_1__1__46_chany_bottom_out ;
wire [0:19] sb_1__1__46_chany_top_out ;
wire [0:0] sb_1__1__47_ccff_tail ;
wire [0:19] sb_1__1__47_chanx_left_out ;
wire [0:19] sb_1__1__47_chanx_right_out ;
wire [0:19] sb_1__1__47_chany_bottom_out ;
wire [0:19] sb_1__1__47_chany_top_out ;
wire [0:0] sb_1__1__48_ccff_tail ;
wire [0:19] sb_1__1__48_chanx_left_out ;
wire [0:19] sb_1__1__48_chanx_right_out ;
wire [0:19] sb_1__1__48_chany_bottom_out ;
wire [0:19] sb_1__1__48_chany_top_out ;
wire [0:0] sb_1__1__49_ccff_tail ;
wire [0:19] sb_1__1__49_chanx_left_out ;
wire [0:19] sb_1__1__49_chanx_right_out ;
wire [0:19] sb_1__1__49_chany_bottom_out ;
wire [0:19] sb_1__1__49_chany_top_out ;
wire [0:0] sb_1__1__4_ccff_tail ;
wire [0:19] sb_1__1__4_chanx_left_out ;
wire [0:19] sb_1__1__4_chanx_right_out ;
wire [0:19] sb_1__1__4_chany_bottom_out ;
wire [0:19] sb_1__1__4_chany_top_out ;
wire [0:0] sb_1__1__50_ccff_tail ;
wire [0:19] sb_1__1__50_chanx_left_out ;
wire [0:19] sb_1__1__50_chanx_right_out ;
wire [0:19] sb_1__1__50_chany_bottom_out ;
wire [0:19] sb_1__1__50_chany_top_out ;
wire [0:0] sb_1__1__51_ccff_tail ;
wire [0:19] sb_1__1__51_chanx_left_out ;
wire [0:19] sb_1__1__51_chanx_right_out ;
wire [0:19] sb_1__1__51_chany_bottom_out ;
wire [0:19] sb_1__1__51_chany_top_out ;
wire [0:0] sb_1__1__52_ccff_tail ;
wire [0:19] sb_1__1__52_chanx_left_out ;
wire [0:19] sb_1__1__52_chanx_right_out ;
wire [0:19] sb_1__1__52_chany_bottom_out ;
wire [0:19] sb_1__1__52_chany_top_out ;
wire [0:0] sb_1__1__53_ccff_tail ;
wire [0:19] sb_1__1__53_chanx_left_out ;
wire [0:19] sb_1__1__53_chanx_right_out ;
wire [0:19] sb_1__1__53_chany_bottom_out ;
wire [0:19] sb_1__1__53_chany_top_out ;
wire [0:0] sb_1__1__54_ccff_tail ;
wire [0:19] sb_1__1__54_chanx_left_out ;
wire [0:19] sb_1__1__54_chanx_right_out ;
wire [0:19] sb_1__1__54_chany_bottom_out ;
wire [0:19] sb_1__1__54_chany_top_out ;
wire [0:0] sb_1__1__55_ccff_tail ;
wire [0:19] sb_1__1__55_chanx_left_out ;
wire [0:19] sb_1__1__55_chanx_right_out ;
wire [0:19] sb_1__1__55_chany_bottom_out ;
wire [0:19] sb_1__1__55_chany_top_out ;
wire [0:0] sb_1__1__56_ccff_tail ;
wire [0:19] sb_1__1__56_chanx_left_out ;
wire [0:19] sb_1__1__56_chanx_right_out ;
wire [0:19] sb_1__1__56_chany_bottom_out ;
wire [0:19] sb_1__1__56_chany_top_out ;
wire [0:0] sb_1__1__57_ccff_tail ;
wire [0:19] sb_1__1__57_chanx_left_out ;
wire [0:19] sb_1__1__57_chanx_right_out ;
wire [0:19] sb_1__1__57_chany_bottom_out ;
wire [0:19] sb_1__1__57_chany_top_out ;
wire [0:0] sb_1__1__58_ccff_tail ;
wire [0:19] sb_1__1__58_chanx_left_out ;
wire [0:19] sb_1__1__58_chanx_right_out ;
wire [0:19] sb_1__1__58_chany_bottom_out ;
wire [0:19] sb_1__1__58_chany_top_out ;
wire [0:0] sb_1__1__59_ccff_tail ;
wire [0:19] sb_1__1__59_chanx_left_out ;
wire [0:19] sb_1__1__59_chanx_right_out ;
wire [0:19] sb_1__1__59_chany_bottom_out ;
wire [0:19] sb_1__1__59_chany_top_out ;
wire [0:0] sb_1__1__5_ccff_tail ;
wire [0:19] sb_1__1__5_chanx_left_out ;
wire [0:19] sb_1__1__5_chanx_right_out ;
wire [0:19] sb_1__1__5_chany_bottom_out ;
wire [0:19] sb_1__1__5_chany_top_out ;
wire [0:0] sb_1__1__60_ccff_tail ;
wire [0:19] sb_1__1__60_chanx_left_out ;
wire [0:19] sb_1__1__60_chanx_right_out ;
wire [0:19] sb_1__1__60_chany_bottom_out ;
wire [0:19] sb_1__1__60_chany_top_out ;
wire [0:0] sb_1__1__61_ccff_tail ;
wire [0:19] sb_1__1__61_chanx_left_out ;
wire [0:19] sb_1__1__61_chanx_right_out ;
wire [0:19] sb_1__1__61_chany_bottom_out ;
wire [0:19] sb_1__1__61_chany_top_out ;
wire [0:0] sb_1__1__62_ccff_tail ;
wire [0:19] sb_1__1__62_chanx_left_out ;
wire [0:19] sb_1__1__62_chanx_right_out ;
wire [0:19] sb_1__1__62_chany_bottom_out ;
wire [0:19] sb_1__1__62_chany_top_out ;
wire [0:0] sb_1__1__63_ccff_tail ;
wire [0:19] sb_1__1__63_chanx_left_out ;
wire [0:19] sb_1__1__63_chanx_right_out ;
wire [0:19] sb_1__1__63_chany_bottom_out ;
wire [0:19] sb_1__1__63_chany_top_out ;
wire [0:0] sb_1__1__64_ccff_tail ;
wire [0:19] sb_1__1__64_chanx_left_out ;
wire [0:19] sb_1__1__64_chanx_right_out ;
wire [0:19] sb_1__1__64_chany_bottom_out ;
wire [0:19] sb_1__1__64_chany_top_out ;
wire [0:0] sb_1__1__65_ccff_tail ;
wire [0:19] sb_1__1__65_chanx_left_out ;
wire [0:19] sb_1__1__65_chanx_right_out ;
wire [0:19] sb_1__1__65_chany_bottom_out ;
wire [0:19] sb_1__1__65_chany_top_out ;
wire [0:0] sb_1__1__66_ccff_tail ;
wire [0:19] sb_1__1__66_chanx_left_out ;
wire [0:19] sb_1__1__66_chanx_right_out ;
wire [0:19] sb_1__1__66_chany_bottom_out ;
wire [0:19] sb_1__1__66_chany_top_out ;
wire [0:0] sb_1__1__67_ccff_tail ;
wire [0:19] sb_1__1__67_chanx_left_out ;
wire [0:19] sb_1__1__67_chanx_right_out ;
wire [0:19] sb_1__1__67_chany_bottom_out ;
wire [0:19] sb_1__1__67_chany_top_out ;
wire [0:0] sb_1__1__68_ccff_tail ;
wire [0:19] sb_1__1__68_chanx_left_out ;
wire [0:19] sb_1__1__68_chanx_right_out ;
wire [0:19] sb_1__1__68_chany_bottom_out ;
wire [0:19] sb_1__1__68_chany_top_out ;
wire [0:0] sb_1__1__69_ccff_tail ;
wire [0:19] sb_1__1__69_chanx_left_out ;
wire [0:19] sb_1__1__69_chanx_right_out ;
wire [0:19] sb_1__1__69_chany_bottom_out ;
wire [0:19] sb_1__1__69_chany_top_out ;
wire [0:0] sb_1__1__6_ccff_tail ;
wire [0:19] sb_1__1__6_chanx_left_out ;
wire [0:19] sb_1__1__6_chanx_right_out ;
wire [0:19] sb_1__1__6_chany_bottom_out ;
wire [0:19] sb_1__1__6_chany_top_out ;
wire [0:0] sb_1__1__70_ccff_tail ;
wire [0:19] sb_1__1__70_chanx_left_out ;
wire [0:19] sb_1__1__70_chanx_right_out ;
wire [0:19] sb_1__1__70_chany_bottom_out ;
wire [0:19] sb_1__1__70_chany_top_out ;
wire [0:0] sb_1__1__71_ccff_tail ;
wire [0:19] sb_1__1__71_chanx_left_out ;
wire [0:19] sb_1__1__71_chanx_right_out ;
wire [0:19] sb_1__1__71_chany_bottom_out ;
wire [0:19] sb_1__1__71_chany_top_out ;
wire [0:0] sb_1__1__72_ccff_tail ;
wire [0:19] sb_1__1__72_chanx_left_out ;
wire [0:19] sb_1__1__72_chanx_right_out ;
wire [0:19] sb_1__1__72_chany_bottom_out ;
wire [0:19] sb_1__1__72_chany_top_out ;
wire [0:0] sb_1__1__73_ccff_tail ;
wire [0:19] sb_1__1__73_chanx_left_out ;
wire [0:19] sb_1__1__73_chanx_right_out ;
wire [0:19] sb_1__1__73_chany_bottom_out ;
wire [0:19] sb_1__1__73_chany_top_out ;
wire [0:0] sb_1__1__74_ccff_tail ;
wire [0:19] sb_1__1__74_chanx_left_out ;
wire [0:19] sb_1__1__74_chanx_right_out ;
wire [0:19] sb_1__1__74_chany_bottom_out ;
wire [0:19] sb_1__1__74_chany_top_out ;
wire [0:0] sb_1__1__75_ccff_tail ;
wire [0:19] sb_1__1__75_chanx_left_out ;
wire [0:19] sb_1__1__75_chanx_right_out ;
wire [0:19] sb_1__1__75_chany_bottom_out ;
wire [0:19] sb_1__1__75_chany_top_out ;
wire [0:0] sb_1__1__76_ccff_tail ;
wire [0:19] sb_1__1__76_chanx_left_out ;
wire [0:19] sb_1__1__76_chanx_right_out ;
wire [0:19] sb_1__1__76_chany_bottom_out ;
wire [0:19] sb_1__1__76_chany_top_out ;
wire [0:0] sb_1__1__77_ccff_tail ;
wire [0:19] sb_1__1__77_chanx_left_out ;
wire [0:19] sb_1__1__77_chanx_right_out ;
wire [0:19] sb_1__1__77_chany_bottom_out ;
wire [0:19] sb_1__1__77_chany_top_out ;
wire [0:0] sb_1__1__78_ccff_tail ;
wire [0:19] sb_1__1__78_chanx_left_out ;
wire [0:19] sb_1__1__78_chanx_right_out ;
wire [0:19] sb_1__1__78_chany_bottom_out ;
wire [0:19] sb_1__1__78_chany_top_out ;
wire [0:0] sb_1__1__79_ccff_tail ;
wire [0:19] sb_1__1__79_chanx_left_out ;
wire [0:19] sb_1__1__79_chanx_right_out ;
wire [0:19] sb_1__1__79_chany_bottom_out ;
wire [0:19] sb_1__1__79_chany_top_out ;
wire [0:0] sb_1__1__7_ccff_tail ;
wire [0:19] sb_1__1__7_chanx_left_out ;
wire [0:19] sb_1__1__7_chanx_right_out ;
wire [0:19] sb_1__1__7_chany_bottom_out ;
wire [0:19] sb_1__1__7_chany_top_out ;
wire [0:0] sb_1__1__80_ccff_tail ;
wire [0:19] sb_1__1__80_chanx_left_out ;
wire [0:19] sb_1__1__80_chanx_right_out ;
wire [0:19] sb_1__1__80_chany_bottom_out ;
wire [0:19] sb_1__1__80_chany_top_out ;
wire [0:0] sb_1__1__81_ccff_tail ;
wire [0:19] sb_1__1__81_chanx_left_out ;
wire [0:19] sb_1__1__81_chanx_right_out ;
wire [0:19] sb_1__1__81_chany_bottom_out ;
wire [0:19] sb_1__1__81_chany_top_out ;
wire [0:0] sb_1__1__82_ccff_tail ;
wire [0:19] sb_1__1__82_chanx_left_out ;
wire [0:19] sb_1__1__82_chanx_right_out ;
wire [0:19] sb_1__1__82_chany_bottom_out ;
wire [0:19] sb_1__1__82_chany_top_out ;
wire [0:0] sb_1__1__83_ccff_tail ;
wire [0:19] sb_1__1__83_chanx_left_out ;
wire [0:19] sb_1__1__83_chanx_right_out ;
wire [0:19] sb_1__1__83_chany_bottom_out ;
wire [0:19] sb_1__1__83_chany_top_out ;
wire [0:0] sb_1__1__84_ccff_tail ;
wire [0:19] sb_1__1__84_chanx_left_out ;
wire [0:19] sb_1__1__84_chanx_right_out ;
wire [0:19] sb_1__1__84_chany_bottom_out ;
wire [0:19] sb_1__1__84_chany_top_out ;
wire [0:0] sb_1__1__85_ccff_tail ;
wire [0:19] sb_1__1__85_chanx_left_out ;
wire [0:19] sb_1__1__85_chanx_right_out ;
wire [0:19] sb_1__1__85_chany_bottom_out ;
wire [0:19] sb_1__1__85_chany_top_out ;
wire [0:0] sb_1__1__86_ccff_tail ;
wire [0:19] sb_1__1__86_chanx_left_out ;
wire [0:19] sb_1__1__86_chanx_right_out ;
wire [0:19] sb_1__1__86_chany_bottom_out ;
wire [0:19] sb_1__1__86_chany_top_out ;
wire [0:0] sb_1__1__87_ccff_tail ;
wire [0:19] sb_1__1__87_chanx_left_out ;
wire [0:19] sb_1__1__87_chanx_right_out ;
wire [0:19] sb_1__1__87_chany_bottom_out ;
wire [0:19] sb_1__1__87_chany_top_out ;
wire [0:0] sb_1__1__88_ccff_tail ;
wire [0:19] sb_1__1__88_chanx_left_out ;
wire [0:19] sb_1__1__88_chanx_right_out ;
wire [0:19] sb_1__1__88_chany_bottom_out ;
wire [0:19] sb_1__1__88_chany_top_out ;
wire [0:0] sb_1__1__89_ccff_tail ;
wire [0:19] sb_1__1__89_chanx_left_out ;
wire [0:19] sb_1__1__89_chanx_right_out ;
wire [0:19] sb_1__1__89_chany_bottom_out ;
wire [0:19] sb_1__1__89_chany_top_out ;
wire [0:0] sb_1__1__8_ccff_tail ;
wire [0:19] sb_1__1__8_chanx_left_out ;
wire [0:19] sb_1__1__8_chanx_right_out ;
wire [0:19] sb_1__1__8_chany_bottom_out ;
wire [0:19] sb_1__1__8_chany_top_out ;
wire [0:0] sb_1__1__90_ccff_tail ;
wire [0:19] sb_1__1__90_chanx_left_out ;
wire [0:19] sb_1__1__90_chanx_right_out ;
wire [0:19] sb_1__1__90_chany_bottom_out ;
wire [0:19] sb_1__1__90_chany_top_out ;
wire [0:0] sb_1__1__91_ccff_tail ;
wire [0:19] sb_1__1__91_chanx_left_out ;
wire [0:19] sb_1__1__91_chanx_right_out ;
wire [0:19] sb_1__1__91_chany_bottom_out ;
wire [0:19] sb_1__1__91_chany_top_out ;
wire [0:0] sb_1__1__92_ccff_tail ;
wire [0:19] sb_1__1__92_chanx_left_out ;
wire [0:19] sb_1__1__92_chanx_right_out ;
wire [0:19] sb_1__1__92_chany_bottom_out ;
wire [0:19] sb_1__1__92_chany_top_out ;
wire [0:0] sb_1__1__93_ccff_tail ;
wire [0:19] sb_1__1__93_chanx_left_out ;
wire [0:19] sb_1__1__93_chanx_right_out ;
wire [0:19] sb_1__1__93_chany_bottom_out ;
wire [0:19] sb_1__1__93_chany_top_out ;
wire [0:0] sb_1__1__94_ccff_tail ;
wire [0:19] sb_1__1__94_chanx_left_out ;
wire [0:19] sb_1__1__94_chanx_right_out ;
wire [0:19] sb_1__1__94_chany_bottom_out ;
wire [0:19] sb_1__1__94_chany_top_out ;
wire [0:0] sb_1__1__95_ccff_tail ;
wire [0:19] sb_1__1__95_chanx_left_out ;
wire [0:19] sb_1__1__95_chanx_right_out ;
wire [0:19] sb_1__1__95_chany_bottom_out ;
wire [0:19] sb_1__1__95_chany_top_out ;
wire [0:0] sb_1__1__96_ccff_tail ;
wire [0:19] sb_1__1__96_chanx_left_out ;
wire [0:19] sb_1__1__96_chanx_right_out ;
wire [0:19] sb_1__1__96_chany_bottom_out ;
wire [0:19] sb_1__1__96_chany_top_out ;
wire [0:0] sb_1__1__97_ccff_tail ;
wire [0:19] sb_1__1__97_chanx_left_out ;
wire [0:19] sb_1__1__97_chanx_right_out ;
wire [0:19] sb_1__1__97_chany_bottom_out ;
wire [0:19] sb_1__1__97_chany_top_out ;
wire [0:0] sb_1__1__98_ccff_tail ;
wire [0:19] sb_1__1__98_chanx_left_out ;
wire [0:19] sb_1__1__98_chanx_right_out ;
wire [0:19] sb_1__1__98_chany_bottom_out ;
wire [0:19] sb_1__1__98_chany_top_out ;
wire [0:0] sb_1__1__99_ccff_tail ;
wire [0:19] sb_1__1__99_chanx_left_out ;
wire [0:19] sb_1__1__99_chanx_right_out ;
wire [0:19] sb_1__1__99_chany_bottom_out ;
wire [0:19] sb_1__1__99_chany_top_out ;
wire [0:0] sb_1__1__9_ccff_tail ;
wire [0:19] sb_1__1__9_chanx_left_out ;
wire [0:19] sb_1__1__9_chanx_right_out ;
wire [0:19] sb_1__1__9_chany_bottom_out ;
wire [0:19] sb_1__1__9_chany_top_out ;
wire [0:0] Test_en__FEEDTHRU_1 ;
wire [0:0] Test_en__FEEDTHRU_2 ;
wire [0:0] Test_en__FEEDTHRU_3 ;
wire [0:0] Test_en__FEEDTHRU_4 ;
wire [0:0] Test_en__FEEDTHRU_5 ;
wire [0:0] Test_en__FEEDTHRU_6 ;
wire [0:0] Test_en__FEEDTHRU_7 ;
wire [0:0] Test_en__FEEDTHRU_8 ;
wire [0:0] Test_en__FEEDTHRU_9 ;
wire [0:0] Test_en__FEEDTHRU_10 ;
wire [0:0] Test_en__FEEDTHRU_11 ;
wire [0:0] Test_en__FEEDTHRU_12 ;
wire [0:0] Test_en__FEEDTHRU_13 ;
wire [0:0] Test_en__FEEDTHRU_14 ;
wire [0:0] Test_en__FEEDTHRU_15 ;
wire [0:0] Test_en__FEEDTHRU_16 ;
wire [0:0] Test_en__FEEDTHRU_17 ;
wire [0:0] Test_en__FEEDTHRU_18 ;
wire [0:0] Test_en__FEEDTHRU_19 ;
wire [0:0] Test_en__FEEDTHRU_20 ;
wire [0:0] Test_en__FEEDTHRU_21 ;
wire [0:0] Test_en__FEEDTHRU_22 ;
wire [0:0] Test_en__FEEDTHRU_23 ;
wire [0:0] Test_en__FEEDTHRU_24 ;
wire [0:0] Test_en__FEEDTHRU_25 ;
wire [0:0] Test_en__FEEDTHRU_26 ;
wire [0:0] Test_en__FEEDTHRU_27 ;
wire [0:0] Test_en__FEEDTHRU_28 ;
wire [0:0] Test_en__FEEDTHRU_29 ;
wire [0:0] Test_en__FEEDTHRU_30 ;
wire [0:0] Test_en__FEEDTHRU_31 ;
wire [0:0] Test_en__FEEDTHRU_32 ;
wire [0:0] Test_en__FEEDTHRU_33 ;
wire [0:0] Test_en__FEEDTHRU_34 ;
wire [0:0] Test_en__FEEDTHRU_35 ;
wire [0:0] Test_en__FEEDTHRU_36 ;
wire [0:0] Test_en__FEEDTHRU_37 ;
wire [0:0] Test_en__FEEDTHRU_38 ;
wire [0:0] Test_en__FEEDTHRU_39 ;
wire [0:0] Test_en__FEEDTHRU_40 ;
wire [0:0] Test_en__FEEDTHRU_41 ;
wire [0:0] Test_en__FEEDTHRU_42 ;
wire [0:0] Test_en__FEEDTHRU_43 ;
wire [0:0] Test_en__FEEDTHRU_44 ;
wire [0:0] Test_en__FEEDTHRU_45 ;
wire [0:0] Test_en__FEEDTHRU_46 ;
wire [0:0] Test_en__FEEDTHRU_47 ;
wire [0:0] Test_en__FEEDTHRU_48 ;
wire [0:0] Test_en__FEEDTHRU_49 ;
wire [0:0] Test_en__FEEDTHRU_50 ;
wire [0:0] Test_en__FEEDTHRU_51 ;
wire [0:0] Test_en__FEEDTHRU_52 ;
wire [0:0] Test_en__FEEDTHRU_53 ;
wire [0:0] Test_en__FEEDTHRU_54 ;
wire [0:0] Test_en__FEEDTHRU_55 ;
wire [0:0] Test_en__FEEDTHRU_56 ;
wire [0:0] Test_en__FEEDTHRU_57 ;
wire [0:0] Test_en__FEEDTHRU_58 ;
wire [0:0] Test_en__FEEDTHRU_59 ;
wire [0:0] Test_en__FEEDTHRU_60 ;
wire [0:0] Test_en__FEEDTHRU_61 ;
wire [0:0] Test_en__FEEDTHRU_62 ;
wire [0:0] Test_en__FEEDTHRU_63 ;
wire [0:0] Test_en__FEEDTHRU_64 ;
wire [0:0] Test_en__FEEDTHRU_65 ;
wire [0:0] Test_en__FEEDTHRU_66 ;
wire [0:0] Test_en__FEEDTHRU_67 ;
wire [0:0] Test_en__FEEDTHRU_68 ;
wire [0:0] Test_en__FEEDTHRU_69 ;
wire [0:0] Test_en__FEEDTHRU_70 ;
wire [0:0] Test_en__FEEDTHRU_71 ;
wire [0:0] Test_en__FEEDTHRU_72 ;
wire [0:0] Test_en__FEEDTHRU_73 ;
wire [0:0] Test_en__FEEDTHRU_74 ;
wire [0:0] Test_en__FEEDTHRU_75 ;
wire [0:0] Test_en__FEEDTHRU_76 ;
wire [0:0] Test_en__FEEDTHRU_77 ;
wire [0:0] Test_en__FEEDTHRU_78 ;
wire [0:0] Test_en__FEEDTHRU_79 ;
wire [0:0] Test_en__FEEDTHRU_80 ;
wire [0:0] Test_en__FEEDTHRU_81 ;
wire [0:0] Test_en__FEEDTHRU_82 ;
wire [0:0] Test_en__FEEDTHRU_83 ;
wire [0:0] Test_en__FEEDTHRU_84 ;
wire [0:0] Test_en__FEEDTHRU_85 ;
wire [0:0] Test_en__FEEDTHRU_86 ;
wire [0:0] Test_en__FEEDTHRU_87 ;
wire [0:0] Test_en__FEEDTHRU_88 ;
wire [0:0] Test_en__FEEDTHRU_89 ;
wire [0:0] Test_en__FEEDTHRU_90 ;
wire [0:0] Test_en__FEEDTHRU_91 ;
wire [0:0] Test_en__FEEDTHRU_92 ;
wire [0:0] Test_en__FEEDTHRU_93 ;
wire [0:0] Test_en__FEEDTHRU_94 ;
wire [0:0] Test_en__FEEDTHRU_95 ;
wire [0:0] Test_en__FEEDTHRU_96 ;
wire [0:0] Test_en__FEEDTHRU_97 ;
wire [0:0] Test_en__FEEDTHRU_98 ;
wire [0:0] Test_en__FEEDTHRU_99 ;
wire [0:0] Test_en__FEEDTHRU_100 ;
wire [0:0] Test_en__FEEDTHRU_101 ;
wire [0:0] Test_en__FEEDTHRU_102 ;
wire [0:0] Test_en__FEEDTHRU_103 ;
wire [0:0] Test_en__FEEDTHRU_104 ;
wire [0:0] Test_en__FEEDTHRU_105 ;
wire [0:0] Test_en__FEEDTHRU_106 ;
wire [0:0] Test_en__FEEDTHRU_107 ;
wire [0:0] Test_en__FEEDTHRU_108 ;
wire [0:0] Test_en__FEEDTHRU_109 ;
wire [0:0] Test_en__FEEDTHRU_110 ;
wire [0:0] Test_en__FEEDTHRU_111 ;
wire [0:0] Test_en__FEEDTHRU_112 ;
wire [0:0] Test_en__FEEDTHRU_113 ;
wire [0:0] Test_en__FEEDTHRU_114 ;
wire [0:0] Test_en__FEEDTHRU_115 ;
wire [0:0] Test_en__FEEDTHRU_116 ;
wire [0:0] Test_en__FEEDTHRU_117 ;
wire [0:0] Test_en__FEEDTHRU_118 ;
wire [0:0] Test_en__FEEDTHRU_119 ;
wire [0:0] Test_en__FEEDTHRU_120 ;
wire [0:0] Test_en__FEEDTHRU_121 ;
wire [0:0] Test_en__FEEDTHRU_122 ;
wire [0:0] Test_en__FEEDTHRU_123 ;
wire [0:0] Test_en__FEEDTHRU_124 ;
wire [0:0] Test_en__FEEDTHRU_125 ;
wire [0:0] Test_en__FEEDTHRU_126 ;
wire [0:0] Test_en__FEEDTHRU_127 ;
wire [0:0] Test_en__FEEDTHRU_128 ;
wire [0:0] Test_en__FEEDTHRU_129 ;
wire [0:0] Test_en__FEEDTHRU_130 ;
wire [0:0] Test_en__FEEDTHRU_131 ;
wire [0:0] Test_en__FEEDTHRU_132 ;
wire [0:0] Test_en__FEEDTHRU_133 ;
wire [0:0] Test_en__FEEDTHRU_134 ;
wire [0:0] Test_en__FEEDTHRU_135 ;
wire [0:0] Test_en__FEEDTHRU_136 ;
wire [0:0] Test_en__FEEDTHRU_137 ;
wire [0:0] Test_en__FEEDTHRU_138 ;
wire [0:0] Test_en__FEEDTHRU_139 ;
wire [0:0] Test_en__FEEDTHRU_140 ;
wire [0:0] Test_en__FEEDTHRU_141 ;
wire [0:0] Test_en__FEEDTHRU_142 ;
wire [0:0] Test_en__FEEDTHRU_143 ;
wire [0:0] Test_en__FEEDTHRU_144 ;
wire [0:0] Test_en__FEEDTHRU_145 ;
wire [0:0] Test_en__FEEDTHRU_146 ;
wire [0:0] Test_en__FEEDTHRU_147 ;
wire [0:0] Test_en__FEEDTHRU_148 ;
wire [0:0] Test_en__FEEDTHRU_149 ;
wire [0:0] Test_en__FEEDTHRU_150 ;
wire [0:0] Test_en__FEEDTHRU_151 ;
wire [0:0] Test_en__FEEDTHRU_152 ;
wire [0:0] Test_en__FEEDTHRU_153 ;
wire [0:0] Test_en__FEEDTHRU_154 ;
wire [0:0] Test_en__FEEDTHRU_155 ;
wire [0:0] Test_en__FEEDTHRU_156 ;
wire [0:0] Test_en__FEEDTHRU_157 ;
wire [0:0] Test_en__FEEDTHRU_158 ;
wire [0:0] Test_en__FEEDTHRU_159 ;
wire [0:0] Test_en__FEEDTHRU_160 ;
wire [0:0] Test_en__FEEDTHRU_161 ;
wire [0:0] Test_en__FEEDTHRU_162 ;
wire [0:0] Test_en__FEEDTHRU_163 ;
wire [0:0] Test_en__FEEDTHRU_164 ;
wire [0:0] Test_en__FEEDTHRU_165 ;
wire [0:0] Test_en__FEEDTHRU_166 ;
wire [0:0] Test_en__FEEDTHRU_167 ;
wire [0:0] Test_en__FEEDTHRU_168 ;
wire [0:0] Test_en__FEEDTHRU_169 ;
wire [0:0] Test_en__FEEDTHRU_170 ;
wire [0:0] Test_en__FEEDTHRU_171 ;
wire [0:0] Test_en__FEEDTHRU_172 ;
wire [0:0] Test_en__FEEDTHRU_173 ;
wire [0:0] Test_en__FEEDTHRU_174 ;
wire [0:0] Test_en__FEEDTHRU_175 ;
wire [0:0] Test_en__FEEDTHRU_176 ;
wire [0:0] Test_en__FEEDTHRU_177 ;
wire [0:0] Test_en__FEEDTHRU_178 ;
wire [0:0] Test_en__FEEDTHRU_179 ;
wire [0:0] Test_en__FEEDTHRU_180 ;
wire [0:0] Test_en__FEEDTHRU_181 ;
wire [0:0] Test_en__FEEDTHRU_182 ;
wire [0:0] Test_en__FEEDTHRU_183 ;
wire [0:0] Test_en__FEEDTHRU_184 ;
wire [0:0] Test_en__FEEDTHRU_185 ;
wire [0:0] Test_en__FEEDTHRU_186 ;
wire [0:0] Test_en__FEEDTHRU_187 ;
wire [0:0] Test_en__FEEDTHRU_188 ;
wire [0:0] Test_en__FEEDTHRU_189 ;
wire [0:0] Test_en__FEEDTHRU_190 ;
wire [0:0] Test_en__FEEDTHRU_191 ;
wire [0:0] Test_en__FEEDTHRU_192 ;
wire [0:0] Test_en__FEEDTHRU_193 ;
wire [0:0] Test_en__FEEDTHRU_194 ;
wire [0:0] Test_en__FEEDTHRU_195 ;
wire [0:0] Test_en__FEEDTHRU_196 ;
wire [0:0] Test_en__FEEDTHRU_197 ;
wire [0:0] Test_en__FEEDTHRU_198 ;
wire [0:0] Test_en__FEEDTHRU_199 ;
wire [0:0] Test_en__FEEDTHRU_200 ;
wire [0:0] Test_en__FEEDTHRU_201 ;
wire [0:0] Test_en__FEEDTHRU_202 ;
wire [0:0] Test_en__FEEDTHRU_203 ;
wire [0:0] Test_en__FEEDTHRU_204 ;
wire [0:0] Test_en__FEEDTHRU_205 ;
wire [0:0] Test_en__FEEDTHRU_206 ;
wire [0:0] Test_en__FEEDTHRU_207 ;
wire [0:0] Test_en__FEEDTHRU_208 ;
wire [0:0] Test_en__FEEDTHRU_209 ;
wire [0:0] Test_en__FEEDTHRU_210 ;
wire [0:0] Test_en__FEEDTHRU_211 ;
wire [0:0] Test_en__FEEDTHRU_212 ;
wire [0:0] Test_en__FEEDTHRU_213 ;
wire [0:0] Test_en__FEEDTHRU_214 ;
wire [0:0] Test_en__FEEDTHRU_215 ;
wire [0:0] Test_en__FEEDTHRU_216 ;
wire [0:0] Test_en__FEEDTHRU_217 ;
wire [0:0] Test_en__FEEDTHRU_218 ;
wire [0:0] Test_en__FEEDTHRU_219 ;
wire [0:0] Test_en__FEEDTHRU_220 ;
wire [0:0] Test_en__FEEDTHRU_221 ;
wire [0:0] Test_en__FEEDTHRU_222 ;
wire [0:0] Test_en__FEEDTHRU_223 ;
wire [0:0] Test_en__FEEDTHRU_224 ;
wire [0:0] Test_en__FEEDTHRU_225 ;
wire [0:0] Test_en__FEEDTHRU_226 ;
wire [0:0] Test_en__FEEDTHRU_227 ;
wire [0:0] Test_en__FEEDTHRU_228 ;
wire [0:0] Test_en__FEEDTHRU_229 ;
wire [0:0] Test_en__FEEDTHRU_230 ;
wire [0:0] Test_en__FEEDTHRU_231 ;
wire [0:0] Test_en__FEEDTHRU_232 ;
wire [0:0] Test_en__FEEDTHRU_233 ;
wire [0:0] Test_en__FEEDTHRU_234 ;
wire [0:0] Test_en__FEEDTHRU_235 ;
wire [0:0] Test_en__FEEDTHRU_236 ;
wire [0:0] Test_en__FEEDTHRU_237 ;
wire [0:0] Test_en__FEEDTHRU_238 ;
wire [0:0] Test_en__FEEDTHRU_239 ;
wire [0:0] Test_en__FEEDTHRU_240 ;
wire [0:0] Test_en__FEEDTHRU_241 ;
wire [0:0] Test_en__FEEDTHRU_242 ;
wire [0:0] Test_en__FEEDTHRU_243 ;
wire [0:0] Test_en__FEEDTHRU_244 ;
wire [0:0] Test_en__FEEDTHRU_245 ;
wire [0:0] Test_en__FEEDTHRU_246 ;
wire [0:0] Test_en__FEEDTHRU_247 ;
wire [0:0] Test_en__FEEDTHRU_248 ;
wire [0:0] Test_en__FEEDTHRU_249 ;
wire [0:0] Test_en__FEEDTHRU_250 ;
wire [0:0] Test_en__FEEDTHRU_251 ;
wire [0:0] Test_en__FEEDTHRU_252 ;
wire [0:0] Test_en__FEEDTHRU_253 ;
wire [0:0] Test_en__FEEDTHRU_254 ;
wire [0:0] Test_en__FEEDTHRU_255 ;
wire [0:0] Test_en__FEEDTHRU_256 ;
wire [0:0] Test_en__FEEDTHRU_257 ;
wire [0:0] Test_en__FEEDTHRU_258 ;
wire [0:0] Test_en__FEEDTHRU_259 ;
wire [0:0] Test_en__FEEDTHRU_260 ;
wire [0:0] Test_en__FEEDTHRU_261 ;
wire [0:0] Test_en__FEEDTHRU_262 ;
wire [0:0] Test_en__FEEDTHRU_263 ;
wire [0:0] Test_en__FEEDTHRU_264 ;
wire [0:0] Test_en__FEEDTHRU_265 ;
wire [0:0] Test_en__FEEDTHRU_266 ;
wire [0:0] Test_en__FEEDTHRU_267 ;
wire [0:0] Test_en__FEEDTHRU_268 ;
wire [0:0] Test_en__FEEDTHRU_269 ;
wire [0:0] Test_en__FEEDTHRU_270 ;
wire [0:0] Test_en__FEEDTHRU_271 ;
wire [0:0] Test_en__FEEDTHRU_272 ;
wire [0:0] Test_en__FEEDTHRU_273 ;
wire [0:0] Test_en__FEEDTHRU_274 ;
wire [0:0] Test_en__FEEDTHRU_275 ;
wire [0:0] Test_en__FEEDTHRU_276 ;
wire [0:0] Test_en__FEEDTHRU_277 ;
wire [0:0] Test_en__FEEDTHRU_278 ;
wire [0:0] Test_en__FEEDTHRU_279 ;
wire [0:0] Test_en__FEEDTHRU_280 ;
wire [0:0] Test_en__FEEDTHRU_281 ;
wire [0:0] Test_en__FEEDTHRU_282 ;
wire [0:0] Test_en__FEEDTHRU_283 ;
wire [0:0] Test_en__FEEDTHRU_284 ;
wire [0:0] Test_en__FEEDTHRU_285 ;
wire [0:0] Test_en__FEEDTHRU_286 ;
wire [0:0] clk__FEEDTHRU_1 ;
wire [0:0] clk__FEEDTHRU_2 ;
wire [0:0] clk__FEEDTHRU_3 ;
wire [0:0] clk__FEEDTHRU_4 ;
wire [0:0] clk__FEEDTHRU_5 ;
wire [0:0] clk__FEEDTHRU_6 ;
wire [0:0] clk__FEEDTHRU_7 ;
wire [0:0] clk__FEEDTHRU_8 ;
wire [0:0] clk__FEEDTHRU_9 ;
wire [0:0] clk__FEEDTHRU_10 ;
wire [0:0] clk__FEEDTHRU_11 ;
wire [0:0] clk__FEEDTHRU_12 ;
wire [0:0] clk__FEEDTHRU_13 ;
wire [0:0] clk__FEEDTHRU_14 ;
wire [0:0] clk__FEEDTHRU_15 ;
wire [0:0] clk__FEEDTHRU_16 ;
wire [0:0] clk__FEEDTHRU_17 ;
wire [0:0] clk__FEEDTHRU_18 ;
wire [0:0] clk__FEEDTHRU_19 ;
wire [0:0] clk__FEEDTHRU_20 ;
wire [0:0] clk__FEEDTHRU_21 ;
wire [0:0] clk__FEEDTHRU_22 ;
wire [0:0] clk__FEEDTHRU_23 ;
wire [0:0] clk__FEEDTHRU_24 ;
wire [0:0] clk__FEEDTHRU_25 ;
wire [0:0] clk__FEEDTHRU_26 ;
wire [0:0] clk__FEEDTHRU_27 ;
wire [0:0] clk__FEEDTHRU_28 ;
wire [0:0] clk__FEEDTHRU_29 ;
wire [0:0] clk__FEEDTHRU_30 ;
wire [0:0] clk__FEEDTHRU_31 ;
wire [0:0] clk__FEEDTHRU_32 ;
wire [0:0] clk__FEEDTHRU_33 ;
wire [0:0] clk__FEEDTHRU_34 ;
wire [0:0] clk__FEEDTHRU_35 ;
wire [0:0] clk__FEEDTHRU_36 ;
wire [0:0] clk__FEEDTHRU_37 ;
wire [0:0] clk__FEEDTHRU_38 ;
wire [0:0] clk__FEEDTHRU_39 ;
wire [0:0] clk__FEEDTHRU_40 ;
wire [0:0] clk__FEEDTHRU_41 ;
wire [0:0] clk__FEEDTHRU_42 ;
wire [0:0] clk__FEEDTHRU_43 ;
wire [0:0] clk__FEEDTHRU_44 ;
wire [0:0] clk__FEEDTHRU_45 ;
wire [0:0] clk__FEEDTHRU_46 ;
wire [0:0] clk__FEEDTHRU_47 ;
wire [0:0] clk__FEEDTHRU_48 ;
wire [0:0] clk__FEEDTHRU_49 ;
wire [0:0] clk__FEEDTHRU_50 ;
wire [0:0] clk__FEEDTHRU_51 ;
wire [0:0] clk__FEEDTHRU_52 ;
wire [0:0] clk__FEEDTHRU_53 ;
wire [0:0] clk__FEEDTHRU_54 ;
wire [0:0] clk__FEEDTHRU_55 ;
wire [0:0] clk__FEEDTHRU_56 ;
wire [0:0] clk__FEEDTHRU_57 ;
wire [0:0] clk__FEEDTHRU_58 ;
wire [0:0] clk__FEEDTHRU_59 ;
wire [0:0] clk__FEEDTHRU_60 ;
wire [0:0] clk__FEEDTHRU_61 ;
wire [0:0] clk__FEEDTHRU_62 ;
wire [0:0] clk__FEEDTHRU_63 ;
wire [0:0] clk__FEEDTHRU_64 ;
wire [0:0] clk__FEEDTHRU_65 ;
wire [0:0] clk__FEEDTHRU_66 ;
wire [0:0] clk__FEEDTHRU_67 ;
wire [0:0] clk__FEEDTHRU_68 ;
wire [0:0] clk__FEEDTHRU_69 ;
wire [0:0] clk__FEEDTHRU_70 ;
wire [0:0] clk__FEEDTHRU_71 ;
wire [0:0] clk__FEEDTHRU_72 ;
wire [0:0] clk__FEEDTHRU_73 ;
wire [0:0] clk__FEEDTHRU_74 ;
wire [0:0] clk__FEEDTHRU_75 ;
wire [0:0] clk__FEEDTHRU_76 ;
wire [0:0] clk__FEEDTHRU_77 ;
wire [0:0] clk__FEEDTHRU_78 ;
wire [0:0] clk__FEEDTHRU_79 ;
wire [0:0] clk__FEEDTHRU_80 ;
wire [0:0] clk__FEEDTHRU_81 ;
wire [0:0] clk__FEEDTHRU_82 ;
wire [0:0] clk__FEEDTHRU_83 ;
wire [0:0] clk__FEEDTHRU_84 ;
wire [0:0] clk__FEEDTHRU_85 ;
wire [0:0] clk__FEEDTHRU_86 ;
wire [0:0] clk__FEEDTHRU_87 ;
wire [0:0] clk__FEEDTHRU_88 ;
wire [0:0] clk__FEEDTHRU_89 ;
wire [0:0] clk__FEEDTHRU_90 ;
wire [0:0] clk__FEEDTHRU_91 ;
wire [0:0] clk__FEEDTHRU_92 ;
wire [0:0] clk__FEEDTHRU_93 ;
wire [0:0] clk__FEEDTHRU_94 ;
wire [0:0] clk__FEEDTHRU_95 ;
wire [0:0] clk__FEEDTHRU_96 ;
wire [0:0] clk__FEEDTHRU_97 ;
wire [0:0] clk__FEEDTHRU_98 ;
wire [0:0] clk__FEEDTHRU_99 ;
wire [0:0] clk__FEEDTHRU_100 ;
wire [0:0] clk__FEEDTHRU_101 ;
wire [0:0] clk__FEEDTHRU_102 ;
wire [0:0] clk__FEEDTHRU_103 ;
wire [0:0] clk__FEEDTHRU_104 ;
wire [0:0] clk__FEEDTHRU_105 ;
wire [0:0] clk__FEEDTHRU_106 ;
wire [0:0] clk__FEEDTHRU_107 ;
wire [0:0] clk__FEEDTHRU_108 ;
wire [0:0] clk__FEEDTHRU_109 ;
wire [0:0] clk__FEEDTHRU_110 ;
wire [0:0] clk__FEEDTHRU_111 ;
wire [0:0] clk__FEEDTHRU_112 ;
wire [0:0] clk__FEEDTHRU_113 ;
wire [0:0] clk__FEEDTHRU_114 ;
wire [0:0] clk__FEEDTHRU_115 ;
wire [0:0] clk__FEEDTHRU_116 ;
wire [0:0] clk__FEEDTHRU_117 ;
wire [0:0] clk__FEEDTHRU_118 ;
wire [0:0] clk__FEEDTHRU_119 ;
wire [0:0] clk__FEEDTHRU_120 ;
wire [0:0] clk__FEEDTHRU_121 ;
wire [0:0] clk__FEEDTHRU_122 ;
wire [0:0] clk__FEEDTHRU_123 ;
wire [0:0] clk__FEEDTHRU_124 ;
wire [0:0] clk__FEEDTHRU_125 ;
wire [0:0] clk__FEEDTHRU_126 ;
wire [0:0] clk__FEEDTHRU_127 ;
wire [0:0] clk__FEEDTHRU_128 ;
wire [0:0] clk__FEEDTHRU_129 ;
wire [0:0] clk__FEEDTHRU_130 ;
wire [0:0] clk__FEEDTHRU_131 ;
wire [0:0] clk__FEEDTHRU_132 ;
wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_6 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_7 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_8 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_9 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_10 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_11 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_12 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_13 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_14 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_15 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_16 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_17 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_18 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_19 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_20 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_21 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_22 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_23 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_24 ;
wire [0:0] grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_25 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_6 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_7 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_8 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_9 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_10 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_11 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_12 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_13 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_14 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_15 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_16 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_17 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_18 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_19 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_20 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_21 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_22 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_23 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_24 ;
wire [0:0] grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_25 ;
wire [0:0] grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ;
wire [0:0] grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ;
wire [0:0] grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ;
wire [0:0] grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ;
wire [0:0] grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ;
wire [0:0] grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_6 ;
wire [0:0] grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_7 ;
wire [0:0] grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_8 ;
wire [0:0] grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_9 ;
wire [0:0] grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_10 ;
wire [0:0] grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_11 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_6 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_7 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_8 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_9 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_10 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_11 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_12 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_13 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_14 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_15 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_16 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_17 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_18 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_19 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_20 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_21 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_22 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_23 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_24 ;
wire [0:0] grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_25 ;
wire [0:0] grid_clb_120_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ;
wire [27:27] scff_Wires__FEEDTHRU_1 ;
//

grid_clb grid_clb_1__1_ (
    .prog_clk ( { ctsbuf_net_4341352 } ) ,
    .Test_en ( Test_en__FEEDTHRU_149 ) ,
    .clk ( { ctsbuf_net_3921 } ) ,
    .top_width_0_height_0__pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_0_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_1__1__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( grid_io_left_0_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_0_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_0_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_0_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_0_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_0_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_0_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_0_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_0_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_2 } ) ,
    .ccff_tail ( grid_clb_0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_23_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_3 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4 ) , .SC_OUT_BOT ( scff_Wires_25_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_150 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_122 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_487 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_5 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_6 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_898 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_7 } ) ) ;
grid_clb grid_clb_1__2_ (
    .prog_clk ( { ctsbuf_net_3861304 } ) ,
    .Test_en ( Test_en__FEEDTHRU_151 ) , .clk ( clk__FEEDTHRU_122 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_1_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_8 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_1__2__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( grid_io_left_1_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_1_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_1_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_1_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_1_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_1_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_9 } ) ,
    .ccff_tail ( grid_clb_1_ccff_tail ) , .SC_IN_TOP ( scff_Wires_21_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_10 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_11 ) , .SC_OUT_BOT ( scff_Wires_22_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_152 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_123 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_271 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_12 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_13 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_734 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_14 } ) ) ;
grid_clb grid_clb_1__3_ (
    .prog_clk ( { ctsbuf_net_3381256 } ) ,
    .Test_en ( Test_en__FEEDTHRU_153 ) , .clk ( clk__FEEDTHRU_123 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__2_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__2_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__2_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__2_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__2_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__2_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__2_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__2_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__2_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__2_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__2_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__2_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__2_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__2_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__2_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__2_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_2_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_15 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__2_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__2_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__2_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__2_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__2_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__2_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__2_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__2_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__2_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__2_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__2_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__2_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__2_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__2_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__2_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__2_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_1__3__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( grid_io_left_2_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_2_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_2_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_2_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_2_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_2_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_2_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_2_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_16 } ) ,
    .ccff_tail ( grid_clb_2_ccff_tail ) , .SC_IN_TOP ( scff_Wires_19_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_17 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_18 ) , .SC_OUT_BOT ( scff_Wires_20_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_154 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_124 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_472 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_19 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_20 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_273 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_21 } ) ) ;
grid_clb grid_clb_1__4_ (
    .prog_clk ( { ctsbuf_net_2901208 } ) ,
    .Test_en ( Test_en__FEEDTHRU_155 ) , .clk ( clk__FEEDTHRU_124 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__3_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__3_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__3_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__3_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__3_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__3_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__3_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__3_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__3_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__3_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__3_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__3_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__3_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__3_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__3_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__3_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_3_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_22 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__3_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__3_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__3_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__3_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__3_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__3_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__3_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__3_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__3_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__3_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__3_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__3_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__3_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__3_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__3_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__3_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_1__4__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( grid_io_left_3_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_3_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_3_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_3_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_3_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_23 } ) ,
    .ccff_tail ( grid_clb_3_ccff_tail ) , .SC_IN_TOP ( scff_Wires_17_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_24 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_25 ) , .SC_OUT_BOT ( scff_Wires_18_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_156 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_125 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_325 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_26 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_27 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_662 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_28 } ) ) ;
grid_clb grid_clb_1__5_ (
    .prog_clk ( { ctsbuf_net_2421160 } ) ,
    .Test_en ( Test_en__FEEDTHRU_157 ) , .clk ( clk__FEEDTHRU_125 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__4_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__4_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__4_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__4_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__4_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__4_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__4_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__4_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__4_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__4_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__4_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__4_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__4_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__4_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__4_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__4_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_4_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_29 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__4_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__4_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__4_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__4_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__4_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__4_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__4_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__4_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__4_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__4_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__4_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__4_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__4_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__4_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__4_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__4_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_1__5__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( grid_io_left_4_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_4_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_4_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_4_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_4_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_4_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_4_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_4_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_4_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_4_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_4_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_4_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_4_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_4_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_4_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_4_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_4_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_4_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_4_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_4_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_4_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_4_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_4_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_4_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_4_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_4_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_4_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_4_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_4_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_4_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_4_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_4_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_4_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_4_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_30 } ) ,
    .ccff_tail ( grid_clb_4_ccff_tail ) , .SC_IN_TOP ( scff_Wires_15_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_31 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_32 ) , .SC_OUT_BOT ( scff_Wires_16_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_158 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_126 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_395 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_33 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_34 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_771 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_35 } ) ) ;
grid_clb grid_clb_1__6_ (
    .prog_clk ( { ctsbuf_net_1941112 } ) ,
    .Test_en ( Test_en__FEEDTHRU_159 ) , .clk ( clk__FEEDTHRU_126 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__5_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__5_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__5_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__5_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__5_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__5_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__5_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__5_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__5_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__5_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__5_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__5_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__5_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__5_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__5_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__5_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_5_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_36 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__5_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__5_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__5_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__5_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__5_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__5_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__5_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__5_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__5_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__5_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__5_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__5_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__5_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__5_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__5_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__5_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_1__6__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( grid_io_left_5_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_5_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_5_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_5_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_5_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_5_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_5_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_5_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_5_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_5_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_5_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_5_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_5_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_5_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_5_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_5_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_5_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_5_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_5_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_5_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_5_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_5_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_5_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_5_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_5_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_5_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_5_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_5_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_5_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_5_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_5_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_5_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_5_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_5_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_37 } ) ,
    .ccff_tail ( grid_clb_5_ccff_tail ) , .SC_IN_TOP ( scff_Wires_13_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_38 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_39 ) , .SC_OUT_BOT ( scff_Wires_14_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_160 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_127 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_412 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_40 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_41 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_845 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_42 } ) ) ;
grid_clb grid_clb_1__7_ (
    .prog_clk ( { ctsbuf_net_1471065 } ) ,
    .Test_en ( Test_en__FEEDTHRU_161 ) , .clk ( clk__FEEDTHRU_127 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__6_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__6_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__6_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__6_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__6_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__6_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__6_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__6_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__6_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__6_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__6_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__6_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__6_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__6_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__6_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__6_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_6_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_43 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__6_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__6_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__6_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__6_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__6_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__6_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__6_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__6_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__6_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__6_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__6_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__6_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__6_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__6_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__6_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__6_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_1__7__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( grid_io_left_6_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_6_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_6_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_6_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_6_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_6_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_6_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_6_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_6_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_6_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_6_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_6_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_6_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_6_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_6_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_6_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_6_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_6_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_6_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_6_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_6_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_6_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_6_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_6_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_6_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_6_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_6_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_6_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_6_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_6_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_6_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_6_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_6_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_6_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_44 } ) ,
    .ccff_tail ( grid_clb_6_ccff_tail ) , .SC_IN_TOP ( scff_Wires_11_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_45 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_46 ) , .SC_OUT_BOT ( scff_Wires_12_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_162 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_128 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_703 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_47 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_48 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_877 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_49 } ) ) ;
grid_clb grid_clb_1__8_ (
    .prog_clk ( { ctsbuf_net_1051023 } ) ,
    .Test_en ( Test_en__FEEDTHRU_163 ) , .clk ( clk__FEEDTHRU_128 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__7_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__7_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__7_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__7_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__7_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__7_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__7_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__7_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__7_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__7_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__7_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__7_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__7_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__7_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__7_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__7_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_7_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_50 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__7_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__7_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__7_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__7_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__7_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__7_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__7_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__7_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__7_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__7_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__7_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__7_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__7_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__7_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__7_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__7_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_1__8__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( grid_io_left_7_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_7_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_7_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_7_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_7_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_7_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_7_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_7_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_7_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_7_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_7_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_7_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_7_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_7_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_7_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_7_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_7_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_7_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_7_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_7_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_7_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_7_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_7_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_7_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_7_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_7_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_7_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_7_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_7_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_7_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_7_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_7_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_7_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_7_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_51 } ) ,
    .ccff_tail ( grid_clb_7_ccff_tail ) , .SC_IN_TOP ( scff_Wires_9_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_52 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_53 ) , .SC_OUT_BOT ( scff_Wires_10_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_164 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_129 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_518 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_54 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_55 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_261 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_56 } ) ) ;
grid_clb grid_clb_1__9_ (
    .prog_clk ( { ctsbuf_net_70988 } ) ,
    .Test_en ( Test_en__FEEDTHRU_165 ) , .clk ( clk__FEEDTHRU_129 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__8_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__8_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__8_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__8_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__8_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__8_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__8_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__8_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__8_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__8_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__8_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__8_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__8_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__8_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__8_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__8_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_8_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_57 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__8_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__8_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__8_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__8_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__8_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__8_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__8_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__8_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__8_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__8_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__8_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__8_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__8_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__8_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__8_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__8_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_1__9__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( grid_io_left_8_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_8_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_8_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_8_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_8_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_8_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_8_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_8_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_8_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_8_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_8_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_8_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_8_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_8_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_8_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_8_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_8_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_8_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_8_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_8_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_8_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_8_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_8_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_8_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_8_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_8_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_8_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_8_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_8_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_8_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_8_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_8_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_8_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_8_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_58 } ) ,
    .ccff_tail ( grid_clb_8_ccff_tail ) , .SC_IN_TOP ( scff_Wires_7_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_59 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_60 ) , .SC_OUT_BOT ( scff_Wires_8_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_166 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_130 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_554 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_61 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_62 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_496 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_63 } ) ) ;
grid_clb grid_clb_1__10_ (
    .prog_clk ( { ctsbuf_net_43961 } ) ,
    .Test_en ( Test_en__FEEDTHRU_167 ) , .clk ( clk__FEEDTHRU_130 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__9_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__9_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__9_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__9_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__9_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__9_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__9_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__9_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__9_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__9_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__9_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__9_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__9_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__9_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__9_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__9_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_9_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_64 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__9_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__9_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__9_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__9_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__9_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__9_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__9_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__9_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__9_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__9_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__9_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__9_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__9_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__9_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__9_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__9_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_1__10__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( grid_io_left_9_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_9_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_9_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_9_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_9_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_9_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_9_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_9_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_9_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_9_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_9_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_9_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_9_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_9_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_9_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_9_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_9_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_9_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_9_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_9_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_9_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_9_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_9_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_9_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_9_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_9_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_9_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_9_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_9_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_9_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_9_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_9_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_9_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_9_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_65 } ) ,
    .ccff_tail ( grid_clb_9_ccff_tail ) , .SC_IN_TOP ( scff_Wires_5_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_66 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_67 ) , .SC_OUT_BOT ( scff_Wires_6_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_168 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_131 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_500 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_68 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_69 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_844 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_70 } ) ) ;
grid_clb grid_clb_1__11_ (
    .prog_clk ( { ctsbuf_net_23941 } ) ,
    .Test_en ( Test_en__FEEDTHRU_169 ) , .clk ( clk__FEEDTHRU_131 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__10_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__10_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__10_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__10_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__10_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__10_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__10_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__10_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__10_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__10_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__10_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__10_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__10_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__10_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__10_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__10_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_10_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_71 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__10_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__10_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__10_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__10_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__10_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__10_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__10_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__10_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__10_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__10_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__10_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__10_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__10_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__10_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__10_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__10_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_1__11__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( grid_io_left_10_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_10_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_10_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_10_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_10_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_10_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_10_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_10_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_10_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_10_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_10_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_10_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_10_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_10_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_10_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_10_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_10_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_10_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_10_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_10_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_10_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_10_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_10_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_10_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_10_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_10_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_10_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_10_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_10_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_10_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_10_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_10_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_10_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_10_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_72 } ) ,
    .ccff_tail ( grid_clb_10_ccff_tail ) , .SC_IN_TOP ( scff_Wires_3_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_73 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_74 ) , .SC_OUT_BOT ( scff_Wires_4_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_170 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_132 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_750 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_75 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_76 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_442 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_77 } ) ) ;
grid_clb grid_clb_1__12_ (
    .prog_clk ( { ctsbuf_net_12930 } ) ,
    .Test_en ( Test_en__FEEDTHRU_171 ) , .clk ( clk__FEEDTHRU_132 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__12__0_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__12__0_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__12__0_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__12__0_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__12__0_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__12__0_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__12__0_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__12__0_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__12__0_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__12__0_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__12__0_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__12__0_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__12__0_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__12__0_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__12__0_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__12__0_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( grid_clb_1__12__undriven_top_width_0_height_0__pin_32_ ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_78 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__11_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__11_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__11_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__11_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__11_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__11_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__11_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__11_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__11_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__11_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__11_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__11_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__11_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__11_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__11_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__11_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_1__12__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( grid_io_left_11_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_11_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_11_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_11_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_11_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_11_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_11_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_11_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_11_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_11_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_11_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_11_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_11_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_11_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_11_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_11_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_11_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_11_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_11_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_11_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_11_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_11_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_11_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_11_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_11_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_11_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_11_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_11_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_11_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_11_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_11_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_11_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_11_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_11_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_79 } ) ,
    .ccff_tail ( grid_clb_11_ccff_tail ) , .SC_IN_TOP ( scff_Wires_1_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_80 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_81 ) , .SC_OUT_BOT ( scff_Wires_2_ ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_82 } ) ,
    .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_83 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_699 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_84 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_85 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_753 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_86 } ) ) ;
grid_clb grid_clb_2__1_ (
    .prog_clk ( { ctsbuf_net_4791397 } ) ,
    .Test_en ( Test_en__FEEDTHRU_172 ) ,
    .clk ( { ctsbuf_net_5923 } ) ,
    .top_width_0_height_0__pin_0_ ( cbx_1__1__11_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__11_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__11_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__11_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__11_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__11_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__11_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__11_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__11_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__11_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__11_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__11_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__11_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__11_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__11_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__11_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_11_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_87 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__12_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__12_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__12_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__12_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__12_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__12_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__12_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__12_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__12_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__12_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__12_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__12_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__12_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__12_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__12_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__12_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_2__1__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__0_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_12_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_12_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_12_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_12_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_12_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_12_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_12_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_12_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_12_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_12_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_12_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_12_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_12_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_12_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_12_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_12_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_12_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_12_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_12_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_12_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_12_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_12_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_12_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_12_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_12_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_12_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_12_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_12_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_12_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_12_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_12_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_12_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_12_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_88 } ) ,
    .ccff_tail ( grid_clb_12_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_89 ) , .SC_IN_BOT ( scff_Wires_28_ ) , 
    .SC_OUT_TOP ( scff_Wires_29_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_90 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_173 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_111 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_495 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_91 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_92 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { scff_Wires_27_ } ) ,
    .scff_Wires__FEEDTHRU_1 ( scff_Wires__FEEDTHRU_1 ) ) ;
grid_clb grid_clb_2__2_ (
    .prog_clk ( { ctsbuf_net_4361354 } ) ,
    .Test_en ( Test_en__FEEDTHRU_174 ) , .clk ( clk__FEEDTHRU_111 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__12_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__12_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__12_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__12_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__12_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__12_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__12_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__12_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__12_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__12_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__12_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__12_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__12_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__12_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__12_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__12_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_12_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_93 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__13_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__13_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__13_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__13_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__13_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__13_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__13_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__13_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__13_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__13_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__13_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__13_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__13_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__13_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__13_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__13_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_2__2__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__1_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_13_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_13_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_13_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_13_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_13_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_13_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_13_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_13_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_13_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_13_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_13_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_13_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_13_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_13_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_13_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_13_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_13_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_13_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_13_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_13_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_13_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_13_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_13_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_13_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_13_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_13_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_13_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_13_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_13_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_13_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_13_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_13_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_13_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_94 } ) ,
    .ccff_tail ( grid_clb_13_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_95 ) , .SC_IN_BOT ( scff_Wires_30_ ) , 
    .SC_OUT_TOP ( scff_Wires_31_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_96 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_175 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_112 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_384 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_97 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_98 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_854 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_99 } ) ) ;
grid_clb grid_clb_2__3_ (
    .prog_clk ( { ctsbuf_net_3881306 } ) ,
    .Test_en ( Test_en__FEEDTHRU_176 ) , .clk ( clk__FEEDTHRU_112 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__13_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__13_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__13_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__13_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__13_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__13_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__13_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__13_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__13_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__13_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__13_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__13_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__13_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__13_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__13_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__13_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_13_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_100 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__14_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__14_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__14_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__14_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__14_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__14_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__14_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__14_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__14_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__14_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__14_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__14_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__14_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__14_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__14_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__14_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_2__3__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__2_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_14_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_14_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_14_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_14_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_14_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_14_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_14_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_14_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_14_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_14_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_14_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_14_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_14_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_14_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_14_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_14_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_14_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_14_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_14_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_14_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_14_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_14_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_14_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_14_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_14_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_14_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_14_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_14_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_14_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_14_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_14_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_14_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_14_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_101 } ) ,
    .ccff_tail ( grid_clb_14_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_102 ) , .SC_IN_BOT ( scff_Wires_32_ ) , 
    .SC_OUT_TOP ( scff_Wires_33_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_103 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_177 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_113 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_279 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_104 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_105 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_366 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_106 } ) ) ;
grid_clb grid_clb_2__4_ (
    .prog_clk ( { ctsbuf_net_3401258 } ) ,
    .Test_en ( Test_en__FEEDTHRU_178 ) , .clk ( clk__FEEDTHRU_113 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__14_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__14_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__14_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__14_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__14_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__14_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__14_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__14_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__14_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__14_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__14_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__14_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__14_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__14_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__14_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__14_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_14_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_107 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__15_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__15_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__15_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__15_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__15_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__15_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__15_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__15_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__15_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__15_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__15_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__15_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__15_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__15_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__15_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__15_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_2__4__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__3_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_15_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_15_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_15_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_15_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_15_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_15_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_15_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_15_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_15_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_15_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_15_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_15_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_15_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_15_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_15_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_15_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_15_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_15_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_15_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_15_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_15_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_15_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_15_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_15_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_15_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_15_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_15_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_15_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_15_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_15_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_15_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_15_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_15_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_108 } ) ,
    .ccff_tail ( grid_clb_15_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_109 ) , .SC_IN_BOT ( scff_Wires_34_ ) , 
    .SC_OUT_TOP ( scff_Wires_35_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_110 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_179 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_114 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_660 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_111 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_112 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_776 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_113 } ) ) ;
grid_clb grid_clb_2__5_ (
    .prog_clk ( { ctsbuf_net_2921210 } ) ,
    .Test_en ( Test_en__FEEDTHRU_180 ) , .clk ( clk__FEEDTHRU_114 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__15_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__15_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__15_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__15_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__15_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__15_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__15_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__15_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__15_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__15_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__15_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__15_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__15_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__15_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__15_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__15_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_15_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_114 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__16_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__16_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__16_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__16_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__16_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__16_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__16_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__16_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__16_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__16_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__16_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__16_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__16_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__16_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__16_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__16_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_2__5__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__4_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_16_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_16_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_16_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_16_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_16_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_16_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_16_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_16_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_16_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_16_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_16_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_16_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_16_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_16_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_16_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_16_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_16_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_16_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_16_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_16_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_16_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_16_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_16_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_16_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_16_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_16_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_16_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_16_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_16_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_16_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_16_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_16_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_16_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_115 } ) ,
    .ccff_tail ( grid_clb_16_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_116 ) , .SC_IN_BOT ( scff_Wires_36_ ) , 
    .SC_OUT_TOP ( scff_Wires_37_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_117 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_181 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_115 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_408 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_118 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_119 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_587 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_120 } ) ) ;
grid_clb grid_clb_2__6_ (
    .prog_clk ( { ctsbuf_net_2441162 } ) ,
    .Test_en ( Test_en__FEEDTHRU_182 ) , .clk ( clk__FEEDTHRU_115 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__16_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__16_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__16_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__16_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__16_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__16_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__16_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__16_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__16_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__16_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__16_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__16_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__16_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__16_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__16_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__16_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_16_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_121 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__17_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__17_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__17_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__17_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__17_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__17_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__17_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__17_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__17_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__17_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__17_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__17_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__17_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__17_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__17_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__17_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_2__6__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__5_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_17_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_17_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_17_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_17_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_17_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_17_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_17_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_17_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_17_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_17_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_17_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_17_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_17_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_17_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_17_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_17_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_17_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_17_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_17_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_17_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_17_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_17_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_17_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_17_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_17_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_17_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_17_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_17_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_17_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_17_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_17_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_17_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_17_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_122 } ) ,
    .ccff_tail ( grid_clb_17_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_123 ) , .SC_IN_BOT ( scff_Wires_38_ ) , 
    .SC_OUT_TOP ( scff_Wires_39_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_124 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_183 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_116 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_586 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_125 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_126 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_876 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_127 } ) ) ;
grid_clb grid_clb_2__7_ (
    .prog_clk ( { ctsbuf_net_1961114 } ) ,
    .Test_en ( Test_en__FEEDTHRU_184 ) , .clk ( clk__FEEDTHRU_116 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__17_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__17_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__17_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__17_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__17_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__17_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__17_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__17_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__17_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__17_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__17_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__17_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__17_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__17_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__17_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__17_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_17_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_128 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__18_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__18_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__18_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__18_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__18_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__18_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__18_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__18_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__18_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__18_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__18_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__18_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__18_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__18_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__18_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__18_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_2__7__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__6_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_18_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_18_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_18_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_18_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_18_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_18_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_18_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_18_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_18_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_18_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_18_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_18_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_18_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_18_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_18_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_18_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_18_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_18_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_18_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_18_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_18_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_18_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_18_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_18_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_18_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_18_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_18_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_18_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_18_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_18_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_18_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_18_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_18_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_129 } ) ,
    .ccff_tail ( grid_clb_18_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_130 ) , .SC_IN_BOT ( scff_Wires_40_ ) , 
    .SC_OUT_TOP ( scff_Wires_41_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_131 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_185 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_117 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_824 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_132 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_133 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_278 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_134 } ) ) ;
grid_clb grid_clb_2__8_ (
    .prog_clk ( { ctsbuf_net_1491067 } ) ,
    .Test_en ( Test_en__FEEDTHRU_186 ) , .clk ( clk__FEEDTHRU_117 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__18_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__18_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__18_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__18_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__18_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__18_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__18_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__18_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__18_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__18_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__18_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__18_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__18_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__18_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__18_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__18_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_18_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_135 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__19_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__19_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__19_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__19_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__19_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__19_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__19_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__19_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__19_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__19_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__19_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__19_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__19_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__19_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__19_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__19_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_2__8__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__7_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_19_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_19_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_19_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_19_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_19_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_19_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_19_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_19_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_19_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_19_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_19_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_19_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_19_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_19_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_19_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_19_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_19_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_19_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_19_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_19_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_19_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_19_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_19_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_19_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_19_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_19_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_19_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_19_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_19_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_19_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_19_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_19_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_19_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_136 } ) ,
    .ccff_tail ( grid_clb_19_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_137 ) , .SC_IN_BOT ( scff_Wires_42_ ) , 
    .SC_OUT_TOP ( scff_Wires_43_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_138 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_187 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_118 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_663 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_139 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_140 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_379 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_141 } ) ) ;
grid_clb grid_clb_2__9_ (
    .prog_clk ( { ctsbuf_net_1071025 } ) ,
    .Test_en ( Test_en__FEEDTHRU_188 ) , .clk ( clk__FEEDTHRU_118 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__19_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__19_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__19_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__19_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__19_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__19_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__19_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__19_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__19_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__19_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__19_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__19_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__19_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__19_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__19_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__19_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_19_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_142 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__20_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__20_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__20_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__20_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__20_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__20_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__20_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__20_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__20_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__20_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__20_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__20_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__20_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__20_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__20_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__20_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_2__9__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__8_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_20_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_20_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_20_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_20_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_20_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_20_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_20_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_20_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_20_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_20_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_20_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_20_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_20_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_20_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_20_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_20_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_20_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_20_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_20_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_20_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_20_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_20_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_20_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_20_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_20_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_20_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_20_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_20_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_20_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_20_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_20_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_20_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_20_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_143 } ) ,
    .ccff_tail ( grid_clb_20_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_144 ) , .SC_IN_BOT ( scff_Wires_44_ ) , 
    .SC_OUT_TOP ( scff_Wires_45_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_145 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_189 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_119 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_331 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_146 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_147 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_585 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_148 } ) ) ;
grid_clb grid_clb_2__10_ (
    .prog_clk ( { ctsbuf_net_72990 } ) ,
    .Test_en ( Test_en__FEEDTHRU_190 ) , .clk ( clk__FEEDTHRU_119 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__20_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__20_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__20_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__20_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__20_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__20_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__20_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__20_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__20_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__20_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__20_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__20_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__20_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__20_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__20_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__20_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_20_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_149 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__21_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__21_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__21_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__21_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__21_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__21_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__21_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__21_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__21_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__21_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__21_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__21_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__21_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__21_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__21_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__21_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_2__10__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__9_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_21_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_21_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_21_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_21_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_21_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_21_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_21_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_21_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_21_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_21_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_21_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_21_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_21_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_21_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_21_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_21_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_21_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_21_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_21_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_21_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_21_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_21_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_21_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_21_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_21_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_21_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_21_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_21_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_21_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_21_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_21_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_21_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_21_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_150 } ) ,
    .ccff_tail ( grid_clb_21_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_151 ) , .SC_IN_BOT ( scff_Wires_46_ ) , 
    .SC_OUT_TOP ( scff_Wires_47_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_152 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_191 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_120 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_275 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_153 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_154 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_274 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_155 } ) ) ;
grid_clb grid_clb_2__11_ (
    .prog_clk ( { ctsbuf_net_44962 } ) ,
    .Test_en ( Test_en__FEEDTHRU_192 ) , .clk ( clk__FEEDTHRU_120 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__21_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__21_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__21_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__21_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__21_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__21_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__21_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__21_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__21_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__21_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__21_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__21_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__21_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__21_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__21_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__21_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_21_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_156 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__22_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__22_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__22_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__22_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__22_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__22_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__22_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__22_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__22_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__22_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__22_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__22_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__22_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__22_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__22_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__22_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_2__11__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__10_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_22_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_22_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_22_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_22_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_22_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_22_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_22_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_22_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_22_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_22_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_22_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_22_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_22_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_22_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_22_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_22_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_22_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_22_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_22_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_22_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_22_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_22_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_22_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_22_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_22_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_22_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_22_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_22_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_22_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_22_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_22_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_22_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_22_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_157 } ) ,
    .ccff_tail ( grid_clb_22_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_158 ) , .SC_IN_BOT ( scff_Wires_48_ ) , 
    .SC_OUT_TOP ( scff_Wires_49_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_159 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_193 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_121 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_559 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_160 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_161 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_294 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_162 } ) ) ;
grid_clb grid_clb_2__12_ (
    .prog_clk ( { ctsbuf_net_24942 } ) ,
    .Test_en ( Test_en__FEEDTHRU_194 ) , .clk ( clk__FEEDTHRU_121 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__12__1_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__12__1_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__12__1_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__12__1_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__12__1_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__12__1_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__12__1_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__12__1_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__12__1_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__12__1_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__12__1_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__12__1_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__12__1_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__12__1_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__12__1_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__12__1_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_132_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_163 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__23_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__23_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__23_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__23_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__23_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__23_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__23_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__23_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__23_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__23_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__23_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__23_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__23_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__23_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__23_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__23_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_2__12__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__11_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_23_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_23_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_23_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_23_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_23_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_23_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_23_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_23_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_23_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_23_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_23_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_23_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_23_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_23_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_23_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_23_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_23_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_23_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_23_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_23_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_23_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_23_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_23_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_23_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_23_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_23_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_23_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_23_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_23_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_23_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_23_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_23_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_23_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_164 } ) ,
    .ccff_tail ( grid_clb_23_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_165 ) , .SC_IN_BOT ( scff_Wires_50_ ) , 
    .SC_OUT_TOP ( scff_Wires_51_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_166 ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_167 } ) ,
    .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_168 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_860 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_169 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_170 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_272 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_171 } ) ) ;
grid_clb grid_clb_3__1_ (
    .prog_clk ( { ctsbuf_net_5161434 } ) ,
    .Test_en ( Test_en__FEEDTHRU_195 ) ,
    .clk ( { ctsbuf_net_3921 } ) ,
    .top_width_0_height_0__pin_0_ ( cbx_1__1__22_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__22_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__22_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__22_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__22_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__22_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__22_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__22_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__22_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__22_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__22_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__22_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__22_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__22_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__22_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__22_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_22_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_172 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__24_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__24_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__24_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__24_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__24_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__24_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__24_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__24_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__24_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__24_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__24_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__24_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__24_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__24_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__24_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__24_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_3__1__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__12_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_24_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_24_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_24_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_24_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_24_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_24_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_24_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_24_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_24_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_24_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_24_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_24_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_24_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_24_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_24_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_24_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_24_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_24_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_24_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_24_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_24_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_24_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_24_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_24_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_24_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_24_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_24_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_24_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_24_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_24_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_24_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_24_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_24_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_173 } ) ,
    .ccff_tail ( grid_clb_24_ccff_tail ) , .SC_IN_TOP ( scff_Wires_76_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_174 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_175 ) , 
    .SC_OUT_BOT ( scff_Wires_78_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_196 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_100 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_741 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_176 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_177 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_313 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_178 } ) ) ;
grid_clb grid_clb_3__2_ (
    .prog_clk ( { ctsbuf_net_4811399 } ) ,
    .Test_en ( Test_en__FEEDTHRU_197 ) , .clk ( clk__FEEDTHRU_100 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__23_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__23_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__23_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__23_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__23_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__23_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__23_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__23_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__23_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__23_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__23_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__23_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__23_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__23_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__23_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__23_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_23_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_179 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__25_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__25_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__25_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__25_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__25_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__25_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__25_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__25_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__25_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__25_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__25_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__25_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__25_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__25_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__25_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__25_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_3__2__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__13_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_25_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_25_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_25_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_25_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_25_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_25_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_25_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_25_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_25_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_25_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_25_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_25_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_25_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_25_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_25_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_25_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_25_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_25_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_25_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_25_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_25_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_25_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_25_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_25_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_25_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_25_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_25_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_25_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_25_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_25_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_25_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_25_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_25_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_180 } ) ,
    .ccff_tail ( grid_clb_25_ccff_tail ) , .SC_IN_TOP ( scff_Wires_74_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_181 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_182 ) , 
    .SC_OUT_BOT ( scff_Wires_75_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_198 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_101 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_633 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_183 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_184 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_441 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_185 } ) ) ;
grid_clb grid_clb_3__3_ (
    .prog_clk ( { ctsbuf_net_4381356 } ) ,
    .Test_en ( Test_en__FEEDTHRU_199 ) , .clk ( clk__FEEDTHRU_101 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__24_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__24_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__24_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__24_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__24_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__24_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__24_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__24_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__24_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__24_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__24_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__24_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__24_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__24_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__24_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__24_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_24_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_186 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__26_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__26_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__26_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__26_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__26_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__26_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__26_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__26_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__26_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__26_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__26_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__26_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__26_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__26_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__26_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__26_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_3__3__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__14_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_26_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_26_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_26_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_26_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_26_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_26_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_26_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_26_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_26_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_26_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_26_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_26_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_26_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_26_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_26_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_26_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_26_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_26_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_26_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_26_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_26_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_26_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_26_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_26_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_26_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_26_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_26_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_26_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_26_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_26_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_26_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_26_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_26_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_187 } ) ,
    .ccff_tail ( grid_clb_26_ccff_tail ) , .SC_IN_TOP ( scff_Wires_72_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_188 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_189 ) , 
    .SC_OUT_BOT ( scff_Wires_73_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_200 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_102 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_695 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_190 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_191 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_821 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_192 } ) ) ;
grid_clb grid_clb_3__4_ (
    .prog_clk ( { ctsbuf_net_3901308 } ) ,
    .Test_en ( Test_en__FEEDTHRU_201 ) , .clk ( clk__FEEDTHRU_102 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__25_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__25_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__25_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__25_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__25_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__25_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__25_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__25_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__25_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__25_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__25_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__25_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__25_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__25_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__25_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__25_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_25_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_193 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__27_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__27_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__27_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__27_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__27_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__27_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__27_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__27_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__27_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__27_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__27_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__27_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__27_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__27_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__27_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__27_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_3__4__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__15_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_27_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_27_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_27_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_27_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_27_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_27_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_27_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_27_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_27_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_27_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_27_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_27_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_27_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_27_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_27_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_27_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_27_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_27_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_27_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_27_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_27_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_27_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_27_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_27_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_27_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_27_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_27_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_27_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_27_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_27_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_27_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_27_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_27_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_194 } ) ,
    .ccff_tail ( grid_clb_27_ccff_tail ) , .SC_IN_TOP ( scff_Wires_70_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_195 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_196 ) , 
    .SC_OUT_BOT ( scff_Wires_71_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_202 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_103 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_652 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_197 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_198 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_314 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_199 } ) ) ;
grid_clb grid_clb_3__5_ (
    .prog_clk ( { ctsbuf_net_3421260 } ) ,
    .Test_en ( Test_en__FEEDTHRU_203 ) , .clk ( clk__FEEDTHRU_103 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__26_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__26_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__26_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__26_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__26_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__26_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__26_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__26_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__26_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__26_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__26_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__26_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__26_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__26_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__26_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__26_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_26_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_200 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__28_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__28_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__28_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__28_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__28_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__28_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__28_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__28_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__28_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__28_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__28_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__28_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__28_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__28_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__28_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__28_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_3__5__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__16_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_28_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_28_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_28_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_28_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_28_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_28_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_28_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_28_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_28_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_28_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_28_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_28_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_28_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_28_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_28_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_28_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_28_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_28_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_28_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_28_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_28_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_28_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_28_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_28_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_28_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_28_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_28_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_28_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_28_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_28_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_28_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_28_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_28_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_201 } ) ,
    .ccff_tail ( grid_clb_28_ccff_tail ) , .SC_IN_TOP ( scff_Wires_68_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_202 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_203 ) , 
    .SC_OUT_BOT ( scff_Wires_69_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_204 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_104 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_280 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_204 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_205 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_906 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_206 } ) ) ;
grid_clb grid_clb_3__6_ (
    .prog_clk ( { ctsbuf_net_2941212 } ) ,
    .Test_en ( Test_en__FEEDTHRU_205 ) , .clk ( clk__FEEDTHRU_104 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__27_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__27_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__27_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__27_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__27_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__27_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__27_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__27_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__27_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__27_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__27_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__27_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__27_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__27_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__27_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__27_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_27_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_207 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__29_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__29_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__29_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__29_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__29_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__29_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__29_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__29_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__29_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__29_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__29_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__29_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__29_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__29_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__29_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__29_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_3__6__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__17_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_29_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_29_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_29_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_29_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_29_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_29_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_29_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_29_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_29_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_29_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_29_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_29_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_29_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_29_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_29_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_29_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_29_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_29_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_29_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_29_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_29_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_29_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_29_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_29_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_29_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_29_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_29_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_29_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_29_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_29_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_29_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_29_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_29_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_208 } ) ,
    .ccff_tail ( grid_clb_29_ccff_tail ) , .SC_IN_TOP ( scff_Wires_66_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_209 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_210 ) , 
    .SC_OUT_BOT ( scff_Wires_67_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_206 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_105 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_401 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_211 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_212 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_454 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_213 } ) ) ;
grid_clb grid_clb_3__7_ (
    .prog_clk ( { ctsbuf_net_2461164 } ) ,
    .Test_en ( Test_en__FEEDTHRU_207 ) , .clk ( clk__FEEDTHRU_105 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__28_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__28_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__28_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__28_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__28_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__28_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__28_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__28_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__28_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__28_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__28_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__28_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__28_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__28_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__28_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__28_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_28_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_214 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__30_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__30_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__30_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__30_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__30_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__30_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__30_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__30_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__30_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__30_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__30_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__30_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__30_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__30_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__30_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__30_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_3__7__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__18_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_30_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_30_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_30_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_30_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_30_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_30_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_30_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_30_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_30_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_30_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_30_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_30_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_30_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_30_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_30_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_30_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_30_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_30_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_30_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_30_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_30_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_30_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_30_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_30_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_30_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_30_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_30_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_30_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_30_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_30_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_30_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_30_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_30_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_215 } ) ,
    .ccff_tail ( grid_clb_30_ccff_tail ) , .SC_IN_TOP ( scff_Wires_64_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_216 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_217 ) , 
    .SC_OUT_BOT ( scff_Wires_65_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_208 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_106 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_803 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_218 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_219 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_302 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_220 } ) ) ;
grid_clb grid_clb_3__8_ (
    .prog_clk ( { ctsbuf_net_1981116 } ) ,
    .Test_en ( Test_en__FEEDTHRU_209 ) , .clk ( clk__FEEDTHRU_106 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__29_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__29_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__29_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__29_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__29_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__29_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__29_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__29_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__29_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__29_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__29_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__29_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__29_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__29_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__29_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__29_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_29_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_221 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__31_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__31_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__31_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__31_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__31_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__31_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__31_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__31_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__31_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__31_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__31_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__31_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__31_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__31_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__31_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__31_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_3__8__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__19_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_31_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_31_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_31_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_31_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_31_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_31_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_31_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_31_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_31_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_31_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_31_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_31_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_31_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_31_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_31_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_31_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_31_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_31_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_31_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_31_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_31_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_31_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_31_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_31_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_31_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_31_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_31_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_31_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_31_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_31_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_31_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_31_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_31_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_222 } ) ,
    .ccff_tail ( grid_clb_31_ccff_tail ) , .SC_IN_TOP ( scff_Wires_62_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_223 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_224 ) , 
    .SC_OUT_BOT ( scff_Wires_63_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_210 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_107 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_638 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_225 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_226 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_777 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_227 } ) ) ;
grid_clb grid_clb_3__9_ (
    .prog_clk ( { p_abuf15 } ) ,
    .Test_en ( Test_en__FEEDTHRU_211 ) , .clk ( clk__FEEDTHRU_107 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__30_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__30_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__30_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__30_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__30_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__30_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__30_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__30_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__30_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__30_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__30_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__30_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__30_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__30_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__30_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__30_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_30_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_228 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__32_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__32_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__32_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__32_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__32_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__32_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__32_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__32_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__32_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__32_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__32_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__32_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__32_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__32_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__32_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__32_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_3__9__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__20_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_32_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_32_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_32_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_32_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_32_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_32_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_32_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_32_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_32_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_32_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_32_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_32_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_32_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_32_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_32_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_32_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_32_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_32_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_32_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_32_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_32_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_32_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_32_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_32_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_32_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_32_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_32_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_32_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_32_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_32_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_32_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_32_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_32_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_229 } ) ,
    .ccff_tail ( grid_clb_32_ccff_tail ) , .SC_IN_TOP ( scff_Wires_60_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_230 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_231 ) , 
    .SC_OUT_BOT ( scff_Wires_61_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_212 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_108 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_479 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_232 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_233 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_476 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_234 } ) ) ;
grid_clb grid_clb_3__10_ (
    .prog_clk ( { ctsbuf_net_1091027 } ) ,
    .Test_en ( Test_en__FEEDTHRU_213 ) , .clk ( clk__FEEDTHRU_108 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__31_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__31_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__31_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__31_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__31_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__31_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__31_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__31_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__31_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__31_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__31_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__31_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__31_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__31_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__31_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__31_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_31_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_235 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__33_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__33_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__33_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__33_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__33_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__33_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__33_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__33_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__33_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__33_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__33_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__33_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__33_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__33_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__33_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__33_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_3__10__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__21_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_33_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_33_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_33_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_33_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_33_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_33_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_33_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_33_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_33_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_33_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_33_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_33_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_33_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_33_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_33_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_33_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_33_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_33_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_33_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_33_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_33_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_33_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_33_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_33_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_33_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_33_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_33_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_33_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_33_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_33_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_33_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_33_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_33_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_236 } ) ,
    .ccff_tail ( grid_clb_33_ccff_tail ) , .SC_IN_TOP ( scff_Wires_58_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_237 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_238 ) , 
    .SC_OUT_BOT ( scff_Wires_59_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_214 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_109 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_421 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_239 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_240 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_351 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_241 } ) ) ;
grid_clb grid_clb_3__11_ (
    .prog_clk ( { ctsbuf_net_73991 } ) ,
    .Test_en ( Test_en__FEEDTHRU_215 ) , .clk ( clk__FEEDTHRU_109 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__32_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__32_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__32_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__32_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__32_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__32_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__32_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__32_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__32_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__32_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__32_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__32_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__32_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__32_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__32_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__32_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_32_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_242 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__34_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__34_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__34_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__34_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__34_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__34_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__34_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__34_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__34_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__34_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__34_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__34_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__34_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__34_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__34_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__34_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_3__11__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__22_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_34_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_34_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_34_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_34_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_34_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_34_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_34_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_34_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_34_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_34_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_34_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_34_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_34_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_34_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_34_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_34_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_34_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_34_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_34_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_34_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_34_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_34_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_34_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_34_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_34_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_34_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_34_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_34_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_34_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_34_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_34_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_34_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_34_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_243 } ) ,
    .ccff_tail ( grid_clb_34_ccff_tail ) , .SC_IN_TOP ( scff_Wires_56_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_244 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_245 ) , 
    .SC_OUT_BOT ( scff_Wires_57_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_216 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_110 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_602 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_246 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_247 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_390 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_248 } ) ) ;
grid_clb grid_clb_3__12_ (
    .prog_clk ( { ctsbuf_net_45963 } ) ,
    .Test_en ( Test_en__FEEDTHRU_217 ) , .clk ( clk__FEEDTHRU_110 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__12__2_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__12__2_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__12__2_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__12__2_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__12__2_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__12__2_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__12__2_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__12__2_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__12__2_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__12__2_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__12__2_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__12__2_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__12__2_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__12__2_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__12__2_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__12__2_bottom_grid_pin_15_ ) ,
    .top_width_0_height_0__pin_32_ ( { ropt_net_1592 } ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_249 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__35_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__35_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__35_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__35_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__35_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__35_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__35_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__35_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__35_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__35_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__35_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__35_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__35_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__35_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__35_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__35_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_3__12__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__23_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_35_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_35_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_35_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_35_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_35_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_35_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_35_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_35_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_35_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_35_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_35_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_35_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_35_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_35_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_35_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_35_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_35_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_35_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_35_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_35_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_35_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_35_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_35_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_35_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_35_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_35_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_35_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_35_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_35_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_35_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_35_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_35_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_35_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_250 } ) ,
    .ccff_tail ( grid_clb_35_ccff_tail ) , .SC_IN_TOP ( scff_Wires_54_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_251 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_252 ) , 
    .SC_OUT_BOT ( scff_Wires_55_ ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_253 } ) ,
    .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_254 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_701 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_255 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_256 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_678 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_257 } ) ) ;
grid_clb grid_clb_4__1_ (
    .prog_clk ( { ctsbuf_net_5451463 } ) ,
    .Test_en ( Test_en__FEEDTHRU_218 ) ,
    .clk ( { ctsbuf_net_3921 } ) ,
    .top_width_0_height_0__pin_0_ ( cbx_1__1__33_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__33_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__33_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__33_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__33_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__33_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__33_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__33_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__33_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__33_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__33_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__33_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__33_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__33_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__33_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__33_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_33_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_258 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__36_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__36_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__36_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__36_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__36_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__36_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__36_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__36_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__36_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__36_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__36_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__36_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__36_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__36_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__36_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__36_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_4__1__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__24_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_36_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_36_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_36_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_36_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_36_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_36_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_36_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_36_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_36_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_36_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_36_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_36_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_36_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_36_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_36_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_36_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_36_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_36_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_36_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_36_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_36_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_36_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_36_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_36_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_36_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_36_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_36_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_36_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_36_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_36_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_36_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_36_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_36_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_259 } ) ,
    .ccff_tail ( grid_clb_36_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_260 ) , .SC_IN_BOT ( scff_Wires_81_ ) , 
    .SC_OUT_TOP ( scff_Wires_82_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_261 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_219 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_89 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_404 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_262 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_263 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { scff_Wires_80_ } ) ,
    .scff_Wires__FEEDTHRU_1 ( { scff_Wires__FEEDTHRU_1_80_ } ) ) ;
grid_clb grid_clb_4__2_ (
    .prog_clk ( { ctsbuf_net_5181436 } ) ,
    .Test_en ( Test_en__FEEDTHRU_220 ) , .clk ( clk__FEEDTHRU_89 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__34_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__34_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__34_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__34_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__34_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__34_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__34_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__34_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__34_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__34_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__34_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__34_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__34_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__34_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__34_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__34_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_34_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_264 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__37_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__37_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__37_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__37_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__37_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__37_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__37_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__37_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__37_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__37_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__37_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__37_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__37_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__37_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__37_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__37_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_4__2__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__25_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_37_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_37_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_37_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_37_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_37_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_37_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_37_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_37_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_37_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_37_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_37_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_37_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_37_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_37_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_37_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_37_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_37_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_37_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_37_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_37_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_37_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_37_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_37_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_37_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_37_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_37_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_37_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_37_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_37_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_37_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_37_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_37_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_37_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_265 } ) ,
    .ccff_tail ( grid_clb_37_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_266 ) , .SC_IN_BOT ( scff_Wires_83_ ) , 
    .SC_OUT_TOP ( scff_Wires_84_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_267 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_221 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_90 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_515 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_268 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_269 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_837 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_270 } ) ) ;
grid_clb grid_clb_4__3_ (
    .prog_clk ( { ctsbuf_net_4831401 } ) ,
    .Test_en ( Test_en__FEEDTHRU_222 ) , .clk ( clk__FEEDTHRU_90 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__35_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__35_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__35_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__35_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__35_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__35_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__35_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__35_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__35_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__35_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__35_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__35_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__35_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__35_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__35_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__35_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_35_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_271 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__38_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__38_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__38_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__38_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__38_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__38_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__38_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__38_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__38_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__38_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__38_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__38_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__38_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__38_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__38_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__38_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_4__3__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__26_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_38_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_38_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_38_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_38_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_38_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_38_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_38_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_38_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_38_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_38_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_38_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_38_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_38_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_38_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_38_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_38_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_38_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_38_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_38_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_38_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_38_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_38_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_38_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_38_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_38_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_38_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_38_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_38_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_38_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_38_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_38_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_38_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_38_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_272 } ) ,
    .ccff_tail ( grid_clb_38_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_273 ) , .SC_IN_BOT ( scff_Wires_85_ ) , 
    .SC_OUT_TOP ( scff_Wires_86_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_274 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_223 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_91 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_258 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_275 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_276 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_805 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_277 } ) ) ;
grid_clb grid_clb_4__4_ (
    .prog_clk ( { ctsbuf_net_4401358 } ) ,
    .Test_en ( Test_en__FEEDTHRU_224 ) , .clk ( clk__FEEDTHRU_91 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__36_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__36_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__36_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__36_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__36_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__36_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__36_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__36_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__36_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__36_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__36_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__36_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__36_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__36_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__36_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__36_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_36_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_278 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__39_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__39_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__39_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__39_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__39_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__39_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__39_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__39_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__39_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__39_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__39_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__39_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__39_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__39_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__39_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__39_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_4__4__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__27_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_39_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_39_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_39_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_39_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_39_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_39_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_39_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_39_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_39_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_39_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_39_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_39_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_39_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_39_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_39_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_39_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_39_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_39_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_39_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_39_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_39_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_39_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_39_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_39_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_39_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_39_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_39_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_39_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_39_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_39_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_39_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_39_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_39_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_279 } ) ,
    .ccff_tail ( grid_clb_39_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_280 ) , .SC_IN_BOT ( scff_Wires_87_ ) , 
    .SC_OUT_TOP ( scff_Wires_88_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_281 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_225 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_92 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_557 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_282 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_283 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_382 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_284 } ) ) ;
grid_clb grid_clb_4__5_ (
    .prog_clk ( { p_abuf36 } ) ,
    .Test_en ( Test_en__FEEDTHRU_226 ) , .clk ( clk__FEEDTHRU_92 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__37_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__37_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__37_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__37_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__37_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__37_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__37_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__37_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__37_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__37_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__37_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__37_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__37_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__37_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__37_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__37_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_37_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_285 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__40_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__40_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__40_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__40_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__40_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__40_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__40_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__40_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__40_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__40_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__40_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__40_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__40_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__40_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__40_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__40_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_4__5__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__28_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_40_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_40_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_40_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_40_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_40_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_40_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_40_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_40_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_40_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_40_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_40_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_40_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_40_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_40_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_40_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_40_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_40_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_40_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_40_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_40_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_40_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_40_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_40_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_40_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_40_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_40_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_40_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_40_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_40_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_40_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_40_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_40_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_40_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_286 } ) ,
    .ccff_tail ( grid_clb_40_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_287 ) , .SC_IN_BOT ( scff_Wires_89_ ) , 
    .SC_OUT_TOP ( scff_Wires_90_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_288 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_227 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_93 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_890 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_289 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_290 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_567 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_291 } ) ) ;
grid_clb grid_clb_4__6_ (
    .prog_clk ( { ctsbuf_net_3441262 } ) ,
    .Test_en ( Test_en__FEEDTHRU_228 ) , .clk ( clk__FEEDTHRU_93 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__38_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__38_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__38_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__38_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__38_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__38_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__38_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__38_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__38_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__38_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__38_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__38_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__38_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__38_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__38_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__38_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_38_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_292 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__41_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__41_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__41_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__41_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__41_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__41_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__41_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__41_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__41_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__41_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__41_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__41_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__41_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__41_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__41_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__41_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_4__6__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__29_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_41_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_41_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_41_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_41_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_41_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_41_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_41_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_41_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_41_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_41_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_41_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_41_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_41_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_41_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_41_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_41_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_41_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_41_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_41_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_41_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_41_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_41_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_41_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_41_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_41_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_41_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_41_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_41_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_41_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_41_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_41_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_41_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_41_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_293 } ) ,
    .ccff_tail ( grid_clb_41_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_294 ) , .SC_IN_BOT ( scff_Wires_91_ ) , 
    .SC_OUT_TOP ( scff_Wires_92_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_295 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_229 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_94 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_262 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_296 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_297 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_774 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_298 } ) ) ;
grid_clb grid_clb_4__7_ (
    .prog_clk ( { ctsbuf_net_2961214 } ) ,
    .Test_en ( Test_en__FEEDTHRU_230 ) , .clk ( clk__FEEDTHRU_94 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__39_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__39_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__39_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__39_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__39_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__39_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__39_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__39_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__39_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__39_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__39_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__39_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__39_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__39_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__39_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__39_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_39_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_299 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__42_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__42_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__42_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__42_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__42_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__42_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__42_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__42_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__42_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__42_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__42_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__42_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__42_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__42_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__42_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__42_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_4__7__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__30_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_42_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_42_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_42_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_42_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_42_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_42_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_42_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_42_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_42_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_42_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_42_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_42_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_42_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_42_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_42_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_42_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_42_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_42_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_42_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_42_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_42_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_42_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_42_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_42_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_42_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_42_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_42_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_42_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_42_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_42_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_42_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_42_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_42_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_300 } ) ,
    .ccff_tail ( grid_clb_42_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_301 ) , .SC_IN_BOT ( scff_Wires_93_ ) , 
    .SC_OUT_TOP ( scff_Wires_94_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_302 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_231 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_95 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_682 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_303 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_304 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_290 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_305 } ) ) ;
grid_clb grid_clb_4__8_ (
    .prog_clk ( { ctsbuf_net_2481166 } ) ,
    .Test_en ( Test_en__FEEDTHRU_232 ) , .clk ( clk__FEEDTHRU_95 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__40_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__40_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__40_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__40_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__40_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__40_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__40_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__40_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__40_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__40_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__40_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__40_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__40_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__40_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__40_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__40_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_40_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_306 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__43_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__43_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__43_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__43_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__43_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__43_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__43_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__43_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__43_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__43_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__43_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__43_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__43_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__43_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__43_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__43_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_4__8__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__31_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_43_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_43_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_43_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_43_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_43_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_43_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_43_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_43_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_43_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_43_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_43_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_43_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_43_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_43_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_43_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_43_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_43_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_43_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_43_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_43_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_43_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_43_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_43_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_43_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_43_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_43_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_43_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_43_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_43_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_43_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_43_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_43_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_43_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_307 } ) ,
    .ccff_tail ( grid_clb_43_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_308 ) , .SC_IN_BOT ( scff_Wires_95_ ) , 
    .SC_OUT_TOP ( scff_Wires_96_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_309 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_233 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_96 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_775 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_310 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_311 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_858 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_312 } ) ) ;
grid_clb grid_clb_4__9_ (
    .prog_clk ( { ctsbuf_net_2001118 } ) ,
    .Test_en ( Test_en__FEEDTHRU_234 ) , .clk ( clk__FEEDTHRU_96 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__41_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__41_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__41_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__41_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__41_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__41_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__41_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__41_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__41_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__41_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__41_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__41_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__41_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__41_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__41_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__41_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_41_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_313 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__44_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__44_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__44_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__44_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__44_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__44_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__44_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__44_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__44_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__44_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__44_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__44_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__44_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__44_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__44_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__44_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_4__9__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__32_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_44_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_44_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_44_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_44_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_44_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_44_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_44_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_44_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_44_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_44_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_44_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_44_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_44_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_44_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_44_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_44_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_44_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_44_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_44_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_44_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_44_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_44_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_44_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_44_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_44_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_44_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_44_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_44_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_44_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_44_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_44_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_44_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_44_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_314 } ) ,
    .ccff_tail ( grid_clb_44_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_315 ) , .SC_IN_BOT ( scff_Wires_97_ ) , 
    .SC_OUT_TOP ( scff_Wires_98_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_316 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_235 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_97 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_566 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_317 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_318 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_843 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_319 } ) ) ;
grid_clb grid_clb_4__10_ (
    .prog_clk ( { ctsbuf_net_1531071 } ) ,
    .Test_en ( Test_en__FEEDTHRU_236 ) , .clk ( clk__FEEDTHRU_97 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__42_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__42_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__42_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__42_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__42_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__42_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__42_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__42_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__42_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__42_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__42_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__42_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__42_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__42_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__42_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__42_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_42_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_320 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__45_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__45_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__45_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__45_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__45_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__45_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__45_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__45_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__45_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__45_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__45_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__45_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__45_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__45_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__45_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__45_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_4__10__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__33_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_45_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_45_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_45_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_45_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_45_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_45_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_45_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_45_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_45_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_45_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_45_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_45_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_45_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_45_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_45_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_45_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_45_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_45_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_45_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_45_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_45_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_45_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_45_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_45_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_45_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_45_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_45_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_45_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_45_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_45_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_45_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_45_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_45_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_321 } ) ,
    .ccff_tail ( grid_clb_45_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_322 ) , .SC_IN_BOT ( scff_Wires_99_ ) , 
    .SC_OUT_TOP ( scff_Wires_100_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_323 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_237 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_98 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_648 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_324 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_325 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_665 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_326 } ) ) ;
grid_clb grid_clb_4__11_ (
    .prog_clk ( { ctsbuf_net_1101028 } ) ,
    .Test_en ( Test_en__FEEDTHRU_238 ) , .clk ( clk__FEEDTHRU_98 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__43_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__43_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__43_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__43_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__43_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__43_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__43_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__43_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__43_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__43_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__43_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__43_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__43_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__43_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__43_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__43_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_43_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_327 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__46_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__46_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__46_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__46_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__46_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__46_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__46_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__46_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__46_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__46_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__46_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__46_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__46_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__46_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__46_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__46_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_4__11__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__34_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_46_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_46_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_46_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_46_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_46_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_46_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_46_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_46_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_46_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_46_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_46_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_46_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_46_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_46_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_46_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_46_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_46_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_46_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_46_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_46_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_46_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_46_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_46_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_46_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_46_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_46_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_46_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_46_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_46_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_46_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_46_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_46_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_46_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_328 } ) ,
    .ccff_tail ( grid_clb_46_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_329 ) , .SC_IN_BOT ( scff_Wires_101_ ) , 
    .SC_OUT_TOP ( scff_Wires_102_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_330 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_239 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_99 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_827 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_331 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_332 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_904 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_333 } ) ) ;
grid_clb grid_clb_4__12_ (
    .prog_clk ( { ctsbuf_net_74992 } ) ,
    .Test_en ( Test_en__FEEDTHRU_240 ) , .clk ( clk__FEEDTHRU_99 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__12__3_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__12__3_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__12__3_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__12__3_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__12__3_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__12__3_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__12__3_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__12__3_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__12__3_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__12__3_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__12__3_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__12__3_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__12__3_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__12__3_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__12__3_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__12__3_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_134_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_334 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__47_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__47_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__47_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__47_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__47_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__47_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__47_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__47_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__47_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__47_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__47_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__47_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__47_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__47_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__47_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__47_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_4__12__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__35_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_47_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_47_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_47_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_47_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_47_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_47_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_47_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_47_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_47_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_47_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_47_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_47_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_47_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_47_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_47_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_47_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_47_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_47_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_47_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_47_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_47_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_47_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_47_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_47_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_47_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_47_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_47_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_47_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_47_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_47_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_47_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_47_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_47_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_335 } ) ,
    .ccff_tail ( grid_clb_47_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_336 ) , .SC_IN_BOT ( scff_Wires_103_ ) , 
    .SC_OUT_TOP ( scff_Wires_104_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_337 ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_338 } ) ,
    .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_339 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_574 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_340 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_341 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_257 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_342 } ) ) ;
grid_clb grid_clb_5__1_ (
    .prog_clk ( { ctsbuf_net_5661484 } ) ,
    .Test_en ( Test_en__FEEDTHRU_241 ) ,
    .clk ( { ctsbuf_net_2920 } ) ,
    .top_width_0_height_0__pin_0_ ( cbx_1__1__44_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__44_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__44_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__44_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__44_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__44_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__44_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__44_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__44_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__44_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__44_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__44_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__44_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__44_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__44_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__44_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_44_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_343 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__48_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__48_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__48_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__48_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__48_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__48_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__48_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__48_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__48_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__48_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__48_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__48_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__48_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__48_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__48_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__48_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_5__1__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__36_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_48_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_48_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_48_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_48_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_48_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_48_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_48_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_48_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_48_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_48_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_48_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_48_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_48_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_48_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_48_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_48_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_48_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_48_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_48_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_48_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_48_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_48_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_48_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_48_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_48_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_48_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_48_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_48_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_48_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_48_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_48_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_48_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_48_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_344 } ) ,
    .ccff_tail ( grid_clb_48_ccff_tail ) , .SC_IN_TOP ( scff_Wires_129_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_345 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_346 ) , 
    .SC_OUT_BOT ( scff_Wires_131_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_242 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_78 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_790 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_347 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_348 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_710 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_349 } ) ) ;
grid_clb grid_clb_5__2_ (
    .prog_clk ( { ctsbuf_net_5471465 } ) ,
    .Test_en ( Test_en__FEEDTHRU_243 ) , .clk ( clk__FEEDTHRU_78 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__45_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__45_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__45_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__45_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__45_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__45_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__45_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__45_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__45_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__45_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__45_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__45_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__45_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__45_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__45_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__45_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_45_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_350 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__49_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__49_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__49_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__49_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__49_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__49_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__49_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__49_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__49_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__49_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__49_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__49_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__49_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__49_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__49_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__49_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_5__2__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__37_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_49_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_49_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_49_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_49_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_49_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_49_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_49_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_49_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_49_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_49_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_49_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_49_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_49_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_49_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_49_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_49_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_49_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_49_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_49_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_49_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_49_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_49_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_49_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_49_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_49_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_49_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_49_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_49_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_49_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_49_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_49_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_49_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_49_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_351 } ) ,
    .ccff_tail ( grid_clb_49_ccff_tail ) , .SC_IN_TOP ( scff_Wires_127_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_352 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_353 ) , 
    .SC_OUT_BOT ( scff_Wires_128_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_244 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_79 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_369 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_354 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_355 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_897 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_356 } ) ) ;
grid_clb grid_clb_5__3_ (
    .prog_clk ( { ctsbuf_net_5201438 } ) ,
    .Test_en ( Test_en__FEEDTHRU_245 ) , .clk ( clk__FEEDTHRU_79 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__46_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__46_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__46_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__46_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__46_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__46_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__46_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__46_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__46_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__46_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__46_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__46_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__46_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__46_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__46_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__46_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_46_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_357 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__50_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__50_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__50_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__50_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__50_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__50_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__50_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__50_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__50_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__50_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__50_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__50_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__50_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__50_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__50_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__50_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_5__3__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__38_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_50_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_50_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_50_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_50_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_50_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_50_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_50_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_50_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_50_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_50_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_50_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_50_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_50_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_50_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_50_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_50_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_50_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_50_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_50_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_50_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_50_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_50_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_50_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_50_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_50_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_50_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_50_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_50_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_50_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_50_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_50_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_50_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_50_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_358 } ) ,
    .ccff_tail ( grid_clb_50_ccff_tail ) , .SC_IN_TOP ( scff_Wires_125_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_359 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_360 ) , 
    .SC_OUT_BOT ( scff_Wires_126_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_246 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_80 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_503 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_361 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_362 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_887 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_363 } ) ) ;
grid_clb grid_clb_5__4_ (
    .prog_clk ( { ctsbuf_net_4851403 } ) ,
    .Test_en ( Test_en__FEEDTHRU_247 ) , .clk ( clk__FEEDTHRU_80 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__47_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__47_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__47_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__47_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__47_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__47_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__47_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__47_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__47_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__47_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__47_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__47_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__47_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__47_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__47_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__47_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_47_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_364 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__51_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__51_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__51_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__51_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__51_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__51_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__51_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__51_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__51_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__51_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__51_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__51_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__51_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__51_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__51_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__51_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_5__4__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__39_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_51_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_51_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_51_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_51_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_51_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_51_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_51_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_51_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_51_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_51_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_51_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_51_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_51_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_51_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_51_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_51_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_51_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_51_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_51_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_51_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_51_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_51_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_51_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_51_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_51_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_51_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_51_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_51_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_51_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_51_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_51_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_51_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_51_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_365 } ) ,
    .ccff_tail ( grid_clb_51_ccff_tail ) , .SC_IN_TOP ( scff_Wires_123_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_366 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_367 ) , 
    .SC_OUT_BOT ( scff_Wires_124_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_248 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_81 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_525 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_368 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_369 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_321 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_370 } ) ) ;
grid_clb grid_clb_5__5_ (
    .prog_clk ( { ctsbuf_net_4421360 } ) ,
    .Test_en ( Test_en__FEEDTHRU_249 ) , .clk ( clk__FEEDTHRU_81 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__48_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__48_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__48_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__48_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__48_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__48_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__48_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__48_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__48_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__48_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__48_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__48_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__48_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__48_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__48_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__48_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_48_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_371 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__52_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__52_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__52_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__52_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__52_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__52_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__52_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__52_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__52_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__52_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__52_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__52_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__52_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__52_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__52_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__52_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_5__5__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__40_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_52_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_52_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_52_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_52_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_52_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_52_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_52_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_52_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_52_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_52_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_52_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_52_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_52_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_52_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_52_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_52_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_52_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_52_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_52_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_52_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_52_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_52_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_52_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_52_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_52_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_52_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_52_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_52_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_52_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_52_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_52_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_52_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_52_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_372 } ) ,
    .ccff_tail ( grid_clb_52_ccff_tail ) , .SC_IN_TOP ( scff_Wires_121_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_373 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_374 ) , 
    .SC_OUT_BOT ( scff_Wires_122_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_250 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_82 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_458 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_375 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_376 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_443 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_377 } ) ) ;
grid_clb grid_clb_5__6_ (
    .prog_clk ( { ctsbuf_net_3941312 } ) ,
    .Test_en ( Test_en__FEEDTHRU_251 ) , .clk ( clk__FEEDTHRU_82 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__49_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__49_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__49_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__49_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__49_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__49_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__49_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__49_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__49_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__49_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__49_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__49_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__49_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__49_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__49_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__49_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_49_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_378 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__53_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__53_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__53_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__53_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__53_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__53_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__53_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__53_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__53_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__53_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__53_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__53_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__53_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__53_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__53_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__53_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_5__6__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__41_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_53_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_53_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_53_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_53_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_53_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_53_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_53_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_53_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_53_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_53_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_53_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_53_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_53_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_53_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_53_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_53_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_53_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_53_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_53_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_53_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_53_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_53_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_53_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_53_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_53_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_53_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_53_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_53_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_53_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_53_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_53_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_53_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_53_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_379 } ) ,
    .ccff_tail ( grid_clb_53_ccff_tail ) , .SC_IN_TOP ( scff_Wires_119_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_380 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_381 ) , 
    .SC_OUT_BOT ( scff_Wires_120_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_252 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_83 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_681 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_382 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_383 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_865 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_384 } ) ) ;
grid_clb grid_clb_5__7_ (
    .prog_clk ( { ctsbuf_net_3461264 } ) ,
    .Test_en ( Test_en__FEEDTHRU_253 ) , .clk ( clk__FEEDTHRU_83 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__50_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__50_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__50_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__50_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__50_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__50_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__50_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__50_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__50_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__50_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__50_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__50_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__50_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__50_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__50_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__50_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_50_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_385 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__54_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__54_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__54_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__54_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__54_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__54_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__54_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__54_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__54_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__54_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__54_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__54_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__54_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__54_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__54_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__54_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_5__7__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__42_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_54_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_54_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_54_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_54_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_54_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_54_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_54_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_54_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_54_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_54_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_54_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_54_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_54_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_54_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_54_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_54_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_54_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_54_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_54_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_54_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_54_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_54_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_54_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_54_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_54_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_54_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_54_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_54_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_54_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_54_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_54_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_54_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_54_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_386 } ) ,
    .ccff_tail ( grid_clb_54_ccff_tail ) , .SC_IN_TOP ( scff_Wires_117_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_387 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_388 ) , 
    .SC_OUT_BOT ( scff_Wires_118_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_254 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_84 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_490 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_389 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_390 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_508 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_391 } ) ) ;
grid_clb grid_clb_5__8_ (
    .prog_clk ( { ctsbuf_net_2981216 } ) ,
    .Test_en ( Test_en__FEEDTHRU_255 ) , .clk ( clk__FEEDTHRU_84 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__51_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__51_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__51_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__51_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__51_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__51_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__51_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__51_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__51_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__51_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__51_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__51_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__51_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__51_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__51_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__51_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_51_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_392 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__55_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__55_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__55_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__55_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__55_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__55_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__55_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__55_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__55_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__55_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__55_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__55_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__55_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__55_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__55_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__55_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_5__8__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__43_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_55_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_55_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_55_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_55_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_55_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_55_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_55_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_55_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_55_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_55_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_55_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_55_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_55_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_55_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_55_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_55_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_55_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_55_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_55_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_55_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_55_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_55_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_55_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_55_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_55_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_55_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_55_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_55_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_55_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_55_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_55_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_55_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_55_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_393 } ) ,
    .ccff_tail ( grid_clb_55_ccff_tail ) , .SC_IN_TOP ( scff_Wires_115_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_394 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_395 ) , 
    .SC_OUT_BOT ( scff_Wires_116_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_256 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_85 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_293 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_396 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_397 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_867 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_398 } ) ) ;
grid_clb grid_clb_5__9_ (
    .prog_clk ( { p_abuf30 } ) ,
    .Test_en ( Test_en__FEEDTHRU_257 ) , .clk ( clk__FEEDTHRU_85 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__52_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__52_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__52_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__52_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__52_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__52_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__52_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__52_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__52_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__52_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__52_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__52_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__52_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__52_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__52_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__52_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_52_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_399 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__56_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__56_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__56_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__56_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__56_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__56_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__56_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__56_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__56_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__56_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__56_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__56_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__56_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__56_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__56_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__56_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_5__9__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__44_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_56_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_56_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_56_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_56_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_56_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_56_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_56_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_56_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_56_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_56_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_56_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_56_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_56_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_56_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_56_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_56_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_56_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_56_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_56_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_56_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_56_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_56_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_56_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_56_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_56_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_56_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_56_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_56_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_56_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_56_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_56_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_56_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_56_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_400 } ) ,
    .ccff_tail ( grid_clb_56_ccff_tail ) , .SC_IN_TOP ( scff_Wires_113_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_401 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_402 ) , 
    .SC_OUT_BOT ( scff_Wires_114_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_258 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_86 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_829 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_403 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_404 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_722 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_405 } ) ) ;
grid_clb grid_clb_5__10_ (
    .prog_clk ( { ctsbuf_net_2021120 } ) ,
    .Test_en ( Test_en__FEEDTHRU_259 ) , .clk ( clk__FEEDTHRU_86 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__53_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__53_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__53_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__53_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__53_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__53_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__53_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__53_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__53_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__53_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__53_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__53_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__53_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__53_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__53_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__53_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_53_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_406 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__57_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__57_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__57_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__57_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__57_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__57_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__57_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__57_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__57_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__57_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__57_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__57_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__57_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__57_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__57_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__57_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_5__10__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__45_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_57_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_57_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_57_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_57_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_57_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_57_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_57_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_57_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_57_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_57_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_57_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_57_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_57_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_57_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_57_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_57_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_57_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_57_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_57_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_57_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_57_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_57_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_57_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_57_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_57_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_57_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_57_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_57_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_57_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_57_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_57_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_57_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_57_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_407 } ) ,
    .ccff_tail ( grid_clb_57_ccff_tail ) , .SC_IN_TOP ( scff_Wires_111_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_408 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_409 ) , 
    .SC_OUT_BOT ( scff_Wires_112_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_260 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_87 ) , 
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_19 ) , 
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_20 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_410 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_286 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_411 } ) ) ;
grid_clb grid_clb_5__11_ (
    .prog_clk ( { p_abuf16 } ) ,
    .Test_en ( Test_en__FEEDTHRU_261 ) , .clk ( clk__FEEDTHRU_87 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__54_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__54_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__54_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__54_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__54_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__54_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__54_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__54_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__54_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__54_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__54_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__54_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__54_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__54_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__54_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__54_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_54_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_412 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__58_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__58_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__58_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__58_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__58_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__58_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__58_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__58_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__58_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__58_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__58_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__58_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__58_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__58_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__58_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__58_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_5__11__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__46_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_58_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_58_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_58_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_58_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_58_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_58_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_58_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_58_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_58_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_58_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_58_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_58_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_58_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_58_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_58_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_58_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_58_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_58_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_58_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_58_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_58_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_58_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_58_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_58_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_58_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_58_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_58_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_58_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_58_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_58_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_58_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_58_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_58_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_413 } ) ,
    .ccff_tail ( grid_clb_58_ccff_tail ) , .SC_IN_TOP ( scff_Wires_109_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_414 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_415 ) , 
    .SC_OUT_BOT ( scff_Wires_110_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_262 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_88 ) , 
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_21 ) , 
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_22 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_416 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_881 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_417 } ) ) ;
grid_clb grid_clb_5__12_ (
    .prog_clk ( { ctsbuf_net_1111029 } ) ,
    .Test_en ( Test_en__FEEDTHRU_263 ) , .clk ( clk__FEEDTHRU_88 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__12__4_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__12__4_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__12__4_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__12__4_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__12__4_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__12__4_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__12__4_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__12__4_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__12__4_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__12__4_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__12__4_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__12__4_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__12__4_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__12__4_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__12__4_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__12__4_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_135_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_418 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__59_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__59_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__59_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__59_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__59_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__59_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__59_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__59_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__59_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__59_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__59_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__59_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__59_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__59_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__59_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__59_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_5__12__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__47_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_59_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_59_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_59_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_59_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_59_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_59_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_59_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_59_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_59_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_59_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_59_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_59_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_59_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_59_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_59_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_59_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_59_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_59_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_59_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_59_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_59_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_59_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_59_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_59_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_59_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_59_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_59_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_59_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_59_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_59_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_59_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_59_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_59_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_419 } ) ,
    .ccff_tail ( grid_clb_59_ccff_tail ) , .SC_IN_TOP ( scff_Wires_107_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_420 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_421 ) , 
    .SC_OUT_BOT ( scff_Wires_108_ ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_422 } ) ,
    .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_423 } ) ,
    
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_23 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_424 } ) ,
    
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_24 ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_899 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_425 } ) ) ;
grid_clb grid_clb_6__1_ (
    .prog_clk ( { ctsbuf_net_5781496 } ) ,
    .Test_en ( Test_en__FEEDTHRU_264 ) ,
    .clk ( { ctsbuf_net_2920 } ) ,
    .top_width_0_height_0__pin_0_ ( cbx_1__1__55_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__55_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__55_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__55_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__55_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__55_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__55_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__55_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__55_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__55_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__55_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__55_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__55_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__55_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__55_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__55_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_55_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_426 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__60_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__60_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__60_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__60_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__60_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__60_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__60_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__60_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__60_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__60_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__60_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__60_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__60_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__60_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__60_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__60_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_6__1__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__48_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_60_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_60_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_60_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_60_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_60_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_60_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_60_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_60_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_60_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_60_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_60_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_60_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_60_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_60_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_60_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_60_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_60_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_60_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_60_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_60_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_60_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_60_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_60_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_60_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_60_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_60_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_60_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_60_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_60_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_60_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_60_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_60_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_60_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_427 } ) ,
    .ccff_tail ( grid_clb_60_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_428 ) , .SC_IN_BOT ( scff_Wires_134_ ) , 
    .SC_OUT_TOP ( scff_Wires_135_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_429 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_265 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_67 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_463 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_430 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_431 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { scff_Wires_133_ } ) ,
    .scff_Wires__FEEDTHRU_1 ( { scff_Wires__FEEDTHRU_1_133_ } ) ) ;
grid_clb grid_clb_6__2_ (
    .prog_clk ( { ctsbuf_net_5671485 } ) ,
    .Test_en ( Test_en__FEEDTHRU_266 ) , .clk ( clk__FEEDTHRU_67 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__56_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__56_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__56_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__56_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__56_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__56_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__56_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__56_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__56_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__56_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__56_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__56_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__56_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__56_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__56_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__56_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_56_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_432 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__61_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__61_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__61_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__61_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__61_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__61_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__61_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__61_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__61_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__61_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__61_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__61_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__61_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__61_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__61_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__61_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_6__2__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__49_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_61_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_61_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_61_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_61_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_61_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_61_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_61_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_61_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_61_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_61_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_61_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_61_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_61_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_61_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_61_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_61_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_61_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_61_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_61_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_61_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_61_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_61_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_61_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_61_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_61_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_61_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_61_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_61_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_61_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_61_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_61_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_61_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_61_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_433 } ) ,
    .ccff_tail ( grid_clb_61_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_434 ) , .SC_IN_BOT ( scff_Wires_136_ ) , 
    .SC_OUT_TOP ( scff_Wires_137_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_435 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_267 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_68 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_406 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_436 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_437 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_533 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_438 } ) ) ;
grid_clb grid_clb_6__3_ (
    .prog_clk ( { ctsbuf_net_5481466 } ) ,
    .Test_en ( Test_en__FEEDTHRU_268 ) , .clk ( clk__FEEDTHRU_68 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__57_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__57_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__57_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__57_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__57_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__57_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__57_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__57_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__57_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__57_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__57_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__57_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__57_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__57_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__57_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__57_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_57_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_439 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__62_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__62_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__62_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__62_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__62_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__62_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__62_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__62_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__62_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__62_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__62_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__62_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__62_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__62_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__62_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__62_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_6__3__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__50_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_62_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_62_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_62_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_62_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_62_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_62_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_62_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_62_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_62_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_62_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_62_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_62_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_62_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_62_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_62_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_62_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_62_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_62_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_62_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_62_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_62_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_62_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_62_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_62_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_62_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_62_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_62_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_62_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_62_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_62_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_62_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_62_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_62_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_440 } ) ,
    .ccff_tail ( grid_clb_62_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_441 ) , .SC_IN_BOT ( scff_Wires_138_ ) , 
    .SC_OUT_TOP ( scff_Wires_139_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_442 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_269 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_69 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_649 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_443 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_444 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_394 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_445 } ) ) ;
grid_clb grid_clb_6__4_ (
    .prog_clk ( { ctsbuf_net_5211439 } ) ,
    .Test_en ( Test_en__FEEDTHRU_270 ) , .clk ( clk__FEEDTHRU_69 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__58_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__58_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__58_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__58_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__58_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__58_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__58_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__58_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__58_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__58_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__58_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__58_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__58_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__58_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__58_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__58_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_58_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_446 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__63_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__63_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__63_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__63_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__63_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__63_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__63_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__63_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__63_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__63_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__63_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__63_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__63_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__63_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__63_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__63_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_6__4__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__51_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_63_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_63_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_63_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_63_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_63_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_63_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_63_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_63_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_63_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_63_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_63_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_63_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_63_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_63_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_63_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_63_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_63_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_63_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_63_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_63_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_63_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_63_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_63_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_63_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_63_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_63_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_63_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_63_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_63_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_63_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_63_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_63_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_63_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_447 } ) ,
    .ccff_tail ( grid_clb_63_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_448 ) , .SC_IN_BOT ( scff_Wires_140_ ) , 
    .SC_OUT_TOP ( scff_Wires_141_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_449 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_271 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_70 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_628 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_450 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_451 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_799 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_452 } ) ) ;
grid_clb grid_clb_6__5_ (
    .prog_clk ( { p_abuf43 } ) ,
    .Test_en ( Test_en__FEEDTHRU_272 ) , .clk ( clk__FEEDTHRU_70 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__59_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__59_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__59_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__59_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__59_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__59_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__59_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__59_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__59_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__59_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__59_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__59_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__59_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__59_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__59_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__59_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_59_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_453 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__64_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__64_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__64_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__64_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__64_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__64_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__64_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__64_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__64_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__64_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__64_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__64_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__64_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__64_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__64_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__64_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_6__5__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__52_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_64_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_64_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_64_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_64_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_64_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_64_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_64_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_64_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_64_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_64_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_64_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_64_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_64_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_64_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_64_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_64_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_64_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_64_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_64_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_64_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_64_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_64_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_64_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_64_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_64_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_64_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_64_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_64_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_64_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_64_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_64_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_64_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_64_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_454 } ) ,
    .ccff_tail ( grid_clb_64_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_455 ) , .SC_IN_BOT ( scff_Wires_142_ ) , 
    .SC_OUT_TOP ( scff_Wires_143_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_456 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_273 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_71 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_483 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_457 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_458 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_620 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_459 } ) ) ;
grid_clb grid_clb_6__6_ (
    .prog_clk ( { ctsbuf_net_4431361 } ) ,
    .Test_en ( Test_en__FEEDTHRU_274 ) , .clk ( clk__FEEDTHRU_71 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__60_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__60_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__60_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__60_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__60_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__60_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__60_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__60_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__60_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__60_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__60_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__60_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__60_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__60_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__60_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__60_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_60_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_460 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__65_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__65_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__65_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__65_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__65_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__65_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__65_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__65_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__65_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__65_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__65_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__65_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__65_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__65_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__65_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__65_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_6__6__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__53_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_65_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_65_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_65_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_65_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_65_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_65_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_65_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_65_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_65_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_65_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_65_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_65_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_65_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_65_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_65_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_65_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_65_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_65_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_65_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_65_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_65_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_65_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_65_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_65_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_65_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_65_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_65_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_65_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_65_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_65_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_65_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_65_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_65_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_461 } ) ,
    .ccff_tail ( grid_clb_65_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_462 ) , .SC_IN_BOT ( scff_Wires_144_ ) , 
    .SC_OUT_TOP ( scff_Wires_145_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_463 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_275 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_72 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_779 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_464 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_465 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_377 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_466 } ) ) ;
grid_clb grid_clb_6__7_ (
    .prog_clk ( { ctsbuf_net_3951313 } ) ,
    .Test_en ( Test_en__FEEDTHRU_276 ) , .clk ( clk__FEEDTHRU_72 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__61_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__61_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__61_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__61_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__61_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__61_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__61_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__61_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__61_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__61_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__61_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__61_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__61_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__61_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__61_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__61_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_61_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_467 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__66_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__66_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__66_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__66_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__66_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__66_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__66_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__66_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__66_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__66_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__66_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__66_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__66_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__66_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__66_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__66_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_6__7__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__54_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_66_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_66_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_66_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_66_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_66_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_66_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_66_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_66_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_66_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_66_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_66_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_66_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_66_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_66_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_66_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_66_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_66_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_66_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_66_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_66_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_66_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_66_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_66_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_66_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_66_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_66_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_66_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_66_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_66_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_66_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_66_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_66_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_66_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_468 } ) ,
    .ccff_tail ( grid_clb_66_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_469 ) , .SC_IN_BOT ( scff_Wires_146_ ) , 
    .SC_OUT_TOP ( scff_Wires_147_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_470 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_277 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_73 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_597 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_471 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_472 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_300 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_473 } ) ) ;
grid_clb grid_clb_6__8_ (
    .prog_clk ( { ctsbuf_net_3471265 } ) ,
    .Test_en ( Test_en__FEEDTHRU_278 ) , .clk ( clk__FEEDTHRU_73 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__62_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__62_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__62_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__62_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__62_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__62_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__62_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__62_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__62_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__62_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__62_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__62_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__62_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__62_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__62_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__62_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_62_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_474 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__67_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__67_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__67_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__67_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__67_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__67_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__67_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__67_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__67_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__67_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__67_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__67_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__67_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__67_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__67_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__67_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_6__8__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__55_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_67_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_67_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_67_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_67_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_67_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_67_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_67_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_67_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_67_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_67_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_67_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_67_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_67_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_67_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_67_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_67_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_67_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_67_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_67_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_67_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_67_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_67_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_67_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_67_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_67_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_67_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_67_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_67_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_67_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_67_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_67_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_67_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_67_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_475 } ) ,
    .ccff_tail ( grid_clb_67_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_476 ) , .SC_IN_BOT ( scff_Wires_148_ ) , 
    .SC_OUT_TOP ( scff_Wires_149_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_477 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_279 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_74 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_375 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_478 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_479 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_415 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_480 } ) ) ;
grid_clb grid_clb_6__9_ (
    .prog_clk ( { ctsbuf_net_2991217 } ) ,
    .Test_en ( Test_en__FEEDTHRU_280 ) , .clk ( clk__FEEDTHRU_74 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__63_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__63_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__63_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__63_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__63_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__63_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__63_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__63_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__63_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__63_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__63_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__63_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__63_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__63_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__63_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__63_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_63_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_481 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__68_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__68_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__68_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__68_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__68_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__68_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__68_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__68_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__68_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__68_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__68_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__68_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__68_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__68_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__68_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__68_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_6__9__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__56_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_68_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_68_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_68_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_68_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_68_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_68_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_68_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_68_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_68_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_68_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_68_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_68_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_68_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_68_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_68_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_68_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_68_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_68_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_68_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_68_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_68_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_68_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_68_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_68_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_68_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_68_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_68_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_68_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_68_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_68_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_68_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_68_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_68_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_482 } ) ,
    .ccff_tail ( grid_clb_68_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_483 ) , .SC_IN_BOT ( scff_Wires_150_ ) , 
    .SC_OUT_TOP ( scff_Wires_151_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_484 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_281 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_75 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_552 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_485 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_486 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_556 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_487 } ) ) ;
grid_clb grid_clb_6__10_ (
    .prog_clk ( { ctsbuf_net_2511169 } ) ,
    .Test_en ( Test_en__FEEDTHRU_282 ) , .clk ( clk__FEEDTHRU_75 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__64_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__64_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__64_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__64_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__64_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__64_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__64_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__64_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__64_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__64_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__64_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__64_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__64_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__64_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__64_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__64_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_64_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_488 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__69_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__69_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__69_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__69_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__69_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__69_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__69_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__69_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__69_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__69_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__69_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__69_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__69_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__69_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__69_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__69_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_6__10__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__57_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_69_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_69_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_69_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_69_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_69_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_69_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_69_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_69_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_69_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_69_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_69_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_69_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_69_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_69_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_69_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_69_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_69_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_69_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_69_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_69_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_69_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_69_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_69_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_69_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_69_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_69_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_69_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_69_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_69_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_69_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_69_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_69_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_69_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_489 } ) ,
    .ccff_tail ( grid_clb_69_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_490 ) , .SC_IN_BOT ( scff_Wires_152_ ) , 
    .SC_OUT_TOP ( scff_Wires_153_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_491 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_283 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_76 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_657 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_492 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_493 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_737 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_494 } ) ) ;
grid_clb grid_clb_6__11_ (
    .prog_clk ( { ctsbuf_net_2031121 } ) ,
    .Test_en ( Test_en__FEEDTHRU_284 ) , .clk ( clk__FEEDTHRU_76 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__65_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__65_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__65_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__65_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__65_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__65_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__65_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__65_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__65_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__65_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__65_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__65_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__65_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__65_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__65_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__65_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_65_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_495 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__70_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__70_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__70_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__70_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__70_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__70_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__70_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__70_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__70_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__70_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__70_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__70_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__70_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__70_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__70_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__70_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_6__11__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__58_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_70_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_70_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_70_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_70_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_70_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_70_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_70_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_70_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_70_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_70_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_70_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_70_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_70_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_70_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_70_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_70_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_70_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_70_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_70_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_70_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_70_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_70_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_70_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_70_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_70_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_70_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_70_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_70_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_70_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_70_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_70_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_70_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_70_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_496 } ) ,
    .ccff_tail ( grid_clb_70_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_497 ) , .SC_IN_BOT ( scff_Wires_154_ ) , 
    .SC_OUT_TOP ( scff_Wires_155_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_498 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_285 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_77 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_501 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_499 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_500 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_260 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_501 } ) ) ;
grid_clb grid_clb_6__12_ (
    .prog_clk ( { ctsbuf_net_1551073 } ) ,
    .Test_en ( Test_en__FEEDTHRU_286 ) , .clk ( clk__FEEDTHRU_77 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__12__5_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__12__5_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__12__5_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__12__5_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__12__5_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__12__5_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__12__5_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__12__5_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__12__5_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__12__5_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__12__5_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__12__5_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__12__5_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__12__5_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__12__5_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__12__5_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_136_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_502 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__71_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__71_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__71_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__71_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__71_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__71_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__71_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__71_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__71_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__71_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__71_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__71_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__71_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__71_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__71_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__71_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_6__12__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__59_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_71_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_71_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_71_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_71_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_71_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_71_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_71_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_71_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_71_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_71_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_71_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_71_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_71_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_71_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_71_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_71_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_71_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_71_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_71_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_71_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_71_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_71_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_71_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_71_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_71_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_71_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_71_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_71_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_71_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_71_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_71_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_71_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_71_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_503 } ) ,
    .ccff_tail ( grid_clb_71_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_504 ) , .SC_IN_BOT ( scff_Wires_156_ ) , 
    .SC_OUT_TOP ( scff_Wires_157_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_505 ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_506 } ) ,
    .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_507 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_772 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_508 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_509 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_604 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_510 } ) ) ;
grid_clb grid_clb_7__1_ (
    .prog_clk ( { ctsbuf_net_5801498 } ) ,
    .Test_en ( Test_en__FEEDTHRU_1 ) , .clk ( clk ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__66_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__66_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__66_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__66_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__66_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__66_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__66_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__66_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__66_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__66_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__66_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__66_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__66_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__66_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__66_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__66_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_66_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_511 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__72_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__72_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__72_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__72_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__72_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__72_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__72_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__72_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__72_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__72_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__72_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__72_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__72_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__72_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__72_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__72_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_7__1__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__60_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_72_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_72_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_72_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_72_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_72_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_72_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_72_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_72_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_72_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_72_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_72_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_72_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_72_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_72_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_72_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_72_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_72_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_72_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_72_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_72_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_72_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_72_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_72_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_72_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_72_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_72_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_72_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_72_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_72_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_72_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_72_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_72_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_72_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_512 } ) ,
    .ccff_tail ( grid_clb_72_ccff_tail ) , .SC_IN_TOP ( scff_Wires_182_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_513 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_514 ) , 
    .SC_OUT_BOT ( scff_Wires_184_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_2 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_56 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_326 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_515 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_516 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_256 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_517 } ) ) ;
grid_clb grid_clb_7__2_ (
    .prog_clk ( { ctsbuf_net_5711489 } ) ,
    .Test_en ( Test_en__FEEDTHRU_3 ) , .clk ( clk__FEEDTHRU_56 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__67_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__67_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__67_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__67_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__67_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__67_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__67_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__67_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__67_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__67_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__67_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__67_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__67_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__67_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__67_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__67_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_67_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_518 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__73_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__73_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__73_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__73_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__73_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__73_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__73_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__73_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__73_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__73_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__73_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__73_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__73_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__73_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__73_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__73_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_7__2__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__61_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_73_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_73_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_73_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_73_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_73_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_73_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_73_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_73_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_73_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_73_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_73_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_73_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_73_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_73_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_73_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_73_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_73_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_73_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_73_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_73_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_73_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_73_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_73_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_73_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_73_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_73_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_73_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_73_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_73_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_73_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_73_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_73_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_73_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_519 } ) ,
    .ccff_tail ( grid_clb_73_ccff_tail ) , .SC_IN_TOP ( scff_Wires_180_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_520 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_521 ) , 
    .SC_OUT_BOT ( scff_Wires_181_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_4 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_57 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_327 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_522 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_523 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_371 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_524 } ) ) ;
grid_clb grid_clb_7__3_ (
    .prog_clk ( { ctsbuf_net_5551473 } ) ,
    .Test_en ( Test_en__FEEDTHRU_5 ) , .clk ( clk__FEEDTHRU_57 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__68_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__68_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__68_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__68_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__68_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__68_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__68_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__68_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__68_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__68_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__68_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__68_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__68_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__68_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__68_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__68_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_68_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_525 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__74_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__74_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__74_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__74_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__74_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__74_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__74_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__74_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__74_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__74_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__74_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__74_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__74_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__74_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__74_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__74_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_7__3__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__62_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_74_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_74_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_74_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_74_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_74_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_74_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_74_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_74_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_74_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_74_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_74_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_74_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_74_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_74_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_74_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_74_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_74_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_74_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_74_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_74_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_74_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_74_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_74_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_74_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_74_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_74_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_74_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_74_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_74_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_74_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_74_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_74_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_74_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_526 } ) ,
    .ccff_tail ( grid_clb_74_ccff_tail ) , .SC_IN_TOP ( scff_Wires_178_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_527 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_528 ) , 
    .SC_OUT_BOT ( scff_Wires_179_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_6 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_58 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_718 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_529 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_530 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_397 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_531 } ) ) ;
grid_clb grid_clb_7__4_ (
    .prog_clk ( { ctsbuf_net_5311449 } ) ,
    .Test_en ( Test_en__FEEDTHRU_7 ) , .clk ( clk__FEEDTHRU_58 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__69_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__69_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__69_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__69_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__69_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__69_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__69_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__69_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__69_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__69_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__69_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__69_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__69_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__69_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__69_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__69_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_69_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_532 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__75_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__75_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__75_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__75_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__75_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__75_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__75_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__75_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__75_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__75_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__75_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__75_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__75_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__75_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__75_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__75_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_7__4__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__63_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_75_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_75_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_75_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_75_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_75_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_75_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_75_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_75_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_75_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_75_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_75_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_75_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_75_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_75_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_75_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_75_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_75_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_75_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_75_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_75_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_75_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_75_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_75_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_75_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_75_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_75_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_75_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_75_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_75_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_75_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_75_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_75_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_75_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_533 } ) ,
    .ccff_tail ( grid_clb_75_ccff_tail ) , .SC_IN_TOP ( scff_Wires_176_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_534 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_535 ) , 
    .SC_OUT_BOT ( scff_Wires_177_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_8 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_59 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_393 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_536 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_537 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_651 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_538 } ) ) ;
grid_clb grid_clb_7__5_ (
    .prog_clk ( { p_abuf45 } ) ,
    .Test_en ( Test_en__FEEDTHRU_9 ) , .clk ( clk__FEEDTHRU_59 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__70_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__70_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__70_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__70_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__70_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__70_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__70_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__70_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__70_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__70_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__70_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__70_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__70_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__70_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__70_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__70_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_70_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_539 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__76_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__76_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__76_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__76_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__76_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__76_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__76_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__76_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__76_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__76_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__76_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__76_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__76_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__76_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__76_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__76_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_7__5__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__64_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_76_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_76_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_76_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_76_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_76_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_76_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_76_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_76_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_76_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_76_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_76_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_76_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_76_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_76_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_76_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_76_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_76_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_76_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_76_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_76_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_76_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_76_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_76_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_76_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_76_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_76_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_76_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_76_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_76_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_76_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_76_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_76_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_76_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_540 } ) ,
    .ccff_tail ( grid_clb_76_ccff_tail ) , .SC_IN_TOP ( scff_Wires_174_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_541 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_542 ) , 
    .SC_OUT_BOT ( scff_Wires_175_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_10 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_60 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_353 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_543 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_544 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_690 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_545 } ) ) ;
grid_clb grid_clb_7__6_ (
    .prog_clk ( { ctsbuf_net_4611379 } ) ,
    .Test_en ( Test_en__FEEDTHRU_11 ) , .clk ( clk__FEEDTHRU_60 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__71_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__71_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__71_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__71_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__71_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__71_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__71_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__71_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__71_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__71_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__71_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__71_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__71_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__71_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__71_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__71_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_71_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_546 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__77_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__77_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__77_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__77_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__77_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__77_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__77_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__77_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__77_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__77_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__77_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__77_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__77_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__77_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__77_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__77_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_7__6__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__65_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_77_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_77_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_77_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_77_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_77_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_77_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_77_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_77_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_77_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_77_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_77_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_77_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_77_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_77_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_77_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_77_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_77_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_77_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_77_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_77_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_77_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_77_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_77_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_77_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_77_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_77_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_77_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_77_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_77_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_77_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_77_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_77_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_77_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_547 } ) ,
    .ccff_tail ( grid_clb_77_ccff_tail ) , .SC_IN_TOP ( scff_Wires_172_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_548 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_549 ) , 
    .SC_OUT_BOT ( scff_Wires_173_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_12 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_61 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_511 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_550 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_551 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_493 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_552 } ) ) ;
grid_clb grid_clb_7__7_ (
    .prog_clk ( { p_abuf35 } ) ,
    .Test_en ( Test_en__FEEDTHRU_13 ) , .clk ( clk__FEEDTHRU_61 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__72_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__72_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__72_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__72_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__72_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__72_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__72_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__72_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__72_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__72_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__72_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__72_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__72_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__72_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__72_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__72_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_72_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_553 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__78_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__78_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__78_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__78_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__78_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__78_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__78_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__78_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__78_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__78_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__78_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__78_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__78_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__78_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__78_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__78_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_7__7__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__66_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_78_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_78_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_78_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_78_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_78_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_78_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_78_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_78_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_78_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_78_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_78_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_78_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_78_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_78_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_78_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_78_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_78_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_78_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_78_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_78_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_78_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_78_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_78_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_78_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_78_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_78_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_78_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_78_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_78_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_78_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_78_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_78_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_78_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_554 } ) ,
    .ccff_tail ( grid_clb_78_ccff_tail ) , .SC_IN_TOP ( scff_Wires_170_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_555 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_556 ) , 
    .SC_OUT_BOT ( scff_Wires_171_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_14 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_62 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_730 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_557 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_558 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_289 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_559 } ) ) ;
grid_clb grid_clb_7__8_ (
    .prog_clk ( { ctsbuf_net_3651283 } ) ,
    .Test_en ( Test_en__FEEDTHRU_15 ) , .clk ( clk__FEEDTHRU_62 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__73_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__73_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__73_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__73_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__73_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__73_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__73_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__73_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__73_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__73_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__73_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__73_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__73_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__73_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__73_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__73_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_73_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_560 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__79_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__79_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__79_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__79_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__79_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__79_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__79_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__79_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__79_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__79_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__79_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__79_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__79_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__79_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__79_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__79_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_7__8__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__67_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_79_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_79_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_79_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_79_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_79_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_79_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_79_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_79_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_79_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_79_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_79_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_79_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_79_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_79_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_79_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_79_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_79_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_79_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_79_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_79_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_79_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_79_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_79_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_79_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_79_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_79_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_79_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_79_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_79_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_79_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_79_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_79_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_79_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_561 } ) ,
    .ccff_tail ( grid_clb_79_ccff_tail ) , .SC_IN_TOP ( scff_Wires_168_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_562 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_563 ) , 
    .SC_OUT_BOT ( scff_Wires_169_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_16 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_63 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_455 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_564 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_565 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_629 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_566 } ) ) ;
grid_clb grid_clb_7__9_ (
    .prog_clk ( { ctsbuf_net_3171235 } ) ,
    .Test_en ( Test_en__FEEDTHRU_17 ) , .clk ( clk__FEEDTHRU_63 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__74_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__74_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__74_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__74_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__74_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__74_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__74_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__74_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__74_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__74_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__74_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__74_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__74_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__74_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__74_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__74_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_74_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_567 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__80_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__80_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__80_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__80_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__80_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__80_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__80_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__80_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__80_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__80_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__80_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__80_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__80_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__80_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__80_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__80_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_7__9__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__68_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_80_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_80_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_80_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_80_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_80_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_80_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_80_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_80_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_80_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_80_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_80_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_80_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_80_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_80_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_80_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_80_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_80_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_80_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_80_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_80_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_80_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_80_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_80_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_80_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_80_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_80_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_80_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_80_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_80_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_80_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_80_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_80_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_80_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_568 } ) ,
    .ccff_tail ( grid_clb_80_ccff_tail ) , .SC_IN_TOP ( scff_Wires_166_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_569 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_570 ) , 
    .SC_OUT_BOT ( scff_Wires_167_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_18 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_64 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_524 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_571 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_572 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_581 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_573 } ) ) ;
grid_clb grid_clb_7__10_ (
    .prog_clk ( { ctsbuf_net_2691187 } ) ,
    .Test_en ( Test_en__FEEDTHRU_19 ) , .clk ( clk__FEEDTHRU_64 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__75_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__75_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__75_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__75_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__75_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__75_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__75_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__75_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__75_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__75_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__75_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__75_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__75_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__75_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__75_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__75_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_75_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_574 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__81_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__81_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__81_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__81_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__81_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__81_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__81_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__81_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__81_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__81_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__81_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__81_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__81_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__81_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__81_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__81_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_7__10__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__69_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_81_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_81_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_81_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_81_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_81_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_81_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_81_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_81_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_81_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_81_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_81_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_81_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_81_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_81_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_81_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_81_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_81_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_81_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_81_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_81_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_81_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_81_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_81_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_81_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_81_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_81_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_81_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_81_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_81_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_81_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_81_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_81_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_81_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_575 } ) ,
    .ccff_tail ( grid_clb_81_ccff_tail ) , .SC_IN_TOP ( scff_Wires_164_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_576 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_577 ) , 
    .SC_OUT_BOT ( scff_Wires_165_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_20 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_65 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_416 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_578 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_579 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_848 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_580 } ) ) ;
grid_clb grid_clb_7__11_ (
    .prog_clk ( { ctsbuf_net_2211139 } ) ,
    .Test_en ( Test_en__FEEDTHRU_21 ) , .clk ( clk__FEEDTHRU_65 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__76_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__76_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__76_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__76_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__76_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__76_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__76_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__76_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__76_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__76_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__76_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__76_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__76_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__76_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__76_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__76_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_76_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_581 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__82_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__82_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__82_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__82_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__82_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__82_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__82_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__82_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__82_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__82_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__82_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__82_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__82_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__82_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__82_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__82_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_7__11__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__70_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_82_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_82_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_82_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_82_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_82_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_82_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_82_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_82_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_82_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_82_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_82_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_82_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_82_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_82_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_82_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_82_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_82_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_82_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_82_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_82_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_82_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_82_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_82_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_82_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_82_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_82_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_82_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_82_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_82_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_82_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_82_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_82_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_82_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_582 } ) ,
    .ccff_tail ( grid_clb_82_ccff_tail ) , .SC_IN_TOP ( scff_Wires_162_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_583 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_584 ) , 
    .SC_OUT_BOT ( scff_Wires_163_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_22 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_66 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_635 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_585 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_586 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_439 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_587 } ) ) ;
grid_clb grid_clb_7__12_ (
    .prog_clk ( { ctsbuf_net_1731091 } ) ,
    .Test_en ( Test_en__FEEDTHRU_23 ) , .clk ( clk__FEEDTHRU_66 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__12__6_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__12__6_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__12__6_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__12__6_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__12__6_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__12__6_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__12__6_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__12__6_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__12__6_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__12__6_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__12__6_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__12__6_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__12__6_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__12__6_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__12__6_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__12__6_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_137_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_588 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__83_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__83_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__83_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__83_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__83_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__83_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__83_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__83_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__83_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__83_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__83_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__83_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__83_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__83_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__83_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__83_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_7__12__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__71_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_83_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_83_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_83_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_83_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_83_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_83_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_83_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_83_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_83_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_83_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_83_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_83_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_83_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_83_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_83_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_83_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_83_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_83_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_83_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_83_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_83_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_83_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_83_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_83_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_83_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_83_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_83_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_83_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_83_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_83_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_83_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_83_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_83_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_589 } ) ,
    .ccff_tail ( grid_clb_83_ccff_tail ) , .SC_IN_TOP ( scff_Wires_160_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_590 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_591 ) , 
    .SC_OUT_BOT ( scff_Wires_161_ ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_592 } ) ,
    .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_593 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_349 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_594 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_595 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_815 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_596 } ) ) ;
grid_clb grid_clb_8__1_ (
    .prog_clk ( { ctsbuf_net_5701488 } ) ,
    .Test_en ( Test_en__FEEDTHRU_24 ) ,
    .clk ( { ctsbuf_net_1919 } ) ,
    .top_width_0_height_0__pin_0_ ( cbx_1__1__77_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__77_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__77_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__77_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__77_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__77_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__77_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__77_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__77_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__77_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__77_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__77_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__77_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__77_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__77_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__77_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_77_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_597 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__84_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__84_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__84_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__84_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__84_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__84_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__84_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__84_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__84_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__84_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__84_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__84_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__84_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__84_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__84_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__84_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_8__1__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__72_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_84_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_84_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_84_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_84_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_84_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_84_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_84_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_84_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_84_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_84_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_84_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_84_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_84_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_84_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_84_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_84_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_84_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_84_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_84_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_84_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_84_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_84_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_84_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_84_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_84_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_84_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_84_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_84_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_84_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_84_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_84_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_84_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_84_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_598 } ) ,
    .ccff_tail ( grid_clb_84_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_599 ) , .SC_IN_BOT ( scff_Wires_187_ ) , 
    .SC_OUT_TOP ( scff_Wires_188_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_600 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_25 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_45 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_670 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_601 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_602 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { scff_Wires_186_ } ) ,
    .scff_Wires__FEEDTHRU_1 ( { scff_Wires__FEEDTHRU_1_186_ } ) ) ;
grid_clb grid_clb_8__2_ (
    .prog_clk ( { ctsbuf_net_5531471 } ) ,
    .Test_en ( Test_en__FEEDTHRU_26 ) , .clk ( clk__FEEDTHRU_45 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__78_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__78_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__78_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__78_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__78_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__78_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__78_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__78_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__78_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__78_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__78_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__78_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__78_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__78_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__78_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__78_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_78_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_603 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__85_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__85_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__85_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__85_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__85_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__85_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__85_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__85_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__85_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__85_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__85_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__85_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__85_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__85_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__85_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__85_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_8__2__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__73_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_85_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_85_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_85_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_85_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_85_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_85_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_85_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_85_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_85_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_85_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_85_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_85_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_85_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_85_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_85_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_85_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_85_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_85_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_85_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_85_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_85_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_85_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_85_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_85_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_85_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_85_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_85_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_85_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_85_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_85_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_85_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_85_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_85_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_604 } ) ,
    .ccff_tail ( grid_clb_85_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_605 ) , .SC_IN_BOT ( scff_Wires_189_ ) , 
    .SC_OUT_TOP ( scff_Wires_190_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_606 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_27 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_46 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_317 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_607 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_608 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_340 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_609 } ) ) ;
grid_clb grid_clb_8__3_ (
    .prog_clk ( { ctsbuf_net_5291447 } ) ,
    .Test_en ( Test_en__FEEDTHRU_28 ) , .clk ( clk__FEEDTHRU_46 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__79_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__79_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__79_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__79_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__79_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__79_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__79_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__79_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__79_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__79_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__79_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__79_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__79_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__79_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__79_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__79_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_79_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_610 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__86_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__86_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__86_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__86_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__86_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__86_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__86_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__86_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__86_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__86_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__86_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__86_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__86_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__86_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__86_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__86_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_8__3__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__74_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_86_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_86_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_86_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_86_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_86_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_86_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_86_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_86_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_86_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_86_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_86_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_86_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_86_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_86_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_86_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_86_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_86_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_86_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_86_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_86_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_86_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_86_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_86_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_86_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_86_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_86_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_86_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_86_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_86_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_86_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_86_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_86_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_86_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_611 } ) ,
    .ccff_tail ( grid_clb_86_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_612 ) , .SC_IN_BOT ( scff_Wires_191_ ) , 
    .SC_OUT_TOP ( scff_Wires_192_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_613 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_29 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_47 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_782 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_614 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_615 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_281 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_616 } ) ) ;
grid_clb grid_clb_8__4_ (
    .prog_clk ( { ctsbuf_net_4971415 } ) ,
    .Test_en ( Test_en__FEEDTHRU_30 ) , .clk ( clk__FEEDTHRU_47 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__80_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__80_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__80_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__80_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__80_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__80_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__80_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__80_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__80_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__80_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__80_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__80_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__80_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__80_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__80_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__80_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_80_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_617 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__87_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__87_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__87_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__87_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__87_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__87_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__87_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__87_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__87_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__87_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__87_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__87_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__87_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__87_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__87_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__87_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_8__4__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__75_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_87_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_87_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_87_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_87_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_87_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_87_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_87_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_87_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_87_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_87_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_87_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_87_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_87_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_87_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_87_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_87_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_87_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_87_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_87_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_87_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_87_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_87_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_87_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_87_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_87_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_87_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_87_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_87_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_87_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_87_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_87_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_87_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_87_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_618 } ) ,
    .ccff_tail ( grid_clb_87_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_619 ) , .SC_IN_BOT ( scff_Wires_193_ ) , 
    .SC_OUT_TOP ( scff_Wires_194_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_620 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_31 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_48 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_365 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_621 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_622 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_499 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_623 } ) ) ;
grid_clb grid_clb_8__5_ (
    .prog_clk ( { ctsbuf_net_4581376 } ) ,
    .Test_en ( Test_en__FEEDTHRU_32 ) , .clk ( clk__FEEDTHRU_48 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__81_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__81_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__81_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__81_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__81_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__81_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__81_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__81_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__81_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__81_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__81_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__81_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__81_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__81_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__81_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__81_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_81_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_624 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__88_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__88_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__88_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__88_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__88_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__88_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__88_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__88_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__88_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__88_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__88_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__88_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__88_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__88_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__88_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__88_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_8__5__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__76_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_88_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_88_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_88_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_88_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_88_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_88_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_88_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_88_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_88_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_88_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_88_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_88_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_88_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_88_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_88_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_88_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_88_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_88_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_88_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_88_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_88_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_88_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_88_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_88_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_88_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_88_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_88_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_88_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_88_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_88_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_88_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_88_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_88_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_625 } ) ,
    .ccff_tail ( grid_clb_88_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_626 ) , .SC_IN_BOT ( scff_Wires_195_ ) , 
    .SC_OUT_TOP ( scff_Wires_196_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_627 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_33 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_49 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_410 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_628 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_629 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_738 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_630 } ) ) ;
grid_clb grid_clb_8__6_ (
    .prog_clk ( { ctsbuf_net_4101328 } ) ,
    .Test_en ( Test_en__FEEDTHRU_34 ) , .clk ( clk__FEEDTHRU_49 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__82_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__82_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__82_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__82_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__82_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__82_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__82_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__82_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__82_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__82_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__82_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__82_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__82_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__82_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__82_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__82_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_82_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_631 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__89_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__89_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__89_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__89_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__89_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__89_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__89_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__89_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__89_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__89_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__89_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__89_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__89_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__89_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__89_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__89_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_8__6__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__77_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_89_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_89_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_89_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_89_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_89_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_89_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_89_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_89_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_89_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_89_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_89_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_89_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_89_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_89_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_89_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_89_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_89_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_89_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_89_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_89_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_89_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_89_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_89_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_89_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_89_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_89_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_89_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_89_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_89_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_89_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_89_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_89_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_89_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_632 } ) ,
    .ccff_tail ( grid_clb_89_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_633 ) , .SC_IN_BOT ( scff_Wires_197_ ) , 
    .SC_OUT_TOP ( scff_Wires_198_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_634 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_35 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_50 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_573 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_635 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_636 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_259 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_637 } ) ) ;
grid_clb grid_clb_8__7_ (
    .prog_clk ( { ctsbuf_net_3621280 } ) ,
    .Test_en ( Test_en__FEEDTHRU_36 ) , .clk ( clk__FEEDTHRU_50 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__83_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__83_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__83_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__83_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__83_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__83_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__83_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__83_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__83_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__83_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__83_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__83_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__83_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__83_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__83_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__83_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_83_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_638 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__90_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__90_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__90_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__90_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__90_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__90_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__90_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__90_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__90_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__90_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__90_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__90_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__90_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__90_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__90_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__90_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_8__7__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__78_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_90_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_90_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_90_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_90_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_90_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_90_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_90_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_90_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_90_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_90_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_90_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_90_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_90_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_90_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_90_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_90_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_90_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_90_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_90_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_90_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_90_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_90_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_90_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_90_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_90_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_90_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_90_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_90_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_90_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_90_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_90_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_90_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_90_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_639 } ) ,
    .ccff_tail ( grid_clb_90_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_640 ) , .SC_IN_BOT ( scff_Wires_199_ ) , 
    .SC_OUT_TOP ( scff_Wires_200_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_641 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_37 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_51 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_284 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_642 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_643 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_475 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_644 } ) ) ;
grid_clb grid_clb_8__8_ (
    .prog_clk ( { ctsbuf_net_3141232 } ) ,
    .Test_en ( Test_en__FEEDTHRU_38 ) , .clk ( clk__FEEDTHRU_51 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__84_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__84_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__84_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__84_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__84_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__84_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__84_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__84_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__84_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__84_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__84_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__84_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__84_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__84_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__84_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__84_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_84_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_645 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__91_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__91_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__91_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__91_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__91_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__91_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__91_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__91_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__91_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__91_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__91_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__91_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__91_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__91_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__91_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__91_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_8__8__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__79_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_91_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_91_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_91_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_91_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_91_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_91_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_91_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_91_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_91_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_91_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_91_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_91_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_91_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_91_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_91_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_91_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_91_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_91_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_91_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_91_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_91_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_91_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_91_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_91_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_91_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_91_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_91_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_91_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_91_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_91_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_91_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_91_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_91_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_646 } ) ,
    .ccff_tail ( grid_clb_91_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_647 ) , .SC_IN_BOT ( scff_Wires_201_ ) , 
    .SC_OUT_TOP ( scff_Wires_202_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_648 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_39 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_52 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_297 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_649 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_650 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_869 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_651 } ) ) ;
grid_clb grid_clb_8__9_ (
    .prog_clk ( { ctsbuf_net_2661184 } ) ,
    .Test_en ( Test_en__FEEDTHRU_40 ) , .clk ( clk__FEEDTHRU_52 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__85_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__85_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__85_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__85_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__85_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__85_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__85_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__85_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__85_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__85_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__85_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__85_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__85_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__85_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__85_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__85_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_85_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_652 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__92_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__92_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__92_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__92_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__92_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__92_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__92_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__92_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__92_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__92_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__92_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__92_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__92_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__92_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__92_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__92_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_8__9__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__80_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_92_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_92_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_92_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_92_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_92_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_92_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_92_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_92_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_92_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_92_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_92_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_92_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_92_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_92_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_92_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_92_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_92_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_92_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_92_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_92_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_92_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_92_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_92_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_92_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_92_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_92_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_92_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_92_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_92_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_92_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_92_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_92_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_92_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_653 } ) ,
    .ccff_tail ( grid_clb_92_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_654 ) , .SC_IN_BOT ( scff_Wires_203_ ) , 
    .SC_OUT_TOP ( scff_Wires_204_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_655 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_41 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_53 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_847 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_656 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_657 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_292 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_658 } ) ) ;
grid_clb grid_clb_8__10_ (
    .prog_clk ( { ctsbuf_net_2181136 } ) ,
    .Test_en ( Test_en__FEEDTHRU_42 ) , .clk ( clk__FEEDTHRU_53 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__86_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__86_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__86_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__86_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__86_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__86_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__86_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__86_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__86_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__86_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__86_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__86_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__86_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__86_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__86_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__86_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_86_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_659 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__93_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__93_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__93_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__93_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__93_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__93_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__93_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__93_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__93_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__93_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__93_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__93_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__93_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__93_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__93_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__93_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_8__10__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__81_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_93_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_93_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_93_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_93_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_93_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_93_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_93_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_93_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_93_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_93_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_93_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_93_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_93_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_93_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_93_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_93_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_93_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_93_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_93_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_93_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_93_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_93_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_93_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_93_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_93_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_93_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_93_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_93_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_93_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_93_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_93_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_93_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_93_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_660 } ) ,
    .ccff_tail ( grid_clb_93_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_661 ) , .SC_IN_BOT ( scff_Wires_205_ ) , 
    .SC_OUT_TOP ( scff_Wires_206_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_662 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_43 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_54 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_283 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_663 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_664 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_642 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_665 } ) ) ;
grid_clb grid_clb_8__11_ (
    .prog_clk ( { p_abuf13 } ) ,
    .Test_en ( Test_en__FEEDTHRU_44 ) , .clk ( clk__FEEDTHRU_54 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__87_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__87_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__87_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__87_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__87_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__87_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__87_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__87_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__87_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__87_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__87_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__87_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__87_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__87_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__87_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__87_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_87_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_666 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__94_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__94_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__94_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__94_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__94_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__94_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__94_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__94_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__94_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__94_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__94_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__94_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__94_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__94_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__94_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__94_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_8__11__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__82_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_94_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_94_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_94_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_94_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_94_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_94_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_94_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_94_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_94_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_94_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_94_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_94_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_94_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_94_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_94_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_94_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_94_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_94_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_94_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_94_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_94_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_94_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_94_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_94_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_94_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_94_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_94_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_94_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_94_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_94_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_94_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_94_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_94_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_667 } ) ,
    .ccff_tail ( grid_clb_94_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_668 ) , .SC_IN_BOT ( scff_Wires_207_ ) , 
    .SC_OUT_TOP ( scff_Wires_208_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_669 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_45 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_55 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_808 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_670 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_671 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_544 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_672 } ) ) ;
grid_clb grid_clb_8__12_ (
    .prog_clk ( { ctsbuf_net_1261044 } ) ,
    .Test_en ( Test_en__FEEDTHRU_46 ) , .clk ( clk__FEEDTHRU_55 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__12__7_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__12__7_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__12__7_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__12__7_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__12__7_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__12__7_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__12__7_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__12__7_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__12__7_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__12__7_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__12__7_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__12__7_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__12__7_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__12__7_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__12__7_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__12__7_bottom_grid_pin_15_ ) ,
    .top_width_0_height_0__pin_32_ ( { ropt_net_1588 } ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_673 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__95_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__95_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__95_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__95_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__95_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__95_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__95_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__95_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__95_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__95_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__95_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__95_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__95_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__95_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__95_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__95_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_8__12__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__83_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_95_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_95_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_95_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_95_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_95_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_95_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_95_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_95_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_95_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_95_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_95_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_95_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_95_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_95_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_95_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_95_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_95_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_95_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_95_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_95_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_95_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_95_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_95_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_95_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_95_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_95_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_95_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_95_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_95_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_95_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_95_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_95_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_95_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_674 } ) ,
    .ccff_tail ( grid_clb_95_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_675 ) , .SC_IN_BOT ( scff_Wires_209_ ) , 
    .SC_OUT_TOP ( scff_Wires_210_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_676 ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_677 } ) ,
    .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_678 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_389 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_679 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_680 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_791 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_681 } ) ) ;
grid_clb grid_clb_9__1_ (
    .prog_clk ( { ctsbuf_net_5521470 } ) ,
    .Test_en ( Test_en__FEEDTHRU_47 ) ,
    .clk ( { ctsbuf_net_1919 } ) ,
    .top_width_0_height_0__pin_0_ ( cbx_1__1__88_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__88_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__88_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__88_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__88_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__88_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__88_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__88_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__88_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__88_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__88_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__88_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__88_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__88_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__88_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__88_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_88_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_682 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__96_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__96_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__96_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__96_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__96_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__96_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__96_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__96_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__96_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__96_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__96_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__96_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__96_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__96_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__96_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__96_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_9__1__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__84_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_96_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_96_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_96_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_96_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_96_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_96_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_96_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_96_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_96_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_96_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_96_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_96_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_96_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_96_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_96_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_96_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_96_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_96_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_96_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_96_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_96_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_96_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_96_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_96_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_96_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_96_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_96_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_96_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_96_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_96_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_96_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_96_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_96_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_683 } ) ,
    .ccff_tail ( grid_clb_96_ccff_tail ) , .SC_IN_TOP ( scff_Wires_235_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_684 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_685 ) , 
    .SC_OUT_BOT ( scff_Wires_237_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_48 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_34 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_617 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_686 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_687 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_801 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_688 } ) ) ;
grid_clb grid_clb_9__2_ (
    .prog_clk ( { ctsbuf_net_5271445 } ) ,
    .Test_en ( Test_en__FEEDTHRU_49 ) , .clk ( clk__FEEDTHRU_34 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__89_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__89_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__89_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__89_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__89_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__89_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__89_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__89_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__89_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__89_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__89_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__89_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__89_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__89_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__89_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__89_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_89_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_689 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__97_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__97_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__97_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__97_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__97_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__97_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__97_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__97_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__97_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__97_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__97_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__97_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__97_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__97_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__97_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__97_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_9__2__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__85_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_97_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_97_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_97_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_97_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_97_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_97_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_97_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_97_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_97_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_97_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_97_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_97_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_97_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_97_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_97_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_97_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_97_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_97_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_97_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_97_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_97_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_97_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_97_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_97_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_97_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_97_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_97_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_97_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_97_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_97_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_97_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_97_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_97_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_690 } ) ,
    .ccff_tail ( grid_clb_97_ccff_tail ) , .SC_IN_TOP ( scff_Wires_233_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_691 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_692 ) , 
    .SC_OUT_BOT ( scff_Wires_234_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_50 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_35 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_374 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_693 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_694 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_338 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_695 } ) ) ;
grid_clb grid_clb_9__3_ (
    .prog_clk ( { ctsbuf_net_4951413 } ) ,
    .Test_en ( Test_en__FEEDTHRU_51 ) , .clk ( clk__FEEDTHRU_35 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__90_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__90_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__90_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__90_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__90_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__90_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__90_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__90_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__90_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__90_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__90_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__90_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__90_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__90_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__90_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__90_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_90_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_696 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__98_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__98_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__98_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__98_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__98_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__98_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__98_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__98_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__98_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__98_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__98_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__98_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__98_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__98_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__98_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__98_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_9__3__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__86_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_98_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_98_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_98_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_98_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_98_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_98_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_98_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_98_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_98_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_98_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_98_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_98_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_98_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_98_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_98_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_98_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_98_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_98_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_98_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_98_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_98_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_98_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_98_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_98_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_98_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_98_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_98_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_98_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_98_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_98_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_98_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_98_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_98_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_697 } ) ,
    .ccff_tail ( grid_clb_98_ccff_tail ) , .SC_IN_TOP ( scff_Wires_231_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_698 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_699 ) , 
    .SC_OUT_BOT ( scff_Wires_232_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_52 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_36 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_914 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_700 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_701 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_894 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_702 } ) ) ;
grid_clb grid_clb_9__4_ (
    .prog_clk ( { ctsbuf_net_4551373 } ) ,
    .Test_en ( Test_en__FEEDTHRU_53 ) , .clk ( clk__FEEDTHRU_36 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__91_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__91_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__91_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__91_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__91_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__91_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__91_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__91_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__91_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__91_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__91_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__91_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__91_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__91_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__91_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__91_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_91_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_703 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__99_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__99_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__99_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__99_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__99_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__99_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__99_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__99_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__99_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__99_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__99_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__99_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__99_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__99_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__99_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__99_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_9__4__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__87_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_99_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_99_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_99_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_99_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_99_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_99_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_99_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_99_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_99_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_99_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_99_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_99_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_99_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_99_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_99_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_99_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_99_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_99_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_99_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_99_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_99_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_99_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_99_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_99_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_99_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_99_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_99_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_99_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_99_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_99_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_99_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_99_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_99_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_704 } ) ,
    .ccff_tail ( grid_clb_99_ccff_tail ) , .SC_IN_TOP ( scff_Wires_229_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_705 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_706 ) , 
    .SC_OUT_BOT ( scff_Wires_230_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_54 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_37 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_743 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_707 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_708 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_425 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_709 } ) ) ;
grid_clb grid_clb_9__5_ (
    .prog_clk ( { ctsbuf_net_4071325 } ) ,
    .Test_en ( Test_en__FEEDTHRU_55 ) , .clk ( clk__FEEDTHRU_37 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__92_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__92_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__92_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__92_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__92_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__92_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__92_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__92_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__92_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__92_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__92_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__92_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__92_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__92_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__92_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__92_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_92_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_710 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__100_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__100_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__100_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__100_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__100_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__100_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__100_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__100_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__100_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__100_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__100_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__100_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__100_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__100_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__100_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__100_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_9__5__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__88_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_100_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_100_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_100_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_100_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_100_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_100_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_100_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_100_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_100_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_100_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_100_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_100_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_100_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_100_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_100_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_100_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_100_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_100_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_100_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_100_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_100_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_100_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_100_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_100_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_100_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_100_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_100_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_100_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_100_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_100_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_100_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_100_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_100_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_711 } ) ,
    .ccff_tail ( grid_clb_100_ccff_tail ) , .SC_IN_TOP ( scff_Wires_227_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_712 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_713 ) , 
    .SC_OUT_BOT ( scff_Wires_228_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_56 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_38 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_352 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_714 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_715 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_590 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_716 } ) ) ;
grid_clb grid_clb_9__6_ (
    .prog_clk ( { ctsbuf_net_3591277 } ) ,
    .Test_en ( Test_en__FEEDTHRU_57 ) , .clk ( clk__FEEDTHRU_38 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__93_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__93_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__93_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__93_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__93_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__93_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__93_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__93_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__93_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__93_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__93_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__93_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__93_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__93_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__93_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__93_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_93_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_717 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__101_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__101_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__101_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__101_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__101_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__101_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__101_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__101_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__101_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__101_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__101_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__101_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__101_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__101_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__101_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__101_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_9__6__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__89_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_101_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_101_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_101_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_101_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_101_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_101_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_101_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_101_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_101_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_101_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_101_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_101_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_101_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_101_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_101_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_101_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_101_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_101_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_101_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_101_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_101_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_101_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_101_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_101_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_101_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_101_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_101_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_101_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_101_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_101_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_101_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_101_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_101_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_718 } ) ,
    .ccff_tail ( grid_clb_101_ccff_tail ) , .SC_IN_TOP ( scff_Wires_225_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_719 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_720 ) , 
    .SC_OUT_BOT ( scff_Wires_226_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_58 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_39 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_306 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_721 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_722 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_471 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_723 } ) ) ;
grid_clb grid_clb_9__7_ (
    .prog_clk ( { ctsbuf_net_3111229 } ) ,
    .Test_en ( Test_en__FEEDTHRU_59 ) , .clk ( clk__FEEDTHRU_39 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__94_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__94_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__94_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__94_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__94_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__94_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__94_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__94_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__94_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__94_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__94_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__94_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__94_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__94_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__94_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__94_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_94_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_724 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__102_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__102_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__102_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__102_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__102_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__102_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__102_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__102_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__102_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__102_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__102_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__102_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__102_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__102_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__102_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__102_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_9__7__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__90_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_102_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_102_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_102_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_102_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_102_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_102_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_102_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_102_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_102_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_102_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_102_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_102_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_102_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_102_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_102_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_102_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_102_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_102_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_102_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_102_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_102_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_102_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_102_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_102_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_102_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_102_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_102_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_102_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_102_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_102_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_102_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_102_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_102_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_725 } ) ,
    .ccff_tail ( grid_clb_102_ccff_tail ) , .SC_IN_TOP ( scff_Wires_223_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_726 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_727 ) , 
    .SC_OUT_BOT ( scff_Wires_224_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_60 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_40 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_514 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_728 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_729 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_427 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_730 } ) ) ;
grid_clb grid_clb_9__8_ (
    .prog_clk ( { ctsbuf_net_2631181 } ) ,
    .Test_en ( Test_en__FEEDTHRU_61 ) , .clk ( clk__FEEDTHRU_40 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__95_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__95_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__95_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__95_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__95_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__95_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__95_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__95_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__95_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__95_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__95_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__95_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__95_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__95_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__95_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__95_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_95_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_731 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__103_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__103_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__103_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__103_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__103_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__103_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__103_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__103_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__103_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__103_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__103_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__103_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__103_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__103_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__103_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__103_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_9__8__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__91_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_103_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_103_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_103_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_103_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_103_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_103_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_103_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_103_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_103_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_103_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_103_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_103_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_103_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_103_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_103_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_103_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_103_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_103_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_103_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_103_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_103_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_103_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_103_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_103_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_103_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_103_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_103_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_103_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_103_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_103_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_103_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_103_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_103_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_732 } ) ,
    .ccff_tail ( grid_clb_103_ccff_tail ) , .SC_IN_TOP ( scff_Wires_221_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_733 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_734 ) , 
    .SC_OUT_BOT ( scff_Wires_222_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_62 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_41 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_870 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_735 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_736 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_855 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_737 } ) ) ;
grid_clb grid_clb_9__9_ (
    .prog_clk ( { ctsbuf_net_2151133 } ) ,
    .Test_en ( Test_en__FEEDTHRU_63 ) , .clk ( clk__FEEDTHRU_41 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__96_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__96_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__96_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__96_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__96_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__96_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__96_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__96_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__96_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__96_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__96_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__96_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__96_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__96_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__96_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__96_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_96_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_738 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__104_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__104_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__104_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__104_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__104_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__104_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__104_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__104_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__104_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__104_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__104_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__104_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__104_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__104_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__104_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__104_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_9__9__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__92_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_104_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_104_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_104_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_104_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_104_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_104_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_104_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_104_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_104_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_104_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_104_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_104_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_104_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_104_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_104_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_104_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_104_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_104_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_104_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_104_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_104_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_104_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_104_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_104_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_104_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_104_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_104_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_104_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_104_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_104_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_104_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_104_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_104_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_739 } ) ,
    .ccff_tail ( grid_clb_104_ccff_tail ) , .SC_IN_TOP ( scff_Wires_219_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_740 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_741 ) , 
    .SC_OUT_BOT ( scff_Wires_220_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_64 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_42 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_809 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_742 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_743 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_765 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_744 } ) ) ;
grid_clb grid_clb_9__10_ (
    .prog_clk ( { ctsbuf_net_1671085 } ) ,
    .Test_en ( Test_en__FEEDTHRU_65 ) , .clk ( clk__FEEDTHRU_42 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__97_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__97_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__97_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__97_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__97_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__97_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__97_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__97_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__97_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__97_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__97_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__97_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__97_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__97_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__97_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__97_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_97_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_745 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__105_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__105_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__105_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__105_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__105_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__105_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__105_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__105_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__105_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__105_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__105_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__105_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__105_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__105_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__105_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__105_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_9__10__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__93_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_105_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_105_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_105_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_105_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_105_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_105_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_105_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_105_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_105_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_105_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_105_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_105_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_105_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_105_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_105_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_105_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_105_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_105_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_105_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_105_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_105_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_105_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_105_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_105_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_105_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_105_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_105_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_105_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_105_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_105_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_105_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_105_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_105_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_746 } ) ,
    .ccff_tail ( grid_clb_105_ccff_tail ) , .SC_IN_TOP ( scff_Wires_217_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_747 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_748 ) , 
    .SC_OUT_BOT ( scff_Wires_218_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_66 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_43 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_719 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_749 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_750 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_702 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_751 } ) ) ;
grid_clb grid_clb_9__11_ (
    .prog_clk ( { ctsbuf_net_1231041 } ) ,
    .Test_en ( Test_en__FEEDTHRU_67 ) , .clk ( clk__FEEDTHRU_43 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__98_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__98_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__98_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__98_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__98_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__98_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__98_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__98_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__98_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__98_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__98_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__98_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__98_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__98_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__98_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__98_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_98_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_752 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__106_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__106_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__106_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__106_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__106_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__106_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__106_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__106_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__106_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__106_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__106_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__106_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__106_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__106_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__106_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__106_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_9__11__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__94_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_106_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_106_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_106_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_106_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_106_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_106_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_106_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_106_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_106_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_106_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_106_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_106_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_106_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_106_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_106_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_106_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_106_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_106_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_106_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_106_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_106_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_106_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_106_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_106_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_106_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_106_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_106_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_106_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_106_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_106_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_106_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_106_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_106_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_753 } ) ,
    .ccff_tail ( grid_clb_106_ccff_tail ) , .SC_IN_TOP ( scff_Wires_215_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_754 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_755 ) , 
    .SC_OUT_BOT ( scff_Wires_216_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_68 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_44 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_607 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_756 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_757 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_816 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_758 } ) ) ;
grid_clb grid_clb_9__12_ (
    .prog_clk ( { ctsbuf_net_861004 } ) ,
    .Test_en ( Test_en__FEEDTHRU_69 ) , .clk ( clk__FEEDTHRU_44 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__12__8_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__12__8_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__12__8_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__12__8_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__12__8_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__12__8_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__12__8_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__12__8_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__12__8_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__12__8_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__12__8_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__12__8_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__12__8_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__12__8_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__12__8_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__12__8_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_139_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_759 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__107_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__107_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__107_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__107_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__107_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__107_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__107_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__107_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__107_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__107_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__107_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__107_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__107_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__107_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__107_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__107_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_9__12__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__95_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_107_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_107_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_107_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_107_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_107_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_107_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_107_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_107_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_107_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_107_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_107_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_107_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_107_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_107_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_107_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_107_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_107_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_107_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_107_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_107_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_107_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_107_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_107_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_107_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_107_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_107_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_107_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_107_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_107_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_107_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_107_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_107_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_107_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_760 } ) ,
    .ccff_tail ( grid_clb_107_ccff_tail ) , .SC_IN_TOP ( scff_Wires_213_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_761 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_762 ) , 
    .SC_OUT_BOT ( scff_Wires_214_ ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_763 } ) ,
    .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_764 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_308 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_765 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_766 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_307 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_767 } ) ) ;
grid_clb grid_clb_10__1_ (
    .prog_clk ( { ctsbuf_net_5251443 } ) ,
    .Test_en ( Test_en__FEEDTHRU_70 ) ,
    .clk ( { ctsbuf_net_1919 } ) ,
    .top_width_0_height_0__pin_0_ ( cbx_1__1__99_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__99_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__99_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__99_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__99_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__99_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__99_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__99_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__99_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__99_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__99_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__99_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__99_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__99_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__99_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__99_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_99_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_768 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__108_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__108_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__108_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__108_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__108_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__108_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__108_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__108_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__108_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__108_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__108_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__108_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__108_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__108_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__108_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__108_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_10__1__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__96_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_108_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_108_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_108_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_108_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_108_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_108_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_108_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_108_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_108_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_108_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_108_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_108_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_108_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_108_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_108_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_108_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_108_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_108_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_108_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_108_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_108_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_108_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_108_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_108_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_108_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_108_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_108_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_108_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_108_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_108_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_108_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_108_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_108_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_769 } ) ,
    .ccff_tail ( grid_clb_108_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_770 ) , .SC_IN_BOT ( scff_Wires_240_ ) , 
    .SC_OUT_TOP ( scff_Wires_241_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_771 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_71 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_23 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_277 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_772 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_773 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { scff_Wires_239_ } ) ,
    .scff_Wires__FEEDTHRU_1 ( { scff_Wires__FEEDTHRU_1_239_ } ) ) ;
grid_clb grid_clb_10__2_ (
    .prog_clk ( { ctsbuf_net_4921410 } ) ,
    .Test_en ( Test_en__FEEDTHRU_72 ) , .clk ( clk__FEEDTHRU_23 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__100_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__100_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__100_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__100_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__100_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__100_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__100_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__100_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__100_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__100_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__100_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__100_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__100_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__100_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__100_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__100_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_100_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_774 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__109_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__109_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__109_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__109_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__109_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__109_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__109_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__109_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__109_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__109_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__109_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__109_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__109_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__109_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__109_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__109_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_10__2__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__97_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_109_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_109_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_109_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_109_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_109_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_109_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_109_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_109_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_109_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_109_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_109_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_109_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_109_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_109_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_109_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_109_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_109_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_109_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_109_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_109_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_109_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_109_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_109_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_109_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_109_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_109_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_109_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_109_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_109_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_109_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_109_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_109_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_109_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_775 } ) ,
    .ccff_tail ( grid_clb_109_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_776 ) , .SC_IN_BOT ( scff_Wires_242_ ) , 
    .SC_OUT_TOP ( scff_Wires_243_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_777 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_73 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_24 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_420 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_778 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_779 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_787 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_780 } ) ) ;
grid_clb grid_clb_10__3_ (
    .prog_clk ( { p_abuf42 } ) ,
    .Test_en ( Test_en__FEEDTHRU_74 ) , .clk ( clk__FEEDTHRU_24 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__101_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__101_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__101_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__101_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__101_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__101_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__101_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__101_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__101_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__101_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__101_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__101_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__101_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__101_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__101_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__101_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_101_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_781 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__110_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__110_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__110_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__110_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__110_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__110_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__110_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__110_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__110_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__110_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__110_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__110_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__110_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__110_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__110_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__110_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_10__3__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__98_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_110_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_110_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_110_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_110_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_110_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_110_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_110_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_110_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_110_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_110_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_110_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_110_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_110_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_110_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_110_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_110_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_110_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_110_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_110_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_110_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_110_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_110_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_110_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_110_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_110_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_110_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_110_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_110_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_110_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_110_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_110_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_110_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_110_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_782 } ) ,
    .ccff_tail ( grid_clb_110_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_783 ) , .SC_IN_BOT ( scff_Wires_244_ ) , 
    .SC_OUT_TOP ( scff_Wires_245_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_784 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_75 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_25 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_450 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_785 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_786 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_913 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_787 } ) ) ;
grid_clb grid_clb_10__4_ (
    .prog_clk ( { ctsbuf_net_4041322 } ) ,
    .Test_en ( Test_en__FEEDTHRU_76 ) , .clk ( clk__FEEDTHRU_25 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__102_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__102_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__102_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__102_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__102_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__102_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__102_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__102_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__102_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__102_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__102_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__102_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__102_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__102_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__102_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__102_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_102_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_788 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__111_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__111_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__111_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__111_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__111_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__111_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__111_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__111_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__111_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__111_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__111_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__111_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__111_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__111_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__111_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__111_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_10__4__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__99_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_111_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_111_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_111_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_111_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_111_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_111_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_111_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_111_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_111_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_111_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_111_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_111_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_111_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_111_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_111_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_111_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_111_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_111_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_111_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_111_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_111_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_111_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_111_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_111_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_111_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_111_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_111_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_111_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_111_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_111_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_111_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_111_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_111_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_789 } ) ,
    .ccff_tail ( grid_clb_111_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_790 ) , .SC_IN_BOT ( scff_Wires_246_ ) , 
    .SC_OUT_TOP ( scff_Wires_247_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_791 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_77 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_26 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_474 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_792 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_793 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_614 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_794 } ) ) ;
grid_clb grid_clb_10__5_ (
    .prog_clk ( { ctsbuf_net_3561274 } ) ,
    .Test_en ( Test_en__FEEDTHRU_78 ) , .clk ( clk__FEEDTHRU_26 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__103_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__103_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__103_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__103_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__103_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__103_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__103_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__103_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__103_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__103_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__103_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__103_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__103_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__103_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__103_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__103_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_103_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_795 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__112_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__112_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__112_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__112_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__112_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__112_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__112_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__112_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__112_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__112_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__112_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__112_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__112_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__112_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__112_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__112_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_10__5__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__100_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_112_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_112_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_112_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_112_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_112_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_112_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_112_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_112_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_112_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_112_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_112_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_112_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_112_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_112_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_112_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_112_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_112_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_112_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_112_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_112_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_112_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_112_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_112_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_112_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_112_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_112_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_112_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_112_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_112_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_112_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_112_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_112_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_112_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_796 } ) ,
    .ccff_tail ( grid_clb_112_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_797 ) , .SC_IN_BOT ( scff_Wires_248_ ) , 
    .SC_OUT_TOP ( scff_Wires_249_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_798 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_79 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_27 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_470 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_799 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_800 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_862 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_801 } ) ) ;
grid_clb grid_clb_10__6_ (
    .prog_clk ( { ctsbuf_net_3081226 } ) ,
    .Test_en ( Test_en__FEEDTHRU_80 ) , .clk ( clk__FEEDTHRU_27 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__104_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__104_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__104_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__104_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__104_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__104_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__104_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__104_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__104_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__104_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__104_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__104_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__104_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__104_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__104_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__104_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_104_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_802 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__113_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__113_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__113_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__113_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__113_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__113_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__113_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__113_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__113_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__113_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__113_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__113_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__113_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__113_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__113_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__113_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_10__6__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__101_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_113_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_113_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_113_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_113_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_113_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_113_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_113_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_113_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_113_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_113_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_113_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_113_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_113_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_113_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_113_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_113_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_113_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_113_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_113_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_113_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_113_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_113_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_113_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_113_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_113_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_113_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_113_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_113_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_113_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_113_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_113_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_113_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_113_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_803 } ) ,
    .ccff_tail ( grid_clb_113_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_804 ) , .SC_IN_BOT ( scff_Wires_250_ ) , 
    .SC_OUT_TOP ( scff_Wires_251_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_805 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_81 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_28 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_708 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_806 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_807 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_901 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_808 } ) ) ;
grid_clb grid_clb_10__7_ (
    .prog_clk ( { p_abuf27 } ) ,
    .Test_en ( Test_en__FEEDTHRU_82 ) , .clk ( clk__FEEDTHRU_28 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__105_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__105_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__105_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__105_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__105_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__105_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__105_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__105_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__105_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__105_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__105_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__105_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__105_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__105_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__105_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__105_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_105_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_809 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__114_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__114_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__114_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__114_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__114_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__114_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__114_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__114_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__114_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__114_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__114_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__114_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__114_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__114_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__114_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__114_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_10__7__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__102_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_114_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_114_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_114_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_114_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_114_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_114_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_114_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_114_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_114_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_114_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_114_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_114_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_114_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_114_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_114_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_114_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_114_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_114_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_114_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_114_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_114_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_114_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_114_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_114_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_114_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_114_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_114_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_114_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_114_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_114_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_114_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_114_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_114_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_810 } ) ,
    .ccff_tail ( grid_clb_114_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_811 ) , .SC_IN_BOT ( scff_Wires_252_ ) , 
    .SC_OUT_TOP ( scff_Wires_253_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_812 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_83 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_29 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_795 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_813 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_814 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_768 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_815 } ) ) ;
grid_clb grid_clb_10__8_ (
    .prog_clk ( { ctsbuf_net_2121130 } ) ,
    .Test_en ( Test_en__FEEDTHRU_84 ) , .clk ( clk__FEEDTHRU_29 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__106_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__106_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__106_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__106_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__106_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__106_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__106_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__106_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__106_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__106_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__106_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__106_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__106_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__106_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__106_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__106_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_106_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_816 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__115_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__115_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__115_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__115_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__115_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__115_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__115_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__115_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__115_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__115_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__115_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__115_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__115_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__115_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__115_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__115_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_10__8__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__103_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_115_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_115_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_115_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_115_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_115_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_115_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_115_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_115_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_115_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_115_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_115_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_115_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_115_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_115_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_115_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_115_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_115_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_115_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_115_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_115_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_115_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_115_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_115_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_115_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_115_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_115_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_115_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_115_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_115_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_115_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_115_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_115_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_115_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_817 } ) ,
    .ccff_tail ( grid_clb_115_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_818 ) , .SC_IN_BOT ( scff_Wires_254_ ) , 
    .SC_OUT_TOP ( scff_Wires_255_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_819 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_85 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_30 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_873 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_820 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_821 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_510 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_822 } ) ) ;
grid_clb grid_clb_10__9_ (
    .prog_clk ( { ctsbuf_net_1641082 } ) ,
    .Test_en ( Test_en__FEEDTHRU_86 ) , .clk ( clk__FEEDTHRU_30 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__107_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__107_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__107_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__107_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__107_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__107_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__107_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__107_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__107_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__107_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__107_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__107_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__107_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__107_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__107_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__107_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_107_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_823 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__116_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__116_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__116_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__116_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__116_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__116_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__116_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__116_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__116_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__116_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__116_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__116_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__116_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__116_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__116_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__116_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_10__9__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__104_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_116_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_116_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_116_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_116_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_116_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_116_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_116_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_116_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_116_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_116_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_116_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_116_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_116_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_116_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_116_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_116_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_116_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_116_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_116_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_116_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_116_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_116_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_116_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_116_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_116_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_116_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_116_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_116_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_116_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_116_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_116_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_116_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_116_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_824 } ) ,
    .ccff_tail ( grid_clb_116_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_825 ) , .SC_IN_BOT ( scff_Wires_256_ ) , 
    .SC_OUT_TOP ( scff_Wires_257_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_826 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_87 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_31 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_706 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_827 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_828 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_909 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_829 } ) ) ;
grid_clb grid_clb_10__10_ (
    .prog_clk ( { ctsbuf_net_1201038 } ) ,
    .Test_en ( Test_en__FEEDTHRU_88 ) , .clk ( clk__FEEDTHRU_31 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__108_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__108_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__108_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__108_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__108_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__108_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__108_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__108_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__108_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__108_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__108_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__108_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__108_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__108_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__108_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__108_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_108_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_830 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__117_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__117_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__117_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__117_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__117_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__117_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__117_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__117_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__117_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__117_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__117_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__117_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__117_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__117_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__117_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__117_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_10__10__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__105_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_117_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_117_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_117_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_117_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_117_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_117_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_117_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_117_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_117_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_117_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_117_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_117_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_117_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_117_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_117_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_117_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_117_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_117_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_117_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_117_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_117_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_117_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_117_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_117_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_117_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_117_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_117_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_117_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_117_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_117_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_117_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_117_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_117_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_831 } ) ,
    .ccff_tail ( grid_clb_117_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_832 ) , .SC_IN_BOT ( scff_Wires_258_ ) , 
    .SC_OUT_TOP ( scff_Wires_259_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_833 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_89 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_32 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_621 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_834 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_835 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_359 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_836 } ) ) ;
grid_clb grid_clb_10__11_ (
    .prog_clk ( { ctsbuf_net_841002 } ) ,
    .Test_en ( Test_en__FEEDTHRU_90 ) , .clk ( clk__FEEDTHRU_32 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__109_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__109_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__109_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__109_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__109_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__109_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__109_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__109_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__109_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__109_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__109_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__109_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__109_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__109_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__109_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__109_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_109_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_837 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__118_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__118_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__118_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__118_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__118_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__118_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__118_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__118_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__118_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__118_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__118_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__118_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__118_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__118_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__118_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__118_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_10__11__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__106_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_118_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_118_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_118_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_118_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_118_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_118_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_118_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_118_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_118_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_118_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_118_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_118_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_118_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_118_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_118_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_118_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_118_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_118_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_118_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_118_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_118_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_118_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_118_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_118_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_118_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_118_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_118_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_118_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_118_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_118_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_118_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_118_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_118_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_838 } ) ,
    .ccff_tail ( grid_clb_118_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_839 ) , .SC_IN_BOT ( scff_Wires_260_ ) , 
    .SC_OUT_TOP ( scff_Wires_261_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_840 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_91 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_33 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_763 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_841 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_842 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_726 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_843 } ) ) ;
grid_clb grid_clb_10__12_ (
    .prog_clk ( { ctsbuf_net_54972 } ) ,
    .Test_en ( Test_en__FEEDTHRU_92 ) , .clk ( clk__FEEDTHRU_33 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__12__9_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__12__9_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__12__9_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__12__9_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__12__9_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__12__9_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__12__9_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__12__9_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__12__9_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__12__9_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__12__9_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__12__9_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__12__9_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__12__9_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__12__9_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__12__9_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_140_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_844 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__119_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__119_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__119_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__119_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__119_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__119_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__119_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__119_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__119_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__119_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__119_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__119_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__119_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__119_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__119_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__119_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_10__12__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__107_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_119_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_119_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_119_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_119_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_119_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_119_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_119_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_119_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_119_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_119_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_119_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_119_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_119_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_119_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_119_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_119_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_119_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_119_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_119_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_119_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_119_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_119_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_119_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_119_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_119_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_119_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_119_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_119_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_119_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_119_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_119_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_119_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_119_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_845 } ) ,
    .ccff_tail ( grid_clb_119_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_846 ) , .SC_IN_BOT ( scff_Wires_262_ ) , 
    .SC_OUT_TOP ( scff_Wires_263_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_847 ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_848 } ) ,
    .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_849 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_350 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_850 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_851 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_879 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_852 } ) ) ;
grid_clb grid_clb_11__1_ (
    .prog_clk ( { ctsbuf_net_4901408 } ) ,
    .Test_en ( Test_en__FEEDTHRU_93 ) ,
    .clk ( { ctsbuf_net_1919 } ) ,
    .top_width_0_height_0__pin_0_ ( cbx_1__1__110_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__110_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__110_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__110_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__110_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__110_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__110_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__110_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__110_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__110_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__110_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__110_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__110_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__110_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__110_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__110_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_110_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_853 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__120_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__120_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__120_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__120_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__120_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__120_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__120_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__120_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__120_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__120_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__120_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__120_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__120_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__120_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__120_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__120_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_11__1__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__108_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_120_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_120_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_120_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_120_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_120_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_120_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_120_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_120_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_120_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_120_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_120_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_120_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_120_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_120_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_120_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_120_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_120_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_120_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_120_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_120_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_120_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_120_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_120_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_120_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_120_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_120_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_120_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_120_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_120_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_120_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_120_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_120_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_120_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_854 } ) ,
    .ccff_tail ( grid_clb_120_ccff_tail ) , .SC_IN_TOP ( scff_Wires_288_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_855 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_856 ) , 
    .SC_OUT_BOT ( scff_Wires_290_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_94 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_12 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_469 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_857 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_858 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_316 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_859 } ) ) ;
grid_clb grid_clb_11__2_ (
    .prog_clk ( { ctsbuf_net_4491367 } ) ,
    .Test_en ( Test_en__FEEDTHRU_95 ) , .clk ( clk__FEEDTHRU_12 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__111_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__111_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__111_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__111_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__111_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__111_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__111_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__111_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__111_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__111_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__111_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__111_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__111_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__111_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__111_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__111_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_111_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_860 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__121_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__121_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__121_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__121_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__121_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__121_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__121_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__121_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__121_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__121_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__121_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__121_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__121_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__121_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__121_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__121_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_11__2__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__109_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_121_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_121_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_121_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_121_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_121_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_121_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_121_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_121_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_121_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_121_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_121_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_121_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_121_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_121_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_121_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_121_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_121_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_121_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_121_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_121_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_121_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_121_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_121_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_121_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_121_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_121_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_121_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_121_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_121_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_121_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_121_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_121_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_121_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_861 } ) ,
    .ccff_tail ( grid_clb_121_ccff_tail ) , .SC_IN_TOP ( scff_Wires_286_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_862 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_863 ) , 
    .SC_OUT_BOT ( scff_Wires_287_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_96 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_13 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_823 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_864 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_865 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_355 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_866 } ) ) ;
grid_clb grid_clb_11__3_ (
    .prog_clk ( { ctsbuf_net_4011319 } ) ,
    .Test_en ( Test_en__FEEDTHRU_97 ) , .clk ( clk__FEEDTHRU_13 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__112_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__112_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__112_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__112_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__112_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__112_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__112_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__112_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__112_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__112_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__112_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__112_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__112_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__112_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__112_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__112_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_112_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_867 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__122_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__122_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__122_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__122_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__122_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__122_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__122_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__122_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__122_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__122_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__122_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__122_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__122_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__122_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__122_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__122_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_11__3__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__110_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_122_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_122_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_122_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_122_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_122_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_122_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_122_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_122_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_122_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_122_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_122_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_122_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_122_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_122_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_122_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_122_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_122_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_122_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_122_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_122_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_122_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_122_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_122_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_122_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_122_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_122_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_122_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_122_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_122_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_122_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_122_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_122_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_122_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_868 } ) ,
    .ccff_tail ( grid_clb_122_ccff_tail ) , .SC_IN_TOP ( scff_Wires_284_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_869 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_870 ) , 
    .SC_OUT_BOT ( scff_Wires_285_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_98 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_14 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_630 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_871 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_872 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_825 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_873 } ) ) ;
grid_clb grid_clb_11__4_ (
    .prog_clk ( { ctsbuf_net_3531271 } ) ,
    .Test_en ( Test_en__FEEDTHRU_99 ) , .clk ( clk__FEEDTHRU_14 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__113_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__113_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__113_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__113_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__113_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__113_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__113_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__113_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__113_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__113_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__113_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__113_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__113_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__113_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__113_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__113_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_113_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_874 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__123_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__123_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__123_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__123_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__123_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__123_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__123_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__123_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__123_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__123_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__123_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__123_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__123_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__123_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__123_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__123_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_11__4__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__111_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_123_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_123_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_123_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_123_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_123_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_123_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_123_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_123_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_123_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_123_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_123_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_123_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_123_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_123_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_123_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_123_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_123_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_123_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_123_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_123_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_123_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_123_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_123_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_123_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_123_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_123_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_123_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_123_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_123_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_123_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_123_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_123_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_123_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_875 } ) ,
    .ccff_tail ( grid_clb_123_ccff_tail ) , .SC_IN_TOP ( scff_Wires_282_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_876 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_877 ) , 
    .SC_OUT_BOT ( scff_Wires_283_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_100 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_15 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_380 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_878 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_879 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_880 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_880 } ) ) ;
grid_clb grid_clb_11__5_ (
    .prog_clk ( { ctsbuf_net_3051223 } ) ,
    .Test_en ( Test_en__FEEDTHRU_101 ) , .clk ( clk__FEEDTHRU_15 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__114_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__114_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__114_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__114_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__114_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__114_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__114_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__114_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__114_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__114_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__114_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__114_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__114_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__114_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__114_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__114_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_114_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_881 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__124_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__124_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__124_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__124_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__124_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__124_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__124_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__124_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__124_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__124_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__124_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__124_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__124_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__124_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__124_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__124_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_11__5__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__112_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_124_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_124_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_124_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_124_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_124_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_124_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_124_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_124_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_124_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_124_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_124_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_124_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_124_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_124_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_124_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_124_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_124_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_124_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_124_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_124_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_124_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_124_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_124_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_124_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_124_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_124_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_124_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_124_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_124_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_124_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_124_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_124_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_124_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_882 } ) ,
    .ccff_tail ( grid_clb_124_ccff_tail ) , .SC_IN_TOP ( scff_Wires_280_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_883 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_884 ) , 
    .SC_OUT_BOT ( scff_Wires_281_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_102 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_16 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_422 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_885 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_886 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_328 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_887 } ) ) ;
grid_clb grid_clb_11__6_ (
    .prog_clk ( { ctsbuf_net_2571175 } ) ,
    .Test_en ( Test_en__FEEDTHRU_103 ) , .clk ( clk__FEEDTHRU_16 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__115_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__115_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__115_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__115_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__115_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__115_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__115_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__115_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__115_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__115_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__115_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__115_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__115_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__115_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__115_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__115_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_115_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_888 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__125_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__125_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__125_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__125_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__125_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__125_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__125_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__125_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__125_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__125_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__125_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__125_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__125_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__125_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__125_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__125_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_11__6__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__113_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_125_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_125_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_125_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_125_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_125_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_125_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_125_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_125_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_125_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_125_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_125_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_125_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_125_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_125_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_125_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_125_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_125_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_125_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_125_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_125_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_125_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_125_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_125_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_125_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_125_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_125_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_125_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_125_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_125_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_125_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_125_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_125_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_125_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_889 } ) ,
    .ccff_tail ( grid_clb_125_ccff_tail ) , .SC_IN_TOP ( scff_Wires_278_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_890 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_891 ) , 
    .SC_OUT_BOT ( scff_Wires_279_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_104 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_17 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_828 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_892 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_893 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_840 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_894 } ) ) ;
grid_clb grid_clb_11__7_ (
    .prog_clk ( { ctsbuf_net_2091127 } ) ,
    .Test_en ( Test_en__FEEDTHRU_105 ) , .clk ( clk__FEEDTHRU_17 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__116_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__116_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__116_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__116_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__116_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__116_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__116_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__116_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__116_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__116_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__116_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__116_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__116_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__116_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__116_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__116_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_116_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_895 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__126_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__126_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__126_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__126_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__126_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__126_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__126_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__126_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__126_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__126_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__126_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__126_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__126_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__126_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__126_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__126_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_11__7__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__114_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_126_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_126_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_126_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_126_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_126_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_126_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_126_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_126_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_126_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_126_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_126_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_126_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_126_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_126_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_126_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_126_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_126_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_126_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_126_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_126_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_126_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_126_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_126_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_126_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_126_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_126_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_126_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_126_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_126_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_126_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_126_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_126_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_126_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_896 } ) ,
    .ccff_tail ( grid_clb_126_ccff_tail ) , .SC_IN_TOP ( scff_Wires_276_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_897 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_898 ) , 
    .SC_OUT_BOT ( scff_Wires_277_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_106 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_18 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_504 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_899 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_900 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_696 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_901 } ) ) ;
grid_clb grid_clb_11__8_ (
    .prog_clk ( { ctsbuf_net_1611079 } ) ,
    .Test_en ( Test_en__FEEDTHRU_107 ) , .clk ( clk__FEEDTHRU_18 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__117_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__117_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__117_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__117_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__117_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__117_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__117_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__117_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__117_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__117_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__117_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__117_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__117_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__117_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__117_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__117_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_117_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_902 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__127_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__127_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__127_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__127_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__127_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__127_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__127_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__127_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__127_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__127_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__127_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__127_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__127_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__127_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__127_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__127_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_11__8__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__115_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_127_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_127_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_127_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_127_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_127_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_127_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_127_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_127_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_127_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_127_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_127_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_127_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_127_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_127_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_127_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_127_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_127_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_127_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_127_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_127_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_127_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_127_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_127_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_127_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_127_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_127_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_127_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_127_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_127_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_127_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_127_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_127_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_127_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_903 } ) ,
    .ccff_tail ( grid_clb_127_ccff_tail ) , .SC_IN_TOP ( scff_Wires_274_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_904 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_905 ) , 
    .SC_OUT_BOT ( scff_Wires_275_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_108 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_19 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_896 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_906 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_907 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_754 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_908 } ) ) ;
grid_clb grid_clb_11__9_ (
    .prog_clk ( { ctsbuf_net_1171035 } ) ,
    .Test_en ( Test_en__FEEDTHRU_109 ) , .clk ( clk__FEEDTHRU_19 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__118_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__118_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__118_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__118_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__118_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__118_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__118_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__118_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__118_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__118_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__118_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__118_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__118_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__118_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__118_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__118_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_118_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_909 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__128_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__128_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__128_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__128_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__128_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__128_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__128_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__128_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__128_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__128_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__128_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__128_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__128_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__128_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__128_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__128_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_11__9__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__116_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_128_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_128_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_128_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_128_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_128_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_128_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_128_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_128_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_128_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_128_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_128_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_128_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_128_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_128_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_128_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_128_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_128_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_128_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_128_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_128_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_128_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_128_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_128_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_128_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_128_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_128_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_128_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_128_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_128_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_128_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_128_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_128_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_128_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_910 } ) ,
    .ccff_tail ( grid_clb_128_ccff_tail ) , .SC_IN_TOP ( scff_Wires_272_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_911 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_912 ) , 
    .SC_OUT_BOT ( scff_Wires_273_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_110 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_20 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_303 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_913 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_914 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_532 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_915 } ) ) ;
grid_clb grid_clb_11__10_ (
    .prog_clk ( { ctsbuf_net_81999 } ) ,
    .Test_en ( Test_en__FEEDTHRU_111 ) , .clk ( clk__FEEDTHRU_20 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__119_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__119_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__119_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__119_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__119_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__119_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__119_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__119_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__119_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__119_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__119_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__119_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__119_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__119_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__119_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__119_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_119_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_916 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__129_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__129_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__129_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__129_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__129_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__129_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__129_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__129_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__129_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__129_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__129_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__129_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__129_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__129_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__129_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__129_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_11__10__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__117_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_129_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_129_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_129_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_129_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_129_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_129_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_129_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_129_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_129_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_129_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_129_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_129_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_129_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_129_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_129_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_129_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_129_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_129_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_129_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_129_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_129_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_129_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_129_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_129_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_129_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_129_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_129_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_129_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_129_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_129_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_129_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_129_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_129_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_917 } ) ,
    .ccff_tail ( grid_clb_129_ccff_tail ) , .SC_IN_TOP ( scff_Wires_270_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_918 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_919 ) , 
    .SC_OUT_BOT ( scff_Wires_271_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_112 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_21 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_698 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_920 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_921 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_304 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_922 } ) ) ;
grid_clb grid_clb_11__11_ (
    .prog_clk ( { ctsbuf_net_52970 } ) ,
    .Test_en ( Test_en__FEEDTHRU_113 ) , .clk ( clk__FEEDTHRU_21 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__120_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__120_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__120_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__120_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__120_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__120_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__120_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__120_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__120_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__120_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__120_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__120_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__120_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__120_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__120_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__120_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_120_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_923 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__130_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__130_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__130_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__130_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__130_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__130_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__130_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__130_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__130_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__130_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__130_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__130_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__130_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__130_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__130_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__130_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_11__11__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__118_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_130_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_130_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_130_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_130_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_130_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_130_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_130_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_130_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_130_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_130_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_130_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_130_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_130_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_130_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_130_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_130_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_130_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_130_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_130_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_130_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_130_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_130_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_130_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_130_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_130_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_130_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_130_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_130_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_130_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_130_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_130_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_130_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_130_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_924 } ) ,
    .ccff_tail ( grid_clb_130_ccff_tail ) , .SC_IN_TOP ( scff_Wires_268_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_925 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_926 ) , 
    .SC_OUT_BOT ( scff_Wires_269_ ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_114 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_22 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_424 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_927 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_928 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_911 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_929 } ) ) ;
grid_clb grid_clb_11__12_ (
    .prog_clk ( { ctsbuf_net_30948 } ) ,
    .Test_en ( Test_en__FEEDTHRU_115 ) , .clk ( clk__FEEDTHRU_22 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__12__10_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__12__10_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__12__10_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__12__10_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__12__10_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__12__10_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__12__10_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__12__10_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__12__10_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__12__10_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__12__10_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__12__10_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__12__10_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__12__10_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__12__10_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__12__10_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_141_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_930 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_1__1__131_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_1__1__131_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_1__1__131_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_1__1__131_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_1__1__131_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_1__1__131_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_1__1__131_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_1__1__131_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_1__1__131_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_1__1__131_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_1__1__131_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_1__1__131_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_1__1__131_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_1__1__131_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_1__1__131_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_1__1__131_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_11__12__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__119_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_131_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_131_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_131_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_131_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_131_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_131_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_131_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_131_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_131_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_131_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_131_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_131_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_131_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_131_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_131_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_131_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_131_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_131_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_131_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_131_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_131_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_131_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_131_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_131_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_131_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_131_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_131_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_131_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_131_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_131_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_131_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_131_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_131_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_931 } ) ,
    .ccff_tail ( grid_clb_131_ccff_tail ) , .SC_IN_TOP ( scff_Wires_266_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_932 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_933 ) , 
    .SC_OUT_BOT ( scff_Wires_267_ ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_934 } ) ,
    .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_935 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_605 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_936 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_937 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_908 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_938 } ) ) ;
grid_clb grid_clb_12__1_ (
    .prog_clk ( { ctsbuf_net_4471365 } ) ,
    .Test_en ( Test_en__FEEDTHRU_116 ) ,
    .clk ( { ctsbuf_net_1919 } ) ,
    .top_width_0_height_0__pin_0_ ( cbx_1__1__121_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__121_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__121_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__121_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__121_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__121_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__121_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__121_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__121_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__121_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__121_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__121_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__121_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__121_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__121_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__121_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_121_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_939 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_12__1__0_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_12__1__0_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_12__1__0_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_12__1__0_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_12__1__0_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_12__1__0_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_12__1__0_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_12__1__0_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_12__1__0_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_12__1__0_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_12__1__0_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_12__1__0_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_12__1__0_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_12__1__0_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_12__1__0_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_12__1__0_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_12__1__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__120_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_132_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_132_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_132_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_132_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_132_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_132_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_132_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_132_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_132_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_132_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_132_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_132_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_132_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_132_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_132_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_132_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_132_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_132_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_132_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_132_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_132_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_132_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_132_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_132_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_132_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_132_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_132_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_132_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_132_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_132_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_132_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_132_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_12__1__undriven_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_940 } ) ,
    .ccff_tail ( grid_clb_132_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_941 ) , .SC_IN_BOT ( scff_Wires_293_ ) , 
    .SC_OUT_TOP ( scff_Wires_294_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_942 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_117 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_1 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_356 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_943 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_944 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { scff_Wires_292_ } ) ,
    .scff_Wires__FEEDTHRU_1 ( { scff_Wires__FEEDTHRU_1_292_ } ) ) ;
grid_clb grid_clb_12__2_ (
    .prog_clk ( { ctsbuf_net_3991317 } ) ,
    .Test_en ( Test_en__FEEDTHRU_118 ) , .clk ( clk__FEEDTHRU_1 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__122_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__122_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__122_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__122_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__122_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__122_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__122_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__122_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__122_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__122_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__122_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__122_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__122_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__122_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__122_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__122_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_122_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_945 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_12__1__1_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_12__1__1_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_12__1__1_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_12__1__1_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_12__1__1_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_12__1__1_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_12__1__1_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_12__1__1_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_12__1__1_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_12__1__1_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_12__1__1_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_12__1__1_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_12__1__1_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_12__1__1_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_12__1__1_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_12__1__1_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_12__2__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__121_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_133_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_133_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_133_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_133_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_133_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_133_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_133_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_133_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_133_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_133_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_133_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_133_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_133_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_133_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_133_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_133_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_133_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_133_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_133_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_133_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_133_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_133_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_133_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_133_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_133_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_133_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_133_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_133_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_133_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_133_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_133_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_133_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_133_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_946 } ) ,
    .ccff_tail ( grid_clb_133_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_947 ) , .SC_IN_BOT ( scff_Wires_295_ ) , 
    .SC_OUT_TOP ( scff_Wires_296_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_948 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_119 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_2 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_512 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_949 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_950 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_588 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_951 } ) ) ;
grid_clb grid_clb_12__3_ (
    .prog_clk ( { ctsbuf_net_3511269 } ) ,
    .Test_en ( Test_en__FEEDTHRU_120 ) , .clk ( clk__FEEDTHRU_2 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__123_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__123_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__123_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__123_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__123_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__123_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__123_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__123_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__123_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__123_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__123_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__123_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__123_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__123_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__123_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__123_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_123_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_952 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_12__1__2_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_12__1__2_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_12__1__2_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_12__1__2_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_12__1__2_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_12__1__2_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_12__1__2_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_12__1__2_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_12__1__2_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_12__1__2_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_12__1__2_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_12__1__2_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_12__1__2_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_12__1__2_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_12__1__2_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_12__1__2_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_12__3__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__122_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_134_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_134_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_134_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_134_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_134_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_134_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_134_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_134_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_134_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_134_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_134_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_134_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_134_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_134_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_134_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_134_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_134_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_134_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_134_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_134_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_134_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_134_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_134_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_134_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_134_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_134_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_134_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_134_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_134_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_134_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_134_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_134_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_134_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_953 } ) ,
    .ccff_tail ( grid_clb_134_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_954 ) , .SC_IN_BOT ( scff_Wires_297_ ) , 
    .SC_OUT_TOP ( scff_Wires_298_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_955 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_121 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_3 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_467 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_956 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_957 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_653 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_958 } ) ) ;
grid_clb grid_clb_12__4_ (
    .prog_clk ( { ctsbuf_net_3031221 } ) ,
    .Test_en ( Test_en__FEEDTHRU_122 ) , .clk ( clk__FEEDTHRU_3 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__124_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__124_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__124_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__124_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__124_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__124_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__124_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__124_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__124_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__124_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__124_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__124_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__124_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__124_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__124_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__124_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_124_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_959 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_12__1__3_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_12__1__3_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_12__1__3_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_12__1__3_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_12__1__3_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_12__1__3_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_12__1__3_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_12__1__3_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_12__1__3_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_12__1__3_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_12__1__3_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_12__1__3_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_12__1__3_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_12__1__3_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_12__1__3_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_12__1__3_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_12__4__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__123_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_135_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_135_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_135_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_135_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_135_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_135_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_135_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_135_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_135_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_135_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_135_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_135_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_135_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_135_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_135_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_135_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_135_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_135_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_135_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_135_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_135_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_135_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_135_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_135_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_135_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_135_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_135_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_135_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_135_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_135_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_135_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_135_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_135_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_960 } ) ,
    .ccff_tail ( grid_clb_135_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_961 ) , .SC_IN_BOT ( scff_Wires_299_ ) , 
    .SC_OUT_TOP ( scff_Wires_300_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_962 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_123 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_4 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_296 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_963 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_964 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_609 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_965 } ) ) ;
grid_clb grid_clb_12__5_ (
    .prog_clk ( { ctsbuf_net_2551173 } ) ,
    .Test_en ( Test_en__FEEDTHRU_124 ) , .clk ( clk__FEEDTHRU_4 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__125_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__125_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__125_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__125_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__125_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__125_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__125_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__125_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__125_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__125_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__125_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__125_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__125_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__125_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__125_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__125_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_125_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_966 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_12__1__4_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_12__1__4_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_12__1__4_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_12__1__4_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_12__1__4_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_12__1__4_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_12__1__4_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_12__1__4_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_12__1__4_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_12__1__4_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_12__1__4_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_12__1__4_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_12__1__4_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_12__1__4_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_12__1__4_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_12__1__4_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_12__5__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__124_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_136_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_136_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_136_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_136_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_136_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_136_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_136_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_136_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_136_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_136_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_136_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_136_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_136_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_136_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_136_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_136_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_136_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_136_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_136_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_136_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_136_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_136_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_136_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_136_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_136_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_136_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_136_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_136_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_136_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_136_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_136_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_136_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_136_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_967 } ) ,
    .ccff_tail ( grid_clb_136_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_968 ) , .SC_IN_BOT ( scff_Wires_301_ ) , 
    .SC_OUT_TOP ( scff_Wires_302_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_969 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_125 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_5 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_780 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_970 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_971 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_627 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_972 } ) ) ;
grid_clb grid_clb_12__6_ (
    .prog_clk ( { ctsbuf_net_2071125 } ) ,
    .Test_en ( Test_en__FEEDTHRU_126 ) , .clk ( clk__FEEDTHRU_5 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__126_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__126_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__126_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__126_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__126_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__126_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__126_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__126_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__126_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__126_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__126_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__126_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__126_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__126_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__126_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__126_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_126_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_973 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_12__1__5_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_12__1__5_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_12__1__5_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_12__1__5_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_12__1__5_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_12__1__5_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_12__1__5_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_12__1__5_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_12__1__5_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_12__1__5_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_12__1__5_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_12__1__5_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_12__1__5_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_12__1__5_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_12__1__5_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_12__1__5_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_12__6__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__125_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_137_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_137_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_137_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_137_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_137_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_137_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_137_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_137_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_137_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_137_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_137_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_137_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_137_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_137_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_137_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_137_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_137_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_137_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_137_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_137_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_137_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_137_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_137_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_137_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_137_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_137_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_137_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_137_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_137_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_137_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_137_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_137_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_137_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_974 } ) ,
    .ccff_tail ( grid_clb_137_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_975 ) , .SC_IN_BOT ( scff_Wires_303_ ) , 
    .SC_OUT_TOP ( scff_Wires_304_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_976 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_127 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_6 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_334 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_977 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_978 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_449 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_979 } ) ) ;
grid_clb grid_clb_12__7_ (
    .prog_clk ( { ctsbuf_net_1591077 } ) ,
    .Test_en ( Test_en__FEEDTHRU_128 ) , .clk ( clk__FEEDTHRU_6 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__127_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__127_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__127_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__127_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__127_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__127_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__127_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__127_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__127_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__127_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__127_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__127_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__127_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__127_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__127_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__127_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_127_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_980 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_12__1__6_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_12__1__6_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_12__1__6_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_12__1__6_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_12__1__6_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_12__1__6_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_12__1__6_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_12__1__6_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_12__1__6_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_12__1__6_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_12__1__6_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_12__1__6_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_12__1__6_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_12__1__6_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_12__1__6_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_12__1__6_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_12__7__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__126_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_138_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_138_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_138_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_138_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_138_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_138_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_138_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_138_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_138_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_138_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_138_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_138_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_138_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_138_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_138_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_138_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_138_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_138_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_138_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_138_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_138_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_138_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_138_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_138_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_138_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_138_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_138_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_138_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_138_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_138_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_138_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_138_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_138_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_981 } ) ,
    .ccff_tail ( grid_clb_138_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_982 ) , .SC_IN_BOT ( scff_Wires_305_ ) , 
    .SC_OUT_TOP ( scff_Wires_306_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_983 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_129 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_7 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_291 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_984 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_985 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_831 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_986 } ) ) ;
grid_clb grid_clb_12__8_ (
    .prog_clk ( { ctsbuf_net_1151033 } ) ,
    .Test_en ( Test_en__FEEDTHRU_130 ) , .clk ( clk__FEEDTHRU_7 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__128_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__128_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__128_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__128_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__128_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__128_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__128_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__128_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__128_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__128_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__128_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__128_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__128_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__128_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__128_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__128_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_128_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_987 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_12__1__7_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_12__1__7_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_12__1__7_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_12__1__7_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_12__1__7_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_12__1__7_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_12__1__7_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_12__1__7_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_12__1__7_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_12__1__7_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_12__1__7_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_12__1__7_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_12__1__7_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_12__1__7_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_12__1__7_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_12__1__7_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_12__8__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__127_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_139_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_139_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_139_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_139_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_139_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_139_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_139_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_139_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_139_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_139_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_139_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_139_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_139_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_139_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_139_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_139_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_139_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_139_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_139_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_139_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_139_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_139_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_139_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_139_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_139_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_139_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_139_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_139_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_139_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_139_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_139_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_139_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_139_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_988 } ) ,
    .ccff_tail ( grid_clb_139_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_989 ) , .SC_IN_BOT ( scff_Wires_307_ ) , 
    .SC_OUT_TOP ( scff_Wires_308_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_990 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_131 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_8 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_618 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_991 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_992 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_717 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_993 } ) ) ;
grid_clb grid_clb_12__9_ (
    .prog_clk ( { ctsbuf_net_79997 } ) ,
    .Test_en ( Test_en__FEEDTHRU_132 ) , .clk ( clk__FEEDTHRU_8 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__129_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__129_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__129_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__129_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__129_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__129_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__129_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__129_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__129_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__129_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__129_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__129_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__129_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__129_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__129_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__129_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_129_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_994 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_12__1__8_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_12__1__8_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_12__1__8_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_12__1__8_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_12__1__8_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_12__1__8_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_12__1__8_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_12__1__8_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_12__1__8_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_12__1__8_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_12__1__8_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_12__1__8_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_12__1__8_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_12__1__8_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_12__1__8_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_12__1__8_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_12__9__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__128_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_140_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_140_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_140_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_140_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_140_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_140_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_140_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_140_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_140_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_140_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_140_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_140_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_140_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_140_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_140_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_140_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_140_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_140_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_140_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_140_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_140_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_140_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_140_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_140_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_140_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_140_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_140_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_140_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_140_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_140_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_140_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_140_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_140_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_995 } ) ,
    .ccff_tail ( grid_clb_140_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_996 ) , .SC_IN_BOT ( scff_Wires_309_ ) , 
    .SC_OUT_TOP ( scff_Wires_310_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_997 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_133 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_9 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_669 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_998 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_999 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_264 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1000 } ) ) ;
grid_clb grid_clb_12__10_ (
    .prog_clk ( { ctsbuf_net_50968 } ) ,
    .Test_en ( Test_en__FEEDTHRU_134 ) , .clk ( clk__FEEDTHRU_9 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__130_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__130_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__130_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__130_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__130_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__130_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__130_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__130_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__130_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__130_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__130_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__130_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__130_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__130_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__130_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__130_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_130_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1001 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_12__1__9_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_12__1__9_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_12__1__9_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_12__1__9_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_12__1__9_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_12__1__9_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_12__1__9_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_12__1__9_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_12__1__9_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_12__1__9_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_12__1__9_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_12__1__9_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_12__1__9_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_12__1__9_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_12__1__9_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_12__1__9_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_12__10__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__129_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_141_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_141_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_141_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_141_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_141_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_141_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_141_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_141_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_141_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_141_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_141_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_141_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_141_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_141_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_141_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_141_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_141_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_141_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_141_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_141_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_141_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_141_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_141_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_141_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_141_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_141_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_141_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_141_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_141_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_141_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_141_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_141_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_141_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1002 } ) ,
    .ccff_tail ( grid_clb_141_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1003 ) , 
    .SC_IN_BOT ( scff_Wires_311_ ) , .SC_OUT_TOP ( scff_Wires_312_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1004 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_135 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_10 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_312 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1005 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_1006 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_497 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1007 } ) ) ;
grid_clb grid_clb_12__11_ (
    .prog_clk ( { ctsbuf_net_13931 } ) ,
    .Test_en ( Test_en__FEEDTHRU_136 ) , .clk ( clk__FEEDTHRU_10 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__1__131_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__1__131_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__1__131_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__1__131_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__1__131_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__1__131_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__1__131_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__1__131_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__1__131_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__1__131_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__1__131_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__1__131_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__1__131_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__1__131_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__1__131_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__1__131_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_131_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1008 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_12__1__10_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_12__1__10_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_12__1__10_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_12__1__10_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_12__1__10_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_12__1__10_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_12__1__10_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_12__1__10_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_12__1__10_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_12__1__10_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_12__1__10_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_12__1__10_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_12__1__10_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_12__1__10_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_12__1__10_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_12__1__10_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_12__11__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__130_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_142_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_142_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_142_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_142_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_142_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_142_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_142_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_142_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_142_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_142_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_142_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_142_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_142_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_142_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_142_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_142_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_142_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_142_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_142_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_142_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_142_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_142_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_142_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_142_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_142_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_142_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_142_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_142_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_142_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_142_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_142_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_142_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_142_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1009 } ) ,
    .ccff_tail ( grid_clb_142_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1010 ) , 
    .SC_IN_BOT ( scff_Wires_313_ ) , .SC_OUT_TOP ( scff_Wires_314_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1011 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_137 ) , 
    .clk__FEEDTHRU_1 ( clk__FEEDTHRU_11 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_358 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1012 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_1013 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_357 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1014 } ) ) ;
grid_clb grid_clb_12__12_ (
    .prog_clk ( { ctsbuf_net_16934 } ) ,
    .Test_en ( Test_en__FEEDTHRU_138 ) , .clk ( clk__FEEDTHRU_11 ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__12__11_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_1_ ( cbx_1__12__11_bottom_grid_pin_1_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__12__11_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_3_ ( cbx_1__12__11_bottom_grid_pin_3_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__12__11_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_5_ ( cbx_1__12__11_bottom_grid_pin_5_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__12__11_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_7_ ( cbx_1__12__11_bottom_grid_pin_7_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__12__11_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_9_ ( cbx_1__12__11_bottom_grid_pin_9_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__12__11_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_11_ ( cbx_1__12__11_bottom_grid_pin_11_ ) , 
    .top_width_0_height_0__pin_12_ ( cbx_1__12__11_bottom_grid_pin_12_ ) , 
    .top_width_0_height_0__pin_13_ ( cbx_1__12__11_bottom_grid_pin_13_ ) , 
    .top_width_0_height_0__pin_14_ ( cbx_1__12__11_bottom_grid_pin_14_ ) , 
    .top_width_0_height_0__pin_15_ ( cbx_1__12__11_bottom_grid_pin_15_ ) , 
    .top_width_0_height_0__pin_32_ ( direct_interc_142_out ) ,
    .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1015 } ) ,
    .right_width_0_height_0__pin_16_ ( cby_12__1__11_left_grid_pin_16_ ) , 
    .right_width_0_height_0__pin_17_ ( cby_12__1__11_left_grid_pin_17_ ) , 
    .right_width_0_height_0__pin_18_ ( cby_12__1__11_left_grid_pin_18_ ) , 
    .right_width_0_height_0__pin_19_ ( cby_12__1__11_left_grid_pin_19_ ) , 
    .right_width_0_height_0__pin_20_ ( cby_12__1__11_left_grid_pin_20_ ) , 
    .right_width_0_height_0__pin_21_ ( cby_12__1__11_left_grid_pin_21_ ) , 
    .right_width_0_height_0__pin_22_ ( cby_12__1__11_left_grid_pin_22_ ) , 
    .right_width_0_height_0__pin_23_ ( cby_12__1__11_left_grid_pin_23_ ) , 
    .right_width_0_height_0__pin_24_ ( cby_12__1__11_left_grid_pin_24_ ) , 
    .right_width_0_height_0__pin_25_ ( cby_12__1__11_left_grid_pin_25_ ) , 
    .right_width_0_height_0__pin_26_ ( cby_12__1__11_left_grid_pin_26_ ) , 
    .right_width_0_height_0__pin_27_ ( cby_12__1__11_left_grid_pin_27_ ) , 
    .right_width_0_height_0__pin_28_ ( cby_12__1__11_left_grid_pin_28_ ) , 
    .right_width_0_height_0__pin_29_ ( cby_12__1__11_left_grid_pin_29_ ) , 
    .right_width_0_height_0__pin_30_ ( cby_12__1__11_left_grid_pin_30_ ) , 
    .right_width_0_height_0__pin_31_ ( cby_12__1__11_left_grid_pin_31_ ) , 
    .left_width_0_height_0__pin_52_ ( grid_clb_12__12__undriven_left_width_0_height_0__pin_52_ ) , 
    .ccff_head ( cby_1__1__131_ccff_tail ) , 
    .top_width_0_height_0__pin_34_upper ( grid_clb_143_top_width_0_height_0__pin_34_upper ) , 
    .top_width_0_height_0__pin_34_lower ( grid_clb_143_top_width_0_height_0__pin_34_lower ) , 
    .top_width_0_height_0__pin_35_upper ( grid_clb_143_top_width_0_height_0__pin_35_upper ) , 
    .top_width_0_height_0__pin_35_lower ( grid_clb_143_top_width_0_height_0__pin_35_lower ) , 
    .top_width_0_height_0__pin_36_upper ( grid_clb_143_top_width_0_height_0__pin_36_upper ) , 
    .top_width_0_height_0__pin_36_lower ( grid_clb_143_top_width_0_height_0__pin_36_lower ) , 
    .top_width_0_height_0__pin_37_upper ( grid_clb_143_top_width_0_height_0__pin_37_upper ) , 
    .top_width_0_height_0__pin_37_lower ( grid_clb_143_top_width_0_height_0__pin_37_lower ) , 
    .top_width_0_height_0__pin_38_upper ( grid_clb_143_top_width_0_height_0__pin_38_upper ) , 
    .top_width_0_height_0__pin_38_lower ( grid_clb_143_top_width_0_height_0__pin_38_lower ) , 
    .top_width_0_height_0__pin_39_upper ( grid_clb_143_top_width_0_height_0__pin_39_upper ) , 
    .top_width_0_height_0__pin_39_lower ( grid_clb_143_top_width_0_height_0__pin_39_lower ) , 
    .top_width_0_height_0__pin_40_upper ( grid_clb_143_top_width_0_height_0__pin_40_upper ) , 
    .top_width_0_height_0__pin_40_lower ( grid_clb_143_top_width_0_height_0__pin_40_lower ) , 
    .top_width_0_height_0__pin_41_upper ( grid_clb_143_top_width_0_height_0__pin_41_upper ) , 
    .top_width_0_height_0__pin_41_lower ( grid_clb_143_top_width_0_height_0__pin_41_lower ) , 
    .right_width_0_height_0__pin_42_upper ( grid_clb_143_right_width_0_height_0__pin_42_upper ) , 
    .right_width_0_height_0__pin_42_lower ( grid_clb_143_right_width_0_height_0__pin_42_lower ) , 
    .right_width_0_height_0__pin_43_upper ( grid_clb_143_right_width_0_height_0__pin_43_upper ) , 
    .right_width_0_height_0__pin_43_lower ( grid_clb_143_right_width_0_height_0__pin_43_lower ) , 
    .right_width_0_height_0__pin_44_upper ( grid_clb_143_right_width_0_height_0__pin_44_upper ) , 
    .right_width_0_height_0__pin_44_lower ( grid_clb_143_right_width_0_height_0__pin_44_lower ) , 
    .right_width_0_height_0__pin_45_upper ( grid_clb_143_right_width_0_height_0__pin_45_upper ) , 
    .right_width_0_height_0__pin_45_lower ( grid_clb_143_right_width_0_height_0__pin_45_lower ) , 
    .right_width_0_height_0__pin_46_upper ( grid_clb_143_right_width_0_height_0__pin_46_upper ) , 
    .right_width_0_height_0__pin_46_lower ( grid_clb_143_right_width_0_height_0__pin_46_lower ) , 
    .right_width_0_height_0__pin_47_upper ( grid_clb_143_right_width_0_height_0__pin_47_upper ) , 
    .right_width_0_height_0__pin_47_lower ( grid_clb_143_right_width_0_height_0__pin_47_lower ) , 
    .right_width_0_height_0__pin_48_upper ( grid_clb_143_right_width_0_height_0__pin_48_upper ) , 
    .right_width_0_height_0__pin_48_lower ( grid_clb_143_right_width_0_height_0__pin_48_lower ) , 
    .right_width_0_height_0__pin_49_upper ( grid_clb_143_right_width_0_height_0__pin_49_upper ) , 
    .right_width_0_height_0__pin_49_lower ( grid_clb_143_right_width_0_height_0__pin_49_lower ) , 
    .bottom_width_0_height_0__pin_50_ ( grid_clb_143_bottom_width_0_height_0__pin_50_ ) ,
    .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_1016 } ) ,
    .ccff_tail ( grid_clb_143_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1017 ) , 
    .SC_IN_BOT ( scff_Wires_315_ ) , .SC_OUT_TOP ( scff_Wires_316_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1018 ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1019 } ) ,
    .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1020 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_348 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1021 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ( { 
        SYNOPSYS_UNCONNECTED_1022 } ) ,
    .scff_Wires__FEEDTHRU_0 ( { optlc_net_747 } ) ,
    .scff_Wires__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1023 } ) ) ;
sb_0__0_ sb_0__0_ (
    .prog_clk ( { ctsbuf_net_4441362 } ) ,
    .chany_top_in ( cby_0__1__0_chany_bottom_out ) , 
    .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , 
    .chanx_right_in ( cbx_1__0__0_chanx_left_out ) , 
    .right_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , 
    .right_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , 
    .right_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , 
    .right_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , 
    .right_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , 
    .ccff_head ( grid_io_bottom_0_ccff_tail ) , 
    .chany_top_out ( sb_0__0__0_chany_top_out ) , 
    .chanx_right_out ( sb_0__0__0_chanx_right_out ) , 
    .ccff_tail ( ccff_tail ) , 
    .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , 
    .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ) ;
sb_0__1_ sb_0__1_ (
    .prog_clk ( { ctsbuf_net_3981316 } ) ,
    .chany_top_in ( cby_0__1__1_chany_bottom_out ) , 
    .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , 
    .chanx_right_in ( cbx_1__1__0_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_0_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_0_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_0__1__0_chany_top_out ) , 
    .bottom_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , 
    .ccff_head ( cbx_1__1__0_ccff_tail ) , 
    .chany_top_out ( sb_0__1__0_chany_top_out ) , 
    .chanx_right_out ( sb_0__1__0_chanx_right_out ) , 
    .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , 
    .ccff_tail ( sb_0__1__0_ccff_tail ) ) ;
sb_0__1_ sb_0__2_ (
    .prog_clk ( { ctsbuf_net_3501268 } ) ,
    .chany_top_in ( cby_0__1__2_chany_bottom_out ) , 
    .top_left_grid_pin_1_ ( grid_io_left_2_right_width_0_height_0__pin_1_lower ) , 
    .chanx_right_in ( cbx_1__1__1_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_1_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_0__1__1_chany_top_out ) , 
    .bottom_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , 
    .ccff_head ( cbx_1__1__1_ccff_tail ) , 
    .chany_top_out ( sb_0__1__1_chany_top_out ) , 
    .chanx_right_out ( sb_0__1__1_chanx_right_out ) , 
    .chany_bottom_out ( sb_0__1__1_chany_bottom_out ) , 
    .ccff_tail ( sb_0__1__1_ccff_tail ) ) ;
sb_0__1_ sb_0__3_ (
    .prog_clk ( { ctsbuf_net_3021220 } ) ,
    .chany_top_in ( cby_0__1__3_chany_bottom_out ) , 
    .top_left_grid_pin_1_ ( grid_io_left_3_right_width_0_height_0__pin_1_lower ) , 
    .chanx_right_in ( cbx_1__1__2_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_2_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_2_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_0__1__2_chany_top_out ) , 
    .bottom_left_grid_pin_1_ ( grid_io_left_2_right_width_0_height_0__pin_1_upper ) , 
    .ccff_head ( cbx_1__1__2_ccff_tail ) , 
    .chany_top_out ( sb_0__1__2_chany_top_out ) , 
    .chanx_right_out ( sb_0__1__2_chanx_right_out ) , 
    .chany_bottom_out ( sb_0__1__2_chany_bottom_out ) , 
    .ccff_tail ( sb_0__1__2_ccff_tail ) ) ;
sb_0__1_ sb_0__4_ (
    .prog_clk ( { ctsbuf_net_2541172 } ) ,
    .chany_top_in ( cby_0__1__4_chany_bottom_out ) , 
    .top_left_grid_pin_1_ ( grid_io_left_4_right_width_0_height_0__pin_1_lower ) , 
    .chanx_right_in ( cbx_1__1__3_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_3_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_0__1__3_chany_top_out ) , 
    .bottom_left_grid_pin_1_ ( grid_io_left_3_right_width_0_height_0__pin_1_upper ) , 
    .ccff_head ( cbx_1__1__3_ccff_tail ) , 
    .chany_top_out ( sb_0__1__3_chany_top_out ) , 
    .chanx_right_out ( sb_0__1__3_chanx_right_out ) , 
    .chany_bottom_out ( sb_0__1__3_chany_bottom_out ) , 
    .ccff_tail ( sb_0__1__3_ccff_tail ) ) ;
sb_0__1_ sb_0__5_ (
    .prog_clk ( { p_abuf24 } ) ,
    .chany_top_in ( cby_0__1__5_chany_bottom_out ) , 
    .top_left_grid_pin_1_ ( grid_io_left_5_right_width_0_height_0__pin_1_lower ) , 
    .chanx_right_in ( cbx_1__1__4_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_4_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_4_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_4_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_4_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_4_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_4_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_4_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_4_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_0__1__4_chany_top_out ) , 
    .bottom_left_grid_pin_1_ ( grid_io_left_4_right_width_0_height_0__pin_1_upper ) , 
    .ccff_head ( cbx_1__1__4_ccff_tail ) , 
    .chany_top_out ( sb_0__1__4_chany_top_out ) , 
    .chanx_right_out ( sb_0__1__4_chanx_right_out ) , 
    .chany_bottom_out ( sb_0__1__4_chany_bottom_out ) , 
    .ccff_tail ( sb_0__1__4_ccff_tail ) ) ;
sb_0__1_ sb_0__6_ (
    .prog_clk ( { ctsbuf_net_1581076 } ) ,
    .chany_top_in ( cby_0__1__6_chany_bottom_out ) , 
    .top_left_grid_pin_1_ ( grid_io_left_6_right_width_0_height_0__pin_1_lower ) , 
    .chanx_right_in ( cbx_1__1__5_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_5_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_5_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_5_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_5_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_5_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_5_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_5_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_5_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_0__1__5_chany_top_out ) , 
    .bottom_left_grid_pin_1_ ( grid_io_left_5_right_width_0_height_0__pin_1_upper ) , 
    .ccff_head ( cbx_1__1__5_ccff_tail ) , 
    .chany_top_out ( sb_0__1__5_chany_top_out ) , 
    .chanx_right_out ( sb_0__1__5_chanx_right_out ) , 
    .chany_bottom_out ( sb_0__1__5_chany_bottom_out ) , 
    .ccff_tail ( sb_0__1__5_ccff_tail ) ) ;
sb_0__1_ sb_0__7_ (
    .prog_clk ( { ctsbuf_net_1141032 } ) ,
    .chany_top_in ( cby_0__1__7_chany_bottom_out ) , 
    .top_left_grid_pin_1_ ( grid_io_left_7_right_width_0_height_0__pin_1_lower ) , 
    .chanx_right_in ( cbx_1__1__6_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_6_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_6_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_6_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_6_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_6_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_6_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_6_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_6_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_0__1__6_chany_top_out ) , 
    .bottom_left_grid_pin_1_ ( grid_io_left_6_right_width_0_height_0__pin_1_upper ) , 
    .ccff_head ( cbx_1__1__6_ccff_tail ) , 
    .chany_top_out ( sb_0__1__6_chany_top_out ) , 
    .chanx_right_out ( sb_0__1__6_chanx_right_out ) , 
    .chany_bottom_out ( sb_0__1__6_chany_bottom_out ) , 
    .ccff_tail ( sb_0__1__6_ccff_tail ) ) ;
sb_0__1_ sb_0__8_ (
    .prog_clk ( { ctsbuf_net_78996 } ) ,
    .chany_top_in ( cby_0__1__8_chany_bottom_out ) , 
    .top_left_grid_pin_1_ ( grid_io_left_8_right_width_0_height_0__pin_1_lower ) , 
    .chanx_right_in ( cbx_1__1__7_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_7_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_7_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_7_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_7_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_7_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_7_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_7_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_7_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_0__1__7_chany_top_out ) , 
    .bottom_left_grid_pin_1_ ( grid_io_left_7_right_width_0_height_0__pin_1_upper ) , 
    .ccff_head ( cbx_1__1__7_ccff_tail ) , 
    .chany_top_out ( sb_0__1__7_chany_top_out ) , 
    .chanx_right_out ( sb_0__1__7_chanx_right_out ) , 
    .chany_bottom_out ( sb_0__1__7_chany_bottom_out ) , 
    .ccff_tail ( sb_0__1__7_ccff_tail ) ) ;
sb_0__1_ sb_0__9_ (
    .prog_clk ( { ctsbuf_net_49967 } ) ,
    .chany_top_in ( cby_0__1__9_chany_bottom_out ) , 
    .top_left_grid_pin_1_ ( grid_io_left_9_right_width_0_height_0__pin_1_lower ) , 
    .chanx_right_in ( cbx_1__1__8_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_8_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_8_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_8_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_8_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_8_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_8_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_8_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_8_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_0__1__8_chany_top_out ) , 
    .bottom_left_grid_pin_1_ ( grid_io_left_8_right_width_0_height_0__pin_1_upper ) , 
    .ccff_head ( cbx_1__1__8_ccff_tail ) , 
    .chany_top_out ( sb_0__1__8_chany_top_out ) , 
    .chanx_right_out ( sb_0__1__8_chanx_right_out ) , 
    .chany_bottom_out ( sb_0__1__8_chany_bottom_out ) , 
    .ccff_tail ( sb_0__1__8_ccff_tail ) ) ;
sb_0__1_ sb_0__10_ (
    .prog_clk ( { ctsbuf_net_28946 } ) ,
    .chany_top_in ( cby_0__1__10_chany_bottom_out ) , 
    .top_left_grid_pin_1_ ( grid_io_left_10_right_width_0_height_0__pin_1_lower ) , 
    .chanx_right_in ( cbx_1__1__9_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_9_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_9_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_9_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_9_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_9_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_9_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_9_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_9_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_0__1__9_chany_top_out ) , 
    .bottom_left_grid_pin_1_ ( grid_io_left_9_right_width_0_height_0__pin_1_upper ) , 
    .ccff_head ( cbx_1__1__9_ccff_tail ) , 
    .chany_top_out ( sb_0__1__9_chany_top_out ) , 
    .chanx_right_out ( sb_0__1__9_chanx_right_out ) , 
    .chany_bottom_out ( sb_0__1__9_chany_bottom_out ) , 
    .ccff_tail ( sb_0__1__9_ccff_tail ) ) ;
sb_0__1_ sb_0__11_ (
    .prog_clk ( { ctsbuf_net_15933 } ) ,
    .chany_top_in ( cby_0__1__11_chany_bottom_out ) , 
    .top_left_grid_pin_1_ ( grid_io_left_11_right_width_0_height_0__pin_1_lower ) , 
    .chanx_right_in ( cbx_1__1__10_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_10_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_10_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_10_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_10_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_10_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_10_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_10_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_10_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_0__1__10_chany_top_out ) , 
    .bottom_left_grid_pin_1_ ( grid_io_left_10_right_width_0_height_0__pin_1_upper ) , 
    .ccff_head ( cbx_1__1__10_ccff_tail ) , 
    .chany_top_out ( sb_0__1__10_chany_top_out ) , 
    .chanx_right_out ( sb_0__1__10_chanx_right_out ) , 
    .chany_bottom_out ( sb_0__1__10_chany_bottom_out ) , 
    .ccff_tail ( sb_0__1__10_ccff_tail ) ) ;
sb_0__2_ sb_0__12_ (
    .prog_clk ( { ctsbuf_net_8926 } ) ,
    .chanx_right_in ( cbx_1__12__0_chanx_left_out ) , 
    .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_11_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_11_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_11_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_11_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_11_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_11_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_11_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_11_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_0__1__11_chany_top_out ) , 
    .bottom_left_grid_pin_1_ ( grid_io_left_11_right_width_0_height_0__pin_1_upper ) , 
    .ccff_head ( grid_io_top_0_ccff_tail ) , 
    .chanx_right_out ( sb_0__12__0_chanx_right_out ) , 
    .chany_bottom_out ( sb_0__12__0_chany_bottom_out ) , 
    .ccff_tail ( sb_0__12__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1024 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1025 ) , 
    .SC_OUT_BOT ( scff_Wires_0_ ) ) ;
sb_1__0_ sb_1__0_ (
    .prog_clk ( { ctsbuf_net_4441362 } ) ,
    .chany_top_in ( cby_1__1__0_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_0_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__0__1_chanx_left_out ) , 
    .right_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , 
    .right_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , 
    .right_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , 
    .right_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , 
    .right_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , 
    .chanx_left_in ( cbx_1__0__0_chanx_right_out ) , 
    .left_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , 
    .left_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , 
    .left_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , 
    .left_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , 
    .left_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , 
    .ccff_head ( grid_io_bottom_1_ccff_tail ) , 
    .chany_top_out ( sb_1__0__0_chany_top_out ) , 
    .chanx_right_out ( sb_1__0__0_chanx_right_out ) , 
    .chanx_left_out ( sb_1__0__0_chanx_left_out ) , 
    .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_26_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1026 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1027 ) , 
    .SC_OUT_BOT ( scff_Wires_27_ ) ,
    .Test_en__FEEDTHRU_0 ( { optlc_net_713 } ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1028 } ) ,
    .Test_en__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_1029 } ) ,
    .Test_en__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_1030 } ) ,
    .Test_en__FEEDTHRU_4 ( { optlc_net_487 } ) ,
    .Test_en__FEEDTHRU_5 ( { SYNOPSYS_UNCONNECTED_1031 } ) ,
    .Test_en__FEEDTHRU_6 ( Test_en__FEEDTHRU_148 ) , 
    .Test_en__FEEDTHRU_7 ( Test_en__FEEDTHRU_149 ) ,
    .Test_en__FEEDTHRU_8 ( { SYNOPSYS_UNCONNECTED_1032 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_487 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1033 } ) ) ;
sb_1__0_ sb_2__0_ (
    .prog_clk ( { ctsbuf_net_4871405 } ) ,
    .chany_top_in ( cby_1__1__12_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_12_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_12_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_12_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_12_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_12_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_12_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_12_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_12_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__0__2_chanx_left_out ) , 
    .right_bottom_grid_pin_1_ ( grid_io_bottom_2_top_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_3_ ( grid_io_bottom_2_top_width_0_height_0__pin_3_upper ) , 
    .right_bottom_grid_pin_5_ ( grid_io_bottom_2_top_width_0_height_0__pin_5_upper ) , 
    .right_bottom_grid_pin_7_ ( grid_io_bottom_2_top_width_0_height_0__pin_7_upper ) , 
    .right_bottom_grid_pin_9_ ( grid_io_bottom_2_top_width_0_height_0__pin_9_upper ) , 
    .right_bottom_grid_pin_11_ ( grid_io_bottom_2_top_width_0_height_0__pin_11_upper ) , 
    .chanx_left_in ( cbx_1__0__1_chanx_right_out ) , 
    .left_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , 
    .left_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , 
    .left_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , 
    .left_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , 
    .left_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , 
    .ccff_head ( grid_io_bottom_2_ccff_tail ) , 
    .chany_top_out ( sb_1__0__1_chany_top_out ) , 
    .chanx_right_out ( sb_1__0__1_chanx_right_out ) , 
    .chanx_left_out ( sb_1__0__1_chanx_left_out ) , 
    .ccff_tail ( sb_1__0__1_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1034 ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1035 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1036 ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1037 ) ,
    .Test_en__FEEDTHRU_0 ( { optlc_net_361 } ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1038 } ) ,
    .Test_en__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_1039 } ) ,
    .Test_en__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_1040 } ) ,
    .Test_en__FEEDTHRU_4 ( { optlc_net_495 } ) ,
    .Test_en__FEEDTHRU_5 ( { SYNOPSYS_UNCONNECTED_1041 } ) ,
    .Test_en__FEEDTHRU_6 ( Test_en__FEEDTHRU_146 ) , 
    .Test_en__FEEDTHRU_7 ( Test_en__FEEDTHRU_172 ) , 
    .Test_en__FEEDTHRU_8 ( Test_en__FEEDTHRU_147 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_495 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1042 } ) ) ;
sb_1__0_ sb_3__0_ (
    .prog_clk ( { ctsbuf_net_5221440 } ) ,
    .chany_top_in ( cby_1__1__24_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_24_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_24_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_24_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_24_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_24_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_24_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_24_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_24_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__0__3_chanx_left_out ) , 
    .right_bottom_grid_pin_1_ ( grid_io_bottom_3_top_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_3_ ( grid_io_bottom_3_top_width_0_height_0__pin_3_upper ) , 
    .right_bottom_grid_pin_5_ ( grid_io_bottom_3_top_width_0_height_0__pin_5_upper ) , 
    .right_bottom_grid_pin_7_ ( grid_io_bottom_3_top_width_0_height_0__pin_7_upper ) , 
    .right_bottom_grid_pin_9_ ( grid_io_bottom_3_top_width_0_height_0__pin_9_upper ) , 
    .right_bottom_grid_pin_11_ ( grid_io_bottom_3_top_width_0_height_0__pin_11_upper ) , 
    .chanx_left_in ( cbx_1__0__2_chanx_right_out ) , 
    .left_bottom_grid_pin_1_ ( grid_io_bottom_2_top_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_3_ ( grid_io_bottom_2_top_width_0_height_0__pin_3_lower ) , 
    .left_bottom_grid_pin_5_ ( grid_io_bottom_2_top_width_0_height_0__pin_5_lower ) , 
    .left_bottom_grid_pin_7_ ( grid_io_bottom_2_top_width_0_height_0__pin_7_lower ) , 
    .left_bottom_grid_pin_9_ ( grid_io_bottom_2_top_width_0_height_0__pin_9_lower ) , 
    .left_bottom_grid_pin_11_ ( grid_io_bottom_2_top_width_0_height_0__pin_11_lower ) , 
    .ccff_head ( grid_io_bottom_3_ccff_tail ) , 
    .chany_top_out ( sb_1__0__2_chany_top_out ) , 
    .chanx_right_out ( sb_1__0__2_chanx_right_out ) , 
    .chanx_left_out ( sb_1__0__2_chanx_left_out ) , 
    .ccff_tail ( sb_1__0__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires_79_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1043 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1044 ) , 
    .SC_OUT_BOT ( scff_Wires_80_ ) ,
    .Test_en__FEEDTHRU_0 ( { optlc_net_460 } ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1045 } ) ,
    .Test_en__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_1046 } ) ,
    .Test_en__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_1047 } ) ,
    .Test_en__FEEDTHRU_4 ( { optlc_net_528 } ) ,
    .Test_en__FEEDTHRU_5 ( { SYNOPSYS_UNCONNECTED_1048 } ) ,
    .Test_en__FEEDTHRU_6 ( Test_en__FEEDTHRU_144 ) , 
    .Test_en__FEEDTHRU_7 ( Test_en__FEEDTHRU_195 ) , 
    .Test_en__FEEDTHRU_8 ( Test_en__FEEDTHRU_145 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_528 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1049 } ) ) ;
sb_1__0_ sb_4__0_ (
    .prog_clk ( { ctsbuf_net_5491467 } ) ,
    .chany_top_in ( cby_1__1__36_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_36_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_36_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_36_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_36_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_36_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_36_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_36_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_36_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__0__4_chanx_left_out ) , 
    .right_bottom_grid_pin_1_ ( grid_io_bottom_4_top_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_3_ ( grid_io_bottom_4_top_width_0_height_0__pin_3_upper ) , 
    .right_bottom_grid_pin_5_ ( grid_io_bottom_4_top_width_0_height_0__pin_5_upper ) , 
    .right_bottom_grid_pin_7_ ( grid_io_bottom_4_top_width_0_height_0__pin_7_upper ) , 
    .right_bottom_grid_pin_9_ ( grid_io_bottom_4_top_width_0_height_0__pin_9_upper ) , 
    .right_bottom_grid_pin_11_ ( grid_io_bottom_4_top_width_0_height_0__pin_11_upper ) , 
    .chanx_left_in ( cbx_1__0__3_chanx_right_out ) , 
    .left_bottom_grid_pin_1_ ( grid_io_bottom_3_top_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_3_ ( grid_io_bottom_3_top_width_0_height_0__pin_3_lower ) , 
    .left_bottom_grid_pin_5_ ( grid_io_bottom_3_top_width_0_height_0__pin_5_lower ) , 
    .left_bottom_grid_pin_7_ ( grid_io_bottom_3_top_width_0_height_0__pin_7_lower ) , 
    .left_bottom_grid_pin_9_ ( grid_io_bottom_3_top_width_0_height_0__pin_9_lower ) , 
    .left_bottom_grid_pin_11_ ( grid_io_bottom_3_top_width_0_height_0__pin_11_lower ) , 
    .ccff_head ( grid_io_bottom_4_ccff_tail ) , 
    .chany_top_out ( sb_1__0__3_chany_top_out ) , 
    .chanx_right_out ( sb_1__0__3_chanx_right_out ) , 
    .chanx_left_out ( sb_1__0__3_chanx_left_out ) , 
    .ccff_tail ( sb_1__0__3_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1050 ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1051 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1052 ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1053 ) ,
    .Test_en__FEEDTHRU_0 ( { optlc_net_535 } ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1054 } ) ,
    .Test_en__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_1055 } ) ,
    .Test_en__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_1056 } ) ,
    .Test_en__FEEDTHRU_4 ( { optlc_net_404 } ) ,
    .Test_en__FEEDTHRU_5 ( { SYNOPSYS_UNCONNECTED_1057 } ) ,
    .Test_en__FEEDTHRU_6 ( Test_en__FEEDTHRU_142 ) , 
    .Test_en__FEEDTHRU_7 ( Test_en__FEEDTHRU_218 ) , 
    .Test_en__FEEDTHRU_8 ( Test_en__FEEDTHRU_143 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50_ ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ) ;
sb_1__0_ sb_5__0_ (
    .prog_clk ( { ctsbuf_net_5681486 } ) ,
    .chany_top_in ( cby_1__1__48_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_48_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_48_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_48_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_48_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_48_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_48_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_48_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_48_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__0__5_chanx_left_out ) , 
    .right_bottom_grid_pin_1_ ( grid_io_bottom_5_top_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_3_ ( grid_io_bottom_5_top_width_0_height_0__pin_3_upper ) , 
    .right_bottom_grid_pin_5_ ( grid_io_bottom_5_top_width_0_height_0__pin_5_upper ) , 
    .right_bottom_grid_pin_7_ ( grid_io_bottom_5_top_width_0_height_0__pin_7_upper ) , 
    .right_bottom_grid_pin_9_ ( grid_io_bottom_5_top_width_0_height_0__pin_9_upper ) , 
    .right_bottom_grid_pin_11_ ( grid_io_bottom_5_top_width_0_height_0__pin_11_upper ) , 
    .chanx_left_in ( cbx_1__0__4_chanx_right_out ) , 
    .left_bottom_grid_pin_1_ ( grid_io_bottom_4_top_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_3_ ( grid_io_bottom_4_top_width_0_height_0__pin_3_lower ) , 
    .left_bottom_grid_pin_5_ ( grid_io_bottom_4_top_width_0_height_0__pin_5_lower ) , 
    .left_bottom_grid_pin_7_ ( grid_io_bottom_4_top_width_0_height_0__pin_7_lower ) , 
    .left_bottom_grid_pin_9_ ( grid_io_bottom_4_top_width_0_height_0__pin_9_lower ) , 
    .left_bottom_grid_pin_11_ ( grid_io_bottom_4_top_width_0_height_0__pin_11_lower ) , 
    .ccff_head ( grid_io_bottom_5_ccff_tail ) , 
    .chany_top_out ( sb_1__0__4_chany_top_out ) , 
    .chanx_right_out ( sb_1__0__4_chanx_right_out ) , 
    .chanx_left_out ( sb_1__0__4_chanx_left_out ) , 
    .ccff_tail ( sb_1__0__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires_132_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1058 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1059 ) , 
    .SC_OUT_BOT ( scff_Wires_133_ ) ,
    .Test_en__FEEDTHRU_0 ( { optlc_net_492 } ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1060 } ) ,
    .Test_en__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_1061 } ) ,
    .Test_en__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_1062 } ) ,
    .Test_en__FEEDTHRU_4 ( { optlc_net_856 } ) ,
    .Test_en__FEEDTHRU_5 ( { SYNOPSYS_UNCONNECTED_1063 } ) ,
    .Test_en__FEEDTHRU_6 ( Test_en__FEEDTHRU_140 ) , 
    .Test_en__FEEDTHRU_7 ( Test_en__FEEDTHRU_241 ) , 
    .Test_en__FEEDTHRU_8 ( Test_en__FEEDTHRU_141 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50_ ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ) ;
sb_1__0_ sb_6__0_ (
    .prog_clk ( { ctsbuf_net_5791497 } ) ,
    .chany_top_in ( cby_1__1__60_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_60_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_60_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_60_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_60_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_60_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_60_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_60_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_60_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__0__6_chanx_left_out ) , 
    .right_bottom_grid_pin_1_ ( grid_io_bottom_6_top_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_3_ ( grid_io_bottom_6_top_width_0_height_0__pin_3_upper ) , 
    .right_bottom_grid_pin_5_ ( grid_io_bottom_6_top_width_0_height_0__pin_5_upper ) , 
    .right_bottom_grid_pin_7_ ( grid_io_bottom_6_top_width_0_height_0__pin_7_upper ) , 
    .right_bottom_grid_pin_9_ ( grid_io_bottom_6_top_width_0_height_0__pin_9_upper ) , 
    .right_bottom_grid_pin_11_ ( grid_io_bottom_6_top_width_0_height_0__pin_11_upper ) , 
    .chanx_left_in ( cbx_1__0__5_chanx_right_out ) , 
    .left_bottom_grid_pin_1_ ( grid_io_bottom_5_top_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_3_ ( grid_io_bottom_5_top_width_0_height_0__pin_3_lower ) , 
    .left_bottom_grid_pin_5_ ( grid_io_bottom_5_top_width_0_height_0__pin_5_lower ) , 
    .left_bottom_grid_pin_7_ ( grid_io_bottom_5_top_width_0_height_0__pin_7_lower ) , 
    .left_bottom_grid_pin_9_ ( grid_io_bottom_5_top_width_0_height_0__pin_9_lower ) , 
    .left_bottom_grid_pin_11_ ( grid_io_bottom_5_top_width_0_height_0__pin_11_lower ) , 
    .ccff_head ( grid_io_bottom_6_ccff_tail ) , 
    .chany_top_out ( sb_1__0__5_chany_top_out ) , 
    .chanx_right_out ( sb_1__0__5_chanx_right_out ) , 
    .chanx_left_out ( sb_1__0__5_chanx_left_out ) , 
    .ccff_tail ( sb_1__0__5_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1064 ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1065 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1066 ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1067 ) , 
    .Test_en__FEEDTHRU_0 ( Test_en ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_264 ) , 
    .Test_en__FEEDTHRU_2 ( Test_en__FEEDTHRU_139 ) , 
    .Test_en__FEEDTHRU_3 ( Test_en__FEEDTHRU_1 ) ,
    .Test_en__FEEDTHRU_4 ( { optlc_net_463 } ) ,
    .Test_en__FEEDTHRU_5 ( { SYNOPSYS_UNCONNECTED_1068 } ) ,
    .Test_en__FEEDTHRU_6 ( { optlc_net_256 } ) ,
    .Test_en__FEEDTHRU_7 ( { SYNOPSYS_UNCONNECTED_1069 } ) ,
    .Test_en__FEEDTHRU_8 ( { SYNOPSYS_UNCONNECTED_1070 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_463 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1071 } ) ) ;
sb_1__0_ sb_7__0_ (
    .prog_clk ( { ctsbuf_net_5751493 } ) ,
    .chany_top_in ( cby_1__1__72_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_72_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_72_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_72_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_72_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_72_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_72_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_72_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_72_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__0__7_chanx_left_out ) , 
    .right_bottom_grid_pin_1_ ( grid_io_bottom_7_top_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_3_ ( grid_io_bottom_7_top_width_0_height_0__pin_3_upper ) , 
    .right_bottom_grid_pin_5_ ( grid_io_bottom_7_top_width_0_height_0__pin_5_upper ) , 
    .right_bottom_grid_pin_7_ ( grid_io_bottom_7_top_width_0_height_0__pin_7_upper ) , 
    .right_bottom_grid_pin_9_ ( grid_io_bottom_7_top_width_0_height_0__pin_9_upper ) , 
    .right_bottom_grid_pin_11_ ( grid_io_bottom_7_top_width_0_height_0__pin_11_upper ) , 
    .chanx_left_in ( cbx_1__0__6_chanx_right_out ) , 
    .left_bottom_grid_pin_1_ ( grid_io_bottom_6_top_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_3_ ( grid_io_bottom_6_top_width_0_height_0__pin_3_lower ) , 
    .left_bottom_grid_pin_5_ ( grid_io_bottom_6_top_width_0_height_0__pin_5_lower ) , 
    .left_bottom_grid_pin_7_ ( grid_io_bottom_6_top_width_0_height_0__pin_7_lower ) , 
    .left_bottom_grid_pin_9_ ( grid_io_bottom_6_top_width_0_height_0__pin_9_lower ) , 
    .left_bottom_grid_pin_11_ ( grid_io_bottom_6_top_width_0_height_0__pin_11_lower ) , 
    .ccff_head ( grid_io_bottom_7_ccff_tail ) , 
    .chany_top_out ( sb_1__0__6_chany_top_out ) , 
    .chanx_right_out ( sb_1__0__6_chanx_right_out ) , 
    .chanx_left_out ( sb_1__0__6_chanx_left_out ) , 
    .ccff_tail ( sb_1__0__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires_185_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1072 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1073 ) , 
    .SC_OUT_BOT ( scff_Wires_186_ ) ,
    .Test_en__FEEDTHRU_0 ( { optlc_net_409 } ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1074 } ) ,
    .Test_en__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_1075 } ) ,
    .Test_en__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_1076 } ) ,
    .Test_en__FEEDTHRU_4 ( Test_en__FEEDTHRU_1 ) , 
    .Test_en__FEEDTHRU_5 ( Test_en__FEEDTHRU_24 ) ,
    .Test_en__FEEDTHRU_6 ( { optlc_net_700 } ) ,
    .Test_en__FEEDTHRU_7 ( { SYNOPSYS_UNCONNECTED_1077 } ) ,
    .Test_en__FEEDTHRU_8 ( { SYNOPSYS_UNCONNECTED_1078 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_326 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1079 } ) ) ;
sb_1__0_ sb_8__0_ (
    .prog_clk ( { ctsbuf_net_5601478 } ) ,
    .chany_top_in ( cby_1__1__84_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_84_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_84_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_84_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_84_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_84_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_84_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_84_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_84_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__0__8_chanx_left_out ) , 
    .right_bottom_grid_pin_1_ ( grid_io_bottom_8_top_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_3_ ( grid_io_bottom_8_top_width_0_height_0__pin_3_upper ) , 
    .right_bottom_grid_pin_5_ ( grid_io_bottom_8_top_width_0_height_0__pin_5_upper ) , 
    .right_bottom_grid_pin_7_ ( grid_io_bottom_8_top_width_0_height_0__pin_7_upper ) , 
    .right_bottom_grid_pin_9_ ( grid_io_bottom_8_top_width_0_height_0__pin_9_upper ) , 
    .right_bottom_grid_pin_11_ ( grid_io_bottom_8_top_width_0_height_0__pin_11_upper ) , 
    .chanx_left_in ( cbx_1__0__7_chanx_right_out ) , 
    .left_bottom_grid_pin_1_ ( grid_io_bottom_7_top_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_3_ ( grid_io_bottom_7_top_width_0_height_0__pin_3_lower ) , 
    .left_bottom_grid_pin_5_ ( grid_io_bottom_7_top_width_0_height_0__pin_5_lower ) , 
    .left_bottom_grid_pin_7_ ( grid_io_bottom_7_top_width_0_height_0__pin_7_lower ) , 
    .left_bottom_grid_pin_9_ ( grid_io_bottom_7_top_width_0_height_0__pin_9_lower ) , 
    .left_bottom_grid_pin_11_ ( grid_io_bottom_7_top_width_0_height_0__pin_11_lower ) , 
    .ccff_head ( grid_io_bottom_8_ccff_tail ) , 
    .chany_top_out ( sb_1__0__7_chany_top_out ) , 
    .chanx_right_out ( sb_1__0__7_chanx_right_out ) , 
    .chanx_left_out ( sb_1__0__7_chanx_left_out ) , 
    .ccff_tail ( sb_1__0__7_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1080 ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1081 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1082 ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1083 ) ,
    .Test_en__FEEDTHRU_0 ( { optlc_net_438 } ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1084 } ) ,
    .Test_en__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_1085 } ) ,
    .Test_en__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_1086 } ) ,
    .Test_en__FEEDTHRU_4 ( Test_en__FEEDTHRU_24 ) , 
    .Test_en__FEEDTHRU_5 ( Test_en__FEEDTHRU_47 ) ,
    .Test_en__FEEDTHRU_6 ( { optlc_net_671 } ) ,
    .Test_en__FEEDTHRU_7 ( { SYNOPSYS_UNCONNECTED_1087 } ) ,
    .Test_en__FEEDTHRU_8 ( { SYNOPSYS_UNCONNECTED_1088 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_670 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1089 } ) ) ;
sb_1__0_ sb_9__0_ (
    .prog_clk ( { ctsbuf_net_5371455 } ) ,
    .chany_top_in ( cby_1__1__96_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_96_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_96_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_96_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_96_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_96_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_96_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_96_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_96_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__0__9_chanx_left_out ) , 
    .right_bottom_grid_pin_1_ ( grid_io_bottom_9_top_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_3_ ( grid_io_bottom_9_top_width_0_height_0__pin_3_upper ) , 
    .right_bottom_grid_pin_5_ ( grid_io_bottom_9_top_width_0_height_0__pin_5_upper ) , 
    .right_bottom_grid_pin_7_ ( grid_io_bottom_9_top_width_0_height_0__pin_7_upper ) , 
    .right_bottom_grid_pin_9_ ( grid_io_bottom_9_top_width_0_height_0__pin_9_upper ) , 
    .right_bottom_grid_pin_11_ ( grid_io_bottom_9_top_width_0_height_0__pin_11_upper ) , 
    .chanx_left_in ( cbx_1__0__8_chanx_right_out ) , 
    .left_bottom_grid_pin_1_ ( grid_io_bottom_8_top_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_3_ ( grid_io_bottom_8_top_width_0_height_0__pin_3_lower ) , 
    .left_bottom_grid_pin_5_ ( grid_io_bottom_8_top_width_0_height_0__pin_5_lower ) , 
    .left_bottom_grid_pin_7_ ( grid_io_bottom_8_top_width_0_height_0__pin_7_lower ) , 
    .left_bottom_grid_pin_9_ ( grid_io_bottom_8_top_width_0_height_0__pin_9_lower ) , 
    .left_bottom_grid_pin_11_ ( grid_io_bottom_8_top_width_0_height_0__pin_11_lower ) , 
    .ccff_head ( grid_io_bottom_9_ccff_tail ) , 
    .chany_top_out ( sb_1__0__8_chany_top_out ) , 
    .chanx_right_out ( sb_1__0__8_chanx_right_out ) , 
    .chanx_left_out ( sb_1__0__8_chanx_left_out ) , 
    .ccff_tail ( sb_1__0__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires_238_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1090 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1091 ) , 
    .SC_OUT_BOT ( scff_Wires_239_ ) ,
    .Test_en__FEEDTHRU_0 ( { optlc_net_755 } ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1092 } ) ,
    .Test_en__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_1093 } ) ,
    .Test_en__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_1094 } ) ,
    .Test_en__FEEDTHRU_4 ( Test_en__FEEDTHRU_47 ) , 
    .Test_en__FEEDTHRU_5 ( Test_en__FEEDTHRU_70 ) ,
    .Test_en__FEEDTHRU_6 ( { optlc_net_861 } ) ,
    .Test_en__FEEDTHRU_7 ( { SYNOPSYS_UNCONNECTED_1095 } ) ,
    .Test_en__FEEDTHRU_8 ( { SYNOPSYS_UNCONNECTED_1096 } ) ,
    
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50_ ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ) ;
sb_1__0_ sb_10__0_ (
    .prog_clk ( { ctsbuf_net_5061424 } ) ,
    .chany_top_in ( cby_1__1__108_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_108_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_108_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_108_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_108_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_108_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_108_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_108_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_108_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__0__10_chanx_left_out ) , 
    .right_bottom_grid_pin_1_ ( grid_io_bottom_10_top_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_3_ ( grid_io_bottom_10_top_width_0_height_0__pin_3_upper ) , 
    .right_bottom_grid_pin_5_ ( grid_io_bottom_10_top_width_0_height_0__pin_5_upper ) , 
    .right_bottom_grid_pin_7_ ( grid_io_bottom_10_top_width_0_height_0__pin_7_upper ) , 
    .right_bottom_grid_pin_9_ ( grid_io_bottom_10_top_width_0_height_0__pin_9_upper ) , 
    .right_bottom_grid_pin_11_ ( grid_io_bottom_10_top_width_0_height_0__pin_11_upper ) , 
    .chanx_left_in ( cbx_1__0__9_chanx_right_out ) , 
    .left_bottom_grid_pin_1_ ( grid_io_bottom_9_top_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_3_ ( grid_io_bottom_9_top_width_0_height_0__pin_3_lower ) , 
    .left_bottom_grid_pin_5_ ( grid_io_bottom_9_top_width_0_height_0__pin_5_lower ) , 
    .left_bottom_grid_pin_7_ ( grid_io_bottom_9_top_width_0_height_0__pin_7_lower ) , 
    .left_bottom_grid_pin_9_ ( grid_io_bottom_9_top_width_0_height_0__pin_9_lower ) , 
    .left_bottom_grid_pin_11_ ( grid_io_bottom_9_top_width_0_height_0__pin_11_lower ) , 
    .ccff_head ( grid_io_bottom_10_ccff_tail ) , 
    .chany_top_out ( sb_1__0__9_chany_top_out ) , 
    .chanx_right_out ( sb_1__0__9_chanx_right_out ) , 
    .chanx_left_out ( sb_1__0__9_chanx_left_out ) , 
    .ccff_tail ( sb_1__0__9_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1097 ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1098 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1099 ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1100 ) ,
    .Test_en__FEEDTHRU_0 ( { optlc_net_418 } ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1101 } ) ,
    .Test_en__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_1102 } ) ,
    .Test_en__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_1103 } ) ,
    .Test_en__FEEDTHRU_4 ( Test_en__FEEDTHRU_70 ) , 
    .Test_en__FEEDTHRU_5 ( Test_en__FEEDTHRU_93 ) ,
    .Test_en__FEEDTHRU_6 ( { optlc_net_812 } ) ,
    .Test_en__FEEDTHRU_7 ( { SYNOPSYS_UNCONNECTED_1104 } ) ,
    .Test_en__FEEDTHRU_8 ( { SYNOPSYS_UNCONNECTED_1105 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_277 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1106 } ) ) ;
sb_1__0_ sb_11__0_ (
    .prog_clk ( { ctsbuf_net_4671385 } ) ,
    .chany_top_in ( cby_1__1__120_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_120_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_120_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_120_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_120_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_120_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_120_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_120_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_120_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__0__11_chanx_left_out ) , 
    .right_bottom_grid_pin_1_ ( grid_io_bottom_11_top_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_3_ ( grid_io_bottom_11_top_width_0_height_0__pin_3_upper ) , 
    .right_bottom_grid_pin_5_ ( grid_io_bottom_11_top_width_0_height_0__pin_5_upper ) , 
    .right_bottom_grid_pin_7_ ( grid_io_bottom_11_top_width_0_height_0__pin_7_upper ) , 
    .right_bottom_grid_pin_9_ ( grid_io_bottom_11_top_width_0_height_0__pin_9_upper ) , 
    .right_bottom_grid_pin_11_ ( grid_io_bottom_11_top_width_0_height_0__pin_11_upper ) , 
    .chanx_left_in ( cbx_1__0__10_chanx_right_out ) , 
    .left_bottom_grid_pin_1_ ( grid_io_bottom_10_top_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_3_ ( grid_io_bottom_10_top_width_0_height_0__pin_3_lower ) , 
    .left_bottom_grid_pin_5_ ( grid_io_bottom_10_top_width_0_height_0__pin_5_lower ) , 
    .left_bottom_grid_pin_7_ ( grid_io_bottom_10_top_width_0_height_0__pin_7_lower ) , 
    .left_bottom_grid_pin_9_ ( grid_io_bottom_10_top_width_0_height_0__pin_9_lower ) , 
    .left_bottom_grid_pin_11_ ( grid_io_bottom_10_top_width_0_height_0__pin_11_lower ) , 
    .ccff_head ( grid_io_bottom_11_ccff_tail ) , 
    .chany_top_out ( sb_1__0__10_chany_top_out ) , 
    .chanx_right_out ( sb_1__0__10_chanx_right_out ) , 
    .chanx_left_out ( sb_1__0__10_chanx_left_out ) , 
    .ccff_tail ( sb_1__0__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires_291_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1107 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1108 ) , 
    .SC_OUT_BOT ( scff_Wires_292_ ) ,
    .Test_en__FEEDTHRU_0 ( { optlc_net_589 } ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1109 } ) ,
    .Test_en__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_1110 } ) ,
    .Test_en__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_1111 } ) ,
    .Test_en__FEEDTHRU_4 ( Test_en__FEEDTHRU_93 ) , 
    .Test_en__FEEDTHRU_5 ( Test_en__FEEDTHRU_116 ) ,
    .Test_en__FEEDTHRU_6 ( { optlc_net_417 } ) ,
    .Test_en__FEEDTHRU_7 ( { SYNOPSYS_UNCONNECTED_1112 } ) ,
    .Test_en__FEEDTHRU_8 ( { SYNOPSYS_UNCONNECTED_1113 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_469 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1114 } ) ) ;
sb_1__1_ sb_1__1_ (
    .prog_clk ( { ctsbuf_net_4321350 } ) ,
    .chany_top_in ( cby_1__1__1_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__11_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_12_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_12_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_12_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_12_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_12_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_12_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_12_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_12_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__0_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_0_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__0_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_0_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_0_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__11_ccff_tail ) , 
    .chany_top_out ( sb_1__1__0_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__0_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__0_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__0_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_150 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_151 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_832 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1115 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1116 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_667 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1117 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_667 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1118 } ) ) ;
sb_1__1_ sb_1__2_ (
    .prog_clk ( { ctsbuf_net_3841302 } ) ,
    .chany_top_in ( cby_1__1__2_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__12_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_13_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_13_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_13_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_13_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_13_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_13_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_13_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_13_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__1_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__1_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_1_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__12_ccff_tail ) , 
    .chany_top_out ( sb_1__1__1_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__1_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__1_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__1_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__1_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_152 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_153 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_370 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1119 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1120 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_527 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1121 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_757 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1122 } ) ) ;
sb_1__1_ sb_1__3_ (
    .prog_clk ( { ctsbuf_net_3361254 } ) ,
    .chany_top_in ( cby_1__1__3_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__13_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_14_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_14_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_14_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_14_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_14_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_14_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_14_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_14_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__2_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__2_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_2_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_2_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__13_ccff_tail ) , 
    .chany_top_out ( sb_1__1__2_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__2_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__2_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__2_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__2_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_154 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_155 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_385 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1123 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1124 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_817 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1125 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_613 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1126 } ) ) ;
sb_1__1_ sb_1__4_ (
    .prog_clk ( { ctsbuf_net_2881206 } ) ,
    .chany_top_in ( cby_1__1__4_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_4_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_4_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_4_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_4_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_4_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_4_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_4_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_4_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__14_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_15_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_15_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_15_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_15_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_15_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_15_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_15_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_15_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__3_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__3_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_3_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__14_ccff_tail ) , 
    .chany_top_out ( sb_1__1__3_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__3_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__3_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__3_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__3_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_156 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_157 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_445 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1127 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1128 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_594 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1129 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_594 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1130 } ) ) ;
sb_1__1_ sb_1__5_ (
    .prog_clk ( { ctsbuf_net_2401158 } ) ,
    .chany_top_in ( cby_1__1__5_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_5_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_5_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_5_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_5_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_5_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_5_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_5_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_5_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__15_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_16_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_16_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_16_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_16_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_16_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_16_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_16_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_16_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__4_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_4_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_4_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_4_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_4_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_4_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_4_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_4_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_4_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__4_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_4_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_4_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_4_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_4_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_4_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_4_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_4_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_4_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__15_ccff_tail ) , 
    .chany_top_out ( sb_1__1__4_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__4_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__4_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__4_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__4_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_158 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_159 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_794 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1131 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1132 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_875 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1133 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_267 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1134 } ) ) ;
sb_1__1_ sb_1__6_ (
    .prog_clk ( { ctsbuf_net_1921110 } ) ,
    .chany_top_in ( cby_1__1__6_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_6_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_6_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_6_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_6_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_6_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_6_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_6_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_6_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__16_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_17_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_17_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_17_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_17_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_17_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_17_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_17_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_17_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__5_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_5_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_5_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_5_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_5_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_5_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_5_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_5_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_5_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__5_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_5_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_5_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_5_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_5_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_5_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_5_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_5_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_5_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__16_ccff_tail ) , 
    .chany_top_out ( sb_1__1__5_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__5_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__5_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__5_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__5_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_160 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_161 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_367 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1135 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1136 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_654 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1137 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_838 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1138 } ) ) ;
sb_1__1_ sb_1__7_ (
    .prog_clk ( { ctsbuf_net_1451063 } ) ,
    .chany_top_in ( cby_1__1__7_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_7_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_7_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_7_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_7_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_7_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_7_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_7_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_7_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__17_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_18_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_18_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_18_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_18_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_18_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_18_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_18_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_18_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__6_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_6_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_6_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_6_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_6_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_6_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_6_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_6_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_6_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__6_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_6_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_6_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_6_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_6_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_6_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_6_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_6_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_6_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__17_ccff_tail ) , 
    .chany_top_out ( sb_1__1__6_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__6_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__6_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__6_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__6_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_162 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_163 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_431 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1139 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1140 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_905 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1141 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_797 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1142 } ) ) ;
sb_1__1_ sb_1__8_ (
    .prog_clk ( { ctsbuf_net_1031021 } ) ,
    .chany_top_in ( cby_1__1__8_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_8_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_8_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_8_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_8_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_8_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_8_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_8_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_8_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__18_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_19_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_19_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_19_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_19_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_19_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_19_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_19_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_19_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__7_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_7_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_7_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_7_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_7_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_7_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_7_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_7_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_7_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__7_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_7_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_7_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_7_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_7_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_7_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_7_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_7_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_7_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__18_ccff_tail ) , 
    .chany_top_out ( sb_1__1__7_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__7_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__7_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__7_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__7_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_164 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_165 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_659 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1143 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1144 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_428 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1145 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_761 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1146 } ) ) ;
sb_1__1_ sb_1__9_ (
    .prog_clk ( { p_abuf8 } ) ,
    .chany_top_in ( cby_1__1__9_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_9_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_9_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_9_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_9_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_9_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_9_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_9_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_9_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__19_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_20_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_20_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_20_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_20_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_20_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_20_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_20_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_20_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__8_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_8_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_8_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_8_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_8_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_8_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_8_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_8_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_8_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__8_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_8_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_8_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_8_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_8_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_8_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_8_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_8_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_8_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__19_ccff_tail ) , 
    .chany_top_out ( sb_1__1__8_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__8_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__8_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__8_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__8_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_166 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_167 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_480 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1147 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1148 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_564 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1149 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_564 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1150 } ) ) ;
sb_1__1_ sb_1__10_ (
    .prog_clk ( { ctsbuf_net_41959 } ) ,
    .chany_top_in ( cby_1__1__10_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_10_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_10_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_10_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_10_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_10_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_10_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_10_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_10_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__20_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_21_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_21_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_21_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_21_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_21_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_21_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_21_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_21_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__9_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_9_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_9_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_9_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_9_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_9_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_9_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_9_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_9_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__9_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_9_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_9_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_9_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_9_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_9_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_9_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_9_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_9_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__20_ccff_tail ) , 
    .chany_top_out ( sb_1__1__9_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__9_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__9_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__9_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__9_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_168 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_169 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_419 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1151 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1152 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_270 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1153 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_674 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1154 } ) ) ;
sb_1__1_ sb_1__11_ (
    .prog_clk ( { ctsbuf_net_22940 } ) ,
    .chany_top_in ( cby_1__1__11_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_11_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_11_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_11_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_11_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_11_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_11_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_11_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_11_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__21_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_22_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_22_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_22_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_22_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_22_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_22_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_22_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_22_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__10_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_10_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_10_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_10_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_10_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_10_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_10_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_10_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_10_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__10_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_10_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_10_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_10_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_10_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_10_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_10_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_10_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_10_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__21_ccff_tail ) , 
    .chany_top_out ( sb_1__1__10_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__10_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__10_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__10_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__10_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_170 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_171 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_486 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1155 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1156 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_819 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1157 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_819 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1158 } ) ) ;
sb_1__1_ sb_2__1_ (
    .prog_clk ( { ctsbuf_net_4771395 } ) ,
    .chany_top_in ( cby_1__1__13_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_13_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_13_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_13_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_13_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_13_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_13_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_13_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_13_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__22_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_24_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_24_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_24_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_24_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_24_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_24_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_24_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_24_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__12_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_12_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_12_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_12_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_12_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_12_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_12_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_12_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_12_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__11_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_12_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_12_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_12_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_12_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_12_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_12_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_12_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_12_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__22_ccff_tail ) , 
    .chany_top_out ( sb_1__1__11_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__11_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__11_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__11_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__11_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_173 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_174 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_386 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1159 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1160 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_731 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1161 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_849 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1162 } ) ) ;
sb_1__1_ sb_2__2_ (
    .prog_clk ( { ctsbuf_net_4331351 } ) ,
    .chany_top_in ( cby_1__1__14_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_14_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_14_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_14_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_14_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_14_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_14_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_14_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_14_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__23_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_25_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_25_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_25_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_25_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_25_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_25_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_25_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_25_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__13_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_13_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_13_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_13_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_13_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_13_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_13_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_13_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_13_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__12_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_13_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_13_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_13_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_13_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_13_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_13_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_13_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_13_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__23_ccff_tail ) , 
    .chany_top_out ( sb_1__1__12_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__12_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__12_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__12_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__12_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_175 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_176 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_485 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1163 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1164 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_745 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1165 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_745 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1166 } ) ) ;
sb_1__1_ sb_2__3_ (
    .prog_clk ( { ctsbuf_net_3851303 } ) ,
    .chany_top_in ( cby_1__1__15_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_15_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_15_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_15_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_15_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_15_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_15_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_15_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_15_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__24_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_26_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_26_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_26_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_26_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_26_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_26_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_26_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_26_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__14_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_14_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_14_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_14_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_14_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_14_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_14_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_14_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_14_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__13_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_14_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_14_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_14_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_14_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_14_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_14_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_14_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_14_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__24_ccff_tail ) , 
    .chany_top_out ( sb_1__1__13_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__13_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__13_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__13_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__13_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_177 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_178 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_437 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1167 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1168 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_647 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1169 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_647 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1170 } ) ) ;
sb_1__1_ sb_2__4_ (
    .prog_clk ( { p_abuf33 } ) ,
    .chany_top_in ( cby_1__1__16_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_16_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_16_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_16_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_16_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_16_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_16_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_16_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_16_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__25_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_27_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_27_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_27_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_27_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_27_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_27_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_27_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_27_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__15_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_15_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_15_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_15_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_15_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_15_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_15_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_15_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_15_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__14_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_15_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_15_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_15_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_15_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_15_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_15_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_15_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_15_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__25_ccff_tail ) , 
    .chany_top_out ( sb_1__1__14_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__14_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__14_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__14_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__14_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_179 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_180 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_459 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1171 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1172 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_826 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1173 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_826 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1174 } ) ) ;
sb_1__1_ sb_2__5_ (
    .prog_clk ( { ctsbuf_net_2891207 } ) ,
    .chany_top_in ( cby_1__1__17_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_17_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_17_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_17_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_17_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_17_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_17_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_17_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_17_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__26_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_28_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_28_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_28_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_28_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_28_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_28_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_28_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_28_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__16_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_16_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_16_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_16_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_16_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_16_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_16_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_16_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_16_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__15_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_16_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_16_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_16_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_16_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_16_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_16_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_16_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_16_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__26_ccff_tail ) , 
    .chany_top_out ( sb_1__1__15_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__15_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__15_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__15_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__15_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_181 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_182 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_645 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1175 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1176 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_432 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1177 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_912 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1178 } ) ) ;
sb_1__1_ sb_2__6_ (
    .prog_clk ( { ctsbuf_net_2411159 } ) ,
    .chany_top_in ( cby_1__1__18_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_18_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_18_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_18_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_18_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_18_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_18_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_18_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_18_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__27_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_29_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_29_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_29_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_29_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_29_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_29_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_29_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_29_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__17_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_17_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_17_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_17_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_17_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_17_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_17_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_17_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_17_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__16_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_17_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_17_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_17_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_17_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_17_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_17_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_17_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_17_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__27_ccff_tail ) , 
    .chany_top_out ( sb_1__1__16_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__16_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__16_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__16_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__16_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_183 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_184 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_468 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1179 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1180 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_529 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1181 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_830 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1182 } ) ) ;
sb_1__1_ sb_2__7_ (
    .prog_clk ( { ctsbuf_net_1931111 } ) ,
    .chany_top_in ( cby_1__1__19_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_19_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_19_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_19_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_19_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_19_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_19_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_19_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_19_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__28_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_30_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_30_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_30_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_30_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_30_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_30_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_30_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_30_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__18_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_18_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_18_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_18_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_18_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_18_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_18_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_18_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_18_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__17_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_18_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_18_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_18_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_18_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_18_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_18_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_18_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_18_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__28_ccff_tail ) , 
    .chany_top_out ( sb_1__1__17_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__17_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__17_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__17_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__17_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_185 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_186 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_841 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1183 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1184 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_751 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1185 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_751 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1186 } ) ) ;
sb_1__1_ sb_2__8_ (
    .prog_clk ( { p_abuf18 } ) ,
    .chany_top_in ( cby_1__1__20_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_20_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_20_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_20_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_20_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_20_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_20_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_20_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_20_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__29_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_31_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_31_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_31_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_31_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_31_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_31_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_31_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_31_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__19_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_19_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_19_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_19_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_19_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_19_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_19_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_19_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_19_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__18_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_19_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_19_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_19_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_19_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_19_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_19_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_19_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_19_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__29_ccff_tail ) , 
    .chany_top_out ( sb_1__1__18_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__18_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__18_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__18_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__18_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_187 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_188 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_851 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1187 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1188 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_534 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1189 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_534 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1190 } ) ) ;
sb_1__1_ sb_2__9_ (
    .prog_clk ( { ctsbuf_net_1041022 } ) ,
    .chany_top_in ( cby_1__1__21_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_21_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_21_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_21_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_21_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_21_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_21_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_21_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_21_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__30_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_32_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_32_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_32_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_32_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_32_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_32_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_32_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_32_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__20_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_20_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_20_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_20_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_20_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_20_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_20_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_20_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_20_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__19_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_20_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_20_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_20_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_20_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_20_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_20_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_20_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_20_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__30_ccff_tail ) , 
    .chany_top_out ( sb_1__1__19_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__19_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__19_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__19_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__19_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_189 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_190 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_610 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1191 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1192 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_814 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1193 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_378 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1194 } ) ) ;
sb_1__1_ sb_2__10_ (
    .prog_clk ( { ctsbuf_net_69987 } ) ,
    .chany_top_in ( cby_1__1__22_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_22_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_22_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_22_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_22_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_22_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_22_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_22_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_22_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__31_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_33_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_33_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_33_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_33_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_33_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_33_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_33_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_33_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__21_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_21_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_21_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_21_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_21_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_21_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_21_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_21_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_21_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__20_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_21_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_21_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_21_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_21_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_21_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_21_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_21_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_21_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__31_ccff_tail ) , 
    .chany_top_out ( sb_1__1__20_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__20_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__20_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__20_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__20_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_191 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_192 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_640 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1195 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1196 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_295 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1197 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_584 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1198 } ) ) ;
sb_1__1_ sb_2__11_ (
    .prog_clk ( { ctsbuf_net_42960 } ) ,
    .chany_top_in ( cby_1__1__23_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_23_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_23_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_23_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_23_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_23_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_23_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_23_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_23_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__32_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_34_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_34_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_34_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_34_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_34_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_34_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_34_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_34_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__22_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_22_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_22_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_22_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_22_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_22_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_22_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_22_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_22_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__21_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_22_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_22_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_22_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_22_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_22_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_22_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_22_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_22_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__32_ccff_tail ) , 
    .chany_top_out ( sb_1__1__21_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__21_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__21_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__21_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__21_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_193 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_194 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_580 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1199 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1200 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_637 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1201 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_478 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1202 } ) ) ;
sb_1__1_ sb_3__1_ (
    .prog_clk ( { ctsbuf_net_5141432 } ) ,
    .chany_top_in ( cby_1__1__25_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_25_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_25_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_25_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_25_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_25_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_25_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_25_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_25_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__33_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_36_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_36_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_36_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_36_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_36_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_36_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_36_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_36_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__24_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_24_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_24_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_24_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_24_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_24_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_24_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_24_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_24_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__22_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_24_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_24_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_24_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_24_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_24_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_24_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_24_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_24_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__33_ccff_tail ) , 
    .chany_top_out ( sb_1__1__22_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__22_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__22_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__22_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__22_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_196 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_197 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_550 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1203 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1204 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_347 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1205 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_347 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1206 } ) ) ;
sb_1__1_ sb_3__2_ (
    .prog_clk ( { ctsbuf_net_4781396 } ) ,
    .chany_top_in ( cby_1__1__26_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_26_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_26_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_26_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_26_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_26_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_26_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_26_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_26_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__34_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_37_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_37_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_37_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_37_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_37_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_37_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_37_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_37_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__25_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_25_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_25_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_25_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_25_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_25_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_25_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_25_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_25_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__23_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_25_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_25_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_25_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_25_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_25_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_25_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_25_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_25_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__34_ccff_tail ) , 
    .chany_top_out ( sb_1__1__23_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__23_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__23_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__23_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__23_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_198 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_199 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_344 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1207 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1208 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_332 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1209 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_332 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1210 } ) ) ;
sb_1__1_ sb_3__3_ (
    .prog_clk ( { ctsbuf_net_4351353 } ) ,
    .chany_top_in ( cby_1__1__27_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_27_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_27_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_27_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_27_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_27_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_27_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_27_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_27_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__35_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_38_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_38_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_38_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_38_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_38_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_38_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_38_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_38_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__26_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_26_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_26_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_26_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_26_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_26_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_26_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_26_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_26_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__24_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_26_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_26_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_26_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_26_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_26_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_26_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_26_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_26_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__35_ccff_tail ) , 
    .chany_top_out ( sb_1__1__24_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__24_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__24_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__24_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__24_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_200 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_201 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_364 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1211 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1212 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_888 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1213 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_888 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1214 } ) ) ;
sb_1__1_ sb_3__4_ (
    .prog_clk ( { ctsbuf_net_3871305 } ) ,
    .chany_top_in ( cby_1__1__28_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_28_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_28_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_28_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_28_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_28_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_28_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_28_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_28_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__36_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_39_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_39_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_39_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_39_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_39_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_39_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_39_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_39_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__27_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_27_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_27_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_27_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_27_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_27_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_27_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_27_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_27_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__25_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_27_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_27_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_27_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_27_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_27_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_27_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_27_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_27_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__36_ccff_tail ) , 
    .chany_top_out ( sb_1__1__25_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__25_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__25_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__25_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__25_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_202 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_203 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_309 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1215 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1216 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_692 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1217 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_692 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1218 } ) ) ;
sb_1__1_ sb_3__5_ (
    .prog_clk ( { ctsbuf_net_3391257 } ) ,
    .chany_top_in ( cby_1__1__29_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_29_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_29_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_29_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_29_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_29_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_29_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_29_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_29_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__37_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_40_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_40_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_40_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_40_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_40_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_40_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_40_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_40_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__28_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_28_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_28_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_28_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_28_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_28_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_28_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_28_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_28_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__26_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_28_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_28_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_28_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_28_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_28_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_28_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_28_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_28_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__37_ccff_tail ) , 
    .chany_top_out ( sb_1__1__26_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__26_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__26_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__26_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__26_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_204 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_205 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_482 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1219 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1220 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_539 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1221 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_539 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1222 } ) ) ;
sb_1__1_ sb_3__6_ (
    .prog_clk ( { ctsbuf_net_2911209 } ) ,
    .chany_top_in ( cby_1__1__30_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_30_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_30_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_30_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_30_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_30_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_30_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_30_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_30_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__38_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_41_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_41_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_41_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_41_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_41_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_41_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_41_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_41_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__29_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_29_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_29_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_29_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_29_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_29_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_29_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_29_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_29_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__27_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_29_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_29_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_29_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_29_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_29_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_29_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_29_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_29_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__38_ccff_tail ) , 
    .chany_top_out ( sb_1__1__27_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__27_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__27_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__27_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__27_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_206 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_207 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_820 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1223 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1224 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_563 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1225 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_563 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1226 } ) ) ;
sb_1__1_ sb_3__7_ (
    .prog_clk ( { ctsbuf_net_2431161 } ) ,
    .chany_top_in ( cby_1__1__31_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_31_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_31_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_31_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_31_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_31_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_31_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_31_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_31_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__39_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_42_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_42_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_42_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_42_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_42_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_42_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_42_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_42_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__30_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_30_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_30_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_30_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_30_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_30_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_30_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_30_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_30_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__28_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_30_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_30_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_30_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_30_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_30_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_30_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_30_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_30_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__39_ccff_tail ) , 
    .chany_top_out ( sb_1__1__28_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__28_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__28_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__28_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__28_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_208 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_209 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_494 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1227 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1228 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_561 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1229 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_561 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1230 } ) ) ;
sb_1__1_ sb_3__8_ (
    .prog_clk ( { ctsbuf_net_1951113 } ) ,
    .chany_top_in ( cby_1__1__32_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_32_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_32_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_32_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_32_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_32_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_32_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_32_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_32_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__40_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_43_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_43_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_43_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_43_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_43_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_43_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_43_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_43_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__31_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_31_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_31_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_31_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_31_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_31_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_31_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_31_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_31_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__29_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_31_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_31_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_31_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_31_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_31_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_31_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_31_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_31_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__40_ccff_tail ) , 
    .chany_top_out ( sb_1__1__29_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__29_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__29_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__29_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__29_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_210 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_211 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_411 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1231 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1232 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_762 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1233 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_762 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1234 } ) ) ;
sb_1__1_ sb_3__9_ (
    .prog_clk ( { ctsbuf_net_1481066 } ) ,
    .chany_top_in ( cby_1__1__33_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_33_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_33_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_33_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_33_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_33_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_33_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_33_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_33_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__41_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_44_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_44_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_44_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_44_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_44_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_44_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_44_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_44_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__32_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_32_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_32_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_32_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_32_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_32_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_32_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_32_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_32_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__30_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_32_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_32_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_32_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_32_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_32_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_32_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_32_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_32_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__41_ccff_tail ) , 
    .chany_top_out ( sb_1__1__30_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__30_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__30_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__30_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__30_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_212 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_213 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_672 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1235 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1236 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_677 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1237 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_447 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1238 } ) ) ;
sb_1__1_ sb_3__10_ (
    .prog_clk ( { ctsbuf_net_1061024 } ) ,
    .chany_top_in ( cby_1__1__34_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_34_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_34_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_34_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_34_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_34_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_34_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_34_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_34_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__42_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_45_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_45_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_45_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_45_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_45_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_45_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_45_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_45_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__33_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_33_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_33_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_33_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_33_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_33_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_33_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_33_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_33_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__31_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_33_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_33_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_33_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_33_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_33_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_33_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_33_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_33_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__42_ccff_tail ) , 
    .chany_top_out ( sb_1__1__31_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__31_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__31_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__31_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__31_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_214 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_215 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_464 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1239 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1240 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_345 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1241 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_345 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1242 } ) ) ;
sb_1__1_ sb_3__11_ (
    .prog_clk ( { ctsbuf_net_71989 } ) ,
    .chany_top_in ( cby_1__1__35_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_35_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_35_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_35_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_35_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_35_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_35_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_35_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_35_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__43_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_46_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_46_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_46_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_46_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_46_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_46_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_46_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_46_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__34_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_34_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_34_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_34_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_34_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_34_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_34_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_34_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_34_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__32_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_34_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_34_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_34_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_34_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_34_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_34_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_34_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_34_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__43_ccff_tail ) , 
    .chany_top_out ( sb_1__1__32_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__32_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__32_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__32_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__32_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_216 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_217 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_714 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1243 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1244 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_634 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1245 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_634 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1246 } ) ) ;
sb_1__1_ sb_4__1_ (
    .prog_clk ( { ctsbuf_net_5431461 } ) ,
    .chany_top_in ( cby_1__1__37_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_37_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_37_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_37_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_37_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_37_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_37_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_37_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_37_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__44_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_48_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_48_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_48_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_48_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_48_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_48_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_48_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_48_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__36_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_36_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_36_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_36_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_36_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_36_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_36_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_36_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_36_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__33_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_36_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_36_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_36_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_36_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_36_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_36_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_36_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_36_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__44_ccff_tail ) , 
    .chany_top_out ( sb_1__1__33_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__33_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__33_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__33_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__33_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_219 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_220 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1247 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_882 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1248 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_729 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1249 } ) ) ;
sb_1__1_ sb_4__2_ (
    .prog_clk ( { ctsbuf_net_5151433 } ) ,
    .chany_top_in ( cby_1__1__38_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_38_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_38_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_38_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_38_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_38_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_38_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_38_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_38_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__45_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_49_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_49_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_49_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_49_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_49_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_49_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_49_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_49_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__37_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_37_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_37_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_37_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_37_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_37_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_37_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_37_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_37_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__34_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_37_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_37_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_37_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_37_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_37_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_37_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_37_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_37_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__45_ccff_tail ) , 
    .chany_top_out ( sb_1__1__34_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__34_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__34_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__34_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__34_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_221 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_222 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1250 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_611 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1251 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_611 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1252 } ) ) ;
sb_1__1_ sb_4__3_ (
    .prog_clk ( { ctsbuf_net_4801398 } ) ,
    .chany_top_in ( cby_1__1__39_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_39_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_39_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_39_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_39_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_39_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_39_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_39_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_39_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__46_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_50_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_50_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_50_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_50_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_50_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_50_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_50_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_50_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__38_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_38_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_38_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_38_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_38_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_38_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_38_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_38_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_38_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__35_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_38_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_38_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_38_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_38_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_38_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_38_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_38_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_38_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__46_ccff_tail ) , 
    .chany_top_out ( sb_1__1__35_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__35_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__35_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__35_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__35_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_223 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_224 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_6 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_7 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1253 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_705 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1254 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_705 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1255 } ) ) ;
sb_1__1_ sb_4__4_ (
    .prog_clk ( { ctsbuf_net_4371355 } ) ,
    .chany_top_in ( cby_1__1__40_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_40_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_40_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_40_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_40_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_40_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_40_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_40_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_40_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__47_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_51_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_51_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_51_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_51_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_51_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_51_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_51_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_51_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__39_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_39_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_39_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_39_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_39_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_39_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_39_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_39_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_39_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__36_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_39_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_39_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_39_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_39_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_39_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_39_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_39_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_39_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__47_ccff_tail ) , 
    .chany_top_out ( sb_1__1__36_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__36_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__36_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__36_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__36_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_225 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_226 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_8 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_9 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1256 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_484 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1257 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_484 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1258 } ) ) ;
sb_1__1_ sb_4__5_ (
    .prog_clk ( { ctsbuf_net_3891307 } ) ,
    .chany_top_in ( cby_1__1__41_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_41_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_41_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_41_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_41_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_41_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_41_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_41_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_41_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__48_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_52_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_52_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_52_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_52_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_52_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_52_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_52_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_52_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__40_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_40_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_40_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_40_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_40_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_40_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_40_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_40_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_40_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__37_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_40_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_40_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_40_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_40_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_40_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_40_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_40_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_40_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__48_ccff_tail ) , 
    .chany_top_out ( sb_1__1__37_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__37_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__37_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__37_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__37_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_227 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_228 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_10 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_11 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1259 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_641 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1260 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_363 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1261 } ) ) ;
sb_1__1_ sb_4__6_ (
    .prog_clk ( { ctsbuf_net_3411259 } ) ,
    .chany_top_in ( cby_1__1__42_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_42_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_42_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_42_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_42_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_42_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_42_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_42_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_42_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__49_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_53_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_53_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_53_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_53_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_53_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_53_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_53_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_53_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__41_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_41_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_41_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_41_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_41_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_41_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_41_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_41_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_41_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__38_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_41_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_41_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_41_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_41_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_41_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_41_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_41_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_41_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__49_ccff_tail ) , 
    .chany_top_out ( sb_1__1__38_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__38_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__38_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__38_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__38_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_229 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_230 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_12 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_13 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1262 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_346 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1263 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_346 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1264 } ) ) ;
sb_1__1_ sb_4__7_ (
    .prog_clk ( { ctsbuf_net_2931211 } ) ,
    .chany_top_in ( cby_1__1__43_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_43_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_43_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_43_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_43_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_43_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_43_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_43_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_43_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__50_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_54_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_54_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_54_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_54_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_54_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_54_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_54_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_54_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__42_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_42_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_42_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_42_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_42_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_42_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_42_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_42_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_42_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__39_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_42_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_42_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_42_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_42_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_42_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_42_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_42_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_42_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__50_ccff_tail ) , 
    .chany_top_out ( sb_1__1__39_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__39_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__39_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__39_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__39_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_231 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_232 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_14 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_15 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1265 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_728 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1266 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_282 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1267 } ) ) ;
sb_1__1_ sb_4__8_ (
    .prog_clk ( { p_abuf29 } ) ,
    .chany_top_in ( cby_1__1__44_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_44_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_44_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_44_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_44_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_44_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_44_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_44_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_44_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__51_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_55_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_55_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_55_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_55_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_55_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_55_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_55_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_55_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__43_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_43_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_43_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_43_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_43_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_43_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_43_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_43_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_43_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__40_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_43_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_43_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_43_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_43_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_43_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_43_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_43_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_43_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__51_ccff_tail ) , 
    .chany_top_out ( sb_1__1__40_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__40_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__40_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__40_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__40_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_233 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_234 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_16 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_17 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1268 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_691 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1269 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_684 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1270 } ) ) ;
sb_1__1_ sb_4__9_ (
    .prog_clk ( { ctsbuf_net_1971115 } ) ,
    .chany_top_in ( cby_1__1__45_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_45_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_45_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_45_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_45_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_45_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_45_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_45_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_45_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__52_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_56_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_56_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_56_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_56_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_56_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_56_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_56_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_56_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__44_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_44_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_44_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_44_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_44_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_44_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_44_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_44_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_44_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__41_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_44_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_44_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_44_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_44_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_44_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_44_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_44_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_44_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__52_ccff_tail ) , 
    .chany_top_out ( sb_1__1__41_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__41_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__41_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__41_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__41_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_235 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_236 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_18 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_19 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1271 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_473 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1272 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_473 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1273 } ) ) ;
sb_1__1_ sb_4__10_ (
    .prog_clk ( { ctsbuf_net_1501068 } ) ,
    .chany_top_in ( cby_1__1__46_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_46_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_46_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_46_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_46_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_46_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_46_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_46_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_46_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__53_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_57_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_57_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_57_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_57_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_57_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_57_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_57_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_57_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__45_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_45_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_45_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_45_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_45_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_45_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_45_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_45_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_45_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__42_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_45_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_45_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_45_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_45_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_45_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_45_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_45_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_45_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__53_ccff_tail ) , 
    .chany_top_out ( sb_1__1__42_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__42_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__42_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__42_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__42_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_237 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_238 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_20 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_21 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1274 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_639 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1275 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_639 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1276 } ) ) ;
sb_1__1_ sb_4__11_ (
    .prog_clk ( { ctsbuf_net_1081026 } ) ,
    .chany_top_in ( cby_1__1__47_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_47_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_47_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_47_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_47_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_47_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_47_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_47_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_47_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__54_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_58_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_58_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_58_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_58_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_58_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_58_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_58_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_58_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__46_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_46_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_46_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_46_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_46_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_46_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_46_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_46_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_46_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__43_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_46_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_46_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_46_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_46_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_46_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_46_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_46_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_46_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__54_ccff_tail ) , 
    .chany_top_out ( sb_1__1__43_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__43_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__43_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__43_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__43_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_239 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_240 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_22 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_23 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1277 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_883 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1278 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_335 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1279 } ) ) ;
sb_1__1_ sb_5__1_ (
    .prog_clk ( { ctsbuf_net_5641482 } ) ,
    .chany_top_in ( cby_1__1__49_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_49_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_49_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_49_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_49_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_49_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_49_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_49_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_49_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__55_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_60_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_60_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_60_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_60_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_60_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_60_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_60_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_60_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__48_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_48_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_48_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_48_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_48_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_48_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_48_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_48_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_48_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__44_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_48_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_48_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_48_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_48_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_48_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_48_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_48_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_48_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__55_ccff_tail ) , 
    .chany_top_out ( sb_1__1__44_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__44_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__44_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__44_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__44_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_242 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_243 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1280 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_456 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1281 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_456 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1282 } ) ) ;
sb_1__1_ sb_5__2_ (
    .prog_clk ( { ctsbuf_net_5441462 } ) ,
    .chany_top_in ( cby_1__1__50_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_50_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_50_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_50_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_50_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_50_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_50_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_50_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_50_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__56_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_61_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_61_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_61_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_61_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_61_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_61_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_61_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_61_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__49_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_49_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_49_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_49_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_49_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_49_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_49_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_49_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_49_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__45_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_49_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_49_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_49_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_49_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_49_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_49_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_49_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_49_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__56_ccff_tail ) , 
    .chany_top_out ( sb_1__1__45_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__45_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__45_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__45_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__45_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_244 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_245 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1283 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_697 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1284 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_697 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1285 } ) ) ;
sb_1__1_ sb_5__3_ (
    .prog_clk ( { ctsbuf_net_5171435 } ) ,
    .chany_top_in ( cby_1__1__51_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_51_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_51_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_51_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_51_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_51_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_51_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_51_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_51_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__57_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_62_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_62_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_62_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_62_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_62_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_62_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_62_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_62_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__50_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_50_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_50_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_50_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_50_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_50_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_50_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_50_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_50_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__46_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_50_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_50_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_50_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_50_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_50_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_50_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_50_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_50_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__57_ccff_tail ) , 
    .chany_top_out ( sb_1__1__46_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__46_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__46_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__46_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__46_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_246 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_247 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_6 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_7 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1286 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_874 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1287 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_311 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1288 } ) ) ;
sb_1__1_ sb_5__4_ (
    .prog_clk ( { ctsbuf_net_6551573 } ) ,
    .chany_top_in ( cby_1__1__52_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_52_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_52_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_52_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_52_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_52_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_52_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_52_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_52_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__58_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_63_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_63_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_63_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_63_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_63_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_63_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_63_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_63_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__51_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_51_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_51_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_51_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_51_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_51_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_51_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_51_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_51_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__47_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_51_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_51_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_51_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_51_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_51_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_51_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_51_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_51_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__58_ccff_tail ) , 
    .chany_top_out ( sb_1__1__47_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__47_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__47_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__47_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__47_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_248 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_249 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_8 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_9 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1289 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_592 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1290 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_592 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1291 } ) ) ;
sb_1__1_ sb_5__5_ (
    .prog_clk ( { ctsbuf_net_4391357 } ) ,
    .chany_top_in ( cby_1__1__53_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_53_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_53_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_53_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_53_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_53_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_53_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_53_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_53_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__59_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_64_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_64_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_64_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_64_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_64_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_64_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_64_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_64_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__52_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_52_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_52_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_52_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_52_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_52_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_52_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_52_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_52_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__48_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_52_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_52_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_52_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_52_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_52_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_52_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_52_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_52_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__59_ccff_tail ) , 
    .chany_top_out ( sb_1__1__48_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__48_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__48_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__48_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__48_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_250 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_251 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_10 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_11 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1292 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_760 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1293 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_804 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1294 } ) ) ;
sb_1__1_ sb_5__6_ (
    .prog_clk ( { ctsbuf_net_3911309 } ) ,
    .chany_top_in ( cby_1__1__54_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_54_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_54_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_54_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_54_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_54_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_54_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_54_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_54_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__60_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_65_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_65_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_65_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_65_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_65_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_65_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_65_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_65_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__53_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_53_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_53_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_53_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_53_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_53_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_53_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_53_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_53_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__49_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_53_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_53_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_53_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_53_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_53_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_53_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_53_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_53_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__60_ccff_tail ) , 
    .chany_top_out ( sb_1__1__49_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__49_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__49_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__49_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__49_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_252 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_253 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_12 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_13 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1295 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_488 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1296 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_488 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1297 } ) ) ;
sb_1__1_ sb_5__7_ (
    .prog_clk ( { ctsbuf_net_3431261 } ) ,
    .chany_top_in ( cby_1__1__55_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_55_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_55_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_55_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_55_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_55_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_55_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_55_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_55_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__61_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_66_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_66_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_66_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_66_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_66_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_66_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_66_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_66_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__54_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_54_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_54_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_54_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_54_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_54_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_54_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_54_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_54_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__50_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_54_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_54_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_54_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_54_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_54_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_54_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_54_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_54_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__61_ccff_tail ) , 
    .chany_top_out ( sb_1__1__50_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__50_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__50_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__50_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__50_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_254 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_255 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_14 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_15 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1298 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_767 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1299 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_767 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1300 } ) ) ;
sb_1__1_ sb_5__8_ (
    .prog_clk ( { ctsbuf_net_2951213 } ) ,
    .chany_top_in ( cby_1__1__56_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_56_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_56_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_56_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_56_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_56_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_56_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_56_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_56_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__62_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_67_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_67_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_67_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_67_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_67_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_67_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_67_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_67_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__55_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_55_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_55_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_55_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_55_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_55_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_55_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_55_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_55_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__51_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_55_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_55_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_55_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_55_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_55_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_55_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_55_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_55_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__62_ccff_tail ) , 
    .chany_top_out ( sb_1__1__51_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__51_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__51_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__51_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__51_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_256 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_257 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_16 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_17 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1301 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_885 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1302 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_711 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1303 } ) ) ;
sb_1__1_ sb_5__9_ (
    .prog_clk ( { ctsbuf_net_2471165 } ) ,
    .chany_top_in ( cby_1__1__57_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_57_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_57_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_57_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_57_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_57_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_57_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_57_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_57_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__63_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_68_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_68_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_68_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_68_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_68_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_68_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_68_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_68_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__56_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_56_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_56_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_56_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_56_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_56_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_56_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_56_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_56_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__52_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_56_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_56_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_56_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_56_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_56_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_56_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_56_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_56_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__63_ccff_tail ) , 
    .chany_top_out ( sb_1__1__52_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__52_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__52_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__52_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__52_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_258 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_259 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_18 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1304 } ) ,
    
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_19 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_383 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1305 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_491 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1306 } ) ) ;
sb_1__1_ sb_5__10_ (
    .prog_clk ( { ctsbuf_net_1991117 } ) ,
    .chany_top_in ( cby_1__1__58_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_58_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_58_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_58_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_58_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_58_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_58_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_58_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_58_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__64_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_69_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_69_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_69_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_69_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_69_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_69_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_69_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_69_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__57_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_57_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_57_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_57_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_57_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_57_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_57_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_57_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_57_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__53_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_57_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_57_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_57_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_57_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_57_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_57_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_57_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_57_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__64_ccff_tail ) , 
    .chany_top_out ( sb_1__1__53_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__53_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__53_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__53_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__53_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_260 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_261 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_600 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1307 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1308 } ) ,
    
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_20 ) , 
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_21 ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_884 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1309 } ) ) ;
sb_1__1_ sb_5__11_ (
    .prog_clk ( { ctsbuf_net_1521070 } ) ,
    .chany_top_in ( cby_1__1__59_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_59_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_59_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_59_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_59_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_59_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_59_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_59_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_59_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__65_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_70_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_70_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_70_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_70_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_70_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_70_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_70_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_70_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__58_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_58_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_58_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_58_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_58_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_58_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_58_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_58_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_58_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__54_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_58_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_58_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_58_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_58_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_58_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_58_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_58_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_58_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__65_ccff_tail ) , 
    .chany_top_out ( sb_1__1__54_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__54_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__54_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__54_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__54_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_262 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_263 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_553 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1310 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1311 } ) ,
    
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_22 ) , 
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_23 ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_343 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1312 } ) ) ;
sb_1__1_ sb_6__1_ (
    .prog_clk ( { ctsbuf_net_5771495 } ) ,
    .chany_top_in ( cby_1__1__61_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_61_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_61_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_61_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_61_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_61_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_61_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_61_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_61_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__66_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_72_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_72_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_72_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_72_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_72_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_72_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_72_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_72_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__60_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_60_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_60_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_60_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_60_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_60_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_60_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_60_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_60_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__55_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_60_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_60_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_60_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_60_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_60_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_60_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_60_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_60_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__66_ccff_tail ) , 
    .chany_top_out ( sb_1__1__55_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__55_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__55_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__55_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__55_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_265 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_266 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_536 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1313 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1314 } ) ,
    
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_60_bottom_width_0_height_0__pin_50_ ) , 
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_579 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1315 } ) ) ;
sb_1__1_ sb_6__2_ (
    .prog_clk ( { ctsbuf_net_5651483 } ) ,
    .chany_top_in ( cby_1__1__62_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_62_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_62_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_62_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_62_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_62_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_62_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_62_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_62_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__67_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_73_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_73_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_73_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_73_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_73_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_73_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_73_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_73_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__61_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_61_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_61_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_61_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_61_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_61_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_61_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_61_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_61_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__56_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_61_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_61_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_61_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_61_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_61_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_61_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_61_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_61_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__67_ccff_tail ) , 
    .chany_top_out ( sb_1__1__56_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__56_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__56_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__56_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__56_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_267 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_268 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_381 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1316 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1317 } ) ,
    
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) , 
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_513 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1318 } ) ) ;
sb_1__1_ sb_6__3_ (
    .prog_clk ( { ctsbuf_net_5461464 } ) ,
    .chany_top_in ( cby_1__1__63_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_63_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_63_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_63_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_63_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_63_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_63_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_63_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_63_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__68_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_74_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_74_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_74_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_74_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_74_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_74_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_74_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_74_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__62_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_62_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_62_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_62_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_62_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_62_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_62_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_62_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_62_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__57_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_62_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_62_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_62_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_62_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_62_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_62_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_62_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_62_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__68_ccff_tail ) , 
    .chany_top_out ( sb_1__1__57_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__57_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__57_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__57_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__57_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_269 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_270 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_434 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1319 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1320 } ) ,
    
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) , 
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_907 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1321 } ) ) ;
sb_1__1_ sb_6__4_ (
    .prog_clk ( { ctsbuf_net_5191437 } ) ,
    .chany_top_in ( cby_1__1__64_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_64_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_64_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_64_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_64_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_64_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_64_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_64_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_64_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__69_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_75_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_75_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_75_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_75_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_75_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_75_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_75_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_75_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__63_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_63_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_63_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_63_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_63_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_63_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_63_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_63_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_63_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__58_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_63_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_63_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_63_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_63_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_63_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_63_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_63_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_63_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__69_ccff_tail ) , 
    .chany_top_out ( sb_1__1__58_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__58_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__58_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__58_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__58_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_271 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_272 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_288 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1322 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1323 } ) ,
    
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) , 
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_903 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1324 } ) ) ;
sb_1__1_ sb_6__5_ (
    .prog_clk ( { ctsbuf_net_4841402 } ) ,
    .chany_top_in ( cby_1__1__65_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_65_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_65_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_65_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_65_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_65_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_65_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_65_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_65_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__70_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_76_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_76_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_76_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_76_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_76_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_76_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_76_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_76_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__64_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_64_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_64_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_64_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_64_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_64_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_64_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_64_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_64_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__59_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_64_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_64_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_64_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_64_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_64_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_64_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_64_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_64_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__70_ccff_tail ) , 
    .chany_top_out ( sb_1__1__59_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__59_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__59_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__59_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__59_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_273 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_274 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_895 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1325 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1326 } ) ,
    
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) , 
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_646 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1327 } ) ) ;
sb_1__1_ sb_6__6_ (
    .prog_clk ( { p_abuf41 } ) ,
    .chany_top_in ( cby_1__1__66_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_66_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_66_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_66_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_66_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_66_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_66_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_66_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_66_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__71_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_77_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_77_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_77_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_77_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_77_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_77_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_77_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_77_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__65_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_65_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_65_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_65_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_65_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_65_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_65_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_65_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_65_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__60_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_65_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_65_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_65_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_65_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_65_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_65_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_65_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_65_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__71_ccff_tail ) , 
    .chany_top_out ( sb_1__1__60_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__60_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__60_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__60_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__60_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_275 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_276 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_426 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1328 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1329 } ) ,
    
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) , 
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_6 ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_305 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1330 } ) ) ;
sb_1__1_ sb_6__7_ (
    .prog_clk ( { ctsbuf_net_3931311 } ) ,
    .chany_top_in ( cby_1__1__67_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_67_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_67_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_67_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_67_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_67_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_67_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_67_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_67_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__72_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_78_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_78_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_78_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_78_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_78_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_78_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_78_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_78_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__66_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_66_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_66_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_66_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_66_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_66_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_66_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_66_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_66_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__61_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_66_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_66_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_66_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_66_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_66_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_66_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_66_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_66_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__72_ccff_tail ) , 
    .chany_top_out ( sb_1__1__61_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__61_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__61_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__61_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__61_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_277 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_278 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_446 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1331 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1332 } ) ,
    
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_6 ) , 
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_7 ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_769 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1333 } ) ) ;
sb_1__1_ sb_6__8_ (
    .prog_clk ( { ctsbuf_net_3451263 } ) ,
    .chany_top_in ( cby_1__1__68_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_68_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_68_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_68_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_68_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_68_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_68_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_68_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_68_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__73_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_79_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_79_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_79_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_79_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_79_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_79_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_79_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_79_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__67_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_67_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_67_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_67_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_67_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_67_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_67_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_67_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_67_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__62_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_67_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_67_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_67_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_67_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_67_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_67_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_67_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_67_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__73_ccff_tail ) , 
    .chany_top_out ( sb_1__1__62_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__62_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__62_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__62_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__62_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_279 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_280 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_310 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1334 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1335 } ) ,
    
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_7 ) , 
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_8 ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_624 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1336 } ) ) ;
sb_1__1_ sb_6__9_ (
    .prog_clk ( { ctsbuf_net_2971215 } ) ,
    .chany_top_in ( cby_1__1__69_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_69_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_69_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_69_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_69_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_69_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_69_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_69_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_69_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__74_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_80_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_80_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_80_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_80_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_80_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_80_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_80_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_80_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__68_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_68_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_68_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_68_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_68_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_68_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_68_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_68_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_68_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__63_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_68_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_68_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_68_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_68_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_68_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_68_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_68_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_68_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__74_ccff_tail ) , 
    .chany_top_out ( sb_1__1__63_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__63_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__63_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__63_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__63_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_281 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_282 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_452 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1337 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1338 } ) ,
    
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_8 ) , 
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_9 ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_806 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1339 } ) ) ;
sb_1__1_ sb_6__10_ (
    .prog_clk ( { ctsbuf_net_2491167 } ) ,
    .chany_top_in ( cby_1__1__70_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_70_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_70_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_70_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_70_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_70_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_70_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_70_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_70_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__75_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_81_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_81_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_81_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_81_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_81_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_81_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_81_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_81_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__69_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_69_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_69_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_69_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_69_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_69_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_69_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_69_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_69_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__64_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_69_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_69_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_69_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_69_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_69_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_69_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_69_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_69_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__75_ccff_tail ) , 
    .chany_top_out ( sb_1__1__64_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__64_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__64_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__64_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__64_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_283 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_284 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_668 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1340 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1341 } ) ,
    
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_9 ) , 
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_10 ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_448 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1342 } ) ) ;
sb_1__1_ sb_6__11_ (
    .prog_clk ( { ctsbuf_net_2011119 } ) ,
    .chany_top_in ( cby_1__1__71_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_71_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_71_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_71_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_71_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_71_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_71_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_71_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_71_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__76_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_82_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_82_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_82_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_82_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_82_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_82_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_82_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_82_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__70_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_70_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_70_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_70_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_70_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_70_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_70_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_70_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_70_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__65_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_70_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_70_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_70_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_70_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_70_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_70_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_70_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_70_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__76_ccff_tail ) , 
    .chany_top_out ( sb_1__1__65_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__65_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__65_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__65_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__65_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_285 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_286 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_429 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1343 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1344 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_632 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1345 } ) ,
    
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_10 ) , 
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_11 ) ) ;
sb_1__1_ sb_7__1_ (
    .prog_clk ( { ctsbuf_net_5691487 } ) ,
    .chany_top_in ( cby_1__1__73_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_73_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_73_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_73_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_73_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_73_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_73_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_73_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_73_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__77_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_84_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_84_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_84_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_84_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_84_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_84_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_84_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_84_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__72_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_72_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_72_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_72_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_72_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_72_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_72_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_72_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_72_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__66_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_72_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_72_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_72_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_72_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_72_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_72_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_72_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_72_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__77_ccff_tail ) , 
    .chany_top_out ( sb_1__1__66_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__66_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__66_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__66_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__66_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_2 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_3 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_612 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1346 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1347 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_575 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1348 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_900 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1349 } ) ) ;
sb_1__1_ sb_7__2_ (
    .prog_clk ( { ctsbuf_net_5511469 } ) ,
    .chany_top_in ( cby_1__1__74_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_74_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_74_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_74_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_74_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_74_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_74_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_74_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_74_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__78_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_85_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_85_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_85_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_85_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_85_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_85_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_85_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_85_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__73_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_73_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_73_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_73_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_73_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_73_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_73_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_73_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_73_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__67_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_73_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_73_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_73_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_73_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_73_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_73_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_73_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_73_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__78_ccff_tail ) , 
    .chany_top_out ( sb_1__1__67_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__67_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__67_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__67_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__67_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_4 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_5 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_915 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1350 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1351 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_916 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1352 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_916 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1353 } ) ) ;
sb_1__1_ sb_7__3_ (
    .prog_clk ( { ctsbuf_net_5261444 } ) ,
    .chany_top_in ( cby_1__1__75_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_75_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_75_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_75_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_75_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_75_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_75_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_75_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_75_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__79_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_86_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_86_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_86_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_86_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_86_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_86_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_86_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_86_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__74_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_74_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_74_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_74_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_74_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_74_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_74_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_74_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_74_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__68_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_74_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_74_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_74_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_74_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_74_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_74_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_74_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_74_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__79_ccff_tail ) , 
    .chany_top_out ( sb_1__1__68_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__68_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__68_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__68_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__68_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_6 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_7 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_541 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1354 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1355 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_807 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1356 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_807 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1357 } ) ) ;
sb_1__1_ sb_7__4_ (
    .prog_clk ( { ctsbuf_net_4941412 } ) ,
    .chany_top_in ( cby_1__1__76_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_76_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_76_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_76_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_76_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_76_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_76_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_76_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_76_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__80_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_87_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_87_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_87_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_87_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_87_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_87_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_87_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_87_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__75_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_75_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_75_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_75_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_75_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_75_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_75_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_75_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_75_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__69_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_75_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_75_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_75_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_75_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_75_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_75_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_75_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_75_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__80_ccff_tail ) , 
    .chany_top_out ( sb_1__1__69_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__69_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__69_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__69_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__69_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_8 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_9 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_507 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1358 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1359 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_625 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1360 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_785 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1361 } ) ) ;
sb_1__1_ sb_7__5_ (
    .prog_clk ( { ctsbuf_net_4541372 } ) ,
    .chany_top_in ( cby_1__1__77_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_77_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_77_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_77_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_77_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_77_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_77_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_77_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_77_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__81_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_88_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_88_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_88_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_88_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_88_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_88_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_88_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_88_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__76_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_76_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_76_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_76_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_76_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_76_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_76_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_76_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_76_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__70_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_76_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_76_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_76_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_76_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_76_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_76_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_76_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_76_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__81_ccff_tail ) , 
    .chany_top_out ( sb_1__1__70_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__70_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__70_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__70_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__70_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_10 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_11 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_655 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1362 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1363 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_746 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1364 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_746 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1365 } ) ) ;
sb_1__1_ sb_7__6_ (
    .prog_clk ( { ctsbuf_net_4061324 } ) ,
    .chany_top_in ( cby_1__1__78_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_78_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_78_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_78_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_78_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_78_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_78_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_78_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_78_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__82_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_89_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_89_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_89_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_89_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_89_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_89_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_89_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_89_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__77_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_77_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_77_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_77_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_77_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_77_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_77_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_77_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_77_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__71_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_77_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_77_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_77_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_77_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_77_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_77_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_77_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_77_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__82_ccff_tail ) , 
    .chany_top_out ( sb_1__1__71_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__71_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__71_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__71_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__71_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_12 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_13 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_440 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1366 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1367 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_569 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1368 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_403 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1369 } ) ) ;
sb_1__1_ sb_7__7_ (
    .prog_clk ( { ctsbuf_net_3581276 } ) ,
    .chany_top_in ( cby_1__1__79_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_79_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_79_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_79_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_79_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_79_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_79_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_79_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_79_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__83_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_90_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_90_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_90_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_90_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_90_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_90_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_90_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_90_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__78_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_78_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_78_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_78_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_78_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_78_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_78_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_78_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_78_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__72_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_78_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_78_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_78_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_78_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_78_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_78_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_78_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_78_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__83_ccff_tail ) , 
    .chany_top_out ( sb_1__1__72_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__72_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__72_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__72_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__72_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_14 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_15 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_413 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1370 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1371 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_836 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1372 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_836 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1373 } ) ) ;
sb_1__1_ sb_7__8_ (
    .prog_clk ( { ctsbuf_net_3101228 } ) ,
    .chany_top_in ( cby_1__1__80_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_80_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_80_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_80_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_80_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_80_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_80_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_80_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_80_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__84_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_91_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_91_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_91_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_91_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_91_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_91_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_91_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_91_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__79_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_79_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_79_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_79_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_79_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_79_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_79_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_79_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_79_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__73_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_79_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_79_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_79_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_79_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_79_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_79_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_79_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_79_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__84_ccff_tail ) , 
    .chany_top_out ( sb_1__1__73_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__73_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__73_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__73_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__73_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_16 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_17 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_436 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1374 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1375 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_542 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1376 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_542 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1377 } ) ) ;
sb_1__1_ sb_7__9_ (
    .prog_clk ( { ctsbuf_net_2621180 } ) ,
    .chany_top_in ( cby_1__1__81_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_81_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_81_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_81_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_81_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_81_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_81_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_81_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_81_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__85_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_92_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_92_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_92_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_92_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_92_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_92_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_92_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_92_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__80_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_80_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_80_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_80_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_80_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_80_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_80_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_80_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_80_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__74_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_80_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_80_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_80_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_80_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_80_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_80_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_80_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_80_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__85_ccff_tail ) , 
    .chany_top_out ( sb_1__1__74_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__74_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__74_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__74_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__74_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_18 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_19 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_595 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1378 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1379 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_650 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1380 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_650 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1381 } ) ) ;
sb_1__1_ sb_7__10_ (
    .prog_clk ( { ctsbuf_net_2141132 } ) ,
    .chany_top_in ( cby_1__1__82_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_82_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_82_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_82_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_82_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_82_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_82_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_82_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_82_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__86_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_93_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_93_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_93_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_93_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_93_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_93_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_93_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_93_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__81_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_81_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_81_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_81_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_81_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_81_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_81_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_81_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_81_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__75_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_81_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_81_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_81_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_81_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_81_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_81_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_81_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_81_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__86_ccff_tail ) , 
    .chany_top_out ( sb_1__1__75_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__75_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__75_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__75_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__75_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_20 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_21 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_626 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1382 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1383 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_299 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1384 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_299 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1385 } ) ) ;
sb_1__1_ sb_7__11_ (
    .prog_clk ( { ctsbuf_net_1661084 } ) ,
    .chany_top_in ( cby_1__1__83_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_83_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_83_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_83_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_83_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_83_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_83_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_83_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_83_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__87_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_94_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_94_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_94_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_94_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_94_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_94_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_94_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_94_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__82_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_82_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_82_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_82_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_82_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_82_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_82_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_82_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_82_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__76_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_82_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_82_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_82_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_82_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_82_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_82_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_82_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_82_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__87_ccff_tail ) , 
    .chany_top_out ( sb_1__1__76_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__76_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__76_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__76_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__76_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_22 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_23 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_784 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1386 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1387 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_704 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1388 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_704 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1389 } ) ) ;
sb_1__1_ sb_8__1_ (
    .prog_clk ( { ctsbuf_net_5501468 } ) ,
    .chany_top_in ( cby_1__1__85_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_85_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_85_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_85_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_85_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_85_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_85_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_85_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_85_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__88_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_96_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_96_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_96_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_96_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_96_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_96_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_96_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_96_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__84_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_84_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_84_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_84_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_84_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_84_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_84_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_84_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_84_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__77_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_84_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_84_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_84_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_84_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_84_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_84_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_84_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_84_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__88_ccff_tail ) , 
    .chany_top_out ( sb_1__1__77_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__77_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__77_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__77_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__77_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_25 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_26 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_396 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1390 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1391 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_568 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1392 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_568 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1393 } ) ) ;
sb_1__1_ sb_8__2_ (
    .prog_clk ( { ctsbuf_net_5241442 } ) ,
    .chany_top_in ( cby_1__1__86_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_86_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_86_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_86_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_86_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_86_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_86_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_86_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_86_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__89_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_97_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_97_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_97_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_97_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_97_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_97_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_97_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_97_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__85_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_85_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_85_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_85_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_85_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_85_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_85_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_85_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_85_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__78_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_85_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_85_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_85_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_85_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_85_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_85_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_85_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_85_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__89_ccff_tail ) , 
    .chany_top_out ( sb_1__1__78_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__78_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__78_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__78_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__78_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_27 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_28 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_368 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1394 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1395 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_502 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1396 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_502 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1397 } ) ) ;
sb_1__1_ sb_8__3_ (
    .prog_clk ( { ctsbuf_net_4911409 } ) ,
    .chany_top_in ( cby_1__1__87_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_87_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_87_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_87_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_87_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_87_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_87_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_87_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_87_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__90_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_98_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_98_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_98_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_98_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_98_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_98_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_98_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_98_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__86_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_86_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_86_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_86_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_86_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_86_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_86_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_86_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_86_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__79_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_86_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_86_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_86_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_86_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_86_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_86_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_86_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_86_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__90_ccff_tail ) , 
    .chany_top_out ( sb_1__1__79_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__79_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__79_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__79_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__79_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_29 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_30 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_451 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1398 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1399 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_466 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1400 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_466 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1401 } ) ) ;
sb_1__1_ sb_8__4_ (
    .prog_clk ( { ctsbuf_net_4511369 } ) ,
    .chany_top_in ( cby_1__1__88_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_88_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_88_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_88_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_88_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_88_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_88_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_88_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_88_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__91_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_99_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_99_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_99_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_99_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_99_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_99_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_99_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_99_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__87_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_87_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_87_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_87_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_87_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_87_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_87_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_87_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_87_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__80_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_87_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_87_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_87_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_87_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_87_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_87_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_87_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_87_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__91_ccff_tail ) , 
    .chany_top_out ( sb_1__1__80_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__80_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__80_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__80_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__80_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_31 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_32 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_661 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1402 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1403 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_565 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1404 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_565 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1405 } ) ) ;
sb_1__1_ sb_8__5_ (
    .prog_clk ( { ctsbuf_net_4031321 } ) ,
    .chany_top_in ( cby_1__1__89_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_89_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_89_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_89_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_89_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_89_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_89_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_89_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_89_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__92_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_100_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_100_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_100_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_100_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_100_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_100_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_100_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_100_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__88_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_88_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_88_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_88_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_88_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_88_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_88_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_88_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_88_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__81_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_88_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_88_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_88_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_88_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_88_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_88_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_88_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_88_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__92_ccff_tail ) , 
    .chany_top_out ( sb_1__1__81_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__81_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__81_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__81_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__81_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_33 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_34 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_537 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1406 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1407 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_598 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1408 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_598 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1409 } ) ) ;
sb_1__1_ sb_8__6_ (
    .prog_clk ( { ctsbuf_net_3551273 } ) ,
    .chany_top_in ( cby_1__1__90_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_90_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_90_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_90_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_90_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_90_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_90_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_90_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_90_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__93_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_101_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_101_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_101_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_101_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_101_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_101_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_101_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_101_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__89_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_89_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_89_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_89_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_89_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_89_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_89_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_89_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_89_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__82_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_89_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_89_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_89_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_89_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_89_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_89_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_89_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_89_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__93_ccff_tail ) , 
    .chany_top_out ( sb_1__1__82_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__82_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__82_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__82_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__82_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_35 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_36 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_330 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1410 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1411 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_850 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1412 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_850 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1413 } ) ) ;
sb_1__1_ sb_8__7_ (
    .prog_clk ( { ctsbuf_net_3071225 } ) ,
    .chany_top_in ( cby_1__1__91_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_91_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_91_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_91_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_91_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_91_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_91_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_91_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_91_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__94_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_102_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_102_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_102_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_102_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_102_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_102_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_102_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_102_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__90_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_90_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_90_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_90_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_90_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_90_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_90_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_90_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_90_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__83_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_90_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_90_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_90_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_90_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_90_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_90_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_90_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_90_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__94_ccff_tail ) , 
    .chany_top_out ( sb_1__1__83_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__83_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__83_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__83_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__83_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_37 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_38 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_506 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1414 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1415 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_842 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1416 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_727 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1417 } ) ) ;
sb_1__1_ sb_8__8_ (
    .prog_clk ( { ctsbuf_net_2591177 } ) ,
    .chany_top_in ( cby_1__1__92_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_92_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_92_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_92_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_92_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_92_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_92_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_92_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_92_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__95_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_103_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_103_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_103_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_103_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_103_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_103_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_103_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_103_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__91_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_91_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_91_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_91_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_91_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_91_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_91_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_91_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_91_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__84_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_91_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_91_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_91_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_91_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_91_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_91_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_91_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_91_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__95_ccff_tail ) , 
    .chany_top_out ( sb_1__1__84_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__84_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__84_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__84_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__84_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_39 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_40 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_319 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1418 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1419 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_852 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1420 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_724 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1421 } ) ) ;
sb_1__1_ sb_8__9_ (
    .prog_clk ( { ctsbuf_net_2111129 } ) ,
    .chany_top_in ( cby_1__1__93_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_93_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_93_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_93_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_93_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_93_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_93_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_93_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_93_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__96_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_104_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_104_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_104_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_104_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_104_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_104_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_104_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_104_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__92_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_92_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_92_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_92_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_92_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_92_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_92_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_92_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_92_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__85_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_92_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_92_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_92_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_92_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_92_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_92_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_92_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_92_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__96_ccff_tail ) , 
    .chany_top_out ( sb_1__1__85_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__85_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__85_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__85_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__85_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_41 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_42 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_622 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1422 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1423 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_398 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1424 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_398 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1425 } ) ) ;
sb_1__1_ sb_8__10_ (
    .prog_clk ( { ctsbuf_net_1631081 } ) ,
    .chany_top_in ( cby_1__1__94_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_94_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_94_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_94_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_94_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_94_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_94_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_94_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_94_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__97_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_105_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_105_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_105_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_105_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_105_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_105_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_105_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_105_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__93_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_93_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_93_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_93_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_93_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_93_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_93_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_93_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_93_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__86_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_93_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_93_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_93_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_93_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_93_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_93_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_93_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_93_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__97_ccff_tail ) , 
    .chany_top_out ( sb_1__1__86_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__86_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__86_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__86_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__86_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_43 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_44 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_766 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1426 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1427 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_457 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1428 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_800 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1429 } ) ) ;
sb_1__1_ sb_8__11_ (
    .prog_clk ( { ctsbuf_net_1191037 } ) ,
    .chany_top_in ( cby_1__1__95_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_95_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_95_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_95_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_95_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_95_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_95_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_95_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_95_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__98_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_106_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_106_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_106_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_106_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_106_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_106_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_106_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_106_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__94_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_94_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_94_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_94_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_94_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_94_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_94_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_94_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_94_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__87_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_94_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_94_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_94_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_94_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_94_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_94_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_94_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_94_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__98_ccff_tail ) , 
    .chany_top_out ( sb_1__1__87_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__87_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__87_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__87_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__87_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_45 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_46 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_693 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1430 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1431 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_636 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1432 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_636 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1433 } ) ) ;
sb_1__1_ sb_9__1_ (
    .prog_clk ( { ctsbuf_net_5231441 } ) ,
    .chany_top_in ( cby_1__1__97_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_97_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_97_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_97_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_97_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_97_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_97_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_97_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_97_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__99_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_108_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_108_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_108_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_108_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_108_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_108_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_108_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_108_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__96_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_96_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_96_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_96_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_96_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_96_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_96_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_96_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_96_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__88_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_96_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_96_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_96_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_96_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_96_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_96_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_96_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_96_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__99_ccff_tail ) , 
    .chany_top_out ( sb_1__1__88_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__88_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__88_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__88_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__88_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_48 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_49 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1434 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_615 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1435 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_615 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1436 } ) ) ;
sb_1__1_ sb_9__2_ (
    .prog_clk ( { ctsbuf_net_4891407 } ) ,
    .chany_top_in ( cby_1__1__98_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_98_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_98_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_98_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_98_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_98_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_98_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_98_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_98_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__100_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_109_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_109_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_109_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_109_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_109_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_109_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_109_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_109_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__97_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_97_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_97_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_97_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_97_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_97_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_97_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_97_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_97_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__89_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_97_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_97_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_97_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_97_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_97_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_97_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_97_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_97_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__100_ccff_tail ) , 
    .chany_top_out ( sb_1__1__89_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__89_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__89_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__89_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__89_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_50 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_51 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1437 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_788 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1438 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_423 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1439 } ) ) ;
sb_1__1_ sb_9__3_ (
    .prog_clk ( { ctsbuf_net_4481366 } ) ,
    .chany_top_in ( cby_1__1__99_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_99_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_99_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_99_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_99_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_99_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_99_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_99_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_99_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__101_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_110_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_110_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_110_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_110_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_110_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_110_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_110_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_110_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__98_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_98_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_98_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_98_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_98_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_98_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_98_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_98_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_98_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__90_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_98_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_98_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_98_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_98_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_98_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_98_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_98_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_98_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__101_ccff_tail ) , 
    .chany_top_out ( sb_1__1__90_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__90_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__90_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__90_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__90_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_52 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_53 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_6 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_7 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1440 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_315 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1441 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_315 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1442 } ) ) ;
sb_1__1_ sb_9__4_ (
    .prog_clk ( { ctsbuf_net_4001318 } ) ,
    .chany_top_in ( cby_1__1__100_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_100_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_100_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_100_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_100_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_100_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_100_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_100_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_100_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__102_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_111_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_111_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_111_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_111_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_111_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_111_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_111_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_111_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__99_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_99_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_99_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_99_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_99_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_99_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_99_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_99_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_99_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__91_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_99_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_99_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_99_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_99_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_99_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_99_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_99_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_99_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__102_ccff_tail ) , 
    .chany_top_out ( sb_1__1__91_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__91_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__91_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__91_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__91_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_54 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_55 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_8 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_9 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1443 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_558 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1444 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_558 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1445 } ) ) ;
sb_1__1_ sb_9__5_ (
    .prog_clk ( { ctsbuf_net_3521270 } ) ,
    .chany_top_in ( cby_1__1__101_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_101_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_101_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_101_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_101_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_101_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_101_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_101_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_101_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__103_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_112_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_112_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_112_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_112_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_112_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_112_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_112_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_112_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__100_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_100_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_100_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_100_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_100_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_100_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_100_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_100_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_100_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__92_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_100_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_100_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_100_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_100_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_100_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_100_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_100_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_100_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__103_ccff_tail ) , 
    .chany_top_out ( sb_1__1__92_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__92_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__92_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__92_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__92_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_56 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_57 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_10 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_11 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1446 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_616 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1447 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_616 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1448 } ) ) ;
sb_1__1_ sb_9__6_ (
    .prog_clk ( { ctsbuf_net_3041222 } ) ,
    .chany_top_in ( cby_1__1__102_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_102_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_102_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_102_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_102_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_102_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_102_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_102_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_102_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__104_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_113_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_113_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_113_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_113_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_113_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_113_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_113_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_113_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__101_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_101_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_101_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_101_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_101_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_101_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_101_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_101_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_101_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__93_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_101_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_101_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_101_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_101_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_101_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_101_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_101_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_101_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__104_ccff_tail ) , 
    .chany_top_out ( sb_1__1__93_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__93_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__93_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__93_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__93_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_58 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_59 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_12 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_13 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1449 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_643 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1450 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_643 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1451 } ) ) ;
sb_1__1_ sb_9__7_ (
    .prog_clk ( { ctsbuf_net_2561174 } ) ,
    .chany_top_in ( cby_1__1__103_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_103_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_103_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_103_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_103_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_103_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_103_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_103_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_103_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__105_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_114_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_114_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_114_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_114_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_114_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_114_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_114_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_114_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__102_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_102_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_102_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_102_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_102_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_102_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_102_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_102_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_102_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__94_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_102_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_102_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_102_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_102_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_102_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_102_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_102_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_102_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__105_ccff_tail ) , 
    .chany_top_out ( sb_1__1__94_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__94_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__94_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__94_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__94_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_60 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_61 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_14 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_15 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1452 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_748 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1453 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_748 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1454 } ) ) ;
sb_1__1_ sb_9__8_ (
    .prog_clk ( { ctsbuf_net_2081126 } ) ,
    .chany_top_in ( cby_1__1__104_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_104_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_104_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_104_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_104_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_104_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_104_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_104_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_104_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__106_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_115_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_115_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_115_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_115_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_115_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_115_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_115_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_115_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__103_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_103_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_103_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_103_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_103_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_103_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_103_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_103_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_103_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__95_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_103_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_103_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_103_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_103_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_103_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_103_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_103_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_103_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__106_ccff_tail ) , 
    .chany_top_out ( sb_1__1__95_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__95_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__95_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__95_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__95_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_62 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_63 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_16 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_17 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1455 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_725 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1456 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_902 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1457 } ) ) ;
sb_1__1_ sb_9__9_ (
    .prog_clk ( { ctsbuf_net_1601078 } ) ,
    .chany_top_in ( cby_1__1__105_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_105_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_105_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_105_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_105_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_105_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_105_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_105_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_105_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__107_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_116_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_116_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_116_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_116_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_116_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_116_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_116_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_116_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__104_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_104_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_104_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_104_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_104_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_104_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_104_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_104_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_104_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__96_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_104_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_104_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_104_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_104_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_104_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_104_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_104_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_104_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__107_ccff_tail ) , 
    .chany_top_out ( sb_1__1__96_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__96_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__96_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__96_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__96_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_64 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_65 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_18 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_19 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1458 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_285 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1459 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_864 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1460 } ) ) ;
sb_1__1_ sb_9__10_ (
    .prog_clk ( { ctsbuf_net_1161034 } ) ,
    .chany_top_in ( cby_1__1__106_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_106_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_106_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_106_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_106_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_106_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_106_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_106_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_106_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__108_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_117_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_117_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_117_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_117_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_117_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_117_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_117_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_117_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__105_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_105_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_105_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_105_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_105_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_105_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_105_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_105_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_105_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__97_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_105_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_105_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_105_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_105_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_105_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_105_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_105_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_105_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__108_ccff_tail ) , 
    .chany_top_out ( sb_1__1__97_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__97_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__97_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__97_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__97_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_66 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_67 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_20 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_21 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1461 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_578 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1462 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_578 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1463 } ) ) ;
sb_1__1_ sb_9__11_ (
    .prog_clk ( { p_abuf3 } ) ,
    .chany_top_in ( cby_1__1__107_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_107_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_107_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_107_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_107_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_107_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_107_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_107_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_107_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__109_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_118_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_118_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_118_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_118_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_118_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_118_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_118_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_118_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__106_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_106_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_106_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_106_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_106_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_106_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_106_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_106_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_106_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__98_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_106_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_106_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_106_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_106_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_106_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_106_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_106_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_106_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__109_ccff_tail ) , 
    .chany_top_out ( sb_1__1__98_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__98_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__98_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__98_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__98_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_68 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_69 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_22 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_23 ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1464 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_675 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1465 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_675 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1466 } ) ) ;
sb_1__1_ sb_10__1_ (
    .prog_clk ( { ctsbuf_net_4881406 } ) ,
    .chany_top_in ( cby_1__1__109_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_109_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_109_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_109_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_109_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_109_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_109_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_109_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_109_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__110_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_120_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_120_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_120_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_120_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_120_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_120_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_120_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_120_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__108_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_108_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_108_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_108_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_108_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_108_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_108_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_108_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_108_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__99_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_108_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_108_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_108_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_108_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_108_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_108_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_108_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_108_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__110_ccff_tail ) , 
    .chany_top_out ( sb_1__1__99_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__99_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__99_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__99_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__99_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_71 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_72 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_265 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1467 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1468 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_606 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1469 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_606 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1470 } ) ) ;
sb_1__1_ sb_10__2_ (
    .prog_clk ( { ctsbuf_net_4461364 } ) ,
    .chany_top_in ( cby_1__1__110_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_110_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_110_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_110_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_110_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_110_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_110_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_110_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_110_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__111_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_121_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_121_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_121_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_121_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_121_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_121_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_121_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_121_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__109_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_109_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_109_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_109_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_109_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_109_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_109_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_109_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_109_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__100_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_109_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_109_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_109_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_109_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_109_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_109_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_109_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_109_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__111_ccff_tail ) , 
    .chany_top_out ( sb_1__1__100_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__100_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__100_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__100_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__100_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_73 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_74 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_522 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1471 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1472 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_822 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1473 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_822 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1474 } ) ) ;
sb_1__1_ sb_10__3_ (
    .prog_clk ( { ctsbuf_net_3971315 } ) ,
    .chany_top_in ( cby_1__1__111_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_111_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_111_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_111_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_111_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_111_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_111_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_111_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_111_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__112_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_122_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_122_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_122_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_122_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_122_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_122_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_122_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_122_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__110_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_110_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_110_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_110_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_110_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_110_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_110_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_110_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_110_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__101_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_110_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_110_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_110_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_110_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_110_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_110_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_110_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_110_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__112_ccff_tail ) , 
    .chany_top_out ( sb_1__1__101_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__101_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__101_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__101_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__101_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_75 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_76 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_818 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1475 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1476 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_740 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1477 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_320 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1478 } ) ) ;
sb_1__1_ sb_10__4_ (
    .prog_clk ( { ctsbuf_net_3491267 } ) ,
    .chany_top_in ( cby_1__1__112_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_112_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_112_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_112_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_112_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_112_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_112_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_112_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_112_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__113_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_123_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_123_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_123_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_123_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_123_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_123_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_123_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_123_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__111_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_111_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_111_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_111_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_111_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_111_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_111_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_111_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_111_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__102_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_111_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_111_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_111_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_111_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_111_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_111_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_111_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_111_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__113_ccff_tail ) , 
    .chany_top_out ( sb_1__1__102_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__102_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__102_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__102_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__102_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_77 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_78 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_268 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1479 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1480 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_407 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1481 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_407 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1482 } ) ) ;
sb_1__1_ sb_10__5_ (
    .prog_clk ( { ctsbuf_net_3011219 } ) ,
    .chany_top_in ( cby_1__1__113_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_113_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_113_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_113_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_113_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_113_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_113_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_113_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_113_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__114_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_124_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_124_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_124_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_124_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_124_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_124_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_124_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_124_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__112_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_112_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_112_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_112_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_112_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_112_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_112_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_112_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_112_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__103_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_112_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_112_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_112_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_112_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_112_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_112_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_112_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_112_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__114_ccff_tail ) , 
    .chany_top_out ( sb_1__1__103_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__103_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__103_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__103_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__103_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_79 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_80 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_354 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1483 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1484 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_783 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1485 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_783 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1486 } ) ) ;
sb_1__1_ sb_10__6_ (
    .prog_clk ( { ctsbuf_net_2531171 } ) ,
    .chany_top_in ( cby_1__1__114_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_114_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_114_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_114_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_114_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_114_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_114_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_114_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_114_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__115_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_125_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_125_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_125_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_125_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_125_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_125_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_125_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_125_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__113_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_113_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_113_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_113_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_113_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_113_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_113_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_113_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_113_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__104_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_113_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_113_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_113_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_113_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_113_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_113_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_113_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_113_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__115_ccff_tail ) , 
    .chany_top_out ( sb_1__1__104_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__104_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__104_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__104_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__104_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_81 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_82 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_735 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1487 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1488 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_392 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1489 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_392 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1490 } ) ) ;
sb_1__1_ sb_10__7_ (
    .prog_clk ( { ctsbuf_net_2051123 } ) ,
    .chany_top_in ( cby_1__1__115_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_115_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_115_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_115_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_115_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_115_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_115_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_115_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_115_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__116_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_126_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_126_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_126_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_126_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_126_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_126_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_126_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_126_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__114_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_114_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_114_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_114_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_114_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_114_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_114_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_114_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_114_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__105_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_114_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_114_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_114_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_114_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_114_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_114_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_114_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_114_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__116_ccff_tail ) , 
    .chany_top_out ( sb_1__1__105_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__105_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__105_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__105_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__105_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_83 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_84 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_917 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1491 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1492 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_918 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1493 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_918 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1494 } ) ) ;
sb_1__1_ sb_10__8_ (
    .prog_clk ( { ctsbuf_net_1571075 } ) ,
    .chany_top_in ( cby_1__1__116_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_116_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_116_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_116_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_116_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_116_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_116_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_116_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_116_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__117_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_127_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_127_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_127_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_127_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_127_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_127_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_127_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_127_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__115_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_115_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_115_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_115_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_115_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_115_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_115_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_115_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_115_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__106_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_115_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_115_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_115_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_115_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_115_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_115_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_115_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_115_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__117_ccff_tail ) , 
    .chany_top_out ( sb_1__1__106_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__106_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__106_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__106_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__106_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_85 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_86 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_715 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1495 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1496 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_465 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1497 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_465 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1498 } ) ) ;
sb_1__1_ sb_10__9_ (
    .prog_clk ( { ctsbuf_net_1131031 } ) ,
    .chany_top_in ( cby_1__1__117_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_117_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_117_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_117_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_117_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_117_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_117_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_117_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_117_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__118_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_128_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_128_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_128_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_128_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_128_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_128_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_128_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_128_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__116_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_116_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_116_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_116_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_116_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_116_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_116_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_116_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_116_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__107_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_116_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_116_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_116_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_116_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_116_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_116_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_116_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_116_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__118_ccff_tail ) , 
    .chany_top_out ( sb_1__1__107_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__107_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__107_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__107_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__107_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_87 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_88 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_548 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1499 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1500 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_376 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1501 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_886 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1502 } ) ) ;
sb_1__1_ sb_10__10_ (
    .prog_clk ( { p_abuf5 } ) ,
    .chany_top_in ( cby_1__1__118_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_118_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_118_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_118_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_118_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_118_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_118_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_118_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_118_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__119_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_129_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_129_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_129_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_129_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_129_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_129_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_129_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_129_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__117_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_117_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_117_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_117_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_117_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_117_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_117_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_117_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_117_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__108_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_117_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_117_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_117_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_117_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_117_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_117_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_117_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_117_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__119_ccff_tail ) , 
    .chany_top_out ( sb_1__1__108_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__108_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__108_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__108_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__108_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_89 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_90 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_709 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1503 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1504 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_399 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1505 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_399 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1506 } ) ) ;
sb_1__1_ sb_10__11_ (
    .prog_clk ( { p_abuf1 } ) ,
    .chany_top_in ( cby_1__1__119_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_119_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_119_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_119_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_119_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_119_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_119_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_119_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_119_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__120_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_130_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_130_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_130_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_130_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_130_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_130_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_130_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_130_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__118_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_118_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_118_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_118_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_118_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_118_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_118_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_118_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_118_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__109_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_118_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_118_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_118_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_118_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_118_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_118_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_118_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_118_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__120_ccff_tail ) , 
    .chany_top_out ( sb_1__1__109_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__109_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__109_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__109_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__109_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_91 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_92 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_519 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1507 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1508 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_562 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1509 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_562 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1510 } ) ) ;
sb_1__1_ sb_11__1_ (
    .prog_clk ( { ctsbuf_net_4451363 } ) ,
    .chany_top_in ( cby_1__1__121_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_121_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_121_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_121_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_121_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_121_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_121_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_121_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_121_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__121_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_132_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_132_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_132_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_132_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_132_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_132_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_132_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_132_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__120_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_120_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_120_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_120_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_120_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_120_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_120_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_120_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_120_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__110_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_120_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_120_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_120_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_120_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_120_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_120_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_120_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_120_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__121_ccff_tail ) , 
    .chany_top_out ( sb_1__1__110_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__110_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__110_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__110_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__110_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_94 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_95 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_509 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1511 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1512 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_577 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1513 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_868 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1514 } ) ) ;
sb_1__1_ sb_11__2_ (
    .prog_clk ( { ctsbuf_net_3961314 } ) ,
    .chany_top_in ( cby_1__1__122_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_122_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_122_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_122_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_122_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_122_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_122_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_122_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_122_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__122_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_133_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_133_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_133_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_133_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_133_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_133_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_133_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_133_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__121_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_121_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_121_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_121_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_121_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_121_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_121_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_121_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_121_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__111_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_121_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_121_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_121_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_121_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_121_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_121_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_121_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_121_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__122_ccff_tail ) , 
    .chany_top_out ( sb_1__1__111_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__111_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__111_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__111_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__111_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_96 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_97 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_742 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1515 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1516 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_391 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1517 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_391 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1518 } ) ) ;
sb_1__1_ sb_11__3_ (
    .prog_clk ( { ctsbuf_net_3481266 } ) ,
    .chany_top_in ( cby_1__1__123_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_123_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_123_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_123_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_123_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_123_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_123_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_123_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_123_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__123_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_134_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_134_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_134_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_134_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_134_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_134_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_134_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_134_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__122_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_122_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_122_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_122_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_122_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_122_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_122_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_122_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_122_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__112_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_122_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_122_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_122_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_122_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_122_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_122_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_122_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_122_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__123_ccff_tail ) , 
    .chany_top_out ( sb_1__1__112_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__112_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__112_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__112_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__112_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_98 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_99 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_551 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1519 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1520 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_834 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1521 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_545 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1522 } ) ) ;
sb_1__1_ sb_11__4_ (
    .prog_clk ( { ctsbuf_net_3001218 } ) ,
    .chany_top_in ( cby_1__1__124_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_124_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_124_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_124_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_124_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_124_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_124_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_124_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_124_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__124_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_135_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_135_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_135_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_135_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_135_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_135_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_135_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_135_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__123_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_123_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_123_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_123_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_123_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_123_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_123_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_123_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_123_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__113_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_123_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_123_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_123_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_123_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_123_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_123_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_123_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_123_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__124_ccff_tail ) , 
    .chany_top_out ( sb_1__1__113_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__113_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__113_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__113_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__113_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_100 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_101 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_593 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1523 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1524 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_688 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1525 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_688 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1526 } ) ) ;
sb_1__1_ sb_11__5_ (
    .prog_clk ( { ctsbuf_net_2521170 } ) ,
    .chany_top_in ( cby_1__1__125_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_125_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_125_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_125_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_125_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_125_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_125_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_125_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_125_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__125_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_136_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_136_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_136_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_136_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_136_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_136_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_136_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_136_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__124_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_124_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_124_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_124_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_124_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_124_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_124_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_124_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_124_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__114_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_124_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_124_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_124_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_124_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_124_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_124_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_124_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_124_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__125_ccff_tail ) , 
    .chany_top_out ( sb_1__1__114_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__114_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__114_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__114_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__114_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_102 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_103 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_372 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1527 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1528 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_749 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1529 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_749 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1530 } ) ) ;
sb_1__1_ sb_11__6_ (
    .prog_clk ( { ctsbuf_net_2041122 } ) ,
    .chany_top_in ( cby_1__1__126_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_126_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_126_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_126_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_126_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_126_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_126_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_126_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_126_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__126_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_137_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_137_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_137_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_137_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_137_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_137_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_137_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_137_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__125_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_125_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_125_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_125_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_125_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_125_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_125_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_125_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_125_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__115_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_125_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_125_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_125_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_125_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_125_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_125_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_125_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_125_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__126_ccff_tail ) , 
    .chany_top_out ( sb_1__1__115_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__115_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__115_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__115_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__115_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_104 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_105 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_402 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1531 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1532 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_582 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1533 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_582 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1534 } ) ) ;
sb_1__1_ sb_11__7_ (
    .prog_clk ( { ctsbuf_net_1561074 } ) ,
    .chany_top_in ( cby_1__1__127_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_127_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_127_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_127_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_127_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_127_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_127_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_127_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_127_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__127_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_138_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_138_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_138_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_138_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_138_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_138_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_138_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_138_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__126_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_126_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_126_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_126_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_126_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_126_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_126_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_126_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_126_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__116_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_126_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_126_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_126_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_126_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_126_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_126_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_126_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_126_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__127_ccff_tail ) , 
    .chany_top_out ( sb_1__1__116_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__116_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__116_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__116_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__116_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_106 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_107 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_477 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1535 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1536 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_835 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1537 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_689 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1538 } ) ) ;
sb_1__1_ sb_11__8_ (
    .prog_clk ( { ctsbuf_net_1121030 } ) ,
    .chany_top_in ( cby_1__1__128_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_128_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_128_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_128_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_128_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_128_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_128_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_128_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_128_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__128_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_139_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_139_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_139_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_139_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_139_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_139_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_139_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_139_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__127_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_127_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_127_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_127_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_127_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_127_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_127_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_127_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_127_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__117_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_127_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_127_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_127_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_127_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_127_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_127_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_127_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_127_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__128_ccff_tail ) , 
    .chany_top_out ( sb_1__1__117_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__117_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__117_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__117_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__117_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_108 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_109 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_664 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1539 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1540 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_301 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1541 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_301 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1542 } ) ) ;
sb_1__1_ sb_11__9_ (
    .prog_clk ( { p_abuf6 } ) ,
    .chany_top_in ( cby_1__1__129_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_129_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_129_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_129_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_129_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_129_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_129_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_129_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_129_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__129_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_140_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_140_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_140_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_140_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_140_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_140_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_140_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_140_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__128_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_128_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_128_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_128_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_128_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_128_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_128_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_128_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_128_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__118_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_128_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_128_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_128_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_128_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_128_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_128_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_128_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_128_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__129_ccff_tail ) , 
    .chany_top_out ( sb_1__1__118_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__118_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__118_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__118_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__118_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_110 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_111 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_337 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1543 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1544 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_430 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1545 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_430 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1546 } ) ) ;
sb_1__1_ sb_11__10_ (
    .prog_clk ( { ctsbuf_net_47965 } ) ,
    .chany_top_in ( cby_1__1__130_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_130_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_130_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_130_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_130_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_130_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_130_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_130_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_130_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__130_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_141_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_141_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_141_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_141_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_141_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_141_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_141_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_141_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__129_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_129_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_129_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_129_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_129_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_129_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_129_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_129_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_129_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__119_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_129_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_129_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_129_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_129_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_129_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_129_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_129_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_129_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__130_ccff_tail ) , 
    .chany_top_out ( sb_1__1__119_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__119_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__119_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__119_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__119_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_112 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_113 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_759 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1547 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1548 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_576 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1549 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_576 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1550 } ) ) ;
sb_1__1_ sb_11__11_ (
    .prog_clk ( { ctsbuf_net_26944 } ) ,
    .chany_top_in ( cby_1__1__131_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_131_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_131_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_131_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_131_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_131_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_131_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_131_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_131_right_width_0_height_0__pin_49_lower ) , 
    .chanx_right_in ( cbx_1__1__131_chanx_left_out ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_142_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_142_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_142_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_142_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_142_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_142_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_142_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_142_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__130_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_130_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_130_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_130_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_130_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_130_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_130_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_130_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_130_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__120_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_130_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_130_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_130_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_130_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_130_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_130_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_130_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_130_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( cbx_1__1__131_ccff_tail ) , 
    .chany_top_out ( sb_1__1__120_chany_top_out ) , 
    .chanx_right_out ( sb_1__1__120_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__1__120_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__1__120_chanx_left_out ) , 
    .ccff_tail ( sb_1__1__120_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_114 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_115 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_263 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1551 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1552 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_679 } ) ,
    .grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ( { 
        SYNOPSYS_UNCONNECTED_1553 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_792 } ) ,
    .grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1554 } ) ) ;
sb_1__2_ sb_1__12_ (
    .prog_clk ( { p_abuf0 } ) ,
    .chanx_right_in ( cbx_1__12__1_chanx_left_out ) , 
    .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_23_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_23_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_23_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_23_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_23_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_23_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_23_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_23_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__11_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_11_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_11_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_11_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_11_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_11_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_11_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_11_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_11_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__12__0_chanx_right_out ) , 
    .left_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_11_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_11_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_11_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_11_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_11_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_11_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_11_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_11_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_top_1_ccff_tail ) , 
    .chanx_right_out ( sb_1__12__0_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__12__0_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__12__0_chanx_left_out ) , 
    .ccff_tail ( sb_1__12__0_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1555 ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1556 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1557 ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1558 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_685 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1559 } ) ) ;
sb_1__2_ sb_2__12_ (
    .prog_clk ( { ctsbuf_net_17935 } ) ,
    .chanx_right_in ( cbx_1__12__2_chanx_left_out ) , 
    .right_top_grid_pin_1_ ( grid_io_top_2_bottom_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_35_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_35_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_35_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_35_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_35_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_35_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_35_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_35_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__23_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_23_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_23_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_23_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_23_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_23_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_23_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_23_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_23_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__12__1_chanx_right_out ) , 
    .left_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_23_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_23_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_23_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_23_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_23_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_23_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_23_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_23_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_top_2_ccff_tail ) , 
    .chanx_right_out ( sb_1__12__1_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__12__1_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__12__1_chanx_left_out ) , 
    .ccff_tail ( sb_1__12__1_ccff_tail ) , .SC_IN_TOP ( scff_Wires_52_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1560 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1561 ) , 
    .SC_OUT_BOT ( scff_Wires_53_ ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_405 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1562 } ) ) ;
sb_1__2_ sb_3__12_ (
    .prog_clk ( { ctsbuf_net_34952 } ) ,
    .chanx_right_in ( cbx_1__12__3_chanx_left_out ) , 
    .right_top_grid_pin_1_ ( grid_io_top_3_bottom_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_47_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_47_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_47_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_47_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_47_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_47_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_47_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_47_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__35_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_35_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_35_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_35_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_35_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_35_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_35_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_35_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_35_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__12__2_chanx_right_out ) , 
    .left_top_grid_pin_1_ ( grid_io_top_2_bottom_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_35_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_35_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_35_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_35_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_35_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_35_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_35_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_35_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_top_3_ccff_tail ) , 
    .chanx_right_out ( sb_1__12__2_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__12__2_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__12__2_chanx_left_out ) , 
    .ccff_tail ( sb_1__12__2_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1563 ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1564 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1565 ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1566 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_756 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1567 } ) ) ;
sb_1__2_ sb_4__12_ (
    .prog_clk ( { ctsbuf_net_59977 } ) ,
    .chanx_right_in ( cbx_1__12__4_chanx_left_out ) , 
    .right_top_grid_pin_1_ ( grid_io_top_4_bottom_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_59_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_59_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_59_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_59_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_59_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_59_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_59_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_59_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__47_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_47_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_47_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_47_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_47_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_47_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_47_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_47_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_47_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__12__3_chanx_right_out ) , 
    .left_top_grid_pin_1_ ( grid_io_top_3_bottom_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_47_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_47_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_47_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_47_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_47_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_47_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_47_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_47_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_top_4_ccff_tail ) , 
    .chanx_right_out ( sb_1__12__3_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__12__3_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__12__3_chanx_left_out ) , 
    .ccff_tail ( sb_1__12__3_ccff_tail ) , .SC_IN_TOP ( scff_Wires_105_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1568 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1569 ) , 
    .SC_OUT_BOT ( scff_Wires_106_ ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_24 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_25 ) ) ;
sb_1__2_ sb_5__12_ (
    .prog_clk ( { ctsbuf_net_921010 } ) ,
    .chanx_right_in ( cbx_1__12__5_chanx_left_out ) , 
    .right_top_grid_pin_1_ ( grid_io_top_5_bottom_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_71_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_71_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_71_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_71_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_71_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_71_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_71_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_71_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__59_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_59_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_59_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_59_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_59_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_59_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_59_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_59_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_59_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__12__4_chanx_right_out ) , 
    .left_top_grid_pin_1_ ( grid_io_top_4_bottom_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_59_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_59_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_59_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_59_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_59_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_59_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_59_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_59_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_top_5_ccff_tail ) , 
    .chanx_right_out ( sb_1__12__4_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__12__4_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__12__4_chanx_left_out ) , 
    .ccff_tail ( sb_1__12__4_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1570 ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1571 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1572 ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1573 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_24 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_25 ) ) ;
sb_1__2_ sb_6__12_ (
    .prog_clk ( { ctsbuf_net_1321050 } ) ,
    .chanx_right_in ( cbx_1__12__6_chanx_left_out ) , 
    .right_top_grid_pin_1_ ( grid_io_top_6_bottom_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_83_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_83_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_83_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_83_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_83_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_83_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_83_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_83_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__71_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_71_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_71_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_71_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_71_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_71_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_71_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_71_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_71_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__12__5_chanx_right_out ) , 
    .left_top_grid_pin_1_ ( grid_io_top_5_bottom_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_71_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_71_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_71_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_71_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_71_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_71_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_71_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_71_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_top_6_ccff_tail ) , 
    .chanx_right_out ( sb_1__12__5_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__12__5_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__12__5_chanx_left_out ) , 
    .ccff_tail ( sb_1__12__5_ccff_tail ) , .SC_IN_TOP ( scff_Wires_158_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1574 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1575 ) , 
    .SC_OUT_BOT ( scff_Wires_159_ ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_721 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1576 } ) ) ;
sb_1__2_ sb_7__12_ (
    .prog_clk ( { ctsbuf_net_1221040 } ) ,
    .chanx_right_in ( cbx_1__12__7_chanx_left_out ) , 
    .right_top_grid_pin_1_ ( grid_io_top_7_bottom_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_95_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_95_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_95_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_95_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_95_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_95_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_95_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_95_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__83_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_83_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_83_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_83_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_83_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_83_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_83_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_83_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_83_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__12__6_chanx_right_out ) , 
    .left_top_grid_pin_1_ ( grid_io_top_6_bottom_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_83_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_83_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_83_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_83_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_83_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_83_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_83_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_83_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_top_7_ccff_tail ) , 
    .chanx_right_out ( sb_1__12__6_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__12__6_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__12__6_chanx_left_out ) , 
    .ccff_tail ( sb_1__12__6_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1577 ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1578 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1579 ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1580 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_846 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1581 } ) ) ;
sb_1__2_ sb_8__12_ (
    .prog_clk ( { ctsbuf_net_831001 } ) ,
    .chanx_right_in ( cbx_1__12__8_chanx_left_out ) , 
    .right_top_grid_pin_1_ ( grid_io_top_8_bottom_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_107_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_107_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_107_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_107_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_107_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_107_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_107_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_107_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__95_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_95_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_95_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_95_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_95_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_95_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_95_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_95_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_95_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__12__7_chanx_right_out ) , 
    .left_top_grid_pin_1_ ( grid_io_top_7_bottom_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_95_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_95_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_95_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_95_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_95_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_95_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_95_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_95_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_top_8_ccff_tail ) , 
    .chanx_right_out ( sb_1__12__7_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__12__7_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__12__7_chanx_left_out ) , 
    .ccff_tail ( sb_1__12__7_ccff_tail ) , .SC_IN_TOP ( scff_Wires_211_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1582 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1583 ) , 
    .SC_OUT_BOT ( scff_Wires_212_ ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_752 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1584 } ) ) ;
sb_1__2_ sb_9__12_ (
    .prog_clk ( { ctsbuf_net_51969 } ) ,
    .chanx_right_in ( cbx_1__12__9_chanx_left_out ) , 
    .right_top_grid_pin_1_ ( grid_io_top_9_bottom_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_119_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_119_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_119_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_119_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_119_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_119_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_119_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_119_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__107_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_107_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_107_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_107_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_107_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_107_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_107_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_107_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_107_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__12__8_chanx_right_out ) , 
    .left_top_grid_pin_1_ ( grid_io_top_8_bottom_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_107_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_107_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_107_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_107_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_107_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_107_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_107_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_107_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_top_9_ccff_tail ) , 
    .chanx_right_out ( sb_1__12__8_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__12__8_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__12__8_chanx_left_out ) , 
    .ccff_tail ( sb_1__12__8_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1585 ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1586 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1587 ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1588 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_24 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_25 ) ) ;
sb_1__2_ sb_10__12_ (
    .prog_clk ( { ctsbuf_net_27945 } ) ,
    .chanx_right_in ( cbx_1__12__10_chanx_left_out ) , 
    .right_top_grid_pin_1_ ( grid_io_top_10_bottom_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_131_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_131_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_131_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_131_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_131_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_131_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_131_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_131_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__119_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_119_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_119_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_119_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_119_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_119_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_119_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_119_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_119_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__12__9_chanx_right_out ) , 
    .left_top_grid_pin_1_ ( grid_io_top_9_bottom_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_119_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_119_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_119_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_119_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_119_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_119_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_119_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_119_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_top_10_ccff_tail ) , 
    .chanx_right_out ( sb_1__12__9_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__12__9_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__12__9_chanx_left_out ) , 
    .ccff_tail ( sb_1__12__9_ccff_tail ) , .SC_IN_TOP ( scff_Wires_264_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1589 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1590 ) , 
    .SC_OUT_BOT ( scff_Wires_265_ ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_811 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1591 } ) ) ;
sb_1__2_ sb_11__12_ (
    .prog_clk ( { ctsbuf_net_14932 } ) ,
    .chanx_right_in ( cbx_1__12__11_chanx_left_out ) , 
    .right_top_grid_pin_1_ ( grid_io_top_11_bottom_width_0_height_0__pin_1_upper ) , 
    .right_bottom_grid_pin_34_ ( grid_clb_143_top_width_0_height_0__pin_34_upper ) , 
    .right_bottom_grid_pin_35_ ( grid_clb_143_top_width_0_height_0__pin_35_upper ) , 
    .right_bottom_grid_pin_36_ ( grid_clb_143_top_width_0_height_0__pin_36_upper ) , 
    .right_bottom_grid_pin_37_ ( grid_clb_143_top_width_0_height_0__pin_37_upper ) , 
    .right_bottom_grid_pin_38_ ( grid_clb_143_top_width_0_height_0__pin_38_upper ) , 
    .right_bottom_grid_pin_39_ ( grid_clb_143_top_width_0_height_0__pin_39_upper ) , 
    .right_bottom_grid_pin_40_ ( grid_clb_143_top_width_0_height_0__pin_40_upper ) , 
    .right_bottom_grid_pin_41_ ( grid_clb_143_top_width_0_height_0__pin_41_upper ) , 
    .chany_bottom_in ( cby_1__1__131_chany_top_out ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_131_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_131_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_131_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_131_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_131_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_131_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_131_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_131_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__12__10_chanx_right_out ) , 
    .left_top_grid_pin_1_ ( grid_io_top_10_bottom_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_131_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_131_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_131_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_131_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_131_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_131_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_131_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_131_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_top_11_ccff_tail ) , 
    .chanx_right_out ( sb_1__12__10_chanx_right_out ) , 
    .chany_bottom_out ( sb_1__12__10_chany_bottom_out ) , 
    .chanx_left_out ( sb_1__12__10_chanx_left_out ) , 
    .ccff_tail ( sb_1__12__10_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1592 ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1593 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1594 ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1595 ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_538 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1596 } ) ) ;
sb_2__0_ sb_12__0_ (
    .prog_clk ( { ctsbuf_net_4191337 } ) ,
    .chany_top_in ( cby_12__1__0_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_132_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_132_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_132_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_132_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_132_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_132_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_132_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_132_right_width_0_height_0__pin_49_lower ) , 
    .top_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , 
    .chanx_left_in ( cbx_1__0__11_chanx_right_out ) , 
    .left_bottom_grid_pin_1_ ( grid_io_bottom_11_top_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_3_ ( grid_io_bottom_11_top_width_0_height_0__pin_3_lower ) , 
    .left_bottom_grid_pin_5_ ( grid_io_bottom_11_top_width_0_height_0__pin_5_lower ) , 
    .left_bottom_grid_pin_7_ ( grid_io_bottom_11_top_width_0_height_0__pin_7_lower ) , 
    .left_bottom_grid_pin_9_ ( grid_io_bottom_11_top_width_0_height_0__pin_9_lower ) , 
    .left_bottom_grid_pin_11_ ( grid_io_bottom_11_top_width_0_height_0__pin_11_lower ) , 
    .ccff_head ( grid_io_right_0_ccff_tail ) , 
    .chany_top_out ( sb_12__0__0_chany_top_out ) , 
    .chanx_left_out ( sb_12__0__0_chanx_left_out ) , 
    .ccff_tail ( sb_12__0__0_ccff_tail ) ) ;
sb_2__1_ sb_12__1_ (
    .prog_clk ( { ctsbuf_net_3711289 } ) ,
    .chany_top_in ( cby_12__1__1_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_133_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_133_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_133_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_133_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_133_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_133_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_133_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_133_right_width_0_height_0__pin_49_lower ) , 
    .top_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , 
    .chany_bottom_in ( cby_12__1__0_chany_top_out ) , 
    .bottom_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_132_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_132_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_132_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_132_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_132_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_132_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_132_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_132_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__121_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_132_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_132_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_132_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_132_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_132_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_132_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_132_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_132_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_right_1_ccff_tail ) , 
    .chany_top_out ( sb_12__1__0_chany_top_out ) , 
    .chany_bottom_out ( sb_12__1__0_chany_bottom_out ) , 
    .chanx_left_out ( sb_12__1__0_chanx_left_out ) , 
    .ccff_tail ( sb_12__1__0_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_117 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_118 ) ) ;
sb_2__1_ sb_12__2_ (
    .prog_clk ( { ctsbuf_net_3231241 } ) ,
    .chany_top_in ( cby_12__1__2_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_134_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_134_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_134_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_134_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_134_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_134_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_134_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_134_right_width_0_height_0__pin_49_lower ) , 
    .top_right_grid_pin_1_ ( grid_io_right_2_left_width_0_height_0__pin_1_lower ) , 
    .chany_bottom_in ( cby_12__1__1_chany_top_out ) , 
    .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_133_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_133_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_133_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_133_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_133_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_133_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_133_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_133_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__122_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_133_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_133_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_133_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_133_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_133_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_133_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_133_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_133_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_right_2_ccff_tail ) , 
    .chany_top_out ( sb_12__1__1_chany_top_out ) , 
    .chany_bottom_out ( sb_12__1__1_chany_bottom_out ) , 
    .chanx_left_out ( sb_12__1__1_chanx_left_out ) , 
    .ccff_tail ( sb_12__1__1_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_119 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_120 ) ) ;
sb_2__1_ sb_12__3_ (
    .prog_clk ( { ctsbuf_net_2751193 } ) ,
    .chany_top_in ( cby_12__1__3_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_135_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_135_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_135_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_135_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_135_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_135_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_135_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_135_right_width_0_height_0__pin_49_lower ) , 
    .top_right_grid_pin_1_ ( grid_io_right_3_left_width_0_height_0__pin_1_lower ) , 
    .chany_bottom_in ( cby_12__1__2_chany_top_out ) , 
    .bottom_right_grid_pin_1_ ( grid_io_right_2_left_width_0_height_0__pin_1_upper ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_134_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_134_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_134_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_134_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_134_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_134_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_134_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_134_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__123_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_134_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_134_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_134_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_134_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_134_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_134_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_134_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_134_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_right_3_ccff_tail ) , 
    .chany_top_out ( sb_12__1__2_chany_top_out ) , 
    .chany_bottom_out ( sb_12__1__2_chany_bottom_out ) , 
    .chanx_left_out ( sb_12__1__2_chanx_left_out ) , 
    .ccff_tail ( sb_12__1__2_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_121 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_122 ) ) ;
sb_2__1_ sb_12__4_ (
    .prog_clk ( { ctsbuf_net_2271145 } ) ,
    .chany_top_in ( cby_12__1__4_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_136_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_136_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_136_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_136_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_136_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_136_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_136_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_136_right_width_0_height_0__pin_49_lower ) , 
    .top_right_grid_pin_1_ ( grid_io_right_4_left_width_0_height_0__pin_1_lower ) , 
    .chany_bottom_in ( cby_12__1__3_chany_top_out ) , 
    .bottom_right_grid_pin_1_ ( grid_io_right_3_left_width_0_height_0__pin_1_upper ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_135_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_135_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_135_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_135_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_135_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_135_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_135_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_135_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__124_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_135_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_135_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_135_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_135_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_135_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_135_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_135_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_135_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_right_4_ccff_tail ) , 
    .chany_top_out ( sb_12__1__3_chany_top_out ) , 
    .chany_bottom_out ( sb_12__1__3_chany_bottom_out ) , 
    .chanx_left_out ( sb_12__1__3_chanx_left_out ) , 
    .ccff_tail ( sb_12__1__3_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_123 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_124 ) ) ;
sb_2__1_ sb_12__5_ (
    .prog_clk ( { ctsbuf_net_1791097 } ) ,
    .chany_top_in ( cby_12__1__5_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_137_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_137_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_137_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_137_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_137_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_137_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_137_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_137_right_width_0_height_0__pin_49_lower ) , 
    .top_right_grid_pin_1_ ( grid_io_right_5_left_width_0_height_0__pin_1_lower ) , 
    .chany_bottom_in ( cby_12__1__4_chany_top_out ) , 
    .bottom_right_grid_pin_1_ ( grid_io_right_4_left_width_0_height_0__pin_1_upper ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_136_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_136_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_136_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_136_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_136_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_136_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_136_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_136_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__125_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_136_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_136_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_136_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_136_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_136_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_136_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_136_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_136_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_right_5_ccff_tail ) , 
    .chany_top_out ( sb_12__1__4_chany_top_out ) , 
    .chany_bottom_out ( sb_12__1__4_chany_bottom_out ) , 
    .chanx_left_out ( sb_12__1__4_chanx_left_out ) , 
    .ccff_tail ( sb_12__1__4_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_125 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_126 ) ) ;
sb_2__1_ sb_12__6_ (
    .prog_clk ( { ctsbuf_net_1331051 } ) ,
    .chany_top_in ( cby_12__1__6_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_138_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_138_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_138_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_138_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_138_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_138_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_138_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_138_right_width_0_height_0__pin_49_lower ) , 
    .top_right_grid_pin_1_ ( grid_io_right_6_left_width_0_height_0__pin_1_lower ) , 
    .chany_bottom_in ( cby_12__1__5_chany_top_out ) , 
    .bottom_right_grid_pin_1_ ( grid_io_right_5_left_width_0_height_0__pin_1_upper ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_137_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_137_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_137_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_137_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_137_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_137_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_137_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_137_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__126_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_137_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_137_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_137_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_137_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_137_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_137_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_137_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_137_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_right_6_ccff_tail ) , 
    .chany_top_out ( sb_12__1__5_chany_top_out ) , 
    .chany_bottom_out ( sb_12__1__5_chany_bottom_out ) , 
    .chanx_left_out ( sb_12__1__5_chanx_left_out ) , 
    .ccff_tail ( sb_12__1__5_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_127 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_128 ) ) ;
sb_2__1_ sb_12__7_ (
    .prog_clk ( { ctsbuf_net_931011 } ) ,
    .chany_top_in ( cby_12__1__7_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_139_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_139_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_139_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_139_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_139_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_139_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_139_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_139_right_width_0_height_0__pin_49_lower ) , 
    .top_right_grid_pin_1_ ( grid_io_right_7_left_width_0_height_0__pin_1_lower ) , 
    .chany_bottom_in ( cby_12__1__6_chany_top_out ) , 
    .bottom_right_grid_pin_1_ ( grid_io_right_6_left_width_0_height_0__pin_1_upper ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_138_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_138_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_138_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_138_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_138_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_138_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_138_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_138_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__127_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_138_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_138_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_138_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_138_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_138_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_138_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_138_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_138_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_right_7_ccff_tail ) , 
    .chany_top_out ( sb_12__1__6_chany_top_out ) , 
    .chany_bottom_out ( sb_12__1__6_chany_bottom_out ) , 
    .chanx_left_out ( sb_12__1__6_chanx_left_out ) , 
    .ccff_tail ( sb_12__1__6_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_129 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_130 ) ) ;
sb_2__1_ sb_12__8_ (
    .prog_clk ( { ctsbuf_net_75993 } ) ,
    .chany_top_in ( cby_12__1__8_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_140_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_140_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_140_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_140_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_140_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_140_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_140_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_140_right_width_0_height_0__pin_49_lower ) , 
    .top_right_grid_pin_1_ ( grid_io_right_8_left_width_0_height_0__pin_1_lower ) , 
    .chany_bottom_in ( cby_12__1__7_chany_top_out ) , 
    .bottom_right_grid_pin_1_ ( grid_io_right_7_left_width_0_height_0__pin_1_upper ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_139_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_139_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_139_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_139_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_139_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_139_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_139_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_139_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__128_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_139_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_139_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_139_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_139_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_139_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_139_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_139_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_139_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_right_8_ccff_tail ) , 
    .chany_top_out ( sb_12__1__7_chany_top_out ) , 
    .chany_bottom_out ( sb_12__1__7_chany_bottom_out ) , 
    .chanx_left_out ( sb_12__1__7_chanx_left_out ) , 
    .ccff_tail ( sb_12__1__7_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_131 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_132 ) ) ;
sb_2__1_ sb_12__9_ (
    .prog_clk ( { ctsbuf_net_46964 } ) ,
    .chany_top_in ( cby_12__1__9_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_141_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_141_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_141_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_141_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_141_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_141_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_141_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_141_right_width_0_height_0__pin_49_lower ) , 
    .top_right_grid_pin_1_ ( grid_io_right_9_left_width_0_height_0__pin_1_lower ) , 
    .chany_bottom_in ( cby_12__1__8_chany_top_out ) , 
    .bottom_right_grid_pin_1_ ( grid_io_right_8_left_width_0_height_0__pin_1_upper ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_140_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_140_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_140_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_140_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_140_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_140_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_140_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_140_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__129_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_140_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_140_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_140_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_140_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_140_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_140_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_140_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_140_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_right_9_ccff_tail ) , 
    .chany_top_out ( sb_12__1__8_chany_top_out ) , 
    .chany_bottom_out ( sb_12__1__8_chany_bottom_out ) , 
    .chanx_left_out ( sb_12__1__8_chanx_left_out ) , 
    .ccff_tail ( sb_12__1__8_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_133 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_134 ) ) ;
sb_2__1_ sb_12__10_ (
    .prog_clk ( { ctsbuf_net_25943 } ) ,
    .chany_top_in ( cby_12__1__10_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_142_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_142_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_142_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_142_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_142_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_142_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_142_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_142_right_width_0_height_0__pin_49_lower ) , 
    .top_right_grid_pin_1_ ( grid_io_right_10_left_width_0_height_0__pin_1_lower ) , 
    .chany_bottom_in ( cby_12__1__9_chany_top_out ) , 
    .bottom_right_grid_pin_1_ ( grid_io_right_9_left_width_0_height_0__pin_1_upper ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_141_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_141_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_141_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_141_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_141_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_141_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_141_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_141_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__130_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_141_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_141_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_141_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_141_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_141_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_141_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_141_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_141_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_right_10_ccff_tail ) , 
    .chany_top_out ( sb_12__1__9_chany_top_out ) , 
    .chany_bottom_out ( sb_12__1__9_chany_bottom_out ) , 
    .chanx_left_out ( sb_12__1__9_chanx_left_out ) , 
    .ccff_tail ( sb_12__1__9_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_135 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_136 ) ) ;
sb_2__1_ sb_12__11_ (
    .prog_clk ( { ctsbuf_net_29947 } ) ,
    .chany_top_in ( cby_12__1__11_chany_bottom_out ) , 
    .top_left_grid_pin_42_ ( grid_clb_143_right_width_0_height_0__pin_42_lower ) , 
    .top_left_grid_pin_43_ ( grid_clb_143_right_width_0_height_0__pin_43_lower ) , 
    .top_left_grid_pin_44_ ( grid_clb_143_right_width_0_height_0__pin_44_lower ) , 
    .top_left_grid_pin_45_ ( grid_clb_143_right_width_0_height_0__pin_45_lower ) , 
    .top_left_grid_pin_46_ ( grid_clb_143_right_width_0_height_0__pin_46_lower ) , 
    .top_left_grid_pin_47_ ( grid_clb_143_right_width_0_height_0__pin_47_lower ) , 
    .top_left_grid_pin_48_ ( grid_clb_143_right_width_0_height_0__pin_48_lower ) , 
    .top_left_grid_pin_49_ ( grid_clb_143_right_width_0_height_0__pin_49_lower ) , 
    .top_right_grid_pin_1_ ( grid_io_right_11_left_width_0_height_0__pin_1_lower ) , 
    .chany_bottom_in ( cby_12__1__10_chany_top_out ) , 
    .bottom_right_grid_pin_1_ ( grid_io_right_10_left_width_0_height_0__pin_1_upper ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_142_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_142_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_142_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_142_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_142_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_142_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_142_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_142_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__1__131_chanx_right_out ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_142_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_142_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_142_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_142_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_142_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_142_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_142_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_142_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( grid_io_right_11_ccff_tail ) , 
    .chany_top_out ( sb_12__1__10_chany_top_out ) , 
    .chany_bottom_out ( sb_12__1__10_chany_bottom_out ) , 
    .chanx_left_out ( sb_12__1__10_chanx_left_out ) , 
    .ccff_tail ( sb_12__1__10_ccff_tail ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_137 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_138 ) ) ;
sb_2__2_ sb_12__12_ (
    .prog_clk ( { ctsbuf_net_7925 } ) ,
    .chany_bottom_in ( cby_12__1__11_chany_top_out ) , 
    .bottom_right_grid_pin_1_ ( grid_io_right_11_left_width_0_height_0__pin_1_upper ) , 
    .bottom_left_grid_pin_42_ ( grid_clb_143_right_width_0_height_0__pin_42_upper ) , 
    .bottom_left_grid_pin_43_ ( grid_clb_143_right_width_0_height_0__pin_43_upper ) , 
    .bottom_left_grid_pin_44_ ( grid_clb_143_right_width_0_height_0__pin_44_upper ) , 
    .bottom_left_grid_pin_45_ ( grid_clb_143_right_width_0_height_0__pin_45_upper ) , 
    .bottom_left_grid_pin_46_ ( grid_clb_143_right_width_0_height_0__pin_46_upper ) , 
    .bottom_left_grid_pin_47_ ( grid_clb_143_right_width_0_height_0__pin_47_upper ) , 
    .bottom_left_grid_pin_48_ ( grid_clb_143_right_width_0_height_0__pin_48_upper ) , 
    .bottom_left_grid_pin_49_ ( grid_clb_143_right_width_0_height_0__pin_49_upper ) , 
    .chanx_left_in ( cbx_1__12__11_chanx_right_out ) , 
    .left_top_grid_pin_1_ ( grid_io_top_11_bottom_width_0_height_0__pin_1_lower ) , 
    .left_bottom_grid_pin_34_ ( grid_clb_143_top_width_0_height_0__pin_34_lower ) , 
    .left_bottom_grid_pin_35_ ( grid_clb_143_top_width_0_height_0__pin_35_lower ) , 
    .left_bottom_grid_pin_36_ ( grid_clb_143_top_width_0_height_0__pin_36_lower ) , 
    .left_bottom_grid_pin_37_ ( grid_clb_143_top_width_0_height_0__pin_37_lower ) , 
    .left_bottom_grid_pin_38_ ( grid_clb_143_top_width_0_height_0__pin_38_lower ) , 
    .left_bottom_grid_pin_39_ ( grid_clb_143_top_width_0_height_0__pin_39_lower ) , 
    .left_bottom_grid_pin_40_ ( grid_clb_143_top_width_0_height_0__pin_40_lower ) , 
    .left_bottom_grid_pin_41_ ( grid_clb_143_top_width_0_height_0__pin_41_lower ) , 
    .ccff_head ( ccff_head ) , 
    .chany_bottom_out ( sb_12__12__0_chany_bottom_out ) , 
    .chanx_left_out ( sb_12__12__0_chanx_left_out ) , 
    .ccff_tail ( sb_12__12__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_317_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1597 ) , .SC_OUT_TOP ( sc_tail ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1598 ) ,
    .grid_clb_120_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        BUF_net_145 } ) ,
    
    .grid_clb_120_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_120_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ) ;
cbx_1__0_ cbx_1__0_ (
    .prog_clk ( { ctsbuf_net_4441362 } ) ,
    .chanx_left_in ( sb_0__0__0_chanx_right_out ) , 
    .chanx_right_in ( sb_1__0__0_chanx_left_out ) , 
    .ccff_head ( sb_1__0__0_ccff_tail ) , 
    .chanx_left_out ( cbx_1__0__0_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__0__0_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , 
    .ccff_tail ( grid_io_bottom_0_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[24:29] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[24:29] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[24:29] ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_1_upper ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , 
    .top_width_0_height_0__pin_1_lower ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , 
    .top_width_0_height_0__pin_3_upper ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , 
    .top_width_0_height_0__pin_3_lower ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , 
    .top_width_0_height_0__pin_5_upper ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , 
    .top_width_0_height_0__pin_5_lower ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , 
    .top_width_0_height_0__pin_7_upper ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , 
    .top_width_0_height_0__pin_7_lower ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , 
    .top_width_0_height_0__pin_9_upper ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , 
    .top_width_0_height_0__pin_9_lower ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , 
    .top_width_0_height_0__pin_11_upper ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , 
    .top_width_0_height_0__pin_11_lower ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , 
    .SC_IN_TOP ( scff_Wires_25_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1599 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1600 ) , 
    .SC_OUT_BOT ( scff_Wires_26_ ) ,
    .Test_en__FEEDTHRU_0 ( { optlc_net_487 } ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1601 } ) ) ;
cbx_1__0_ cbx_2__0_ (
    .prog_clk ( { ctsbuf_net_4791397 } ) ,
    .chanx_left_in ( sb_1__0__0_chanx_right_out ) , 
    .chanx_right_in ( sb_1__0__1_chanx_left_out ) , 
    .ccff_head ( sb_1__0__1_ccff_tail ) , 
    .chanx_left_out ( cbx_1__0__1_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__0__1_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , 
    .ccff_tail ( grid_io_bottom_1_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[30:35] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[30:35] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[30:35] ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_1_upper ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , 
    .top_width_0_height_0__pin_1_lower ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , 
    .top_width_0_height_0__pin_3_upper ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , 
    .top_width_0_height_0__pin_3_lower ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , 
    .top_width_0_height_0__pin_5_upper ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , 
    .top_width_0_height_0__pin_5_lower ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , 
    .top_width_0_height_0__pin_7_upper ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , 
    .top_width_0_height_0__pin_7_lower ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , 
    .top_width_0_height_0__pin_9_upper ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , 
    .top_width_0_height_0__pin_9_lower ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , 
    .top_width_0_height_0__pin_11_upper ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , 
    .top_width_0_height_0__pin_11_lower ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , 
    .SC_IN_TOP ( scff_Wires__FEEDTHRU_1[27] ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1602 ) , 
    .SC_OUT_TOP ( scff_Wires_28_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1603 ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_147 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_148 ) ) ;
cbx_1__0_ cbx_3__0_ (
    .prog_clk ( { ctsbuf_net_5161434 } ) ,
    .chanx_left_in ( sb_1__0__1_chanx_right_out ) , 
    .chanx_right_in ( sb_1__0__2_chanx_left_out ) , 
    .ccff_head ( sb_1__0__2_ccff_tail ) , 
    .chanx_left_out ( cbx_1__0__2_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__0__2_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__0__2_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__0__2_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__0__2_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__0__2_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__0__2_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__0__2_bottom_grid_pin_10_ ) , 
    .ccff_tail ( grid_io_bottom_2_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[36:41] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[36:41] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[36:41] ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__0__2_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__0__2_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__0__2_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__0__2_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__0__2_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__0__2_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_1_upper ( grid_io_bottom_2_top_width_0_height_0__pin_1_upper ) , 
    .top_width_0_height_0__pin_1_lower ( grid_io_bottom_2_top_width_0_height_0__pin_1_lower ) , 
    .top_width_0_height_0__pin_3_upper ( grid_io_bottom_2_top_width_0_height_0__pin_3_upper ) , 
    .top_width_0_height_0__pin_3_lower ( grid_io_bottom_2_top_width_0_height_0__pin_3_lower ) , 
    .top_width_0_height_0__pin_5_upper ( grid_io_bottom_2_top_width_0_height_0__pin_5_upper ) , 
    .top_width_0_height_0__pin_5_lower ( grid_io_bottom_2_top_width_0_height_0__pin_5_lower ) , 
    .top_width_0_height_0__pin_7_upper ( grid_io_bottom_2_top_width_0_height_0__pin_7_upper ) , 
    .top_width_0_height_0__pin_7_lower ( grid_io_bottom_2_top_width_0_height_0__pin_7_lower ) , 
    .top_width_0_height_0__pin_9_upper ( grid_io_bottom_2_top_width_0_height_0__pin_9_upper ) , 
    .top_width_0_height_0__pin_9_lower ( grid_io_bottom_2_top_width_0_height_0__pin_9_lower ) , 
    .top_width_0_height_0__pin_11_upper ( grid_io_bottom_2_top_width_0_height_0__pin_11_upper ) , 
    .top_width_0_height_0__pin_11_lower ( grid_io_bottom_2_top_width_0_height_0__pin_11_lower ) , 
    .SC_IN_TOP ( scff_Wires_78_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1604 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1605 ) , 
    .SC_OUT_BOT ( scff_Wires_79_ ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_145 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_146 ) ) ;
cbx_1__0_ cbx_4__0_ (
    .prog_clk ( { p_abuf44 } ) ,
    .chanx_left_in ( sb_1__0__2_chanx_right_out ) , 
    .chanx_right_in ( sb_1__0__3_chanx_left_out ) , 
    .ccff_head ( sb_1__0__3_ccff_tail ) , 
    .chanx_left_out ( cbx_1__0__3_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__0__3_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__0__3_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__0__3_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__0__3_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__0__3_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__0__3_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__0__3_bottom_grid_pin_10_ ) , 
    .ccff_tail ( grid_io_bottom_3_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[42:47] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[42:47] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[42:47] ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__0__3_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__0__3_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__0__3_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__0__3_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__0__3_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__0__3_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_1_upper ( grid_io_bottom_3_top_width_0_height_0__pin_1_upper ) , 
    .top_width_0_height_0__pin_1_lower ( grid_io_bottom_3_top_width_0_height_0__pin_1_lower ) , 
    .top_width_0_height_0__pin_3_upper ( grid_io_bottom_3_top_width_0_height_0__pin_3_upper ) , 
    .top_width_0_height_0__pin_3_lower ( grid_io_bottom_3_top_width_0_height_0__pin_3_lower ) , 
    .top_width_0_height_0__pin_5_upper ( grid_io_bottom_3_top_width_0_height_0__pin_5_upper ) , 
    .top_width_0_height_0__pin_5_lower ( grid_io_bottom_3_top_width_0_height_0__pin_5_lower ) , 
    .top_width_0_height_0__pin_7_upper ( grid_io_bottom_3_top_width_0_height_0__pin_7_upper ) , 
    .top_width_0_height_0__pin_7_lower ( grid_io_bottom_3_top_width_0_height_0__pin_7_lower ) , 
    .top_width_0_height_0__pin_9_upper ( grid_io_bottom_3_top_width_0_height_0__pin_9_upper ) , 
    .top_width_0_height_0__pin_9_lower ( grid_io_bottom_3_top_width_0_height_0__pin_9_lower ) , 
    .top_width_0_height_0__pin_11_upper ( grid_io_bottom_3_top_width_0_height_0__pin_11_upper ) , 
    .top_width_0_height_0__pin_11_lower ( grid_io_bottom_3_top_width_0_height_0__pin_11_lower ) , 
    .SC_IN_TOP ( scff_Wires__FEEDTHRU_1_80_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1606 ) , 
    .SC_OUT_TOP ( scff_Wires_81_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1607 ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_143 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_144 ) ) ;
cbx_1__0_ cbx_5__0_ (
    .prog_clk ( { p_abuf46 } ) ,
    .chanx_left_in ( sb_1__0__3_chanx_right_out ) , 
    .chanx_right_in ( sb_1__0__4_chanx_left_out ) , 
    .ccff_head ( sb_1__0__4_ccff_tail ) , 
    .chanx_left_out ( cbx_1__0__4_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__0__4_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__0__4_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__0__4_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__0__4_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__0__4_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__0__4_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__0__4_bottom_grid_pin_10_ ) , 
    .ccff_tail ( grid_io_bottom_4_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[48:53] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[48:53] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[48:53] ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__0__4_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__0__4_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__0__4_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__0__4_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__0__4_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__0__4_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_1_upper ( grid_io_bottom_4_top_width_0_height_0__pin_1_upper ) , 
    .top_width_0_height_0__pin_1_lower ( grid_io_bottom_4_top_width_0_height_0__pin_1_lower ) , 
    .top_width_0_height_0__pin_3_upper ( grid_io_bottom_4_top_width_0_height_0__pin_3_upper ) , 
    .top_width_0_height_0__pin_3_lower ( grid_io_bottom_4_top_width_0_height_0__pin_3_lower ) , 
    .top_width_0_height_0__pin_5_upper ( grid_io_bottom_4_top_width_0_height_0__pin_5_upper ) , 
    .top_width_0_height_0__pin_5_lower ( grid_io_bottom_4_top_width_0_height_0__pin_5_lower ) , 
    .top_width_0_height_0__pin_7_upper ( grid_io_bottom_4_top_width_0_height_0__pin_7_upper ) , 
    .top_width_0_height_0__pin_7_lower ( grid_io_bottom_4_top_width_0_height_0__pin_7_lower ) , 
    .top_width_0_height_0__pin_9_upper ( grid_io_bottom_4_top_width_0_height_0__pin_9_upper ) , 
    .top_width_0_height_0__pin_9_lower ( grid_io_bottom_4_top_width_0_height_0__pin_9_lower ) , 
    .top_width_0_height_0__pin_11_upper ( grid_io_bottom_4_top_width_0_height_0__pin_11_upper ) , 
    .top_width_0_height_0__pin_11_lower ( grid_io_bottom_4_top_width_0_height_0__pin_11_lower ) , 
    .SC_IN_TOP ( scff_Wires_131_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1608 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1609 ) , 
    .SC_OUT_BOT ( scff_Wires_132_ ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_141 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_142 ) ) ;
cbx_1__0_ cbx_6__0_ (
    .prog_clk ( { ctsbuf_net_5791497 } ) ,
    .chanx_left_in ( sb_1__0__4_chanx_right_out ) , 
    .chanx_right_in ( sb_1__0__5_chanx_left_out ) , 
    .ccff_head ( sb_1__0__5_ccff_tail ) , 
    .chanx_left_out ( cbx_1__0__5_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__0__5_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__0__5_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__0__5_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__0__5_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__0__5_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__0__5_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__0__5_bottom_grid_pin_10_ ) , 
    .ccff_tail ( grid_io_bottom_5_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[54:59] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[54:59] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[54:59] ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__0__5_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__0__5_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__0__5_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__0__5_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__0__5_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__0__5_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_1_upper ( grid_io_bottom_5_top_width_0_height_0__pin_1_upper ) , 
    .top_width_0_height_0__pin_1_lower ( grid_io_bottom_5_top_width_0_height_0__pin_1_lower ) , 
    .top_width_0_height_0__pin_3_upper ( grid_io_bottom_5_top_width_0_height_0__pin_3_upper ) , 
    .top_width_0_height_0__pin_3_lower ( grid_io_bottom_5_top_width_0_height_0__pin_3_lower ) , 
    .top_width_0_height_0__pin_5_upper ( grid_io_bottom_5_top_width_0_height_0__pin_5_upper ) , 
    .top_width_0_height_0__pin_5_lower ( grid_io_bottom_5_top_width_0_height_0__pin_5_lower ) , 
    .top_width_0_height_0__pin_7_upper ( grid_io_bottom_5_top_width_0_height_0__pin_7_upper ) , 
    .top_width_0_height_0__pin_7_lower ( grid_io_bottom_5_top_width_0_height_0__pin_7_lower ) , 
    .top_width_0_height_0__pin_9_upper ( grid_io_bottom_5_top_width_0_height_0__pin_9_upper ) , 
    .top_width_0_height_0__pin_9_lower ( grid_io_bottom_5_top_width_0_height_0__pin_9_lower ) , 
    .top_width_0_height_0__pin_11_upper ( grid_io_bottom_5_top_width_0_height_0__pin_11_upper ) , 
    .top_width_0_height_0__pin_11_lower ( grid_io_bottom_5_top_width_0_height_0__pin_11_lower ) , 
    .SC_IN_TOP ( scff_Wires__FEEDTHRU_1_133_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1610 ) , 
    .SC_OUT_TOP ( scff_Wires_134_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1611 ) , 
    .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_139 ) , 
    .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_140 ) ) ;
cbx_1__0_ cbx_7__0_ (
    .prog_clk ( { ctsbuf_net_5761494 } ) ,
    .chanx_left_in ( sb_1__0__5_chanx_right_out ) , 
    .chanx_right_in ( sb_1__0__6_chanx_left_out ) , 
    .ccff_head ( sb_1__0__6_ccff_tail ) , 
    .chanx_left_out ( cbx_1__0__6_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__0__6_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__0__6_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__0__6_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__0__6_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__0__6_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__0__6_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__0__6_bottom_grid_pin_10_ ) , 
    .ccff_tail ( grid_io_bottom_6_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[60:65] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[60:65] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[60:65] ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__0__6_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__0__6_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__0__6_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__0__6_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__0__6_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__0__6_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_1_upper ( grid_io_bottom_6_top_width_0_height_0__pin_1_upper ) , 
    .top_width_0_height_0__pin_1_lower ( grid_io_bottom_6_top_width_0_height_0__pin_1_lower ) , 
    .top_width_0_height_0__pin_3_upper ( grid_io_bottom_6_top_width_0_height_0__pin_3_upper ) , 
    .top_width_0_height_0__pin_3_lower ( grid_io_bottom_6_top_width_0_height_0__pin_3_lower ) , 
    .top_width_0_height_0__pin_5_upper ( grid_io_bottom_6_top_width_0_height_0__pin_5_upper ) , 
    .top_width_0_height_0__pin_5_lower ( grid_io_bottom_6_top_width_0_height_0__pin_5_lower ) , 
    .top_width_0_height_0__pin_7_upper ( grid_io_bottom_6_top_width_0_height_0__pin_7_upper ) , 
    .top_width_0_height_0__pin_7_lower ( grid_io_bottom_6_top_width_0_height_0__pin_7_lower ) , 
    .top_width_0_height_0__pin_9_upper ( grid_io_bottom_6_top_width_0_height_0__pin_9_upper ) , 
    .top_width_0_height_0__pin_9_lower ( grid_io_bottom_6_top_width_0_height_0__pin_9_lower ) , 
    .top_width_0_height_0__pin_11_upper ( grid_io_bottom_6_top_width_0_height_0__pin_11_upper ) , 
    .top_width_0_height_0__pin_11_lower ( grid_io_bottom_6_top_width_0_height_0__pin_11_lower ) , 
    .SC_IN_TOP ( scff_Wires_184_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1612 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1613 ) , 
    .SC_OUT_BOT ( scff_Wires_185_ ) ,
    .Test_en__FEEDTHRU_0 ( { optlc_net_673 } ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1614 } ) ) ;
cbx_1__0_ cbx_8__0_ (
    .prog_clk ( { ctsbuf_net_5621480 } ) ,
    .chanx_left_in ( sb_1__0__6_chanx_right_out ) , 
    .chanx_right_in ( sb_1__0__7_chanx_left_out ) , 
    .ccff_head ( sb_1__0__7_ccff_tail ) , 
    .chanx_left_out ( cbx_1__0__7_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__0__7_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__0__7_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__0__7_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__0__7_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__0__7_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__0__7_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__0__7_bottom_grid_pin_10_ ) , 
    .ccff_tail ( grid_io_bottom_7_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[66:71] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[66:71] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[66:71] ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__0__7_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__0__7_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__0__7_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__0__7_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__0__7_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__0__7_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_1_upper ( grid_io_bottom_7_top_width_0_height_0__pin_1_upper ) , 
    .top_width_0_height_0__pin_1_lower ( grid_io_bottom_7_top_width_0_height_0__pin_1_lower ) , 
    .top_width_0_height_0__pin_3_upper ( grid_io_bottom_7_top_width_0_height_0__pin_3_upper ) , 
    .top_width_0_height_0__pin_3_lower ( grid_io_bottom_7_top_width_0_height_0__pin_3_lower ) , 
    .top_width_0_height_0__pin_5_upper ( grid_io_bottom_7_top_width_0_height_0__pin_5_upper ) , 
    .top_width_0_height_0__pin_5_lower ( grid_io_bottom_7_top_width_0_height_0__pin_5_lower ) , 
    .top_width_0_height_0__pin_7_upper ( grid_io_bottom_7_top_width_0_height_0__pin_7_upper ) , 
    .top_width_0_height_0__pin_7_lower ( grid_io_bottom_7_top_width_0_height_0__pin_7_lower ) , 
    .top_width_0_height_0__pin_9_upper ( grid_io_bottom_7_top_width_0_height_0__pin_9_upper ) , 
    .top_width_0_height_0__pin_9_lower ( grid_io_bottom_7_top_width_0_height_0__pin_9_lower ) , 
    .top_width_0_height_0__pin_11_upper ( grid_io_bottom_7_top_width_0_height_0__pin_11_upper ) , 
    .top_width_0_height_0__pin_11_lower ( grid_io_bottom_7_top_width_0_height_0__pin_11_lower ) , 
    .SC_IN_TOP ( scff_Wires__FEEDTHRU_1_186_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1615 ) , 
    .SC_OUT_TOP ( scff_Wires_187_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1616 ) ,
    .Test_en__FEEDTHRU_0 ( { optlc_net_619 } ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1617 } ) ) ;
cbx_1__0_ cbx_9__0_ (
    .prog_clk ( { ctsbuf_net_5401458 } ) ,
    .chanx_left_in ( sb_1__0__7_chanx_right_out ) , 
    .chanx_right_in ( sb_1__0__8_chanx_left_out ) , 
    .ccff_head ( sb_1__0__8_ccff_tail ) , 
    .chanx_left_out ( cbx_1__0__8_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__0__8_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__0__8_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__0__8_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__0__8_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__0__8_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__0__8_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__0__8_bottom_grid_pin_10_ ) , 
    .ccff_tail ( grid_io_bottom_8_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[72:77] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[72:77] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[72:77] ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__0__8_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__0__8_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__0__8_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__0__8_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__0__8_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__0__8_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_1_upper ( grid_io_bottom_8_top_width_0_height_0__pin_1_upper ) , 
    .top_width_0_height_0__pin_1_lower ( grid_io_bottom_8_top_width_0_height_0__pin_1_lower ) , 
    .top_width_0_height_0__pin_3_upper ( grid_io_bottom_8_top_width_0_height_0__pin_3_upper ) , 
    .top_width_0_height_0__pin_3_lower ( grid_io_bottom_8_top_width_0_height_0__pin_3_lower ) , 
    .top_width_0_height_0__pin_5_upper ( grid_io_bottom_8_top_width_0_height_0__pin_5_upper ) , 
    .top_width_0_height_0__pin_5_lower ( grid_io_bottom_8_top_width_0_height_0__pin_5_lower ) , 
    .top_width_0_height_0__pin_7_upper ( grid_io_bottom_8_top_width_0_height_0__pin_7_upper ) , 
    .top_width_0_height_0__pin_7_lower ( grid_io_bottom_8_top_width_0_height_0__pin_7_lower ) , 
    .top_width_0_height_0__pin_9_upper ( grid_io_bottom_8_top_width_0_height_0__pin_9_upper ) , 
    .top_width_0_height_0__pin_9_lower ( grid_io_bottom_8_top_width_0_height_0__pin_9_lower ) , 
    .top_width_0_height_0__pin_11_upper ( grid_io_bottom_8_top_width_0_height_0__pin_11_upper ) , 
    .top_width_0_height_0__pin_11_lower ( grid_io_bottom_8_top_width_0_height_0__pin_11_lower ) , 
    .SC_IN_TOP ( scff_Wires_237_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1618 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1619 ) , 
    .SC_OUT_BOT ( scff_Wires_238_ ) ,
    .Test_en__FEEDTHRU_0 ( { optlc_net_342 } ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1620 } ) ) ;
cbx_1__0_ cbx_10__0_ (
    .prog_clk ( { ctsbuf_net_5091427 } ) ,
    .chanx_left_in ( sb_1__0__8_chanx_right_out ) , 
    .chanx_right_in ( sb_1__0__9_chanx_left_out ) , 
    .ccff_head ( sb_1__0__9_ccff_tail ) , 
    .chanx_left_out ( cbx_1__0__9_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__0__9_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__0__9_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__0__9_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__0__9_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__0__9_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__0__9_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__0__9_bottom_grid_pin_10_ ) , 
    .ccff_tail ( grid_io_bottom_9_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[78:83] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[78:83] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[78:83] ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__0__9_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__0__9_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__0__9_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__0__9_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__0__9_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__0__9_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_1_upper ( grid_io_bottom_9_top_width_0_height_0__pin_1_upper ) , 
    .top_width_0_height_0__pin_1_lower ( grid_io_bottom_9_top_width_0_height_0__pin_1_lower ) , 
    .top_width_0_height_0__pin_3_upper ( grid_io_bottom_9_top_width_0_height_0__pin_3_upper ) , 
    .top_width_0_height_0__pin_3_lower ( grid_io_bottom_9_top_width_0_height_0__pin_3_lower ) , 
    .top_width_0_height_0__pin_5_upper ( grid_io_bottom_9_top_width_0_height_0__pin_5_upper ) , 
    .top_width_0_height_0__pin_5_lower ( grid_io_bottom_9_top_width_0_height_0__pin_5_lower ) , 
    .top_width_0_height_0__pin_7_upper ( grid_io_bottom_9_top_width_0_height_0__pin_7_upper ) , 
    .top_width_0_height_0__pin_7_lower ( grid_io_bottom_9_top_width_0_height_0__pin_7_lower ) , 
    .top_width_0_height_0__pin_9_upper ( grid_io_bottom_9_top_width_0_height_0__pin_9_upper ) , 
    .top_width_0_height_0__pin_9_lower ( grid_io_bottom_9_top_width_0_height_0__pin_9_lower ) , 
    .top_width_0_height_0__pin_11_upper ( grid_io_bottom_9_top_width_0_height_0__pin_11_upper ) , 
    .top_width_0_height_0__pin_11_lower ( grid_io_bottom_9_top_width_0_height_0__pin_11_lower ) , 
    .SC_IN_TOP ( scff_Wires__FEEDTHRU_1_239_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1621 ) , 
    .SC_OUT_TOP ( scff_Wires_240_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1622 ) ,
    .Test_en__FEEDTHRU_0 ( { optlc_net_893 } ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1623 } ) ) ;
cbx_1__0_ cbx_11__0_ (
    .prog_clk ( { ctsbuf_net_4701388 } ) ,
    .chanx_left_in ( sb_1__0__9_chanx_right_out ) , 
    .chanx_right_in ( sb_1__0__10_chanx_left_out ) , 
    .ccff_head ( sb_1__0__10_ccff_tail ) , 
    .chanx_left_out ( cbx_1__0__10_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__0__10_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__0__10_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__0__10_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__0__10_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__0__10_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__0__10_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__0__10_bottom_grid_pin_10_ ) , 
    .ccff_tail ( grid_io_bottom_10_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[84:89] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[84:89] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[84:89] ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__0__10_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__0__10_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__0__10_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__0__10_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__0__10_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__0__10_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_1_upper ( grid_io_bottom_10_top_width_0_height_0__pin_1_upper ) , 
    .top_width_0_height_0__pin_1_lower ( grid_io_bottom_10_top_width_0_height_0__pin_1_lower ) , 
    .top_width_0_height_0__pin_3_upper ( grid_io_bottom_10_top_width_0_height_0__pin_3_upper ) , 
    .top_width_0_height_0__pin_3_lower ( grid_io_bottom_10_top_width_0_height_0__pin_3_lower ) , 
    .top_width_0_height_0__pin_5_upper ( grid_io_bottom_10_top_width_0_height_0__pin_5_upper ) , 
    .top_width_0_height_0__pin_5_lower ( grid_io_bottom_10_top_width_0_height_0__pin_5_lower ) , 
    .top_width_0_height_0__pin_7_upper ( grid_io_bottom_10_top_width_0_height_0__pin_7_upper ) , 
    .top_width_0_height_0__pin_7_lower ( grid_io_bottom_10_top_width_0_height_0__pin_7_lower ) , 
    .top_width_0_height_0__pin_9_upper ( grid_io_bottom_10_top_width_0_height_0__pin_9_upper ) , 
    .top_width_0_height_0__pin_9_lower ( grid_io_bottom_10_top_width_0_height_0__pin_9_lower ) , 
    .top_width_0_height_0__pin_11_upper ( grid_io_bottom_10_top_width_0_height_0__pin_11_upper ) , 
    .top_width_0_height_0__pin_11_lower ( grid_io_bottom_10_top_width_0_height_0__pin_11_lower ) , 
    .SC_IN_TOP ( scff_Wires_290_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1624 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1625 ) , 
    .SC_OUT_BOT ( scff_Wires_291_ ) ,
    .Test_en__FEEDTHRU_0 ( { optlc_net_872 } ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1626 } ) ) ;
cbx_1__0_ cbx_12__0_ (
    .prog_clk ( { ctsbuf_net_4191337 } ) ,
    .chanx_left_in ( sb_1__0__10_chanx_right_out ) , 
    .chanx_right_in ( sb_12__0__0_chanx_left_out ) , 
    .ccff_head ( sb_12__0__0_ccff_tail ) , 
    .chanx_left_out ( cbx_1__0__11_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__0__11_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__0__11_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__0__11_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__0__11_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__0__11_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__0__11_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__0__11_bottom_grid_pin_10_ ) , 
    .ccff_tail ( grid_io_bottom_11_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[90:95] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[90:95] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[90:95] ) , 
    .top_width_0_height_0__pin_0_ ( cbx_1__0__11_bottom_grid_pin_0_ ) , 
    .top_width_0_height_0__pin_2_ ( cbx_1__0__11_bottom_grid_pin_2_ ) , 
    .top_width_0_height_0__pin_4_ ( cbx_1__0__11_bottom_grid_pin_4_ ) , 
    .top_width_0_height_0__pin_6_ ( cbx_1__0__11_bottom_grid_pin_6_ ) , 
    .top_width_0_height_0__pin_8_ ( cbx_1__0__11_bottom_grid_pin_8_ ) , 
    .top_width_0_height_0__pin_10_ ( cbx_1__0__11_bottom_grid_pin_10_ ) , 
    .top_width_0_height_0__pin_1_upper ( grid_io_bottom_11_top_width_0_height_0__pin_1_upper ) , 
    .top_width_0_height_0__pin_1_lower ( grid_io_bottom_11_top_width_0_height_0__pin_1_lower ) , 
    .top_width_0_height_0__pin_3_upper ( grid_io_bottom_11_top_width_0_height_0__pin_3_upper ) , 
    .top_width_0_height_0__pin_3_lower ( grid_io_bottom_11_top_width_0_height_0__pin_3_lower ) , 
    .top_width_0_height_0__pin_5_upper ( grid_io_bottom_11_top_width_0_height_0__pin_5_upper ) , 
    .top_width_0_height_0__pin_5_lower ( grid_io_bottom_11_top_width_0_height_0__pin_5_lower ) , 
    .top_width_0_height_0__pin_7_upper ( grid_io_bottom_11_top_width_0_height_0__pin_7_upper ) , 
    .top_width_0_height_0__pin_7_lower ( grid_io_bottom_11_top_width_0_height_0__pin_7_lower ) , 
    .top_width_0_height_0__pin_9_upper ( grid_io_bottom_11_top_width_0_height_0__pin_9_upper ) , 
    .top_width_0_height_0__pin_9_lower ( grid_io_bottom_11_top_width_0_height_0__pin_9_lower ) , 
    .top_width_0_height_0__pin_11_upper ( grid_io_bottom_11_top_width_0_height_0__pin_11_upper ) , 
    .top_width_0_height_0__pin_11_lower ( grid_io_bottom_11_top_width_0_height_0__pin_11_lower ) , 
    .SC_IN_TOP ( scff_Wires__FEEDTHRU_1_292_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1627 ) , 
    .SC_OUT_TOP ( scff_Wires_293_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1628 ) ,
    .Test_en__FEEDTHRU_0 ( { optlc_net_356 } ) ,
    .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_1629 } ) ) ;
cbx_1__1_ cbx_1__1_ (
    .prog_clk ( { ctsbuf_net_3981316 } ) ,
    .chanx_left_in ( sb_0__1__0_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__0_chanx_left_out ) , 
    .ccff_head ( sb_1__1__0_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__0_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__0_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_22_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1630 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1631 ) , 
    .SC_OUT_BOT ( scff_Wires_23_ ) ) ;
cbx_1__1_ cbx_1__2_ (
    .prog_clk ( { ctsbuf_net_3501268 } ) ,
    .chanx_left_in ( sb_0__1__1_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__1_chanx_left_out ) , 
    .ccff_head ( sb_1__1__1_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__1_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__1_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__1_ccff_tail ) , .SC_IN_TOP ( scff_Wires_20_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1632 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1633 ) , 
    .SC_OUT_BOT ( scff_Wires_21_ ) ) ;
cbx_1__1_ cbx_1__3_ (
    .prog_clk ( { ctsbuf_net_3021220 } ) ,
    .chanx_left_in ( sb_0__1__2_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__2_chanx_left_out ) , 
    .ccff_head ( sb_1__1__2_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__2_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__2_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__2_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__2_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__2_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__2_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__2_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__2_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__2_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__2_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__2_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__2_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__2_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__2_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__2_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__2_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__2_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__2_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires_18_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1634 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1635 ) , 
    .SC_OUT_BOT ( scff_Wires_19_ ) ) ;
cbx_1__1_ cbx_1__4_ (
    .prog_clk ( { ctsbuf_net_2541172 } ) ,
    .chanx_left_in ( sb_0__1__3_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__3_chanx_left_out ) , 
    .ccff_head ( sb_1__1__3_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__3_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__3_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__3_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__3_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__3_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__3_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__3_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__3_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__3_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__3_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__3_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__3_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__3_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__3_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__3_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__3_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__3_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__3_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__3_ccff_tail ) , .SC_IN_TOP ( scff_Wires_16_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1636 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1637 ) , 
    .SC_OUT_BOT ( scff_Wires_17_ ) ) ;
cbx_1__1_ cbx_1__5_ (
    .prog_clk ( { p_abuf24 } ) ,
    .chanx_left_in ( sb_0__1__4_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__4_chanx_left_out ) , 
    .ccff_head ( sb_1__1__4_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__4_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__4_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__4_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__4_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__4_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__4_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__4_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__4_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__4_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__4_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__4_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__4_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__4_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__4_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__4_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__4_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__4_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__4_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires_14_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1638 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1639 ) , 
    .SC_OUT_BOT ( scff_Wires_15_ ) ) ;
cbx_1__1_ cbx_1__6_ (
    .prog_clk ( { ctsbuf_net_1581076 } ) ,
    .chanx_left_in ( sb_0__1__5_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__5_chanx_left_out ) , 
    .ccff_head ( sb_1__1__5_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__5_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__5_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__5_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__5_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__5_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__5_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__5_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__5_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__5_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__5_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__5_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__5_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__5_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__5_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__5_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__5_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__5_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__5_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__5_ccff_tail ) , .SC_IN_TOP ( scff_Wires_12_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1640 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1641 ) , 
    .SC_OUT_BOT ( scff_Wires_13_ ) ) ;
cbx_1__1_ cbx_1__7_ (
    .prog_clk ( { ctsbuf_net_1141032 } ) ,
    .chanx_left_in ( sb_0__1__6_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__6_chanx_left_out ) , 
    .ccff_head ( sb_1__1__6_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__6_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__6_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__6_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__6_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__6_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__6_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__6_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__6_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__6_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__6_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__6_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__6_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__6_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__6_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__6_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__6_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__6_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__6_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires_10_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1642 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1643 ) , 
    .SC_OUT_BOT ( scff_Wires_11_ ) ) ;
cbx_1__1_ cbx_1__8_ (
    .prog_clk ( { ctsbuf_net_78996 } ) ,
    .chanx_left_in ( sb_0__1__7_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__7_chanx_left_out ) , 
    .ccff_head ( sb_1__1__7_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__7_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__7_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__7_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__7_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__7_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__7_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__7_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__7_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__7_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__7_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__7_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__7_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__7_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__7_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__7_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__7_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__7_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__7_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__7_ccff_tail ) , .SC_IN_TOP ( scff_Wires_8_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1644 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1645 ) , 
    .SC_OUT_BOT ( scff_Wires_9_ ) ) ;
cbx_1__1_ cbx_1__9_ (
    .prog_clk ( { ctsbuf_net_49967 } ) ,
    .chanx_left_in ( sb_0__1__8_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__8_chanx_left_out ) , 
    .ccff_head ( sb_1__1__8_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__8_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__8_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__8_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__8_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__8_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__8_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__8_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__8_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__8_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__8_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__8_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__8_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__8_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__8_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__8_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__8_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__8_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__8_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires_6_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1646 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1647 ) , 
    .SC_OUT_BOT ( scff_Wires_7_ ) ) ;
cbx_1__1_ cbx_1__10_ (
    .prog_clk ( { ctsbuf_net_28946 } ) ,
    .chanx_left_in ( sb_0__1__9_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__9_chanx_left_out ) , 
    .ccff_head ( sb_1__1__9_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__9_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__9_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__9_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__9_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__9_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__9_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__9_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__9_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__9_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__9_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__9_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__9_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__9_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__9_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__9_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__9_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__9_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__9_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__9_ccff_tail ) , .SC_IN_TOP ( scff_Wires_4_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1648 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1649 ) , 
    .SC_OUT_BOT ( scff_Wires_5_ ) ) ;
cbx_1__1_ cbx_1__11_ (
    .prog_clk ( { ctsbuf_net_15933 } ) ,
    .chanx_left_in ( sb_0__1__10_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__10_chanx_left_out ) , 
    .ccff_head ( sb_1__1__10_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__10_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__10_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__10_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__10_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__10_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__10_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__10_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__10_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__10_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__10_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__10_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__10_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__10_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__10_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__10_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__10_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__10_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__10_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires_2_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1650 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1651 ) , 
    .SC_OUT_BOT ( scff_Wires_3_ ) ) ;
cbx_1__1_ cbx_2__1_ (
    .prog_clk ( { ctsbuf_net_4571375 } ) ,
    .chanx_left_in ( sb_1__1__0_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__11_chanx_left_out ) , 
    .ccff_head ( sb_1__1__11_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__11_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__11_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__11_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__11_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__11_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__11_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__11_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__11_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__11_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__11_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__11_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__11_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__11_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__11_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__11_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__11_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__11_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__11_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__11_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1652 ) , .SC_IN_BOT ( scff_Wires_29_ ) , 
    .SC_OUT_TOP ( scff_Wires_30_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1653 ) ) ;
cbx_1__1_ cbx_2__2_ (
    .prog_clk ( { ctsbuf_net_4091327 } ) ,
    .chanx_left_in ( sb_1__1__1_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__12_chanx_left_out ) , 
    .ccff_head ( sb_1__1__12_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__12_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__12_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__12_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__12_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__12_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__12_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__12_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__12_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__12_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__12_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__12_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__12_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__12_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__12_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__12_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__12_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__12_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__12_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__12_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1654 ) , .SC_IN_BOT ( scff_Wires_31_ ) , 
    .SC_OUT_TOP ( scff_Wires_32_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1655 ) ) ;
cbx_1__1_ cbx_2__3_ (
    .prog_clk ( { ctsbuf_net_3611279 } ) ,
    .chanx_left_in ( sb_1__1__2_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__13_chanx_left_out ) , 
    .ccff_head ( sb_1__1__13_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__13_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__13_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__13_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__13_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__13_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__13_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__13_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__13_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__13_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__13_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__13_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__13_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__13_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__13_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__13_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__13_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__13_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__13_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__13_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1656 ) , .SC_IN_BOT ( scff_Wires_33_ ) , 
    .SC_OUT_TOP ( scff_Wires_34_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1657 ) ) ;
cbx_1__1_ cbx_2__4_ (
    .prog_clk ( { ctsbuf_net_3131231 } ) ,
    .chanx_left_in ( sb_1__1__3_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__14_chanx_left_out ) , 
    .ccff_head ( sb_1__1__14_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__14_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__14_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__14_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__14_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__14_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__14_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__14_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__14_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__14_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__14_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__14_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__14_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__14_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__14_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__14_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__14_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__14_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__14_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__14_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1658 ) , .SC_IN_BOT ( scff_Wires_35_ ) , 
    .SC_OUT_TOP ( scff_Wires_36_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1659 ) ) ;
cbx_1__1_ cbx_2__5_ (
    .prog_clk ( { ctsbuf_net_2651183 } ) ,
    .chanx_left_in ( sb_1__1__4_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__15_chanx_left_out ) , 
    .ccff_head ( sb_1__1__15_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__15_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__15_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__15_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__15_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__15_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__15_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__15_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__15_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__15_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__15_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__15_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__15_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__15_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__15_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__15_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__15_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__15_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__15_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__15_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1660 ) , .SC_IN_BOT ( scff_Wires_37_ ) , 
    .SC_OUT_TOP ( scff_Wires_38_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1661 ) ) ;
cbx_1__1_ cbx_2__6_ (
    .prog_clk ( { ctsbuf_net_2171135 } ) ,
    .chanx_left_in ( sb_1__1__5_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__16_chanx_left_out ) , 
    .ccff_head ( sb_1__1__16_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__16_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__16_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__16_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__16_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__16_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__16_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__16_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__16_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__16_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__16_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__16_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__16_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__16_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__16_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__16_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__16_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__16_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__16_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__16_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1662 ) , .SC_IN_BOT ( scff_Wires_39_ ) , 
    .SC_OUT_TOP ( scff_Wires_40_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1663 ) ) ;
cbx_1__1_ cbx_2__7_ (
    .prog_clk ( { p_abuf17 } ) ,
    .chanx_left_in ( sb_1__1__6_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__17_chanx_left_out ) , 
    .ccff_head ( sb_1__1__17_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__17_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__17_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__17_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__17_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__17_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__17_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__17_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__17_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__17_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__17_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__17_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__17_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__17_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__17_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__17_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__17_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__17_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__17_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__17_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1664 ) , .SC_IN_BOT ( scff_Wires_41_ ) , 
    .SC_OUT_TOP ( scff_Wires_42_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1665 ) ) ;
cbx_1__1_ cbx_2__8_ (
    .prog_clk ( { ctsbuf_net_1251043 } ) ,
    .chanx_left_in ( sb_1__1__7_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__18_chanx_left_out ) , 
    .ccff_head ( sb_1__1__18_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__18_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__18_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__18_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__18_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__18_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__18_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__18_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__18_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__18_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__18_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__18_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__18_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__18_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__18_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__18_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__18_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__18_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__18_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__18_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1666 ) , .SC_IN_BOT ( scff_Wires_43_ ) , 
    .SC_OUT_TOP ( scff_Wires_44_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1667 ) ) ;
cbx_1__1_ cbx_2__9_ (
    .prog_clk ( { ctsbuf_net_881006 } ) ,
    .chanx_left_in ( sb_1__1__8_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__19_chanx_left_out ) , 
    .ccff_head ( sb_1__1__19_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__19_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__19_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__19_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__19_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__19_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__19_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__19_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__19_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__19_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__19_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__19_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__19_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__19_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__19_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__19_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__19_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__19_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__19_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__19_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1668 ) , .SC_IN_BOT ( scff_Wires_45_ ) , 
    .SC_OUT_TOP ( scff_Wires_46_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1669 ) ) ;
cbx_1__1_ cbx_2__10_ (
    .prog_clk ( { ctsbuf_net_57975 } ) ,
    .chanx_left_in ( sb_1__1__9_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__20_chanx_left_out ) , 
    .ccff_head ( sb_1__1__20_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__20_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__20_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__20_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__20_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__20_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__20_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__20_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__20_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__20_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__20_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__20_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__20_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__20_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__20_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__20_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__20_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__20_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__20_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__20_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1670 ) , .SC_IN_BOT ( scff_Wires_47_ ) , 
    .SC_OUT_TOP ( scff_Wires_48_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1671 ) ) ;
cbx_1__1_ cbx_2__11_ (
    .prog_clk ( { ctsbuf_net_33951 } ) ,
    .chanx_left_in ( sb_1__1__10_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__21_chanx_left_out ) , 
    .ccff_head ( sb_1__1__21_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__21_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__21_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__21_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__21_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__21_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__21_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__21_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__21_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__21_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__21_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__21_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__21_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__21_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__21_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__21_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__21_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__21_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__21_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__21_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1672 ) , .SC_IN_BOT ( scff_Wires_49_ ) , 
    .SC_OUT_TOP ( scff_Wires_50_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1673 ) ) ;
cbx_1__1_ cbx_3__1_ (
    .prog_clk ( { ctsbuf_net_4991417 } ) ,
    .chanx_left_in ( sb_1__1__11_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__22_chanx_left_out ) , 
    .ccff_head ( sb_1__1__22_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__22_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__22_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__22_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__22_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__22_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__22_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__22_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__22_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__22_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__22_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__22_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__22_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__22_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__22_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__22_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__22_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__22_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__22_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__22_ccff_tail ) , .SC_IN_TOP ( scff_Wires_75_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1674 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1675 ) , 
    .SC_OUT_BOT ( scff_Wires_76_ ) ) ;
cbx_1__1_ cbx_3__2_ (
    .prog_clk ( { ctsbuf_net_4601378 } ) ,
    .chanx_left_in ( sb_1__1__12_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__23_chanx_left_out ) , 
    .ccff_head ( sb_1__1__23_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__23_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__23_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__23_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__23_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__23_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__23_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__23_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__23_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__23_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__23_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__23_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__23_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__23_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__23_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__23_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__23_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__23_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__23_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__23_ccff_tail ) , .SC_IN_TOP ( scff_Wires_73_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1676 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1677 ) , 
    .SC_OUT_BOT ( scff_Wires_74_ ) ) ;
cbx_1__1_ cbx_3__3_ (
    .prog_clk ( { ctsbuf_net_4121330 } ) ,
    .chanx_left_in ( sb_1__1__13_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__24_chanx_left_out ) , 
    .ccff_head ( sb_1__1__24_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__24_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__24_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__24_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__24_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__24_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__24_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__24_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__24_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__24_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__24_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__24_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__24_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__24_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__24_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__24_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__24_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__24_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__24_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__24_ccff_tail ) , .SC_IN_TOP ( scff_Wires_71_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1678 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1679 ) , 
    .SC_OUT_BOT ( scff_Wires_72_ ) ) ;
cbx_1__1_ cbx_3__4_ (
    .prog_clk ( { ctsbuf_net_3641282 } ) ,
    .chanx_left_in ( sb_1__1__14_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__25_chanx_left_out ) , 
    .ccff_head ( sb_1__1__25_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__25_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__25_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__25_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__25_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__25_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__25_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__25_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__25_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__25_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__25_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__25_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__25_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__25_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__25_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__25_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__25_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__25_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__25_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__25_ccff_tail ) , .SC_IN_TOP ( scff_Wires_69_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1680 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1681 ) , 
    .SC_OUT_BOT ( scff_Wires_70_ ) ) ;
cbx_1__1_ cbx_3__5_ (
    .prog_clk ( { ctsbuf_net_3161234 } ) ,
    .chanx_left_in ( sb_1__1__15_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__26_chanx_left_out ) , 
    .ccff_head ( sb_1__1__26_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__26_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__26_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__26_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__26_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__26_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__26_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__26_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__26_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__26_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__26_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__26_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__26_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__26_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__26_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__26_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__26_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__26_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__26_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__26_ccff_tail ) , .SC_IN_TOP ( scff_Wires_67_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1682 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1683 ) , 
    .SC_OUT_BOT ( scff_Wires_68_ ) ) ;
cbx_1__1_ cbx_3__6_ (
    .prog_clk ( { ctsbuf_net_2681186 } ) ,
    .chanx_left_in ( sb_1__1__16_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__27_chanx_left_out ) , 
    .ccff_head ( sb_1__1__27_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__27_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__27_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__27_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__27_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__27_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__27_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__27_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__27_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__27_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__27_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__27_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__27_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__27_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__27_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__27_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__27_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__27_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__27_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__27_ccff_tail ) , .SC_IN_TOP ( scff_Wires_65_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1684 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1685 ) , 
    .SC_OUT_BOT ( scff_Wires_66_ ) ) ;
cbx_1__1_ cbx_3__7_ (
    .prog_clk ( { ctsbuf_net_2201138 } ) ,
    .chanx_left_in ( sb_1__1__17_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__28_chanx_left_out ) , 
    .ccff_head ( sb_1__1__28_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__28_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__28_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__28_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__28_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__28_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__28_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__28_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__28_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__28_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__28_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__28_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__28_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__28_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__28_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__28_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__28_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__28_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__28_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__28_ccff_tail ) , .SC_IN_TOP ( scff_Wires_63_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1686 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1687 ) , 
    .SC_OUT_BOT ( scff_Wires_64_ ) ) ;
cbx_1__1_ cbx_3__8_ (
    .prog_clk ( { ctsbuf_net_1721090 } ) ,
    .chanx_left_in ( sb_1__1__18_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__29_chanx_left_out ) , 
    .ccff_head ( sb_1__1__29_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__29_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__29_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__29_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__29_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__29_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__29_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__29_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__29_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__29_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__29_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__29_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__29_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__29_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__29_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__29_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__29_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__29_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__29_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__29_ccff_tail ) , .SC_IN_TOP ( scff_Wires_61_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1688 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1689 ) , 
    .SC_OUT_BOT ( scff_Wires_62_ ) ) ;
cbx_1__1_ cbx_3__9_ (
    .prog_clk ( { p_abuf9 } ) ,
    .chanx_left_in ( sb_1__1__19_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__30_chanx_left_out ) , 
    .ccff_head ( sb_1__1__30_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__30_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__30_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__30_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__30_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__30_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__30_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__30_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__30_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__30_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__30_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__30_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__30_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__30_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__30_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__30_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__30_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__30_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__30_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__30_ccff_tail ) , .SC_IN_TOP ( scff_Wires_59_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1690 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1691 ) , 
    .SC_OUT_BOT ( scff_Wires_60_ ) ) ;
cbx_1__1_ cbx_3__10_ (
    .prog_clk ( { ctsbuf_net_901008 } ) ,
    .chanx_left_in ( sb_1__1__20_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__31_chanx_left_out ) , 
    .ccff_head ( sb_1__1__31_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__31_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__31_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__31_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__31_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__31_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__31_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__31_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__31_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__31_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__31_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__31_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__31_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__31_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__31_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__31_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__31_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__31_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__31_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__31_ccff_tail ) , .SC_IN_TOP ( scff_Wires_57_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1692 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1693 ) , 
    .SC_OUT_BOT ( scff_Wires_58_ ) ) ;
cbx_1__1_ cbx_3__11_ (
    .prog_clk ( { ctsbuf_net_58976 } ) ,
    .chanx_left_in ( sb_1__1__21_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__32_chanx_left_out ) , 
    .ccff_head ( sb_1__1__32_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__32_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__32_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__32_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__32_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__32_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__32_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__32_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__32_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__32_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__32_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__32_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__32_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__32_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__32_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__32_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__32_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__32_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__32_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__32_ccff_tail ) , .SC_IN_TOP ( scff_Wires_55_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1694 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1695 ) , 
    .SC_OUT_BOT ( scff_Wires_56_ ) ) ;
cbx_1__1_ cbx_4__1_ (
    .prog_clk ( { ctsbuf_net_5331451 } ) ,
    .chanx_left_in ( sb_1__1__22_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__33_chanx_left_out ) , 
    .ccff_head ( sb_1__1__33_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__33_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__33_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__33_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__33_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__33_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__33_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__33_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__33_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__33_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__33_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__33_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__33_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__33_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__33_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__33_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__33_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__33_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__33_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__33_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1696 ) , .SC_IN_BOT ( scff_Wires_82_ ) , 
    .SC_OUT_TOP ( scff_Wires_83_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1697 ) ) ;
cbx_1__1_ cbx_4__2_ (
    .prog_clk ( { ctsbuf_net_5021420 } ) ,
    .chanx_left_in ( sb_1__1__23_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__34_chanx_left_out ) , 
    .ccff_head ( sb_1__1__34_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__34_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__34_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__34_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__34_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__34_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__34_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__34_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__34_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__34_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__34_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__34_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__34_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__34_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__34_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__34_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__34_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__34_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__34_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__34_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1698 ) , .SC_IN_BOT ( scff_Wires_84_ ) , 
    .SC_OUT_TOP ( scff_Wires_85_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1699 ) ) ;
cbx_1__1_ cbx_4__3_ (
    .prog_clk ( { ctsbuf_net_4631381 } ) ,
    .chanx_left_in ( sb_1__1__24_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__35_chanx_left_out ) , 
    .ccff_head ( sb_1__1__35_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__35_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__35_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__35_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__35_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__35_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__35_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__35_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__35_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__35_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__35_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__35_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__35_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__35_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__35_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__35_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__35_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__35_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__35_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__35_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1700 ) , .SC_IN_BOT ( scff_Wires_86_ ) , 
    .SC_OUT_TOP ( scff_Wires_87_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1701 ) ) ;
cbx_1__1_ cbx_4__4_ (
    .prog_clk ( { ctsbuf_net_4151333 } ) ,
    .chanx_left_in ( sb_1__1__25_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__36_chanx_left_out ) , 
    .ccff_head ( sb_1__1__36_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__36_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__36_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__36_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__36_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__36_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__36_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__36_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__36_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__36_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__36_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__36_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__36_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__36_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__36_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__36_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__36_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__36_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__36_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__36_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1702 ) , .SC_IN_BOT ( scff_Wires_88_ ) , 
    .SC_OUT_TOP ( scff_Wires_89_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1703 ) ) ;
cbx_1__1_ cbx_4__5_ (
    .prog_clk ( { ctsbuf_net_3921310 } ) ,
    .chanx_left_in ( sb_1__1__26_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__37_chanx_left_out ) , 
    .ccff_head ( sb_1__1__37_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__37_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__37_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__37_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__37_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__37_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__37_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__37_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__37_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__37_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__37_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__37_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__37_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__37_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__37_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__37_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__37_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__37_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__37_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__37_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1704 ) , .SC_IN_BOT ( scff_Wires_90_ ) , 
    .SC_OUT_TOP ( scff_Wires_91_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1705 ) ) ;
cbx_1__1_ cbx_4__6_ (
    .prog_clk ( { ctsbuf_net_3191237 } ) ,
    .chanx_left_in ( sb_1__1__27_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__38_chanx_left_out ) , 
    .ccff_head ( sb_1__1__38_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__38_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__38_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__38_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__38_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__38_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__38_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__38_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__38_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__38_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__38_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__38_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__38_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__38_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__38_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__38_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__38_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__38_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__38_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__38_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1706 ) , .SC_IN_BOT ( scff_Wires_92_ ) , 
    .SC_OUT_TOP ( scff_Wires_93_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1707 ) ) ;
cbx_1__1_ cbx_4__7_ (
    .prog_clk ( { ctsbuf_net_2711189 } ) ,
    .chanx_left_in ( sb_1__1__28_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__39_chanx_left_out ) , 
    .ccff_head ( sb_1__1__39_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__39_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__39_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__39_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__39_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__39_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__39_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__39_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__39_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__39_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__39_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__39_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__39_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__39_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__39_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__39_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__39_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__39_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__39_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__39_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1708 ) , .SC_IN_BOT ( scff_Wires_94_ ) , 
    .SC_OUT_TOP ( scff_Wires_95_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1709 ) ) ;
cbx_1__1_ cbx_4__8_ (
    .prog_clk ( { ctsbuf_net_2231141 } ) ,
    .chanx_left_in ( sb_1__1__29_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__40_chanx_left_out ) , 
    .ccff_head ( sb_1__1__40_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__40_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__40_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__40_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__40_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__40_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__40_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__40_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__40_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__40_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__40_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__40_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__40_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__40_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__40_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__40_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__40_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__40_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__40_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__40_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1710 ) , .SC_IN_BOT ( scff_Wires_96_ ) , 
    .SC_OUT_TOP ( scff_Wires_97_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1711 ) ) ;
cbx_1__1_ cbx_4__9_ (
    .prog_clk ( { ctsbuf_net_1751093 } ) ,
    .chanx_left_in ( sb_1__1__30_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__41_chanx_left_out ) , 
    .ccff_head ( sb_1__1__41_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__41_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__41_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__41_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__41_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__41_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__41_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__41_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__41_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__41_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__41_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__41_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__41_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__41_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__41_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__41_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__41_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__41_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__41_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__41_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1712 ) , .SC_IN_BOT ( scff_Wires_98_ ) , 
    .SC_OUT_TOP ( scff_Wires_99_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1713 ) ) ;
cbx_1__1_ cbx_4__10_ (
    .prog_clk ( { ctsbuf_net_1301048 } ) ,
    .chanx_left_in ( sb_1__1__31_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__42_chanx_left_out ) , 
    .ccff_head ( sb_1__1__42_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__42_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__42_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__42_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__42_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__42_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__42_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__42_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__42_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__42_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__42_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__42_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__42_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__42_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__42_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__42_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__42_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__42_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__42_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__42_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1714 ) , 
    .SC_IN_BOT ( scff_Wires_100_ ) , .SC_OUT_TOP ( scff_Wires_101_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1715 ) ) ;
cbx_1__1_ cbx_4__11_ (
    .prog_clk ( { ctsbuf_net_911009 } ) ,
    .chanx_left_in ( sb_1__1__32_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__43_chanx_left_out ) , 
    .ccff_head ( sb_1__1__43_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__43_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__43_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__43_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__43_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__43_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__43_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__43_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__43_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__43_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__43_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__43_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__43_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__43_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__43_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__43_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__43_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__43_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__43_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__43_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1716 ) , 
    .SC_IN_BOT ( scff_Wires_102_ ) , .SC_OUT_TOP ( scff_Wires_103_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1717 ) ) ;
cbx_1__1_ cbx_5__1_ (
    .prog_clk ( { ctsbuf_net_5581476 } ) ,
    .chanx_left_in ( sb_1__1__33_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__44_chanx_left_out ) , 
    .ccff_head ( sb_1__1__44_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__44_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__44_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__44_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__44_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__44_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__44_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__44_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__44_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__44_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__44_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__44_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__44_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__44_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__44_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__44_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__44_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__44_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__44_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__44_ccff_tail ) , .SC_IN_TOP ( scff_Wires_128_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1718 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1719 ) , 
    .SC_OUT_BOT ( scff_Wires_129_ ) ) ;
cbx_1__1_ cbx_5__2_ (
    .prog_clk ( { ctsbuf_net_5351453 } ) ,
    .chanx_left_in ( sb_1__1__34_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__45_chanx_left_out ) , 
    .ccff_head ( sb_1__1__45_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__45_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__45_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__45_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__45_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__45_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__45_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__45_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__45_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__45_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__45_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__45_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__45_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__45_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__45_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__45_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__45_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__45_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__45_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__45_ccff_tail ) , .SC_IN_TOP ( scff_Wires_126_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1720 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1721 ) , 
    .SC_OUT_BOT ( scff_Wires_127_ ) ) ;
cbx_1__1_ cbx_5__3_ (
    .prog_clk ( { ctsbuf_net_5041422 } ) ,
    .chanx_left_in ( sb_1__1__35_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__46_chanx_left_out ) , 
    .ccff_head ( sb_1__1__46_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__46_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__46_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__46_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__46_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__46_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__46_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__46_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__46_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__46_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__46_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__46_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__46_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__46_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__46_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__46_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__46_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__46_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__46_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__46_ccff_tail ) , .SC_IN_TOP ( scff_Wires_124_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1722 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1723 ) , 
    .SC_OUT_BOT ( scff_Wires_125_ ) ) ;
cbx_1__1_ cbx_5__4_ (
    .prog_clk ( { ctsbuf_net_4651383 } ) ,
    .chanx_left_in ( sb_1__1__36_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__47_chanx_left_out ) , 
    .ccff_head ( sb_1__1__47_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__47_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__47_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__47_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__47_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__47_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__47_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__47_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__47_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__47_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__47_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__47_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__47_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__47_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__47_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__47_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__47_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__47_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__47_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__47_ccff_tail ) , .SC_IN_TOP ( scff_Wires_122_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1724 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1725 ) , 
    .SC_OUT_BOT ( scff_Wires_123_ ) ) ;
cbx_1__1_ cbx_5__5_ (
    .prog_clk ( { ctsbuf_net_4171335 } ) ,
    .chanx_left_in ( sb_1__1__37_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__48_chanx_left_out ) , 
    .ccff_head ( sb_1__1__48_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__48_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__48_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__48_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__48_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__48_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__48_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__48_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__48_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__48_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__48_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__48_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__48_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__48_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__48_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__48_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__48_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__48_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__48_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__48_ccff_tail ) , .SC_IN_TOP ( scff_Wires_120_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1726 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1727 ) , 
    .SC_OUT_BOT ( scff_Wires_121_ ) ) ;
cbx_1__1_ cbx_5__6_ (
    .prog_clk ( { ctsbuf_net_3691287 } ) ,
    .chanx_left_in ( sb_1__1__38_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__49_chanx_left_out ) , 
    .ccff_head ( sb_1__1__49_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__49_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__49_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__49_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__49_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__49_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__49_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__49_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__49_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__49_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__49_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__49_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__49_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__49_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__49_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__49_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__49_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__49_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__49_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__49_ccff_tail ) , .SC_IN_TOP ( scff_Wires_118_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1728 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1729 ) , 
    .SC_OUT_BOT ( scff_Wires_119_ ) ) ;
cbx_1__1_ cbx_5__7_ (
    .prog_clk ( { p_abuf31 } ) ,
    .chanx_left_in ( sb_1__1__39_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__50_chanx_left_out ) , 
    .ccff_head ( sb_1__1__50_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__50_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__50_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__50_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__50_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__50_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__50_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__50_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__50_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__50_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__50_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__50_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__50_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__50_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__50_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__50_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__50_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__50_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__50_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__50_ccff_tail ) , .SC_IN_TOP ( scff_Wires_116_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1730 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1731 ) , 
    .SC_OUT_BOT ( scff_Wires_117_ ) ) ;
cbx_1__1_ cbx_5__8_ (
    .prog_clk ( { ctsbuf_net_2731191 } ) ,
    .chanx_left_in ( sb_1__1__40_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__51_chanx_left_out ) , 
    .ccff_head ( sb_1__1__51_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__51_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__51_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__51_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__51_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__51_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__51_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__51_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__51_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__51_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__51_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__51_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__51_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__51_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__51_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__51_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__51_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__51_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__51_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__51_ccff_tail ) , .SC_IN_TOP ( scff_Wires_114_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1732 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1733 ) , 
    .SC_OUT_BOT ( scff_Wires_115_ ) ) ;
cbx_1__1_ cbx_5__9_ (
    .prog_clk ( { ctsbuf_net_2251143 } ) ,
    .chanx_left_in ( sb_1__1__41_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__52_chanx_left_out ) , 
    .ccff_head ( sb_1__1__52_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__52_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__52_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__52_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__52_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__52_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__52_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__52_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__52_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__52_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__52_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__52_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__52_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__52_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__52_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__52_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__52_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__52_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__52_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__52_ccff_tail ) , .SC_IN_TOP ( scff_Wires_112_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1734 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1735 ) , 
    .SC_OUT_BOT ( scff_Wires_113_ ) ) ;
cbx_1__1_ cbx_5__10_ (
    .prog_clk ( { ctsbuf_net_1771095 } ) ,
    .chanx_left_in ( sb_1__1__42_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__53_chanx_left_out ) , 
    .ccff_head ( sb_1__1__53_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__53_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__53_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__53_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__53_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__53_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__53_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__53_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__53_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__53_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__53_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__53_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__53_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__53_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__53_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__53_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__53_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__53_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__53_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__53_ccff_tail ) , .SC_IN_TOP ( scff_Wires_110_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1736 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1737 ) , 
    .SC_OUT_BOT ( scff_Wires_111_ ) ) ;
cbx_1__1_ cbx_5__11_ (
    .prog_clk ( { ctsbuf_net_1311049 } ) ,
    .chanx_left_in ( sb_1__1__43_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__54_chanx_left_out ) , 
    .ccff_head ( sb_1__1__54_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__54_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__54_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__54_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__54_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__54_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__54_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__54_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__54_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__54_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__54_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__54_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__54_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__54_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__54_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__54_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__54_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__54_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__54_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__54_ccff_tail ) , .SC_IN_TOP ( scff_Wires_108_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1738 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1739 ) , 
    .SC_OUT_BOT ( scff_Wires_109_ ) ) ;
cbx_1__1_ cbx_6__1_ (
    .prog_clk ( { ctsbuf_net_5741492 } ) ,
    .chanx_left_in ( sb_1__1__44_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__55_chanx_left_out ) , 
    .ccff_head ( sb_1__1__55_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__55_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__55_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__55_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__55_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__55_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__55_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__55_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__55_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__55_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__55_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__55_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__55_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__55_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__55_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__55_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__55_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__55_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__55_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__55_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1740 ) , 
    .SC_IN_BOT ( scff_Wires_135_ ) , .SC_OUT_TOP ( scff_Wires_136_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1741 ) ) ;
cbx_1__1_ cbx_6__2_ (
    .prog_clk ( { ctsbuf_net_5591477 } ) ,
    .chanx_left_in ( sb_1__1__45_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__56_chanx_left_out ) , 
    .ccff_head ( sb_1__1__56_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__56_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__56_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__56_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__56_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__56_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__56_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__56_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__56_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__56_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__56_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__56_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__56_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__56_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__56_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__56_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__56_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__56_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__56_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__56_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1742 ) , 
    .SC_IN_BOT ( scff_Wires_137_ ) , .SC_OUT_TOP ( scff_Wires_138_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1743 ) ) ;
cbx_1__1_ cbx_6__3_ (
    .prog_clk ( { ctsbuf_net_5361454 } ) ,
    .chanx_left_in ( sb_1__1__46_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__57_chanx_left_out ) , 
    .ccff_head ( sb_1__1__57_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__57_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__57_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__57_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__57_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__57_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__57_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__57_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__57_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__57_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__57_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__57_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__57_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__57_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__57_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__57_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__57_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__57_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__57_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__57_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1744 ) , 
    .SC_IN_BOT ( scff_Wires_139_ ) , .SC_OUT_TOP ( scff_Wires_140_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1745 ) ) ;
cbx_1__1_ cbx_6__4_ (
    .prog_clk ( { ctsbuf_net_5051423 } ) ,
    .chanx_left_in ( sb_1__1__47_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__58_chanx_left_out ) , 
    .ccff_head ( sb_1__1__58_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__58_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__58_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__58_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__58_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__58_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__58_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__58_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__58_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__58_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__58_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__58_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__58_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__58_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__58_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__58_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__58_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__58_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__58_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__58_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1746 ) , 
    .SC_IN_BOT ( scff_Wires_141_ ) , .SC_OUT_TOP ( scff_Wires_142_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1747 ) ) ;
cbx_1__1_ cbx_6__5_ (
    .prog_clk ( { ctsbuf_net_6551573 } ) ,
    .chanx_left_in ( sb_1__1__48_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__59_chanx_left_out ) , 
    .ccff_head ( sb_1__1__59_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__59_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__59_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__59_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__59_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__59_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__59_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__59_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__59_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__59_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__59_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__59_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__59_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__59_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__59_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__59_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__59_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__59_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__59_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__59_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1748 ) , 
    .SC_IN_BOT ( scff_Wires_143_ ) , .SC_OUT_TOP ( scff_Wires_144_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1749 ) ) ;
cbx_1__1_ cbx_6__6_ (
    .prog_clk ( { ctsbuf_net_4181336 } ) ,
    .chanx_left_in ( sb_1__1__49_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__60_chanx_left_out ) , 
    .ccff_head ( sb_1__1__60_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__60_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__60_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__60_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__60_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__60_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__60_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__60_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__60_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__60_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__60_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__60_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__60_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__60_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__60_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__60_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__60_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__60_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__60_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__60_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1750 ) , 
    .SC_IN_BOT ( scff_Wires_145_ ) , .SC_OUT_TOP ( scff_Wires_146_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1751 ) ) ;
cbx_1__1_ cbx_6__7_ (
    .prog_clk ( { ctsbuf_net_3701288 } ) ,
    .chanx_left_in ( sb_1__1__50_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__61_chanx_left_out ) , 
    .ccff_head ( sb_1__1__61_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__61_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__61_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__61_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__61_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__61_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__61_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__61_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__61_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__61_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__61_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__61_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__61_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__61_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__61_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__61_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__61_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__61_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__61_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__61_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1752 ) , 
    .SC_IN_BOT ( scff_Wires_147_ ) , .SC_OUT_TOP ( scff_Wires_148_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1753 ) ) ;
cbx_1__1_ cbx_6__8_ (
    .prog_clk ( { ctsbuf_net_3221240 } ) ,
    .chanx_left_in ( sb_1__1__51_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__62_chanx_left_out ) , 
    .ccff_head ( sb_1__1__62_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__62_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__62_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__62_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__62_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__62_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__62_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__62_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__62_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__62_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__62_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__62_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__62_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__62_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__62_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__62_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__62_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__62_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__62_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__62_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1754 ) , 
    .SC_IN_BOT ( scff_Wires_149_ ) , .SC_OUT_TOP ( scff_Wires_150_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1755 ) ) ;
cbx_1__1_ cbx_6__9_ (
    .prog_clk ( { ctsbuf_net_2741192 } ) ,
    .chanx_left_in ( sb_1__1__52_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__63_chanx_left_out ) , 
    .ccff_head ( sb_1__1__63_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__63_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__63_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__63_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__63_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__63_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__63_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__63_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__63_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__63_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__63_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__63_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__63_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__63_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__63_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__63_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__63_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__63_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__63_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__63_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1756 ) , 
    .SC_IN_BOT ( scff_Wires_151_ ) , .SC_OUT_TOP ( scff_Wires_152_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1757 ) ) ;
cbx_1__1_ cbx_6__10_ (
    .prog_clk ( { ctsbuf_net_2261144 } ) ,
    .chanx_left_in ( sb_1__1__53_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__64_chanx_left_out ) , 
    .ccff_head ( sb_1__1__64_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__64_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__64_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__64_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__64_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__64_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__64_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__64_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__64_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__64_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__64_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__64_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__64_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__64_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__64_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__64_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__64_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__64_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__64_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__64_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1758 ) , 
    .SC_IN_BOT ( scff_Wires_153_ ) , .SC_OUT_TOP ( scff_Wires_154_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1759 ) ) ;
cbx_1__1_ cbx_6__11_ (
    .prog_clk ( { p_abuf11 } ) ,
    .chanx_left_in ( sb_1__1__54_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__65_chanx_left_out ) , 
    .ccff_head ( sb_1__1__65_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__65_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__65_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__65_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__65_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__65_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__65_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__65_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__65_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__65_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__65_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__65_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__65_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__65_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__65_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__65_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__65_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__65_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__65_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__65_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1760 ) , 
    .SC_IN_BOT ( scff_Wires_155_ ) , .SC_OUT_TOP ( scff_Wires_156_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1761 ) ) ;
cbx_1__1_ cbx_7__1_ (
    .prog_clk ( { ctsbuf_net_5761494 } ) ,
    .chanx_left_in ( sb_1__1__55_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__66_chanx_left_out ) , 
    .ccff_head ( sb_1__1__66_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__66_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__66_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__66_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__66_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__66_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__66_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__66_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__66_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__66_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__66_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__66_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__66_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__66_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__66_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__66_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__66_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__66_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__66_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__66_ccff_tail ) , .SC_IN_TOP ( scff_Wires_181_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1762 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1763 ) , 
    .SC_OUT_BOT ( scff_Wires_182_ ) ) ;
cbx_1__1_ cbx_7__2_ (
    .prog_clk ( { ctsbuf_net_5631481 } ) ,
    .chanx_left_in ( sb_1__1__56_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__67_chanx_left_out ) , 
    .ccff_head ( sb_1__1__67_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__67_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__67_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__67_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__67_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__67_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__67_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__67_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__67_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__67_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__67_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__67_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__67_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__67_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__67_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__67_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__67_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__67_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__67_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__67_ccff_tail ) , .SC_IN_TOP ( scff_Wires_179_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1764 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1765 ) , 
    .SC_OUT_BOT ( scff_Wires_180_ ) ) ;
cbx_1__1_ cbx_7__3_ (
    .prog_clk ( { ctsbuf_net_5421460 } ) ,
    .chanx_left_in ( sb_1__1__57_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__68_chanx_left_out ) , 
    .ccff_head ( sb_1__1__68_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__68_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__68_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__68_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__68_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__68_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__68_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__68_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__68_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__68_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__68_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__68_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__68_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__68_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__68_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__68_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__68_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__68_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__68_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__68_ccff_tail ) , .SC_IN_TOP ( scff_Wires_177_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1766 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1767 ) , 
    .SC_OUT_BOT ( scff_Wires_178_ ) ) ;
cbx_1__1_ cbx_7__4_ (
    .prog_clk ( { ctsbuf_net_5131431 } ) ,
    .chanx_left_in ( sb_1__1__58_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__69_chanx_left_out ) , 
    .ccff_head ( sb_1__1__69_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__69_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__69_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__69_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__69_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__69_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__69_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__69_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__69_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__69_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__69_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__69_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__69_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__69_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__69_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__69_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__69_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__69_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__69_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__69_ccff_tail ) , .SC_IN_TOP ( scff_Wires_175_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1768 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1769 ) , 
    .SC_OUT_BOT ( scff_Wires_176_ ) ) ;
cbx_1__1_ cbx_7__5_ (
    .prog_clk ( { ctsbuf_net_4761394 } ) ,
    .chanx_left_in ( sb_1__1__59_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__70_chanx_left_out ) , 
    .ccff_head ( sb_1__1__70_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__70_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__70_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__70_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__70_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__70_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__70_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__70_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__70_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__70_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__70_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__70_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__70_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__70_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__70_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__70_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__70_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__70_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__70_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__70_ccff_tail ) , .SC_IN_TOP ( scff_Wires_173_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1770 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1771 ) , 
    .SC_OUT_BOT ( scff_Wires_174_ ) ) ;
cbx_1__1_ cbx_7__6_ (
    .prog_clk ( { ctsbuf_net_4311349 } ) ,
    .chanx_left_in ( sb_1__1__60_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__71_chanx_left_out ) , 
    .ccff_head ( sb_1__1__71_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__71_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__71_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__71_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__71_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__71_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__71_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__71_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__71_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__71_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__71_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__71_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__71_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__71_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__71_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__71_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__71_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__71_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__71_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__71_ccff_tail ) , .SC_IN_TOP ( scff_Wires_171_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1772 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1773 ) , 
    .SC_OUT_BOT ( scff_Wires_172_ ) ) ;
cbx_1__1_ cbx_7__7_ (
    .prog_clk ( { ctsbuf_net_3831301 } ) ,
    .chanx_left_in ( sb_1__1__61_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__72_chanx_left_out ) , 
    .ccff_head ( sb_1__1__72_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__72_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__72_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__72_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__72_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__72_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__72_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__72_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__72_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__72_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__72_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__72_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__72_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__72_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__72_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__72_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__72_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__72_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__72_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__72_ccff_tail ) , .SC_IN_TOP ( scff_Wires_169_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1774 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1775 ) , 
    .SC_OUT_BOT ( scff_Wires_170_ ) ) ;
cbx_1__1_ cbx_7__8_ (
    .prog_clk ( { ctsbuf_net_3351253 } ) ,
    .chanx_left_in ( sb_1__1__62_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__73_chanx_left_out ) , 
    .ccff_head ( sb_1__1__73_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__73_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__73_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__73_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__73_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__73_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__73_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__73_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__73_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__73_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__73_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__73_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__73_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__73_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__73_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__73_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__73_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__73_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__73_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__73_ccff_tail ) , .SC_IN_TOP ( scff_Wires_167_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1776 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1777 ) , 
    .SC_OUT_BOT ( scff_Wires_168_ ) ) ;
cbx_1__1_ cbx_7__9_ (
    .prog_clk ( { ctsbuf_net_2871205 } ) ,
    .chanx_left_in ( sb_1__1__63_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__74_chanx_left_out ) , 
    .ccff_head ( sb_1__1__74_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__74_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__74_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__74_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__74_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__74_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__74_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__74_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__74_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__74_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__74_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__74_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__74_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__74_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__74_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__74_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__74_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__74_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__74_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__74_ccff_tail ) , .SC_IN_TOP ( scff_Wires_165_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1778 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1779 ) , 
    .SC_OUT_BOT ( scff_Wires_166_ ) ) ;
cbx_1__1_ cbx_7__10_ (
    .prog_clk ( { ctsbuf_net_2391157 } ) ,
    .chanx_left_in ( sb_1__1__64_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__75_chanx_left_out ) , 
    .ccff_head ( sb_1__1__75_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__75_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__75_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__75_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__75_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__75_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__75_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__75_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__75_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__75_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__75_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__75_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__75_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__75_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__75_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__75_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__75_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__75_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__75_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__75_ccff_tail ) , .SC_IN_TOP ( scff_Wires_163_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1780 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1781 ) , 
    .SC_OUT_BOT ( scff_Wires_164_ ) ) ;
cbx_1__1_ cbx_7__11_ (
    .prog_clk ( { ctsbuf_net_1911109 } ) ,
    .chanx_left_in ( sb_1__1__65_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__76_chanx_left_out ) , 
    .ccff_head ( sb_1__1__76_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__76_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__76_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__76_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__76_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__76_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__76_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__76_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__76_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__76_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__76_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__76_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__76_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__76_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__76_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__76_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__76_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__76_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__76_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__76_ccff_tail ) , .SC_IN_TOP ( scff_Wires_161_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1782 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1783 ) , 
    .SC_OUT_BOT ( scff_Wires_162_ ) ) ;
cbx_1__1_ cbx_8__1_ (
    .prog_clk ( { ctsbuf_net_5621480 } ) ,
    .chanx_left_in ( sb_1__1__66_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__77_chanx_left_out ) , 
    .ccff_head ( sb_1__1__77_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__77_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__77_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__77_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__77_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__77_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__77_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__77_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__77_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__77_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__77_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__77_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__77_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__77_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__77_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__77_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__77_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__77_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__77_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__77_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1784 ) , 
    .SC_IN_BOT ( scff_Wires_188_ ) , .SC_OUT_TOP ( scff_Wires_189_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1785 ) ) ;
cbx_1__1_ cbx_8__2_ (
    .prog_clk ( { ctsbuf_net_5411459 } ) ,
    .chanx_left_in ( sb_1__1__67_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__78_chanx_left_out ) , 
    .ccff_head ( sb_1__1__78_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__78_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__78_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__78_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__78_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__78_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__78_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__78_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__78_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__78_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__78_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__78_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__78_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__78_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__78_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__78_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__78_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__78_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__78_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__78_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1786 ) , 
    .SC_IN_BOT ( scff_Wires_190_ ) , .SC_OUT_TOP ( scff_Wires_191_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1787 ) ) ;
cbx_1__1_ cbx_8__3_ (
    .prog_clk ( { ctsbuf_net_5121430 } ) ,
    .chanx_left_in ( sb_1__1__68_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__79_chanx_left_out ) , 
    .ccff_head ( sb_1__1__79_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__79_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__79_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__79_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__79_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__79_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__79_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__79_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__79_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__79_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__79_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__79_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__79_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__79_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__79_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__79_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__79_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__79_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__79_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__79_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1788 ) , 
    .SC_IN_BOT ( scff_Wires_192_ ) , .SC_OUT_TOP ( scff_Wires_193_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1789 ) ) ;
cbx_1__1_ cbx_8__4_ (
    .prog_clk ( { ctsbuf_net_4751393 } ) ,
    .chanx_left_in ( sb_1__1__69_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__80_chanx_left_out ) , 
    .ccff_head ( sb_1__1__80_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__80_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__80_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__80_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__80_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__80_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__80_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__80_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__80_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__80_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__80_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__80_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__80_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__80_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__80_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__80_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__80_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__80_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__80_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__80_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1790 ) , 
    .SC_IN_BOT ( scff_Wires_194_ ) , .SC_OUT_TOP ( scff_Wires_195_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1791 ) ) ;
cbx_1__1_ cbx_8__5_ (
    .prog_clk ( { ctsbuf_net_4301348 } ) ,
    .chanx_left_in ( sb_1__1__70_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__81_chanx_left_out ) , 
    .ccff_head ( sb_1__1__81_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__81_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__81_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__81_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__81_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__81_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__81_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__81_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__81_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__81_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__81_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__81_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__81_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__81_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__81_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__81_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__81_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__81_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__81_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__81_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1792 ) , 
    .SC_IN_BOT ( scff_Wires_196_ ) , .SC_OUT_TOP ( scff_Wires_197_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1793 ) ) ;
cbx_1__1_ cbx_8__6_ (
    .prog_clk ( { ctsbuf_net_3821300 } ) ,
    .chanx_left_in ( sb_1__1__71_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__82_chanx_left_out ) , 
    .ccff_head ( sb_1__1__82_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__82_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__82_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__82_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__82_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__82_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__82_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__82_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__82_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__82_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__82_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__82_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__82_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__82_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__82_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__82_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__82_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__82_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__82_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__82_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1794 ) , 
    .SC_IN_BOT ( scff_Wires_198_ ) , .SC_OUT_TOP ( scff_Wires_199_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1795 ) ) ;
cbx_1__1_ cbx_8__7_ (
    .prog_clk ( { ctsbuf_net_3341252 } ) ,
    .chanx_left_in ( sb_1__1__72_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__83_chanx_left_out ) , 
    .ccff_head ( sb_1__1__83_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__83_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__83_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__83_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__83_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__83_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__83_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__83_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__83_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__83_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__83_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__83_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__83_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__83_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__83_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__83_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__83_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__83_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__83_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__83_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1796 ) , 
    .SC_IN_BOT ( scff_Wires_200_ ) , .SC_OUT_TOP ( scff_Wires_201_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1797 ) ) ;
cbx_1__1_ cbx_8__8_ (
    .prog_clk ( { ctsbuf_net_2861204 } ) ,
    .chanx_left_in ( sb_1__1__73_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__84_chanx_left_out ) , 
    .ccff_head ( sb_1__1__84_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__84_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__84_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__84_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__84_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__84_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__84_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__84_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__84_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__84_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__84_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__84_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__84_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__84_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__84_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__84_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__84_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__84_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__84_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__84_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1798 ) , 
    .SC_IN_BOT ( scff_Wires_202_ ) , .SC_OUT_TOP ( scff_Wires_203_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1799 ) ) ;
cbx_1__1_ cbx_8__9_ (
    .prog_clk ( { ctsbuf_net_2381156 } ) ,
    .chanx_left_in ( sb_1__1__74_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__85_chanx_left_out ) , 
    .ccff_head ( sb_1__1__85_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__85_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__85_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__85_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__85_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__85_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__85_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__85_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__85_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__85_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__85_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__85_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__85_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__85_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__85_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__85_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__85_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__85_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__85_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__85_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1800 ) , 
    .SC_IN_BOT ( scff_Wires_204_ ) , .SC_OUT_TOP ( scff_Wires_205_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1801 ) ) ;
cbx_1__1_ cbx_8__10_ (
    .prog_clk ( { ctsbuf_net_1901108 } ) ,
    .chanx_left_in ( sb_1__1__75_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__86_chanx_left_out ) , 
    .ccff_head ( sb_1__1__86_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__86_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__86_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__86_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__86_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__86_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__86_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__86_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__86_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__86_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__86_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__86_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__86_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__86_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__86_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__86_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__86_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__86_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__86_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__86_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1802 ) , 
    .SC_IN_BOT ( scff_Wires_206_ ) , .SC_OUT_TOP ( scff_Wires_207_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1803 ) ) ;
cbx_1__1_ cbx_8__11_ (
    .prog_clk ( { ctsbuf_net_1441062 } ) ,
    .chanx_left_in ( sb_1__1__76_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__87_chanx_left_out ) , 
    .ccff_head ( sb_1__1__87_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__87_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__87_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__87_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__87_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__87_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__87_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__87_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__87_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__87_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__87_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__87_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__87_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__87_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__87_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__87_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__87_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__87_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__87_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__87_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1804 ) , 
    .SC_IN_BOT ( scff_Wires_208_ ) , .SC_OUT_TOP ( scff_Wires_209_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1805 ) ) ;
cbx_1__1_ cbx_9__1_ (
    .prog_clk ( { ctsbuf_net_5401458 } ) ,
    .chanx_left_in ( sb_1__1__77_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__88_chanx_left_out ) , 
    .ccff_head ( sb_1__1__88_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__88_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__88_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__88_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__88_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__88_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__88_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__88_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__88_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__88_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__88_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__88_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__88_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__88_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__88_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__88_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__88_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__88_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__88_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__88_ccff_tail ) , .SC_IN_TOP ( scff_Wires_234_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1806 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1807 ) , 
    .SC_OUT_BOT ( scff_Wires_235_ ) ) ;
cbx_1__1_ cbx_9__2_ (
    .prog_clk ( { ctsbuf_net_5111429 } ) ,
    .chanx_left_in ( sb_1__1__78_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__89_chanx_left_out ) , 
    .ccff_head ( sb_1__1__89_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__89_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__89_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__89_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__89_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__89_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__89_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__89_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__89_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__89_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__89_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__89_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__89_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__89_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__89_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__89_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__89_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__89_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__89_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__89_ccff_tail ) , .SC_IN_TOP ( scff_Wires_232_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1808 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1809 ) , 
    .SC_OUT_BOT ( scff_Wires_233_ ) ) ;
cbx_1__1_ cbx_9__3_ (
    .prog_clk ( { ctsbuf_net_4741392 } ) ,
    .chanx_left_in ( sb_1__1__79_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__90_chanx_left_out ) , 
    .ccff_head ( sb_1__1__90_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__90_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__90_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__90_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__90_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__90_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__90_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__90_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__90_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__90_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__90_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__90_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__90_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__90_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__90_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__90_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__90_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__90_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__90_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__90_ccff_tail ) , .SC_IN_TOP ( scff_Wires_230_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1810 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1811 ) , 
    .SC_OUT_BOT ( scff_Wires_231_ ) ) ;
cbx_1__1_ cbx_9__4_ (
    .prog_clk ( { ctsbuf_net_4291347 } ) ,
    .chanx_left_in ( sb_1__1__80_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__91_chanx_left_out ) , 
    .ccff_head ( sb_1__1__91_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__91_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__91_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__91_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__91_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__91_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__91_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__91_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__91_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__91_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__91_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__91_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__91_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__91_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__91_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__91_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__91_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__91_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__91_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__91_ccff_tail ) , .SC_IN_TOP ( scff_Wires_228_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1812 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1813 ) , 
    .SC_OUT_BOT ( scff_Wires_229_ ) ) ;
cbx_1__1_ cbx_9__5_ (
    .prog_clk ( { ctsbuf_net_3811299 } ) ,
    .chanx_left_in ( sb_1__1__81_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__92_chanx_left_out ) , 
    .ccff_head ( sb_1__1__92_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__92_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__92_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__92_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__92_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__92_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__92_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__92_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__92_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__92_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__92_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__92_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__92_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__92_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__92_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__92_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__92_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__92_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__92_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__92_ccff_tail ) , .SC_IN_TOP ( scff_Wires_226_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1814 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1815 ) , 
    .SC_OUT_BOT ( scff_Wires_227_ ) ) ;
cbx_1__1_ cbx_9__6_ (
    .prog_clk ( { ctsbuf_net_3331251 } ) ,
    .chanx_left_in ( sb_1__1__82_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__93_chanx_left_out ) , 
    .ccff_head ( sb_1__1__93_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__93_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__93_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__93_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__93_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__93_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__93_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__93_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__93_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__93_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__93_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__93_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__93_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__93_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__93_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__93_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__93_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__93_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__93_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__93_ccff_tail ) , .SC_IN_TOP ( scff_Wires_224_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1816 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1817 ) , 
    .SC_OUT_BOT ( scff_Wires_225_ ) ) ;
cbx_1__1_ cbx_9__7_ (
    .prog_clk ( { ctsbuf_net_2851203 } ) ,
    .chanx_left_in ( sb_1__1__83_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__94_chanx_left_out ) , 
    .ccff_head ( sb_1__1__94_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__94_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__94_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__94_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__94_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__94_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__94_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__94_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__94_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__94_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__94_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__94_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__94_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__94_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__94_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__94_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__94_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__94_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__94_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__94_ccff_tail ) , .SC_IN_TOP ( scff_Wires_222_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1818 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1819 ) , 
    .SC_OUT_BOT ( scff_Wires_223_ ) ) ;
cbx_1__1_ cbx_9__8_ (
    .prog_clk ( { ctsbuf_net_2371155 } ) ,
    .chanx_left_in ( sb_1__1__84_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__95_chanx_left_out ) , 
    .ccff_head ( sb_1__1__95_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__95_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__95_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__95_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__95_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__95_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__95_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__95_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__95_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__95_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__95_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__95_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__95_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__95_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__95_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__95_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__95_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__95_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__95_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__95_ccff_tail ) , .SC_IN_TOP ( scff_Wires_220_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1820 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1821 ) , 
    .SC_OUT_BOT ( scff_Wires_221_ ) ) ;
cbx_1__1_ cbx_9__9_ (
    .prog_clk ( { ctsbuf_net_1891107 } ) ,
    .chanx_left_in ( sb_1__1__85_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__96_chanx_left_out ) , 
    .ccff_head ( sb_1__1__96_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__96_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__96_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__96_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__96_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__96_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__96_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__96_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__96_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__96_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__96_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__96_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__96_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__96_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__96_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__96_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__96_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__96_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__96_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__96_ccff_tail ) , .SC_IN_TOP ( scff_Wires_218_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1822 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1823 ) , 
    .SC_OUT_BOT ( scff_Wires_219_ ) ) ;
cbx_1__1_ cbx_9__10_ (
    .prog_clk ( { ctsbuf_net_1431061 } ) ,
    .chanx_left_in ( sb_1__1__86_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__97_chanx_left_out ) , 
    .ccff_head ( sb_1__1__97_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__97_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__97_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__97_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__97_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__97_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__97_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__97_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__97_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__97_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__97_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__97_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__97_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__97_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__97_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__97_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__97_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__97_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__97_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__97_ccff_tail ) , .SC_IN_TOP ( scff_Wires_216_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1824 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1825 ) , 
    .SC_OUT_BOT ( scff_Wires_217_ ) ) ;
cbx_1__1_ cbx_9__11_ (
    .prog_clk ( { ctsbuf_net_1021020 } ) ,
    .chanx_left_in ( sb_1__1__87_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__98_chanx_left_out ) , 
    .ccff_head ( sb_1__1__98_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__98_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__98_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__98_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__98_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__98_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__98_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__98_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__98_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__98_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__98_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__98_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__98_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__98_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__98_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__98_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__98_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__98_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__98_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__98_ccff_tail ) , .SC_IN_TOP ( scff_Wires_214_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1826 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1827 ) , 
    .SC_OUT_BOT ( scff_Wires_215_ ) ) ;
cbx_1__1_ cbx_10__1_ (
    .prog_clk ( { ctsbuf_net_5091427 } ) ,
    .chanx_left_in ( sb_1__1__88_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__99_chanx_left_out ) , 
    .ccff_head ( sb_1__1__99_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__99_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__99_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__99_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__99_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__99_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__99_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__99_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__99_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__99_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__99_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__99_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__99_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__99_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__99_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__99_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__99_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__99_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__99_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__99_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1828 ) , 
    .SC_IN_BOT ( scff_Wires_241_ ) , .SC_OUT_TOP ( scff_Wires_242_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1829 ) ) ;
cbx_1__1_ cbx_10__2_ (
    .prog_clk ( { ctsbuf_net_4721390 } ) ,
    .chanx_left_in ( sb_1__1__89_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__100_chanx_left_out ) , 
    .ccff_head ( sb_1__1__100_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__100_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__100_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__100_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__100_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__100_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__100_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__100_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__100_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__100_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__100_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__100_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__100_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__100_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__100_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__100_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__100_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__100_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__100_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__100_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1830 ) , 
    .SC_IN_BOT ( scff_Wires_243_ ) , .SC_OUT_TOP ( scff_Wires_244_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1831 ) ) ;
cbx_1__1_ cbx_10__3_ (
    .prog_clk ( { ctsbuf_net_4271345 } ) ,
    .chanx_left_in ( sb_1__1__90_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__101_chanx_left_out ) , 
    .ccff_head ( sb_1__1__101_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__101_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__101_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__101_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__101_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__101_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__101_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__101_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__101_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__101_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__101_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__101_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__101_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__101_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__101_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__101_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__101_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__101_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__101_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__101_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1832 ) , 
    .SC_IN_BOT ( scff_Wires_245_ ) , .SC_OUT_TOP ( scff_Wires_246_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1833 ) ) ;
cbx_1__1_ cbx_10__4_ (
    .prog_clk ( { ctsbuf_net_3791297 } ) ,
    .chanx_left_in ( sb_1__1__91_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__102_chanx_left_out ) , 
    .ccff_head ( sb_1__1__102_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__102_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__102_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__102_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__102_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__102_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__102_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__102_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__102_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__102_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__102_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__102_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__102_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__102_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__102_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__102_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__102_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__102_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__102_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__102_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1834 ) , 
    .SC_IN_BOT ( scff_Wires_247_ ) , .SC_OUT_TOP ( scff_Wires_248_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1835 ) ) ;
cbx_1__1_ cbx_10__5_ (
    .prog_clk ( { ctsbuf_net_3311249 } ) ,
    .chanx_left_in ( sb_1__1__92_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__103_chanx_left_out ) , 
    .ccff_head ( sb_1__1__103_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__103_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__103_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__103_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__103_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__103_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__103_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__103_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__103_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__103_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__103_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__103_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__103_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__103_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__103_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__103_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__103_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__103_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__103_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__103_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1836 ) , 
    .SC_IN_BOT ( scff_Wires_249_ ) , .SC_OUT_TOP ( scff_Wires_250_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1837 ) ) ;
cbx_1__1_ cbx_10__6_ (
    .prog_clk ( { ctsbuf_net_2831201 } ) ,
    .chanx_left_in ( sb_1__1__93_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__104_chanx_left_out ) , 
    .ccff_head ( sb_1__1__104_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__104_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__104_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__104_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__104_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__104_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__104_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__104_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__104_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__104_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__104_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__104_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__104_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__104_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__104_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__104_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__104_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__104_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__104_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__104_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1838 ) , 
    .SC_IN_BOT ( scff_Wires_251_ ) , .SC_OUT_TOP ( scff_Wires_252_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1839 ) ) ;
cbx_1__1_ cbx_10__7_ (
    .prog_clk ( { ctsbuf_net_2351153 } ) ,
    .chanx_left_in ( sb_1__1__94_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__105_chanx_left_out ) , 
    .ccff_head ( sb_1__1__105_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__105_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__105_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__105_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__105_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__105_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__105_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__105_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__105_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__105_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__105_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__105_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__105_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__105_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__105_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__105_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__105_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__105_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__105_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__105_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1840 ) , 
    .SC_IN_BOT ( scff_Wires_253_ ) , .SC_OUT_TOP ( scff_Wires_254_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1841 ) ) ;
cbx_1__1_ cbx_10__8_ (
    .prog_clk ( { ctsbuf_net_1871105 } ) ,
    .chanx_left_in ( sb_1__1__95_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__106_chanx_left_out ) , 
    .ccff_head ( sb_1__1__106_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__106_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__106_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__106_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__106_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__106_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__106_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__106_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__106_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__106_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__106_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__106_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__106_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__106_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__106_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__106_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__106_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__106_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__106_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__106_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1842 ) , 
    .SC_IN_BOT ( scff_Wires_255_ ) , .SC_OUT_TOP ( scff_Wires_256_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1843 ) ) ;
cbx_1__1_ cbx_10__9_ (
    .prog_clk ( { ctsbuf_net_1411059 } ) ,
    .chanx_left_in ( sb_1__1__96_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__107_chanx_left_out ) , 
    .ccff_head ( sb_1__1__107_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__107_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__107_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__107_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__107_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__107_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__107_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__107_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__107_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__107_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__107_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__107_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__107_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__107_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__107_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__107_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__107_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__107_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__107_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__107_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1844 ) , 
    .SC_IN_BOT ( scff_Wires_257_ ) , .SC_OUT_TOP ( scff_Wires_258_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1845 ) ) ;
cbx_1__1_ cbx_10__10_ (
    .prog_clk ( { ctsbuf_net_1011019 } ) ,
    .chanx_left_in ( sb_1__1__97_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__108_chanx_left_out ) , 
    .ccff_head ( sb_1__1__108_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__108_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__108_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__108_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__108_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__108_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__108_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__108_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__108_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__108_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__108_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__108_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__108_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__108_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__108_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__108_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__108_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__108_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__108_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__108_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1846 ) , 
    .SC_IN_BOT ( scff_Wires_259_ ) , .SC_OUT_TOP ( scff_Wires_260_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1847 ) ) ;
cbx_1__1_ cbx_10__11_ (
    .prog_clk ( { ctsbuf_net_67985 } ) ,
    .chanx_left_in ( sb_1__1__98_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__109_chanx_left_out ) , 
    .ccff_head ( sb_1__1__109_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__109_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__109_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__109_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__109_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__109_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__109_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__109_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__109_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__109_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__109_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__109_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__109_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__109_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__109_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__109_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__109_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__109_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__109_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__109_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1848 ) , 
    .SC_IN_BOT ( scff_Wires_261_ ) , .SC_OUT_TOP ( scff_Wires_262_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1849 ) ) ;
cbx_1__1_ cbx_11__1_ (
    .prog_clk ( { ctsbuf_net_4701388 } ) ,
    .chanx_left_in ( sb_1__1__99_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__110_chanx_left_out ) , 
    .ccff_head ( sb_1__1__110_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__110_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__110_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__110_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__110_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__110_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__110_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__110_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__110_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__110_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__110_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__110_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__110_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__110_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__110_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__110_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__110_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__110_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__110_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__110_ccff_tail ) , .SC_IN_TOP ( scff_Wires_287_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1850 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1851 ) , 
    .SC_OUT_BOT ( scff_Wires_288_ ) ) ;
cbx_1__1_ cbx_11__2_ (
    .prog_clk ( { ctsbuf_net_4251343 } ) ,
    .chanx_left_in ( sb_1__1__100_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__111_chanx_left_out ) , 
    .ccff_head ( sb_1__1__111_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__111_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__111_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__111_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__111_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__111_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__111_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__111_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__111_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__111_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__111_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__111_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__111_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__111_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__111_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__111_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__111_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__111_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__111_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__111_ccff_tail ) , .SC_IN_TOP ( scff_Wires_285_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1852 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1853 ) , 
    .SC_OUT_BOT ( scff_Wires_286_ ) ) ;
cbx_1__1_ cbx_11__3_ (
    .prog_clk ( { ctsbuf_net_3771295 } ) ,
    .chanx_left_in ( sb_1__1__101_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__112_chanx_left_out ) , 
    .ccff_head ( sb_1__1__112_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__112_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__112_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__112_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__112_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__112_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__112_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__112_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__112_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__112_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__112_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__112_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__112_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__112_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__112_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__112_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__112_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__112_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__112_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__112_ccff_tail ) , .SC_IN_TOP ( scff_Wires_283_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1854 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1855 ) , 
    .SC_OUT_BOT ( scff_Wires_284_ ) ) ;
cbx_1__1_ cbx_11__4_ (
    .prog_clk ( { ctsbuf_net_3291247 } ) ,
    .chanx_left_in ( sb_1__1__102_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__113_chanx_left_out ) , 
    .ccff_head ( sb_1__1__113_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__113_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__113_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__113_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__113_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__113_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__113_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__113_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__113_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__113_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__113_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__113_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__113_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__113_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__113_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__113_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__113_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__113_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__113_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__113_ccff_tail ) , .SC_IN_TOP ( scff_Wires_281_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1856 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1857 ) , 
    .SC_OUT_BOT ( scff_Wires_282_ ) ) ;
cbx_1__1_ cbx_11__5_ (
    .prog_clk ( { ctsbuf_net_2811199 } ) ,
    .chanx_left_in ( sb_1__1__103_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__114_chanx_left_out ) , 
    .ccff_head ( sb_1__1__114_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__114_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__114_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__114_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__114_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__114_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__114_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__114_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__114_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__114_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__114_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__114_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__114_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__114_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__114_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__114_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__114_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__114_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__114_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__114_ccff_tail ) , .SC_IN_TOP ( scff_Wires_279_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1858 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1859 ) , 
    .SC_OUT_BOT ( scff_Wires_280_ ) ) ;
cbx_1__1_ cbx_11__6_ (
    .prog_clk ( { ctsbuf_net_2331151 } ) ,
    .chanx_left_in ( sb_1__1__104_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__115_chanx_left_out ) , 
    .ccff_head ( sb_1__1__115_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__115_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__115_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__115_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__115_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__115_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__115_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__115_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__115_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__115_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__115_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__115_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__115_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__115_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__115_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__115_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__115_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__115_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__115_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__115_ccff_tail ) , .SC_IN_TOP ( scff_Wires_277_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1860 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1861 ) , 
    .SC_OUT_BOT ( scff_Wires_278_ ) ) ;
cbx_1__1_ cbx_11__7_ (
    .prog_clk ( { ctsbuf_net_1851103 } ) ,
    .chanx_left_in ( sb_1__1__105_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__116_chanx_left_out ) , 
    .ccff_head ( sb_1__1__116_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__116_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__116_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__116_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__116_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__116_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__116_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__116_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__116_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__116_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__116_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__116_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__116_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__116_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__116_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__116_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__116_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__116_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__116_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__116_ccff_tail ) , .SC_IN_TOP ( scff_Wires_275_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1862 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1863 ) , 
    .SC_OUT_BOT ( scff_Wires_276_ ) ) ;
cbx_1__1_ cbx_11__8_ (
    .prog_clk ( { ctsbuf_net_1391057 } ) ,
    .chanx_left_in ( sb_1__1__106_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__117_chanx_left_out ) , 
    .ccff_head ( sb_1__1__117_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__117_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__117_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__117_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__117_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__117_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__117_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__117_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__117_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__117_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__117_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__117_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__117_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__117_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__117_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__117_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__117_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__117_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__117_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__117_ccff_tail ) , .SC_IN_TOP ( scff_Wires_273_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1864 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1865 ) , 
    .SC_OUT_BOT ( scff_Wires_274_ ) ) ;
cbx_1__1_ cbx_11__9_ (
    .prog_clk ( { ctsbuf_net_991017 } ) ,
    .chanx_left_in ( sb_1__1__107_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__118_chanx_left_out ) , 
    .ccff_head ( sb_1__1__118_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__118_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__118_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__118_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__118_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__118_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__118_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__118_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__118_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__118_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__118_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__118_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__118_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__118_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__118_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__118_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__118_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__118_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__118_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__118_ccff_tail ) , .SC_IN_TOP ( scff_Wires_271_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1866 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1867 ) , 
    .SC_OUT_BOT ( scff_Wires_272_ ) ) ;
cbx_1__1_ cbx_11__10_ (
    .prog_clk ( { ctsbuf_net_66984 } ) ,
    .chanx_left_in ( sb_1__1__108_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__119_chanx_left_out ) , 
    .ccff_head ( sb_1__1__119_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__119_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__119_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__119_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__119_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__119_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__119_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__119_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__119_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__119_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__119_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__119_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__119_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__119_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__119_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__119_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__119_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__119_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__119_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__119_ccff_tail ) , .SC_IN_TOP ( scff_Wires_269_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1868 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1869 ) , 
    .SC_OUT_BOT ( scff_Wires_270_ ) ) ;
cbx_1__1_ cbx_11__11_ (
    .prog_clk ( { ctsbuf_net_40958 } ) ,
    .chanx_left_in ( sb_1__1__109_chanx_right_out ) , 
    .chanx_right_in ( sb_1__1__120_chanx_left_out ) , 
    .ccff_head ( sb_1__1__120_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__120_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__120_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__120_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__120_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__120_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__120_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__120_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__120_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__120_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__120_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__120_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__120_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__120_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__120_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__120_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__120_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__120_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__120_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__120_ccff_tail ) , .SC_IN_TOP ( scff_Wires_267_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1870 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1871 ) , 
    .SC_OUT_BOT ( scff_Wires_268_ ) ) ;
cbx_1__1_ cbx_12__1_ (
    .prog_clk ( { ctsbuf_net_4231341 } ) ,
    .chanx_left_in ( sb_1__1__110_chanx_right_out ) , 
    .chanx_right_in ( sb_12__1__0_chanx_left_out ) , 
    .ccff_head ( sb_12__1__0_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__121_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__121_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__121_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__121_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__121_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__121_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__121_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__121_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__121_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__121_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__121_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__121_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__121_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__121_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__121_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__121_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__121_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__121_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__121_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1872 ) , 
    .SC_IN_BOT ( scff_Wires_294_ ) , .SC_OUT_TOP ( scff_Wires_295_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1873 ) ) ;
cbx_1__1_ cbx_12__2_ (
    .prog_clk ( { ctsbuf_net_3751293 } ) ,
    .chanx_left_in ( sb_1__1__111_chanx_right_out ) , 
    .chanx_right_in ( sb_12__1__1_chanx_left_out ) , 
    .ccff_head ( sb_12__1__1_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__122_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__122_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__122_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__122_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__122_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__122_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__122_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__122_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__122_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__122_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__122_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__122_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__122_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__122_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__122_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__122_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__122_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__122_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__122_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1874 ) , 
    .SC_IN_BOT ( scff_Wires_296_ ) , .SC_OUT_TOP ( scff_Wires_297_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1875 ) ) ;
cbx_1__1_ cbx_12__3_ (
    .prog_clk ( { ctsbuf_net_3271245 } ) ,
    .chanx_left_in ( sb_1__1__112_chanx_right_out ) , 
    .chanx_right_in ( sb_12__1__2_chanx_left_out ) , 
    .ccff_head ( sb_12__1__2_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__123_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__123_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__123_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__123_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__123_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__123_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__123_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__123_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__123_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__123_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__123_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__123_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__123_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__123_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__123_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__123_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__123_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__123_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__123_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1876 ) , 
    .SC_IN_BOT ( scff_Wires_298_ ) , .SC_OUT_TOP ( scff_Wires_299_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1877 ) ) ;
cbx_1__1_ cbx_12__4_ (
    .prog_clk ( { ctsbuf_net_2791197 } ) ,
    .chanx_left_in ( sb_1__1__113_chanx_right_out ) , 
    .chanx_right_in ( sb_12__1__3_chanx_left_out ) , 
    .ccff_head ( sb_12__1__3_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__124_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__124_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__124_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__124_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__124_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__124_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__124_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__124_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__124_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__124_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__124_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__124_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__124_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__124_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__124_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__124_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__124_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__124_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__124_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1878 ) , 
    .SC_IN_BOT ( scff_Wires_300_ ) , .SC_OUT_TOP ( scff_Wires_301_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1879 ) ) ;
cbx_1__1_ cbx_12__5_ (
    .prog_clk ( { ctsbuf_net_2311149 } ) ,
    .chanx_left_in ( sb_1__1__114_chanx_right_out ) , 
    .chanx_right_in ( sb_12__1__4_chanx_left_out ) , 
    .ccff_head ( sb_12__1__4_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__125_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__125_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__125_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__125_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__125_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__125_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__125_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__125_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__125_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__125_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__125_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__125_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__125_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__125_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__125_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__125_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__125_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__125_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__125_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1880 ) , 
    .SC_IN_BOT ( scff_Wires_302_ ) , .SC_OUT_TOP ( scff_Wires_303_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1881 ) ) ;
cbx_1__1_ cbx_12__6_ (
    .prog_clk ( { ctsbuf_net_1831101 } ) ,
    .chanx_left_in ( sb_1__1__115_chanx_right_out ) , 
    .chanx_right_in ( sb_12__1__5_chanx_left_out ) , 
    .ccff_head ( sb_12__1__5_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__126_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__126_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__126_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__126_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__126_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__126_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__126_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__126_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__126_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__126_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__126_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__126_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__126_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__126_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__126_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__126_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__126_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__126_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__126_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1882 ) , 
    .SC_IN_BOT ( scff_Wires_304_ ) , .SC_OUT_TOP ( scff_Wires_305_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1883 ) ) ;
cbx_1__1_ cbx_12__7_ (
    .prog_clk ( { ctsbuf_net_1371055 } ) ,
    .chanx_left_in ( sb_1__1__116_chanx_right_out ) , 
    .chanx_right_in ( sb_12__1__6_chanx_left_out ) , 
    .ccff_head ( sb_12__1__6_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__127_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__127_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__127_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__127_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__127_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__127_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__127_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__127_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__127_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__127_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__127_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__127_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__127_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__127_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__127_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__127_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__127_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__127_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__127_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1884 ) , 
    .SC_IN_BOT ( scff_Wires_306_ ) , .SC_OUT_TOP ( scff_Wires_307_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1885 ) ) ;
cbx_1__1_ cbx_12__8_ (
    .prog_clk ( { ctsbuf_net_971015 } ) ,
    .chanx_left_in ( sb_1__1__117_chanx_right_out ) , 
    .chanx_right_in ( sb_12__1__7_chanx_left_out ) , 
    .ccff_head ( sb_12__1__7_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__128_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__128_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__128_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__128_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__128_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__128_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__128_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__128_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__128_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__128_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__128_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__128_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__128_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__128_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__128_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__128_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__128_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__128_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__128_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1886 ) , 
    .SC_IN_BOT ( scff_Wires_308_ ) , .SC_OUT_TOP ( scff_Wires_309_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1887 ) ) ;
cbx_1__1_ cbx_12__9_ (
    .prog_clk ( { ctsbuf_net_64982 } ) ,
    .chanx_left_in ( sb_1__1__118_chanx_right_out ) , 
    .chanx_right_in ( sb_12__1__8_chanx_left_out ) , 
    .ccff_head ( sb_12__1__8_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__129_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__129_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__129_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__129_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__129_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__129_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__129_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__129_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__129_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__129_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__129_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__129_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__129_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__129_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__129_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__129_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__129_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__129_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__129_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1888 ) , 
    .SC_IN_BOT ( scff_Wires_310_ ) , .SC_OUT_TOP ( scff_Wires_311_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1889 ) ) ;
cbx_1__1_ cbx_12__10_ (
    .prog_clk ( { ctsbuf_net_39957 } ) ,
    .chanx_left_in ( sb_1__1__119_chanx_right_out ) , 
    .chanx_right_in ( sb_12__1__9_chanx_left_out ) , 
    .ccff_head ( sb_12__1__9_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__130_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__130_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__130_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__130_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__130_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__130_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__130_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__130_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__130_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__130_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__130_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__130_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__130_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__130_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__130_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__130_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__130_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__130_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__130_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1890 ) , 
    .SC_IN_BOT ( scff_Wires_312_ ) , .SC_OUT_TOP ( scff_Wires_313_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1891 ) ) ;
cbx_1__1_ cbx_12__11_ (
    .prog_clk ( { ctsbuf_net_21939 } ) ,
    .chanx_left_in ( sb_1__1__120_chanx_right_out ) , 
    .chanx_right_in ( sb_12__1__10_chanx_left_out ) , 
    .ccff_head ( sb_12__1__10_ccff_tail ) , 
    .chanx_left_out ( cbx_1__1__131_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__1__131_chanx_right_out ) , 
    .bottom_grid_pin_0_ ( cbx_1__1__131_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__1__131_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__1__131_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__1__131_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__1__131_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__1__131_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__1__131_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__1__131_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__1__131_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__1__131_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__1__131_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__1__131_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__1__131_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__1__131_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__1__131_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__1__131_bottom_grid_pin_15_ ) , 
    .ccff_tail ( cbx_1__1__131_ccff_tail ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1892 ) , 
    .SC_IN_BOT ( scff_Wires_314_ ) , .SC_OUT_TOP ( scff_Wires_315_ ) , 
    .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1893 ) ) ;
cbx_1__2_ cbx_1__12_ (
    .prog_clk ( { ctsbuf_net_8926 } ) ,
    .chanx_left_in ( sb_0__12__0_chanx_right_out ) , 
    .chanx_right_in ( sb_1__12__0_chanx_left_out ) , 
    .ccff_head ( sb_1__12__0_ccff_tail ) , 
    .chanx_left_out ( cbx_1__12__0_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__12__0_chanx_right_out ) , 
    .top_grid_pin_0_ ( cbx_1__12__0_top_grid_pin_0_ ) , 
    .bottom_grid_pin_0_ ( cbx_1__12__0_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__12__0_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__12__0_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__12__0_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__12__0_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__12__0_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__12__0_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__12__0_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__12__0_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__12__0_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__12__0_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__12__0_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__12__0_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__12__0_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__12__0_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__12__0_bottom_grid_pin_15_ ) , 
    .ccff_tail ( grid_io_top_0_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , 
    .bottom_width_0_height_0__pin_0_ ( cbx_1__12__0_top_grid_pin_0_ ) , 
    .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , 
    .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , 
    .SC_IN_TOP ( scff_Wires_0_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1894 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1895 ) , 
    .SC_OUT_BOT ( scff_Wires_1_ ) ) ;
cbx_1__2_ cbx_2__12_ (
    .prog_clk ( { ctsbuf_net_17935 } ) ,
    .chanx_left_in ( sb_1__12__0_chanx_right_out ) , 
    .chanx_right_in ( sb_1__12__1_chanx_left_out ) , 
    .ccff_head ( sb_1__12__1_ccff_tail ) , 
    .chanx_left_out ( cbx_1__12__1_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__12__1_chanx_right_out ) , 
    .top_grid_pin_0_ ( cbx_1__12__1_top_grid_pin_0_ ) , 
    .bottom_grid_pin_0_ ( cbx_1__12__1_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__12__1_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__12__1_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__12__1_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__12__1_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__12__1_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__12__1_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__12__1_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__12__1_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__12__1_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__12__1_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__12__1_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__12__1_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__12__1_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__12__1_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__12__1_bottom_grid_pin_15_ ) , 
    .ccff_tail ( grid_io_top_1_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , 
    .bottom_width_0_height_0__pin_0_ ( cbx_1__12__1_top_grid_pin_0_ ) , 
    .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , 
    .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1896 ) , .SC_IN_BOT ( scff_Wires_51_ ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1897 ) , 
    .SC_OUT_BOT ( scff_Wires_52_ ) ) ;
cbx_1__2_ cbx_3__12_ (
    .prog_clk ( { ctsbuf_net_34952 } ) ,
    .chanx_left_in ( sb_1__12__1_chanx_right_out ) , 
    .chanx_right_in ( sb_1__12__2_chanx_left_out ) , 
    .ccff_head ( sb_1__12__2_ccff_tail ) , 
    .chanx_left_out ( cbx_1__12__2_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__12__2_chanx_right_out ) , 
    .top_grid_pin_0_ ( cbx_1__12__2_top_grid_pin_0_ ) , 
    .bottom_grid_pin_0_ ( cbx_1__12__2_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__12__2_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__12__2_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__12__2_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__12__2_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__12__2_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__12__2_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__12__2_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__12__2_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__12__2_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__12__2_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__12__2_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__12__2_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__12__2_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__12__2_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__12__2_bottom_grid_pin_15_ ) , 
    .ccff_tail ( grid_io_top_2_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , 
    .bottom_width_0_height_0__pin_0_ ( cbx_1__12__2_top_grid_pin_0_ ) , 
    .bottom_width_0_height_0__pin_1_upper ( grid_io_top_2_bottom_width_0_height_0__pin_1_upper ) , 
    .bottom_width_0_height_0__pin_1_lower ( grid_io_top_2_bottom_width_0_height_0__pin_1_lower ) , 
    .SC_IN_TOP ( scff_Wires_53_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1898 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1899 ) , 
    .SC_OUT_BOT ( scff_Wires_54_ ) ) ;
cbx_1__2_ cbx_4__12_ (
    .prog_clk ( { ctsbuf_net_59977 } ) ,
    .chanx_left_in ( sb_1__12__2_chanx_right_out ) , 
    .chanx_right_in ( sb_1__12__3_chanx_left_out ) , 
    .ccff_head ( sb_1__12__3_ccff_tail ) , 
    .chanx_left_out ( cbx_1__12__3_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__12__3_chanx_right_out ) , 
    .top_grid_pin_0_ ( cbx_1__12__3_top_grid_pin_0_ ) , 
    .bottom_grid_pin_0_ ( cbx_1__12__3_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__12__3_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__12__3_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__12__3_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__12__3_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__12__3_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__12__3_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__12__3_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__12__3_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__12__3_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__12__3_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__12__3_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__12__3_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__12__3_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__12__3_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__12__3_bottom_grid_pin_15_ ) , 
    .ccff_tail ( grid_io_top_3_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , 
    .bottom_width_0_height_0__pin_0_ ( cbx_1__12__3_top_grid_pin_0_ ) , 
    .bottom_width_0_height_0__pin_1_upper ( grid_io_top_3_bottom_width_0_height_0__pin_1_upper ) , 
    .bottom_width_0_height_0__pin_1_lower ( grid_io_top_3_bottom_width_0_height_0__pin_1_lower ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1900 ) , 
    .SC_IN_BOT ( scff_Wires_104_ ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1901 ) , 
    .SC_OUT_BOT ( scff_Wires_105_ ) ) ;
cbx_1__2_ cbx_5__12_ (
    .prog_clk ( { ctsbuf_net_921010 } ) ,
    .chanx_left_in ( sb_1__12__3_chanx_right_out ) , 
    .chanx_right_in ( sb_1__12__4_chanx_left_out ) , 
    .ccff_head ( sb_1__12__4_ccff_tail ) , 
    .chanx_left_out ( cbx_1__12__4_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__12__4_chanx_right_out ) , 
    .top_grid_pin_0_ ( cbx_1__12__4_top_grid_pin_0_ ) , 
    .bottom_grid_pin_0_ ( cbx_1__12__4_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__12__4_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__12__4_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__12__4_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__12__4_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__12__4_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__12__4_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__12__4_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__12__4_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__12__4_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__12__4_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__12__4_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__12__4_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__12__4_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__12__4_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__12__4_bottom_grid_pin_15_ ) , 
    .ccff_tail ( grid_io_top_4_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) , 
    .bottom_width_0_height_0__pin_0_ ( cbx_1__12__4_top_grid_pin_0_ ) , 
    .bottom_width_0_height_0__pin_1_upper ( grid_io_top_4_bottom_width_0_height_0__pin_1_upper ) , 
    .bottom_width_0_height_0__pin_1_lower ( grid_io_top_4_bottom_width_0_height_0__pin_1_lower ) , 
    .SC_IN_TOP ( scff_Wires_106_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1902 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1903 ) , 
    .SC_OUT_BOT ( scff_Wires_107_ ) ) ;
cbx_1__2_ cbx_6__12_ (
    .prog_clk ( { ctsbuf_net_1321050 } ) ,
    .chanx_left_in ( sb_1__12__4_chanx_right_out ) , 
    .chanx_right_in ( sb_1__12__5_chanx_left_out ) , 
    .ccff_head ( sb_1__12__5_ccff_tail ) , 
    .chanx_left_out ( cbx_1__12__5_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__12__5_chanx_right_out ) , 
    .top_grid_pin_0_ ( cbx_1__12__5_top_grid_pin_0_ ) , 
    .bottom_grid_pin_0_ ( cbx_1__12__5_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__12__5_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__12__5_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__12__5_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__12__5_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__12__5_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__12__5_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__12__5_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__12__5_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__12__5_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__12__5_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__12__5_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__12__5_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__12__5_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__12__5_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__12__5_bottom_grid_pin_15_ ) , 
    .ccff_tail ( grid_io_top_5_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , 
    .bottom_width_0_height_0__pin_0_ ( cbx_1__12__5_top_grid_pin_0_ ) , 
    .bottom_width_0_height_0__pin_1_upper ( grid_io_top_5_bottom_width_0_height_0__pin_1_upper ) , 
    .bottom_width_0_height_0__pin_1_lower ( grid_io_top_5_bottom_width_0_height_0__pin_1_lower ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1904 ) , 
    .SC_IN_BOT ( scff_Wires_157_ ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1905 ) , 
    .SC_OUT_BOT ( scff_Wires_158_ ) ) ;
cbx_1__2_ cbx_7__12_ (
    .prog_clk ( { ctsbuf_net_1221040 } ) ,
    .chanx_left_in ( sb_1__12__5_chanx_right_out ) , 
    .chanx_right_in ( sb_1__12__6_chanx_left_out ) , 
    .ccff_head ( sb_1__12__6_ccff_tail ) , 
    .chanx_left_out ( cbx_1__12__6_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__12__6_chanx_right_out ) , 
    .top_grid_pin_0_ ( cbx_1__12__6_top_grid_pin_0_ ) , 
    .bottom_grid_pin_0_ ( cbx_1__12__6_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__12__6_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__12__6_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__12__6_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__12__6_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__12__6_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__12__6_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__12__6_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__12__6_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__12__6_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__12__6_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__12__6_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__12__6_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__12__6_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__12__6_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__12__6_bottom_grid_pin_15_ ) , 
    .ccff_tail ( grid_io_top_6_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[6] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[6] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[6] ) , 
    .bottom_width_0_height_0__pin_0_ ( cbx_1__12__6_top_grid_pin_0_ ) , 
    .bottom_width_0_height_0__pin_1_upper ( grid_io_top_6_bottom_width_0_height_0__pin_1_upper ) , 
    .bottom_width_0_height_0__pin_1_lower ( grid_io_top_6_bottom_width_0_height_0__pin_1_lower ) , 
    .SC_IN_TOP ( scff_Wires_159_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1906 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1907 ) , 
    .SC_OUT_BOT ( scff_Wires_160_ ) ) ;
cbx_1__2_ cbx_8__12_ (
    .prog_clk ( { ctsbuf_net_831001 } ) ,
    .chanx_left_in ( sb_1__12__6_chanx_right_out ) , 
    .chanx_right_in ( sb_1__12__7_chanx_left_out ) , 
    .ccff_head ( sb_1__12__7_ccff_tail ) , 
    .chanx_left_out ( cbx_1__12__7_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__12__7_chanx_right_out ) , 
    .top_grid_pin_0_ ( cbx_1__12__7_top_grid_pin_0_ ) , 
    .bottom_grid_pin_0_ ( cbx_1__12__7_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__12__7_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__12__7_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__12__7_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__12__7_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__12__7_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__12__7_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__12__7_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__12__7_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__12__7_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__12__7_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__12__7_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__12__7_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__12__7_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__12__7_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__12__7_bottom_grid_pin_15_ ) , 
    .ccff_tail ( grid_io_top_7_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[7] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[7] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[7] ) , 
    .bottom_width_0_height_0__pin_0_ ( cbx_1__12__7_top_grid_pin_0_ ) , 
    .bottom_width_0_height_0__pin_1_upper ( grid_io_top_7_bottom_width_0_height_0__pin_1_upper ) , 
    .bottom_width_0_height_0__pin_1_lower ( grid_io_top_7_bottom_width_0_height_0__pin_1_lower ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1908 ) , 
    .SC_IN_BOT ( scff_Wires_210_ ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1909 ) , 
    .SC_OUT_BOT ( scff_Wires_211_ ) ) ;
cbx_1__2_ cbx_9__12_ (
    .prog_clk ( { ctsbuf_net_51969 } ) ,
    .chanx_left_in ( sb_1__12__7_chanx_right_out ) , 
    .chanx_right_in ( sb_1__12__8_chanx_left_out ) , 
    .ccff_head ( sb_1__12__8_ccff_tail ) , 
    .chanx_left_out ( cbx_1__12__8_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__12__8_chanx_right_out ) , 
    .top_grid_pin_0_ ( cbx_1__12__8_top_grid_pin_0_ ) , 
    .bottom_grid_pin_0_ ( cbx_1__12__8_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__12__8_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__12__8_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__12__8_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__12__8_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__12__8_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__12__8_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__12__8_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__12__8_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__12__8_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__12__8_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__12__8_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__12__8_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__12__8_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__12__8_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__12__8_bottom_grid_pin_15_ ) , 
    .ccff_tail ( grid_io_top_8_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[8] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[8] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[8] ) , 
    .bottom_width_0_height_0__pin_0_ ( cbx_1__12__8_top_grid_pin_0_ ) , 
    .bottom_width_0_height_0__pin_1_upper ( grid_io_top_8_bottom_width_0_height_0__pin_1_upper ) , 
    .bottom_width_0_height_0__pin_1_lower ( grid_io_top_8_bottom_width_0_height_0__pin_1_lower ) , 
    .SC_IN_TOP ( scff_Wires_212_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1910 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1911 ) , 
    .SC_OUT_BOT ( scff_Wires_213_ ) ) ;
cbx_1__2_ cbx_10__12_ (
    .prog_clk ( { ctsbuf_net_27945 } ) ,
    .chanx_left_in ( sb_1__12__8_chanx_right_out ) , 
    .chanx_right_in ( sb_1__12__9_chanx_left_out ) , 
    .ccff_head ( sb_1__12__9_ccff_tail ) , 
    .chanx_left_out ( cbx_1__12__9_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__12__9_chanx_right_out ) , 
    .top_grid_pin_0_ ( cbx_1__12__9_top_grid_pin_0_ ) , 
    .bottom_grid_pin_0_ ( cbx_1__12__9_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__12__9_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__12__9_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__12__9_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__12__9_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__12__9_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__12__9_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__12__9_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__12__9_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__12__9_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__12__9_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__12__9_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__12__9_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__12__9_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__12__9_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__12__9_bottom_grid_pin_15_ ) , 
    .ccff_tail ( grid_io_top_9_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[9] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[9] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[9] ) , 
    .bottom_width_0_height_0__pin_0_ ( cbx_1__12__9_top_grid_pin_0_ ) , 
    .bottom_width_0_height_0__pin_1_upper ( grid_io_top_9_bottom_width_0_height_0__pin_1_upper ) , 
    .bottom_width_0_height_0__pin_1_lower ( grid_io_top_9_bottom_width_0_height_0__pin_1_lower ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1912 ) , 
    .SC_IN_BOT ( scff_Wires_263_ ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1913 ) , 
    .SC_OUT_BOT ( scff_Wires_264_ ) ) ;
cbx_1__2_ cbx_11__12_ (
    .prog_clk ( { ctsbuf_net_14932 } ) ,
    .chanx_left_in ( sb_1__12__9_chanx_right_out ) , 
    .chanx_right_in ( sb_1__12__10_chanx_left_out ) , 
    .ccff_head ( sb_1__12__10_ccff_tail ) , 
    .chanx_left_out ( cbx_1__12__10_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__12__10_chanx_right_out ) , 
    .top_grid_pin_0_ ( cbx_1__12__10_top_grid_pin_0_ ) , 
    .bottom_grid_pin_0_ ( cbx_1__12__10_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__12__10_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__12__10_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__12__10_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__12__10_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__12__10_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__12__10_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__12__10_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__12__10_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__12__10_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__12__10_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__12__10_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__12__10_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__12__10_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__12__10_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__12__10_bottom_grid_pin_15_ ) , 
    .ccff_tail ( grid_io_top_10_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[10] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[10] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[10] ) , 
    .bottom_width_0_height_0__pin_0_ ( cbx_1__12__10_top_grid_pin_0_ ) , 
    .bottom_width_0_height_0__pin_1_upper ( grid_io_top_10_bottom_width_0_height_0__pin_1_upper ) , 
    .bottom_width_0_height_0__pin_1_lower ( grid_io_top_10_bottom_width_0_height_0__pin_1_lower ) , 
    .SC_IN_TOP ( scff_Wires_265_ ) , 
    .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1914 ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1915 ) , 
    .SC_OUT_BOT ( scff_Wires_266_ ) ) ;
cbx_1__2_ cbx_12__12_ (
    .prog_clk ( { ctsbuf_net_7925 } ) ,
    .chanx_left_in ( sb_1__12__10_chanx_right_out ) , 
    .chanx_right_in ( sb_12__12__0_chanx_left_out ) , 
    .ccff_head ( sb_12__12__0_ccff_tail ) , 
    .chanx_left_out ( cbx_1__12__11_chanx_left_out ) , 
    .chanx_right_out ( cbx_1__12__11_chanx_right_out ) , 
    .top_grid_pin_0_ ( cbx_1__12__11_top_grid_pin_0_ ) , 
    .bottom_grid_pin_0_ ( cbx_1__12__11_bottom_grid_pin_0_ ) , 
    .bottom_grid_pin_1_ ( cbx_1__12__11_bottom_grid_pin_1_ ) , 
    .bottom_grid_pin_2_ ( cbx_1__12__11_bottom_grid_pin_2_ ) , 
    .bottom_grid_pin_3_ ( cbx_1__12__11_bottom_grid_pin_3_ ) , 
    .bottom_grid_pin_4_ ( cbx_1__12__11_bottom_grid_pin_4_ ) , 
    .bottom_grid_pin_5_ ( cbx_1__12__11_bottom_grid_pin_5_ ) , 
    .bottom_grid_pin_6_ ( cbx_1__12__11_bottom_grid_pin_6_ ) , 
    .bottom_grid_pin_7_ ( cbx_1__12__11_bottom_grid_pin_7_ ) , 
    .bottom_grid_pin_8_ ( cbx_1__12__11_bottom_grid_pin_8_ ) , 
    .bottom_grid_pin_9_ ( cbx_1__12__11_bottom_grid_pin_9_ ) , 
    .bottom_grid_pin_10_ ( cbx_1__12__11_bottom_grid_pin_10_ ) , 
    .bottom_grid_pin_11_ ( cbx_1__12__11_bottom_grid_pin_11_ ) , 
    .bottom_grid_pin_12_ ( cbx_1__12__11_bottom_grid_pin_12_ ) , 
    .bottom_grid_pin_13_ ( cbx_1__12__11_bottom_grid_pin_13_ ) , 
    .bottom_grid_pin_14_ ( cbx_1__12__11_bottom_grid_pin_14_ ) , 
    .bottom_grid_pin_15_ ( cbx_1__12__11_bottom_grid_pin_15_ ) , 
    .ccff_tail ( grid_io_top_11_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[11] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[11] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[11] ) , 
    .bottom_width_0_height_0__pin_0_ ( cbx_1__12__11_top_grid_pin_0_ ) , 
    .bottom_width_0_height_0__pin_1_upper ( grid_io_top_11_bottom_width_0_height_0__pin_1_upper ) , 
    .bottom_width_0_height_0__pin_1_lower ( grid_io_top_11_bottom_width_0_height_0__pin_1_lower ) , 
    .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1916 ) , 
    .SC_IN_BOT ( scff_Wires_316_ ) , 
    .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1917 ) , 
    .SC_OUT_BOT ( scff_Wires_317_ ) ) ;
cby_0__1_ cby_0__1_ (
    .prog_clk ( { ctsbuf_net_4221340 } ) ,
    .chany_bottom_in ( sb_0__0__0_chany_top_out ) , 
    .chany_top_in ( sb_0__1__0_chany_bottom_out ) , 
    .ccff_head ( sb_0__1__0_ccff_tail ) , 
    .chany_bottom_out ( cby_0__1__0_chany_bottom_out ) , 
    .chany_top_out ( cby_0__1__0_chany_top_out ) , 
    .left_grid_pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , 
    .ccff_tail ( grid_io_left_0_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[96] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[96] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[96] ) , 
    .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , 
    .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , 
    .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) ) ;
cby_0__1_ cby_0__2_ (
    .prog_clk ( { ctsbuf_net_3741292 } ) ,
    .chany_bottom_in ( sb_0__1__0_chany_top_out ) , 
    .chany_top_in ( sb_0__1__1_chany_bottom_out ) , 
    .ccff_head ( sb_0__1__1_ccff_tail ) , 
    .chany_bottom_out ( cby_0__1__1_chany_bottom_out ) , 
    .chany_top_out ( cby_0__1__1_chany_top_out ) , 
    .left_grid_pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , 
    .ccff_tail ( grid_io_left_1_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[97] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[97] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[97] ) , 
    .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , 
    .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , 
    .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) ) ;
cby_0__1_ cby_0__3_ (
    .prog_clk ( { ctsbuf_net_3261244 } ) ,
    .chany_bottom_in ( sb_0__1__1_chany_top_out ) , 
    .chany_top_in ( sb_0__1__2_chany_bottom_out ) , 
    .ccff_head ( sb_0__1__2_ccff_tail ) , 
    .chany_bottom_out ( cby_0__1__2_chany_bottom_out ) , 
    .chany_top_out ( cby_0__1__2_chany_top_out ) , 
    .left_grid_pin_0_ ( cby_0__1__2_left_grid_pin_0_ ) , 
    .ccff_tail ( grid_io_left_2_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[98] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[98] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[98] ) , 
    .right_width_0_height_0__pin_0_ ( cby_0__1__2_left_grid_pin_0_ ) , 
    .right_width_0_height_0__pin_1_upper ( grid_io_left_2_right_width_0_height_0__pin_1_upper ) , 
    .right_width_0_height_0__pin_1_lower ( grid_io_left_2_right_width_0_height_0__pin_1_lower ) ) ;
cby_0__1_ cby_0__4_ (
    .prog_clk ( { ctsbuf_net_2781196 } ) ,
    .chany_bottom_in ( sb_0__1__2_chany_top_out ) , 
    .chany_top_in ( sb_0__1__3_chany_bottom_out ) , 
    .ccff_head ( sb_0__1__3_ccff_tail ) , 
    .chany_bottom_out ( cby_0__1__3_chany_bottom_out ) , 
    .chany_top_out ( cby_0__1__3_chany_top_out ) , 
    .left_grid_pin_0_ ( cby_0__1__3_left_grid_pin_0_ ) , 
    .ccff_tail ( grid_io_left_3_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[99] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[99] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[99] ) , 
    .right_width_0_height_0__pin_0_ ( cby_0__1__3_left_grid_pin_0_ ) , 
    .right_width_0_height_0__pin_1_upper ( grid_io_left_3_right_width_0_height_0__pin_1_upper ) , 
    .right_width_0_height_0__pin_1_lower ( grid_io_left_3_right_width_0_height_0__pin_1_lower ) ) ;
cby_0__1_ cby_0__5_ (
    .prog_clk ( { ctsbuf_net_2301148 } ) ,
    .chany_bottom_in ( sb_0__1__3_chany_top_out ) , 
    .chany_top_in ( sb_0__1__4_chany_bottom_out ) , 
    .ccff_head ( sb_0__1__4_ccff_tail ) , 
    .chany_bottom_out ( cby_0__1__4_chany_bottom_out ) , 
    .chany_top_out ( cby_0__1__4_chany_top_out ) , 
    .left_grid_pin_0_ ( cby_0__1__4_left_grid_pin_0_ ) , 
    .ccff_tail ( grid_io_left_4_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[100] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[100] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[100] ) , 
    .right_width_0_height_0__pin_0_ ( cby_0__1__4_left_grid_pin_0_ ) , 
    .right_width_0_height_0__pin_1_upper ( grid_io_left_4_right_width_0_height_0__pin_1_upper ) , 
    .right_width_0_height_0__pin_1_lower ( grid_io_left_4_right_width_0_height_0__pin_1_lower ) ) ;
cby_0__1_ cby_0__6_ (
    .prog_clk ( { ctsbuf_net_1821100 } ) ,
    .chany_bottom_in ( sb_0__1__4_chany_top_out ) , 
    .chany_top_in ( sb_0__1__5_chany_bottom_out ) , 
    .ccff_head ( sb_0__1__5_ccff_tail ) , 
    .chany_bottom_out ( cby_0__1__5_chany_bottom_out ) , 
    .chany_top_out ( cby_0__1__5_chany_top_out ) , 
    .left_grid_pin_0_ ( cby_0__1__5_left_grid_pin_0_ ) , 
    .ccff_tail ( grid_io_left_5_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[101] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[101] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[101] ) , 
    .right_width_0_height_0__pin_0_ ( cby_0__1__5_left_grid_pin_0_ ) , 
    .right_width_0_height_0__pin_1_upper ( grid_io_left_5_right_width_0_height_0__pin_1_upper ) , 
    .right_width_0_height_0__pin_1_lower ( grid_io_left_5_right_width_0_height_0__pin_1_lower ) ) ;
cby_0__1_ cby_0__7_ (
    .prog_clk ( { ctsbuf_net_1361054 } ) ,
    .chany_bottom_in ( sb_0__1__5_chany_top_out ) , 
    .chany_top_in ( sb_0__1__6_chany_bottom_out ) , 
    .ccff_head ( sb_0__1__6_ccff_tail ) , 
    .chany_bottom_out ( cby_0__1__6_chany_bottom_out ) , 
    .chany_top_out ( cby_0__1__6_chany_top_out ) , 
    .left_grid_pin_0_ ( cby_0__1__6_left_grid_pin_0_ ) , 
    .ccff_tail ( grid_io_left_6_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[102] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[102] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[102] ) , 
    .right_width_0_height_0__pin_0_ ( cby_0__1__6_left_grid_pin_0_ ) , 
    .right_width_0_height_0__pin_1_upper ( grid_io_left_6_right_width_0_height_0__pin_1_upper ) , 
    .right_width_0_height_0__pin_1_lower ( grid_io_left_6_right_width_0_height_0__pin_1_lower ) ) ;
cby_0__1_ cby_0__8_ (
    .prog_clk ( { ctsbuf_net_961014 } ) ,
    .chany_bottom_in ( sb_0__1__6_chany_top_out ) , 
    .chany_top_in ( sb_0__1__7_chany_bottom_out ) , 
    .ccff_head ( sb_0__1__7_ccff_tail ) , 
    .chany_bottom_out ( cby_0__1__7_chany_bottom_out ) , 
    .chany_top_out ( cby_0__1__7_chany_top_out ) , 
    .left_grid_pin_0_ ( cby_0__1__7_left_grid_pin_0_ ) , 
    .ccff_tail ( grid_io_left_7_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[103] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[103] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[103] ) , 
    .right_width_0_height_0__pin_0_ ( cby_0__1__7_left_grid_pin_0_ ) , 
    .right_width_0_height_0__pin_1_upper ( grid_io_left_7_right_width_0_height_0__pin_1_upper ) , 
    .right_width_0_height_0__pin_1_lower ( grid_io_left_7_right_width_0_height_0__pin_1_lower ) ) ;
cby_0__1_ cby_0__9_ (
    .prog_clk ( { ctsbuf_net_63981 } ) ,
    .chany_bottom_in ( sb_0__1__7_chany_top_out ) , 
    .chany_top_in ( sb_0__1__8_chany_bottom_out ) , 
    .ccff_head ( sb_0__1__8_ccff_tail ) , 
    .chany_bottom_out ( cby_0__1__8_chany_bottom_out ) , 
    .chany_top_out ( cby_0__1__8_chany_top_out ) , 
    .left_grid_pin_0_ ( cby_0__1__8_left_grid_pin_0_ ) , 
    .ccff_tail ( grid_io_left_8_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[104] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[104] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[104] ) , 
    .right_width_0_height_0__pin_0_ ( cby_0__1__8_left_grid_pin_0_ ) , 
    .right_width_0_height_0__pin_1_upper ( grid_io_left_8_right_width_0_height_0__pin_1_upper ) , 
    .right_width_0_height_0__pin_1_lower ( grid_io_left_8_right_width_0_height_0__pin_1_lower ) ) ;
cby_0__1_ cby_0__10_ (
    .prog_clk ( { ctsbuf_net_38956 } ) ,
    .chany_bottom_in ( sb_0__1__8_chany_top_out ) , 
    .chany_top_in ( sb_0__1__9_chany_bottom_out ) , 
    .ccff_head ( sb_0__1__9_ccff_tail ) , 
    .chany_bottom_out ( cby_0__1__9_chany_bottom_out ) , 
    .chany_top_out ( cby_0__1__9_chany_top_out ) , 
    .left_grid_pin_0_ ( cby_0__1__9_left_grid_pin_0_ ) , 
    .ccff_tail ( grid_io_left_9_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[105] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[105] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[105] ) , 
    .right_width_0_height_0__pin_0_ ( cby_0__1__9_left_grid_pin_0_ ) , 
    .right_width_0_height_0__pin_1_upper ( grid_io_left_9_right_width_0_height_0__pin_1_upper ) , 
    .right_width_0_height_0__pin_1_lower ( grid_io_left_9_right_width_0_height_0__pin_1_lower ) ) ;
cby_0__1_ cby_0__11_ (
    .prog_clk ( { ctsbuf_net_20938 } ) ,
    .chany_bottom_in ( sb_0__1__9_chany_top_out ) , 
    .chany_top_in ( sb_0__1__10_chany_bottom_out ) , 
    .ccff_head ( sb_0__1__10_ccff_tail ) , 
    .chany_bottom_out ( cby_0__1__10_chany_bottom_out ) , 
    .chany_top_out ( cby_0__1__10_chany_top_out ) , 
    .left_grid_pin_0_ ( cby_0__1__10_left_grid_pin_0_ ) , 
    .ccff_tail ( grid_io_left_10_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[106] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[106] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[106] ) , 
    .right_width_0_height_0__pin_0_ ( cby_0__1__10_left_grid_pin_0_ ) , 
    .right_width_0_height_0__pin_1_upper ( grid_io_left_10_right_width_0_height_0__pin_1_upper ) , 
    .right_width_0_height_0__pin_1_lower ( grid_io_left_10_right_width_0_height_0__pin_1_lower ) ) ;
cby_0__1_ cby_0__12_ (
    .prog_clk ( { ctsbuf_net_10928 } ) ,
    .chany_bottom_in ( sb_0__1__10_chany_top_out ) , 
    .chany_top_in ( sb_0__12__0_chany_bottom_out ) , 
    .ccff_head ( sb_0__12__0_ccff_tail ) , 
    .chany_bottom_out ( cby_0__1__11_chany_bottom_out ) , 
    .chany_top_out ( cby_0__1__11_chany_top_out ) , 
    .left_grid_pin_0_ ( cby_0__1__11_left_grid_pin_0_ ) , 
    .ccff_tail ( grid_io_left_11_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[107] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[107] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[107] ) , 
    .right_width_0_height_0__pin_0_ ( cby_0__1__11_left_grid_pin_0_ ) , 
    .right_width_0_height_0__pin_1_upper ( grid_io_left_11_right_width_0_height_0__pin_1_upper ) , 
    .right_width_0_height_0__pin_1_lower ( grid_io_left_11_right_width_0_height_0__pin_1_lower ) ) ;
cby_1__1_ cby_1__1_ (
    .prog_clk ( { ctsbuf_net_4501368 } ) ,
    .chany_bottom_in ( sb_1__0__0_chany_top_out ) , 
    .chany_top_in ( sb_1__1__0_chany_bottom_out ) , 
    .ccff_head ( grid_clb_0_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__0_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__0_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__0_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_658 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1918 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_658 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1919 } ) ) ;
cby_1__1_ cby_1__2_ (
    .prog_clk ( { ctsbuf_net_4021320 } ) ,
    .chany_bottom_in ( sb_1__1__0_chany_top_out ) , 
    .chany_top_in ( sb_1__1__1_chany_bottom_out ) , 
    .ccff_head ( grid_clb_1_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__1_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__1_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__1_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_623 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1920 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_623 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1921 } ) ) ;
cby_1__1_ cby_1__3_ (
    .prog_clk ( { ctsbuf_net_3541272 } ) ,
    .chany_bottom_in ( sb_1__1__1_chany_top_out ) , 
    .chany_top_in ( sb_1__1__2_chany_bottom_out ) , 
    .ccff_head ( grid_clb_2_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__2_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__2_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__2_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__2_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__2_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__2_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__2_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__2_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__2_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__2_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__2_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__2_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__2_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__2_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__2_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__2_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__2_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__2_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__2_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_549 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1922 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_549 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1923 } ) ) ;
cby_1__1_ cby_1__4_ (
    .prog_clk ( { ctsbuf_net_3061224 } ) ,
    .chany_bottom_in ( sb_1__1__2_chany_top_out ) , 
    .chany_top_in ( sb_1__1__3_chany_bottom_out ) , 
    .ccff_head ( grid_clb_3_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__3_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__3_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__3_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__3_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__3_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__3_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__3_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__3_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__3_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__3_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__3_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__3_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__3_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__3_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__3_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__3_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__3_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__3_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__3_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_269 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1924 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_269 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1925 } ) ) ;
cby_1__1_ cby_1__5_ (
    .prog_clk ( { ctsbuf_net_2581176 } ) ,
    .chany_bottom_in ( sb_1__1__3_chany_top_out ) , 
    .chany_top_in ( sb_1__1__4_chany_bottom_out ) , 
    .ccff_head ( grid_clb_4_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__4_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__4_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__4_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__4_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__4_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__4_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__4_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__4_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__4_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__4_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__4_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__4_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__4_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__4_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__4_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__4_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__4_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__4_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__4_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_910 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1926 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_910 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1927 } ) ) ;
cby_1__1_ cby_1__6_ (
    .prog_clk ( { ctsbuf_net_2101128 } ) ,
    .chany_bottom_in ( sb_1__1__4_chany_top_out ) , 
    .chany_top_in ( sb_1__1__5_chany_bottom_out ) , 
    .ccff_head ( grid_clb_5_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__5_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__5_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__5_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__5_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__5_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__5_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__5_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__5_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__5_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__5_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__5_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__5_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__5_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__5_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__5_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__5_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__5_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__5_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__5_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_680 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1928 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_680 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1929 } ) ) ;
cby_1__1_ cby_1__7_ (
    .prog_clk ( { ctsbuf_net_1621080 } ) ,
    .chany_bottom_in ( sb_1__1__5_chany_top_out ) , 
    .chany_top_in ( sb_1__1__6_chany_bottom_out ) , 
    .ccff_head ( grid_clb_6_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__6_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__6_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__6_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__6_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__6_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__6_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__6_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__6_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__6_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__6_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__6_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__6_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__6_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__6_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__6_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__6_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__6_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__6_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__6_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_603 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1930 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_603 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1931 } ) ) ;
cby_1__1_ cby_1__8_ (
    .prog_clk ( { ctsbuf_net_1181036 } ) ,
    .chany_bottom_in ( sb_1__1__6_chany_top_out ) , 
    .chany_top_in ( sb_1__1__7_chany_bottom_out ) , 
    .ccff_head ( grid_clb_7_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__7_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__7_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__7_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__7_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__7_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__7_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__7_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__7_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__7_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__7_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__7_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__7_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__7_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__7_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__7_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__7_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__7_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__7_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__7_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_683 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1932 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_683 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1933 } ) ) ;
cby_1__1_ cby_1__9_ (
    .prog_clk ( { ctsbuf_net_821000 } ) ,
    .chany_bottom_in ( sb_1__1__7_chany_top_out ) , 
    .chany_top_in ( sb_1__1__8_chany_bottom_out ) , 
    .ccff_head ( grid_clb_8_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__8_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__8_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__8_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__8_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__8_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__8_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__8_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__8_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__8_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__8_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__8_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__8_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__8_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__8_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__8_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__8_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__8_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__8_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__8_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_585 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1934 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_585 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1935 } ) ) ;
cby_1__1_ cby_1__10_ (
    .prog_clk ( { ctsbuf_net_53971 } ) ,
    .chany_bottom_in ( sb_1__1__8_chany_top_out ) , 
    .chany_top_in ( sb_1__1__9_chany_bottom_out ) , 
    .ccff_head ( grid_clb_9_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__9_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__9_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__9_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__9_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__9_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__9_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__9_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__9_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__9_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__9_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__9_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__9_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__9_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__9_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__9_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__9_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__9_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__9_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__9_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_517 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1936 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_517 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1937 } ) ) ;
cby_1__1_ cby_1__11_ (
    .prog_clk ( { ctsbuf_net_31949 } ) ,
    .chany_bottom_in ( sb_1__1__9_chany_top_out ) , 
    .chany_top_in ( sb_1__1__10_chany_bottom_out ) , 
    .ccff_head ( grid_clb_10_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__10_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__10_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__10_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__10_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__10_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__10_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__10_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__10_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__10_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__10_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__10_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__10_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__10_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__10_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__10_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__10_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__10_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__10_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__10_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_736 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1938 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_736 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1939 } ) ) ;
cby_1__1_ cby_1__12_ (
    .prog_clk ( { p_abuf0 } ) ,
    .chany_bottom_in ( sb_1__1__10_chany_top_out ) , 
    .chany_top_in ( sb_1__12__0_chany_bottom_out ) , 
    .ccff_head ( grid_clb_11_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__11_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__11_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__11_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__11_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__11_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__11_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__11_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__11_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__11_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__11_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__11_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__11_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__11_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__11_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__11_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__11_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__11_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__11_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__11_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_699 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1940 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_699 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1941 } ) ) ;
cby_1__1_ cby_2__1_ (
    .prog_clk ( { ctsbuf_net_4931411 } ) ,
    .chany_bottom_in ( sb_1__0__1_chany_top_out ) , 
    .chany_top_in ( sb_1__1__11_chany_bottom_out ) , 
    .ccff_head ( grid_clb_12_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__12_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__12_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__12_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__12_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__12_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__12_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__12_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__12_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__12_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__12_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__12_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__12_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__12_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__12_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__12_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__12_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__12_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__12_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__12_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_313 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1942 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_313 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1943 } ) ) ;
cby_1__1_ cby_2__2_ (
    .prog_clk ( { ctsbuf_net_4531371 } ) ,
    .chany_bottom_in ( sb_1__1__11_chany_top_out ) , 
    .chany_top_in ( sb_1__1__12_chany_bottom_out ) , 
    .ccff_head ( grid_clb_13_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__13_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__13_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__13_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__13_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__13_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__13_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__13_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__13_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__13_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__13_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__13_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__13_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__13_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__13_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__13_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__13_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__13_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__13_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__13_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_461 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1944 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_461 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1945 } ) ) ;
cby_1__1_ cby_2__3_ (
    .prog_clk ( { ctsbuf_net_4051323 } ) ,
    .chany_bottom_in ( sb_1__1__12_chany_top_out ) , 
    .chany_top_in ( sb_1__1__13_chany_bottom_out ) , 
    .ccff_head ( grid_clb_14_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__14_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__14_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__14_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__14_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__14_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__14_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__14_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__14_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__14_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__14_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__14_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__14_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__14_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__14_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__14_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__14_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__14_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__14_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__14_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_360 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1946 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_360 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1947 } ) ) ;
cby_1__1_ cby_2__4_ (
    .prog_clk ( { ctsbuf_net_3571275 } ) ,
    .chany_bottom_in ( sb_1__1__13_chany_top_out ) , 
    .chany_top_in ( sb_1__1__14_chany_bottom_out ) , 
    .ccff_head ( grid_clb_15_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__15_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__15_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__15_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__15_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__15_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__15_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__15_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__15_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__15_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__15_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__15_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__15_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__15_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__15_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__15_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__15_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__15_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__15_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__15_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_314 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1948 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_314 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1949 } ) ) ;
cby_1__1_ cby_2__5_ (
    .prog_clk ( { ctsbuf_net_3091227 } ) ,
    .chany_bottom_in ( sb_1__1__14_chany_top_out ) , 
    .chany_top_in ( sb_1__1__15_chany_bottom_out ) , 
    .ccff_head ( grid_clb_16_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__16_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__16_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__16_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__16_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__16_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__16_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__16_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__16_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__16_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__16_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__16_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__16_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__16_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__16_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__16_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__16_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__16_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__16_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__16_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_572 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1950 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_572 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1951 } ) ) ;
cby_1__1_ cby_2__6_ (
    .prog_clk ( { ctsbuf_net_2611179 } ) ,
    .chany_bottom_in ( sb_1__1__15_chany_top_out ) , 
    .chany_top_in ( sb_1__1__16_chany_bottom_out ) , 
    .ccff_head ( grid_clb_17_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__17_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__17_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__17_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__17_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__17_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__17_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__17_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__17_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__17_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__17_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__17_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__17_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__17_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__17_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__17_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__17_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__17_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__17_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__17_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_387 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1952 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_387 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1953 } ) ) ;
cby_1__1_ cby_2__7_ (
    .prog_clk ( { ctsbuf_net_2131131 } ) ,
    .chany_bottom_in ( sb_1__1__16_chany_top_out ) , 
    .chany_top_in ( sb_1__1__17_chany_bottom_out ) , 
    .ccff_head ( grid_clb_18_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__18_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__18_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__18_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__18_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__18_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__18_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__18_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__18_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__18_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__18_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__18_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__18_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__18_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__18_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__18_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__18_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__18_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__18_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__18_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_453 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1954 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_453 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1955 } ) ) ;
cby_1__1_ cby_2__8_ (
    .prog_clk ( { ctsbuf_net_1651083 } ) ,
    .chany_bottom_in ( sb_1__1__17_chany_top_out ) , 
    .chany_top_in ( sb_1__1__18_chany_bottom_out ) , 
    .ccff_head ( grid_clb_19_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__19_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__19_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__19_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__19_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__19_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__19_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__19_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__19_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__19_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__19_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__19_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__19_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__19_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__19_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__19_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__19_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__19_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__19_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__19_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_758 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1956 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_758 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1957 } ) ) ;
cby_1__1_ cby_2__9_ (
    .prog_clk ( { ctsbuf_net_1211039 } ) ,
    .chany_bottom_in ( sb_1__1__18_chany_top_out ) , 
    .chany_top_in ( sb_1__1__19_chany_bottom_out ) , 
    .ccff_head ( grid_clb_20_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__20_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__20_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__20_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__20_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__20_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__20_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__20_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__20_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__20_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__20_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__20_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__20_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__20_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__20_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__20_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__20_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__20_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__20_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__20_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_833 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1958 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_833 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1959 } ) ) ;
cby_1__1_ cby_2__10_ (
    .prog_clk ( { ctsbuf_net_851003 } ) ,
    .chany_bottom_in ( sb_1__1__19_chany_top_out ) , 
    .chany_top_in ( sb_1__1__20_chany_bottom_out ) , 
    .ccff_head ( grid_clb_21_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__21_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__21_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__21_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__21_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__21_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__21_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__21_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__21_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__21_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__21_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__21_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__21_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__21_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__21_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__21_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__21_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__21_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__21_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__21_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_444 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1960 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_444 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1961 } ) ) ;
cby_1__1_ cby_2__11_ (
    .prog_clk ( { ctsbuf_net_55973 } ) ,
    .chany_bottom_in ( sb_1__1__20_chany_top_out ) , 
    .chany_top_in ( sb_1__1__21_chany_bottom_out ) , 
    .ccff_head ( grid_clb_22_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__22_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__22_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__22_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__22_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__22_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__22_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__22_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__22_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__22_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__22_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__22_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__22_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__22_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__22_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__22_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__22_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__22_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__22_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__22_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_390 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1962 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_390 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1963 } ) ) ;
cby_1__1_ cby_2__12_ (
    .prog_clk ( { ctsbuf_net_32950 } ) ,
    .chany_bottom_in ( sb_1__1__21_chany_top_out ) , 
    .chany_top_in ( sb_1__12__1_chany_bottom_out ) , 
    .ccff_head ( grid_clb_23_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__23_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__23_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__23_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__23_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__23_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__23_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__23_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__23_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__23_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__23_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__23_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__23_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__23_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__23_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__23_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__23_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__23_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__23_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__23_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_687 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1964 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_687 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1965 } ) ) ;
cby_1__1_ cby_3__1_ (
    .prog_clk ( { ctsbuf_net_5281446 } ) ,
    .chany_bottom_in ( sb_1__0__2_chany_top_out ) , 
    .chany_top_in ( sb_1__1__22_chany_bottom_out ) , 
    .ccff_head ( grid_clb_24_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__24_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__24_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__24_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__24_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__24_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__24_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__24_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__24_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__24_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__24_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__24_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__24_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__24_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__24_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__24_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__24_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__24_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__24_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__24_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_871 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1966 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_871 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1967 } ) ) ;
cby_1__1_ cby_3__2_ (
    .prog_clk ( { ctsbuf_net_4961414 } ) ,
    .chany_bottom_in ( sb_1__1__22_chany_top_out ) , 
    .chany_top_in ( sb_1__1__23_chany_bottom_out ) , 
    .ccff_head ( grid_clb_25_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__25_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__25_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__25_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__25_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__25_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__25_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__25_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__25_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__25_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__25_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__25_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__25_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__25_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__25_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__25_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__25_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__25_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__25_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__25_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_720 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1968 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_720 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1969 } ) ) ;
cby_1__1_ cby_3__3_ (
    .prog_clk ( { ctsbuf_net_4561374 } ) ,
    .chany_bottom_in ( sb_1__1__23_chany_top_out ) , 
    .chany_top_in ( sb_1__1__24_chany_bottom_out ) , 
    .ccff_head ( grid_clb_26_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__26_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__26_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__26_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__26_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__26_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__26_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__26_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__26_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__26_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__26_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__26_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__26_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__26_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__26_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__26_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__26_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__26_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__26_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__26_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_323 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1970 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_323 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1971 } ) ) ;
cby_1__1_ cby_3__4_ (
    .prog_clk ( { ctsbuf_net_4081326 } ) ,
    .chany_bottom_in ( sb_1__1__24_chany_top_out ) , 
    .chany_top_in ( sb_1__1__25_chany_bottom_out ) , 
    .ccff_head ( grid_clb_27_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__27_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__27_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__27_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__27_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__27_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__27_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__27_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__27_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__27_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__27_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__27_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__27_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__27_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__27_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__27_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__27_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__27_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__27_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__27_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_481 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1972 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_481 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1973 } ) ) ;
cby_1__1_ cby_3__5_ (
    .prog_clk ( { ctsbuf_net_3601278 } ) ,
    .chany_bottom_in ( sb_1__1__25_chany_top_out ) , 
    .chany_top_in ( sb_1__1__26_chany_bottom_out ) , 
    .ccff_head ( grid_clb_28_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__28_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__28_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__28_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__28_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__28_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__28_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__28_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__28_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__28_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__28_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__28_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__28_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__28_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__28_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__28_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__28_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__28_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__28_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__28_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_608 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1974 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_608 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1975 } ) ) ;
cby_1__1_ cby_3__6_ (
    .prog_clk ( { ctsbuf_net_3121230 } ) ,
    .chany_bottom_in ( sb_1__1__26_chany_top_out ) , 
    .chany_top_in ( sb_1__1__27_chany_bottom_out ) , 
    .ccff_head ( grid_clb_29_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__29_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__29_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__29_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__29_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__29_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__29_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__29_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__29_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__29_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__29_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__29_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__29_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__29_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__29_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__29_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__29_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__29_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__29_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__29_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_388 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1976 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_388 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1977 } ) ) ;
cby_1__1_ cby_3__7_ (
    .prog_clk ( { ctsbuf_net_2641182 } ) ,
    .chany_bottom_in ( sb_1__1__27_chany_top_out ) , 
    .chany_top_in ( sb_1__1__28_chany_bottom_out ) , 
    .ccff_head ( grid_clb_30_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__30_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__30_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__30_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__30_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__30_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__30_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__30_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__30_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__30_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__30_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__30_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__30_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__30_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__30_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__30_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__30_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__30_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__30_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__30_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_531 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1978 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_531 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1979 } ) ) ;
cby_1__1_ cby_3__8_ (
    .prog_clk ( { ctsbuf_net_2161134 } ) ,
    .chany_bottom_in ( sb_1__1__28_chany_top_out ) , 
    .chany_top_in ( sb_1__1__29_chany_bottom_out ) , 
    .ccff_head ( grid_clb_31_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__31_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__31_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__31_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__31_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__31_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__31_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__31_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__31_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__31_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__31_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__31_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__31_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__31_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__31_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__31_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__31_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__31_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__31_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__31_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_276 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1980 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_276 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1981 } ) ) ;
cby_1__1_ cby_3__9_ (
    .prog_clk ( { ctsbuf_net_1681086 } ) ,
    .chany_bottom_in ( sb_1__1__29_chany_top_out ) , 
    .chany_top_in ( sb_1__1__30_chany_bottom_out ) , 
    .ccff_head ( grid_clb_32_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__32_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__32_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__32_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__32_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__32_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__32_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__32_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__32_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__32_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__32_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__32_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__32_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__32_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__32_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__32_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__32_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__32_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__32_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__32_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_843 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1982 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_843 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1983 } ) ) ;
cby_1__1_ cby_3__10_ (
    .prog_clk ( { ctsbuf_net_1241042 } ) ,
    .chany_bottom_in ( sb_1__1__30_chany_top_out ) , 
    .chany_top_in ( sb_1__1__31_chany_bottom_out ) , 
    .ccff_head ( grid_clb_33_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__33_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__33_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__33_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__33_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__33_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__33_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__33_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__33_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__33_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__33_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__33_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__33_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__33_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__33_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__33_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__33_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__33_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__33_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__33_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_656 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1984 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_656 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1985 } ) ) ;
cby_1__1_ cby_3__11_ (
    .prog_clk ( { ctsbuf_net_871005 } ) ,
    .chany_bottom_in ( sb_1__1__31_chany_top_out ) , 
    .chany_top_in ( sb_1__1__32_chany_bottom_out ) , 
    .ccff_head ( grid_clb_34_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__34_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__34_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__34_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__34_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__34_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__34_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__34_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__34_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__34_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__34_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__34_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__34_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__34_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__34_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__34_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__34_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__34_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__34_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__34_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_521 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1986 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_521 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1987 } ) ) ;
cby_1__1_ cby_3__12_ (
    .prog_clk ( { ctsbuf_net_56974 } ) ,
    .chany_bottom_in ( sb_1__1__32_chany_top_out ) , 
    .chany_top_in ( sb_1__12__2_chany_bottom_out ) , 
    .ccff_head ( grid_clb_35_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__35_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__35_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__35_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__35_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__35_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__35_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__35_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__35_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__35_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__35_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__35_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__35_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__35_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__35_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__35_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__35_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__35_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__35_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__35_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_257 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1988 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_257 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1989 } ) ) ;
cby_1__1_ cby_4__1_ (
    .prog_clk ( { ctsbuf_net_5541472 } ) ,
    .chany_bottom_in ( sb_1__0__3_chany_top_out ) , 
    .chany_top_in ( sb_1__1__33_chany_bottom_out ) , 
    .ccff_head ( grid_clb_36_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__36_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__36_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__36_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__36_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__36_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__36_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__36_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__36_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__36_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__36_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__36_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__36_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__36_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__36_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__36_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__36_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__36_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__36_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__36_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_710 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1990 } ) ) ;
cby_1__1_ cby_4__2_ (
    .prog_clk ( { ctsbuf_net_5301448 } ) ,
    .chany_bottom_in ( sb_1__1__33_chany_top_out ) , 
    .chany_top_in ( sb_1__1__34_chany_bottom_out ) , 
    .ccff_head ( grid_clb_37_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__37_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__37_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__37_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__37_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__37_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__37_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__37_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__37_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__37_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__37_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__37_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__37_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__37_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__37_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__37_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__37_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__37_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__37_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__37_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_583 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1991 } ) ) ;
cby_1__1_ cby_4__3_ (
    .prog_clk ( { ctsbuf_net_4981416 } ) ,
    .chany_bottom_in ( sb_1__1__34_chany_top_out ) , 
    .chany_top_in ( sb_1__1__35_chany_bottom_out ) , 
    .ccff_head ( grid_clb_38_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__38_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__38_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__38_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__38_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__38_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__38_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__38_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__38_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__38_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__38_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__38_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__38_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__38_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__38_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__38_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__38_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__38_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__38_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__38_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_6 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_764 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1992 } ) ) ;
cby_1__1_ cby_4__4_ (
    .prog_clk ( { ctsbuf_net_4591377 } ) ,
    .chany_bottom_in ( sb_1__1__35_chany_top_out ) , 
    .chany_top_in ( sb_1__1__36_chany_bottom_out ) , 
    .ccff_head ( grid_clb_39_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__39_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__39_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__39_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__39_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__39_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__39_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__39_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__39_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__39_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__39_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__39_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__39_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__39_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__39_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__39_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__39_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__39_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__39_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__39_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_7 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_8 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_540 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1993 } ) ) ;
cby_1__1_ cby_4__5_ (
    .prog_clk ( { ctsbuf_net_4111329 } ) ,
    .chany_bottom_in ( sb_1__1__36_chany_top_out ) , 
    .chany_top_in ( sb_1__1__37_chany_bottom_out ) , 
    .ccff_head ( grid_clb_40_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__40_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__40_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__40_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__40_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__40_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__40_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__40_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__40_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__40_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__40_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__40_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__40_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__40_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__40_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__40_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__40_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__40_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__40_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__40_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_9 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_10 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_443 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1994 } ) ) ;
cby_1__1_ cby_4__6_ (
    .prog_clk ( { ctsbuf_net_3631281 } ) ,
    .chany_bottom_in ( sb_1__1__37_chany_top_out ) , 
    .chany_top_in ( sb_1__1__38_chany_bottom_out ) , 
    .ccff_head ( grid_clb_41_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__41_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__41_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__41_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__41_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__41_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__41_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__41_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__41_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__41_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__41_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__41_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__41_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__41_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__41_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__41_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__41_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__41_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__41_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__41_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_11 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_12 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_686 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1995 } ) ) ;
cby_1__1_ cby_4__7_ (
    .prog_clk ( { ctsbuf_net_3151233 } ) ,
    .chany_bottom_in ( sb_1__1__38_chany_top_out ) , 
    .chany_top_in ( sb_1__1__39_chany_bottom_out ) , 
    .ccff_head ( grid_clb_42_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__42_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__42_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__42_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__42_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__42_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__42_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__42_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__42_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__42_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__42_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__42_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__42_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__42_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__42_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__42_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__42_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__42_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__42_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__42_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_13 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_14 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_508 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1996 } ) ) ;
cby_1__1_ cby_4__8_ (
    .prog_clk ( { ctsbuf_net_2671185 } ) ,
    .chany_bottom_in ( sb_1__1__39_chany_top_out ) , 
    .chany_top_in ( sb_1__1__40_chany_bottom_out ) , 
    .ccff_head ( grid_clb_43_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__43_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__43_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__43_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__43_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__43_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__43_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__43_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__43_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__43_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__43_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__43_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__43_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__43_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__43_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__43_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__43_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__43_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__43_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__43_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_15 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_16 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_336 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1997 } ) ) ;
cby_1__1_ cby_4__9_ (
    .prog_clk ( { ctsbuf_net_2191137 } ) ,
    .chany_bottom_in ( sb_1__1__40_chany_top_out ) , 
    .chany_top_in ( sb_1__1__41_chany_bottom_out ) , 
    .ccff_head ( grid_clb_44_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__44_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__44_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__44_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__44_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__44_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__44_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__44_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__44_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__44_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__44_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__44_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__44_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__44_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__44_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__44_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__44_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__44_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__44_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__44_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_17 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_18 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_329 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1998 } ) ) ;
cby_1__1_ cby_4__10_ (
    .prog_clk ( { ctsbuf_net_1711089 } ) ,
    .chany_bottom_in ( sb_1__1__41_chany_top_out ) , 
    .chany_top_in ( sb_1__1__42_chany_bottom_out ) , 
    .ccff_head ( grid_clb_45_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__45_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__45_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__45_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__45_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__45_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__45_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__45_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__45_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__45_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__45_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__45_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__45_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__45_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__45_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__45_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__45_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__45_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__45_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__45_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_19 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_20 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_286 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_1999 } ) ) ;
cby_1__1_ cby_4__11_ (
    .prog_clk ( { ctsbuf_net_1271045 } ) ,
    .chany_bottom_in ( sb_1__1__42_chany_top_out ) , 
    .chany_top_in ( sb_1__1__43_chany_bottom_out ) , 
    .ccff_head ( grid_clb_46_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__46_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__46_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__46_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__46_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__46_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__46_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__46_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__46_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__46_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__46_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__46_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__46_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__46_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__46_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__46_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__46_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__46_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__46_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__46_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_21 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_22 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_523 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2000 } ) ) ;
cby_1__1_ cby_4__12_ (
    .prog_clk ( { ctsbuf_net_891007 } ) ,
    .chany_bottom_in ( sb_1__1__43_chany_top_out ) , 
    .chany_top_in ( sb_1__12__3_chany_bottom_out ) , 
    .ccff_head ( grid_clb_47_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__47_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__47_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__47_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__47_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__47_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__47_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__47_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__47_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__47_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__47_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__47_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__47_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__47_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__47_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__47_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__47_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__47_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__47_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__47_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_23 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_24 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_878 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2001 } ) ) ;
cby_1__1_ cby_5__1_ (
    .prog_clk ( { ctsbuf_net_5721490 } ) ,
    .chany_bottom_in ( sb_1__0__4_chany_top_out ) , 
    .chany_top_in ( sb_1__1__44_chany_bottom_out ) , 
    .ccff_head ( grid_clb_48_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__48_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__48_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__48_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__48_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__48_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__48_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__48_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__48_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__48_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__48_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__48_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__48_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__48_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__48_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__48_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__48_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__48_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__48_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__48_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_362 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2002 } ) ) ;
cby_1__1_ cby_5__2_ (
    .prog_clk ( { ctsbuf_net_5561474 } ) ,
    .chany_bottom_in ( sb_1__1__44_chany_top_out ) , 
    .chany_top_in ( sb_1__1__45_chany_bottom_out ) , 
    .ccff_head ( grid_clb_49_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__49_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__49_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__49_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__49_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__49_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__49_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__49_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__49_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__49_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__49_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__49_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__49_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__49_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__49_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__49_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__49_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__49_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__49_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__49_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_516 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2003 } ) ) ;
cby_1__1_ cby_5__3_ (
    .prog_clk ( { ctsbuf_net_5321450 } ) ,
    .chany_bottom_in ( sb_1__1__45_chany_top_out ) , 
    .chany_top_in ( sb_1__1__46_chany_bottom_out ) , 
    .ccff_head ( grid_clb_50_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__50_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__50_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__50_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__50_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__50_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__50_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__50_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__50_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__50_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__50_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__50_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__50_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__50_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__50_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__50_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__50_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__50_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__50_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__50_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_6 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_891 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2004 } ) ) ;
cby_1__1_ cby_5__4_ (
    .prog_clk ( { ctsbuf_net_5011419 } ) ,
    .chany_bottom_in ( sb_1__1__46_chany_top_out ) , 
    .chany_top_in ( sb_1__1__47_chany_bottom_out ) , 
    .ccff_head ( grid_clb_51_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__51_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__51_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__51_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__51_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__51_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__51_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__51_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__51_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__51_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__51_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__51_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__51_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__51_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__51_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__51_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__51_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__51_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__51_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__51_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_7 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_8 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_799 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2005 } ) ) ;
cby_1__1_ cby_5__5_ (
    .prog_clk ( { ctsbuf_net_4621380 } ) ,
    .chany_bottom_in ( sb_1__1__47_chany_top_out ) , 
    .chany_top_in ( sb_1__1__48_chany_bottom_out ) , 
    .ccff_head ( grid_clb_52_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__52_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__52_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__52_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__52_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__52_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__52_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__52_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__52_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__52_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__52_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__52_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__52_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__52_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__52_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__52_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__52_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__52_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__52_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__52_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_9 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_10 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_620 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2006 } ) ) ;
cby_1__1_ cby_5__6_ (
    .prog_clk ( { ctsbuf_net_4141332 } ) ,
    .chany_bottom_in ( sb_1__1__48_chany_top_out ) , 
    .chany_top_in ( sb_1__1__49_chany_bottom_out ) , 
    .ccff_head ( grid_clb_53_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__53_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__53_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__53_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__53_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__53_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__53_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__53_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__53_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__53_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__53_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__53_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__53_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__53_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__53_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__53_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__53_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__53_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__53_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__53_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_11 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_12 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_789 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2007 } ) ) ;
cby_1__1_ cby_5__7_ (
    .prog_clk ( { ctsbuf_net_3661284 } ) ,
    .chany_bottom_in ( sb_1__1__49_chany_top_out ) , 
    .chany_top_in ( sb_1__1__50_chany_bottom_out ) , 
    .ccff_head ( grid_clb_54_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__54_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__54_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__54_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__54_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__54_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__54_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__54_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__54_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__54_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__54_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__54_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__54_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__54_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__54_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__54_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__54_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__54_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__54_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__54_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_13 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_14 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_547 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2008 } ) ) ;
cby_1__1_ cby_5__8_ (
    .prog_clk ( { ctsbuf_net_3181236 } ) ,
    .chany_bottom_in ( sb_1__1__50_chany_top_out ) , 
    .chany_top_in ( sb_1__1__51_chany_bottom_out ) , 
    .ccff_head ( grid_clb_55_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__55_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__55_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__55_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__55_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__55_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__55_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__55_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__55_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__55_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__55_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__55_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__55_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__55_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__55_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__55_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__55_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__55_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__55_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__55_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_15 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_16 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_770 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2009 } ) ) ;
cby_1__1_ cby_5__9_ (
    .prog_clk ( { ctsbuf_net_2701188 } ) ,
    .chany_bottom_in ( sb_1__1__51_chany_top_out ) , 
    .chany_top_in ( sb_1__1__52_chany_bottom_out ) , 
    .ccff_head ( grid_clb_56_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__56_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__56_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__56_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__56_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__56_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__56_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__56_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__56_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__56_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__56_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__56_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__56_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__56_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__56_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__56_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__56_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__56_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__56_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__56_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_17 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_18 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_462 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2010 } ) ) ;
cby_1__1_ cby_5__10_ (
    .prog_clk ( { ctsbuf_net_2221140 } ) ,
    .chany_bottom_in ( sb_1__1__52_chany_top_out ) , 
    .chany_top_in ( sb_1__1__53_chany_bottom_out ) , 
    .ccff_head ( grid_clb_57_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__57_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__57_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__57_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__57_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__57_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__57_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__57_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__57_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__57_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__57_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__57_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__57_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__57_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__57_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__57_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__57_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__57_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__57_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__57_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_712 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2011 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_712 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2012 } ) ) ;
cby_1__1_ cby_5__11_ (
    .prog_clk ( { ctsbuf_net_1741092 } ) ,
    .chany_bottom_in ( sb_1__1__53_chany_top_out ) , 
    .chany_top_in ( sb_1__1__54_chany_bottom_out ) , 
    .ccff_head ( grid_clb_58_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__58_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__58_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__58_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__58_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__58_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__58_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__58_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__58_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__58_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__58_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__58_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__58_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__58_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__58_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__58_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__58_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__58_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__58_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__58_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_260 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2013 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_260 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2014 } ) ) ;
cby_1__1_ cby_5__12_ (
    .prog_clk ( { ctsbuf_net_1291047 } ) ,
    .chany_bottom_in ( sb_1__1__54_chany_top_out ) , 
    .chany_top_in ( sb_1__12__4_chany_bottom_out ) , 
    .ccff_head ( grid_clb_59_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__59_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__59_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__59_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__59_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__59_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__59_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__59_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__59_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__59_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__59_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__59_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__59_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__59_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__59_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__59_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__59_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__59_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__59_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__59_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_571 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2015 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_571 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2016 } ) ) ;
cby_1__1_ cby_6__1_ (
    .prog_clk ( { ctsbuf_net_5811499 } ) ,
    .chany_bottom_in ( sb_1__0__5_chany_top_out ) , 
    .chany_top_in ( sb_1__1__55_chany_bottom_out ) , 
    .ccff_head ( grid_clb_60_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__60_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__60_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__60_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__60_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__60_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__60_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__60_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__60_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__60_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__60_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__60_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__60_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__60_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__60_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__60_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__60_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__60_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__60_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__60_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_892 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2017 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_892 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2018 } ) ) ;
cby_1__1_ cby_6__2_ (
    .prog_clk ( { ctsbuf_net_5731491 } ) ,
    .chany_bottom_in ( sb_1__1__55_chany_top_out ) , 
    .chany_top_in ( sb_1__1__56_chany_bottom_out ) , 
    .ccff_head ( grid_clb_61_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__61_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__61_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__61_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__61_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__61_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__61_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__61_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__61_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__61_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__61_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__61_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__61_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__61_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__61_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__61_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__61_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__61_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__61_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__61_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_644 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2019 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_644 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2020 } ) ) ;
cby_1__1_ cby_6__3_ (
    .prog_clk ( { ctsbuf_net_5571475 } ) ,
    .chany_bottom_in ( sb_1__1__56_chany_top_out ) , 
    .chany_top_in ( sb_1__1__57_chany_bottom_out ) , 
    .ccff_head ( grid_clb_62_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__62_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__62_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__62_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__62_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__62_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__62_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__62_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__62_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__62_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__62_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__62_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__62_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__62_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__62_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__62_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__62_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__62_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__62_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__62_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_786 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2021 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_786 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2022 } ) ) ;
cby_1__1_ cby_6__4_ (
    .prog_clk ( { ctsbuf_net_5341452 } ) ,
    .chany_bottom_in ( sb_1__1__57_chany_top_out ) , 
    .chany_top_in ( sb_1__1__58_chany_bottom_out ) , 
    .ccff_head ( grid_clb_63_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__63_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__63_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__63_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__63_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__63_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__63_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__63_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__63_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__63_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__63_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__63_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__63_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__63_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__63_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__63_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__63_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__63_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__63_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__63_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_863 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2023 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_863 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2024 } ) ) ;
cby_1__1_ cby_6__5_ (
    .prog_clk ( { ctsbuf_net_5031421 } ) ,
    .chany_bottom_in ( sb_1__1__58_chany_top_out ) , 
    .chany_top_in ( sb_1__1__59_chany_bottom_out ) , 
    .ccff_head ( grid_clb_64_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__64_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__64_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__64_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__64_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__64_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__64_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__64_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__64_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__64_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__64_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__64_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__64_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__64_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__64_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__64_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__64_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__64_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__64_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__64_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_723 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2025 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_723 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2026 } ) ) ;
cby_1__1_ cby_6__6_ (
    .prog_clk ( { ctsbuf_net_4641382 } ) ,
    .chany_bottom_in ( sb_1__1__59_chany_top_out ) , 
    .chany_top_in ( sb_1__1__60_chany_bottom_out ) , 
    .ccff_head ( grid_clb_65_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__65_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__65_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__65_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__65_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__65_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__65_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__65_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__65_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__65_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__65_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__65_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__65_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__65_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__65_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__65_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__65_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__65_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__65_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__65_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_493 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2027 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_493 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2028 } ) ) ;
cby_1__1_ cby_6__7_ (
    .prog_clk ( { ctsbuf_net_4161334 } ) ,
    .chany_bottom_in ( sb_1__1__60_chany_top_out ) , 
    .chany_top_in ( sb_1__1__61_chany_bottom_out ) , 
    .ccff_head ( grid_clb_66_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__66_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__66_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__66_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__66_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__66_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__66_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__66_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__66_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__66_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__66_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__66_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__66_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__66_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__66_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__66_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__66_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__66_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__66_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__66_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_289 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2029 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_289 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2030 } ) ) ;
cby_1__1_ cby_6__8_ (
    .prog_clk ( { ctsbuf_net_3681286 } ) ,
    .chany_bottom_in ( sb_1__1__61_chany_top_out ) , 
    .chany_top_in ( sb_1__1__62_chany_bottom_out ) , 
    .ccff_head ( grid_clb_67_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__67_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__67_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__67_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__67_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__67_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__67_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__67_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__67_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__67_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__67_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__67_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__67_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__67_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__67_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__67_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__67_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__67_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__67_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__67_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_707 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2031 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_707 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2032 } ) ) ;
cby_1__1_ cby_6__9_ (
    .prog_clk ( { ctsbuf_net_3201238 } ) ,
    .chany_bottom_in ( sb_1__1__62_chany_top_out ) , 
    .chany_top_in ( sb_1__1__63_chany_bottom_out ) , 
    .ccff_head ( grid_clb_68_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__68_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__68_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__68_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__68_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__68_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__68_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__68_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__68_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__68_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__68_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__68_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__68_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__68_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__68_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__68_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__68_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__68_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__68_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__68_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_581 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2033 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_581 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2034 } ) ) ;
cby_1__1_ cby_6__10_ (
    .prog_clk ( { ctsbuf_net_2721190 } ) ,
    .chany_bottom_in ( sb_1__1__63_chany_top_out ) , 
    .chany_top_in ( sb_1__1__64_chany_bottom_out ) , 
    .ccff_head ( grid_clb_69_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__69_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__69_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__69_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__69_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__69_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__69_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__69_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__69_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__69_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__69_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__69_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__69_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__69_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__69_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__69_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__69_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__69_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__69_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__69_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_324 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2035 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_324 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2036 } ) ) ;
cby_1__1_ cby_6__11_ (
    .prog_clk ( { ctsbuf_net_2241142 } ) ,
    .chany_bottom_in ( sb_1__1__64_chany_top_out ) , 
    .chany_top_in ( sb_1__1__65_chany_bottom_out ) , 
    .ccff_head ( grid_clb_70_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__70_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__70_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__70_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__70_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__70_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__70_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__70_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__70_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__70_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__70_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__70_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__70_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__70_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__70_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__70_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__70_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__70_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__70_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__70_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_802 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2037 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_802 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2038 } ) ) ;
cby_1__1_ cby_6__12_ (
    .prog_clk ( { ctsbuf_net_1761094 } ) ,
    .chany_bottom_in ( sb_1__1__65_chany_top_out ) , 
    .chany_top_in ( sb_1__12__5_chany_bottom_out ) , 
    .ccff_head ( grid_clb_71_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__71_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__71_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__71_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__71_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__71_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__71_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__71_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__71_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__71_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__71_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__71_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__71_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__71_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__71_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__71_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__71_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__71_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__71_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__71_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_266 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2039 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_266 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2040 } ) ) ;
cby_1__1_ cby_7__1_ (
    .prog_clk ( { ctsbuf_net_5751493 } ) ,
    .chany_bottom_in ( sb_1__0__6_chany_top_out ) , 
    .chany_top_in ( sb_1__1__66_chany_bottom_out ) , 
    .ccff_head ( grid_clb_72_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__72_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__72_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__72_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__72_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__72_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__72_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__72_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__72_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__72_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__72_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__72_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__72_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__72_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__72_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__72_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__72_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__72_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__72_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__72_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_520 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2041 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_520 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2042 } ) ) ;
cby_1__1_ cby_7__2_ (
    .prog_clk ( { ctsbuf_net_5611479 } ) ,
    .chany_bottom_in ( sb_1__1__66_chany_top_out ) , 
    .chany_top_in ( sb_1__1__67_chany_bottom_out ) , 
    .ccff_head ( grid_clb_73_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__73_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__73_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__73_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__73_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__73_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__73_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__73_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__73_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__73_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__73_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__73_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__73_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__73_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__73_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__73_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__73_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__73_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__73_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__73_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_732 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2043 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_732 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2044 } ) ) ;
cby_1__1_ cby_7__3_ (
    .prog_clk ( { ctsbuf_net_5391457 } ) ,
    .chany_bottom_in ( sb_1__1__67_chany_top_out ) , 
    .chany_top_in ( sb_1__1__68_chany_bottom_out ) , 
    .ccff_head ( grid_clb_74_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__74_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__74_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__74_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__74_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__74_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__74_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__74_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__74_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__74_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__74_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__74_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__74_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__74_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__74_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__74_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__74_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__74_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__74_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__74_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_281 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2045 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_281 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2046 } ) ) ;
cby_1__1_ cby_7__4_ (
    .prog_clk ( { ctsbuf_net_5101428 } ) ,
    .chany_bottom_in ( sb_1__1__68_chany_top_out ) , 
    .chany_top_in ( sb_1__1__69_chany_bottom_out ) , 
    .ccff_head ( grid_clb_75_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__75_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__75_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__75_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__75_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__75_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__75_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__75_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__75_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__75_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__75_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__75_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__75_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__75_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__75_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__75_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__75_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__75_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__75_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__75_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_631 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2047 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_631 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2048 } ) ) ;
cby_1__1_ cby_7__5_ (
    .prog_clk ( { ctsbuf_net_4731391 } ) ,
    .chany_bottom_in ( sb_1__1__69_chany_top_out ) , 
    .chany_top_in ( sb_1__1__70_chany_bottom_out ) , 
    .ccff_head ( grid_clb_76_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__76_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__76_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__76_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__76_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__76_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__76_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__76_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__76_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__76_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__76_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__76_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__76_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__76_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__76_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__76_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__76_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__76_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__76_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__76_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_744 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2049 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_744 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2050 } ) ) ;
cby_1__1_ cby_7__6_ (
    .prog_clk ( { ctsbuf_net_4281346 } ) ,
    .chany_bottom_in ( sb_1__1__70_chany_top_out ) , 
    .chany_top_in ( sb_1__1__71_chany_bottom_out ) , 
    .ccff_head ( grid_clb_77_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__77_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__77_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__77_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__77_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__77_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__77_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__77_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__77_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__77_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__77_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__77_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__77_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__77_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__77_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__77_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__77_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__77_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__77_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__77_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_694 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2051 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_694 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2052 } ) ) ;
cby_1__1_ cby_7__7_ (
    .prog_clk ( { ctsbuf_net_3801298 } ) ,
    .chany_bottom_in ( sb_1__1__71_chany_top_out ) , 
    .chany_top_in ( sb_1__1__72_chany_bottom_out ) , 
    .ccff_head ( grid_clb_78_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__78_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__78_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__78_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__78_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__78_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__78_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__78_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__78_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__78_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__78_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__78_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__78_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__78_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__78_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__78_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__78_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__78_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__78_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__78_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_475 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2053 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_475 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2054 } ) ) ;
cby_1__1_ cby_7__8_ (
    .prog_clk ( { ctsbuf_net_3321250 } ) ,
    .chany_bottom_in ( sb_1__1__72_chany_top_out ) , 
    .chany_top_in ( sb_1__1__73_chany_bottom_out ) , 
    .ccff_head ( grid_clb_79_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__79_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__79_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__79_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__79_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__79_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__79_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__79_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__79_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__79_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__79_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__79_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__79_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__79_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__79_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__79_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__79_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__79_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__79_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__79_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_793 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2055 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_793 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2056 } ) ) ;
cby_1__1_ cby_7__9_ (
    .prog_clk ( { ctsbuf_net_2841202 } ) ,
    .chany_bottom_in ( sb_1__1__73_chany_top_out ) , 
    .chany_top_in ( sb_1__1__74_chany_bottom_out ) , 
    .ccff_head ( grid_clb_80_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__80_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__80_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__80_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__80_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__80_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__80_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__80_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__80_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__80_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__80_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__80_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__80_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__80_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__80_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__80_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__80_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__80_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__80_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__80_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_505 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2057 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_505 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2058 } ) ) ;
cby_1__1_ cby_7__10_ (
    .prog_clk ( { ctsbuf_net_2361154 } ) ,
    .chany_bottom_in ( sb_1__1__74_chany_top_out ) , 
    .chany_top_in ( sb_1__1__75_chany_bottom_out ) , 
    .ccff_head ( grid_clb_81_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__81_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__81_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__81_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__81_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__81_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__81_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__81_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__81_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__81_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__81_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__81_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__81_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__81_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__81_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__81_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__81_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__81_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__81_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__81_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_433 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2059 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_433 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2060 } ) ) ;
cby_1__1_ cby_7__11_ (
    .prog_clk ( { ctsbuf_net_1881106 } ) ,
    .chany_bottom_in ( sb_1__1__75_chany_top_out ) , 
    .chany_top_in ( sb_1__1__76_chany_bottom_out ) , 
    .ccff_head ( grid_clb_82_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__82_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__82_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__82_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__82_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__82_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__82_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__82_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__82_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__82_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__82_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__82_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__82_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__82_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__82_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__82_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__82_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__82_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__82_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__82_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_781 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2061 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_781 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2062 } ) ) ;
cby_1__1_ cby_7__12_ (
    .prog_clk ( { ctsbuf_net_1421060 } ) ,
    .chany_bottom_in ( sb_1__1__76_chany_top_out ) , 
    .chany_top_in ( sb_1__12__6_chany_bottom_out ) , 
    .ccff_head ( grid_clb_83_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__83_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__83_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__83_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__83_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__83_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__83_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__83_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__83_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__83_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__83_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__83_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__83_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__83_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__83_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__83_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__83_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__83_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__83_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__83_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_543 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2063 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_543 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2064 } ) ) ;
cby_1__1_ cby_8__1_ (
    .prog_clk ( { ctsbuf_net_5601478 } ) ,
    .chany_bottom_in ( sb_1__0__7_chany_top_out ) , 
    .chany_top_in ( sb_1__1__77_chany_bottom_out ) , 
    .ccff_head ( grid_clb_84_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__84_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__84_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__84_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__84_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__84_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__84_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__84_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__84_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__84_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__84_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__84_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__84_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__84_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__84_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__84_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__84_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__84_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__84_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__84_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_414 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2065 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_414 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2066 } ) ) ;
cby_1__1_ cby_8__2_ (
    .prog_clk ( { ctsbuf_net_5381456 } ) ,
    .chany_bottom_in ( sb_1__1__77_chany_top_out ) , 
    .chany_top_in ( sb_1__1__78_chany_bottom_out ) , 
    .ccff_head ( grid_clb_85_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__85_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__85_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__85_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__85_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__85_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__85_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__85_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__85_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__85_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__85_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__85_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__85_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__85_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__85_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__85_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__85_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__85_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__85_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__85_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_489 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2067 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_489 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2068 } ) ) ;
cby_1__1_ cby_8__3_ (
    .prog_clk ( { ctsbuf_net_5081426 } ) ,
    .chany_bottom_in ( sb_1__1__78_chany_top_out ) , 
    .chany_top_in ( sb_1__1__79_chany_bottom_out ) , 
    .ccff_head ( grid_clb_86_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__86_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__86_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__86_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__86_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__86_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__86_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__86_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__86_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__86_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__86_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__86_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__86_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__86_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__86_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__86_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__86_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__86_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__86_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__86_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_526 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2069 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_526 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2070 } ) ) ;
cby_1__1_ cby_8__4_ (
    .prog_clk ( { ctsbuf_net_4711389 } ) ,
    .chany_bottom_in ( sb_1__1__79_chany_top_out ) , 
    .chany_top_in ( sb_1__1__80_chany_bottom_out ) , 
    .ccff_head ( grid_clb_87_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__87_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__87_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__87_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__87_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__87_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__87_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__87_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__87_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__87_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__87_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__87_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__87_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__87_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__87_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__87_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__87_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__87_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__87_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__87_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_733 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2071 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_733 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2072 } ) ) ;
cby_1__1_ cby_8__5_ (
    .prog_clk ( { p_abuf40 } ) ,
    .chany_bottom_in ( sb_1__1__80_chany_top_out ) , 
    .chany_top_in ( sb_1__1__81_chany_bottom_out ) , 
    .ccff_head ( grid_clb_88_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__88_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__88_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__88_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__88_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__88_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__88_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__88_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__88_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__88_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__88_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__88_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__88_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__88_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__88_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__88_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__88_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__88_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__88_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__88_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_889 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2073 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_889 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2074 } ) ) ;
cby_1__1_ cby_8__6_ (
    .prog_clk ( { ctsbuf_net_3781296 } ) ,
    .chany_bottom_in ( sb_1__1__81_chany_top_out ) , 
    .chany_top_in ( sb_1__1__82_chany_bottom_out ) , 
    .ccff_head ( grid_clb_89_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__89_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__89_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__89_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__89_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__89_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__89_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__89_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__89_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__89_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__89_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__89_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__89_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__89_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__89_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__89_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__89_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__89_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__89_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__89_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_859 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2075 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_859 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2076 } ) ) ;
cby_1__1_ cby_8__7_ (
    .prog_clk ( { p_abuf32 } ) ,
    .chany_bottom_in ( sb_1__1__82_chany_top_out ) , 
    .chany_top_in ( sb_1__1__83_chany_bottom_out ) , 
    .ccff_head ( grid_clb_90_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__90_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__90_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__90_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__90_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__90_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__90_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__90_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__90_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__90_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__90_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__90_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__90_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__90_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__90_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__90_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__90_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__90_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__90_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__90_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_810 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2077 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_810 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2078 } ) ) ;
cby_1__1_ cby_8__8_ (
    .prog_clk ( { ctsbuf_net_2821200 } ) ,
    .chany_bottom_in ( sb_1__1__83_chany_top_out ) , 
    .chany_top_in ( sb_1__1__84_chany_bottom_out ) , 
    .ccff_head ( grid_clb_91_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__91_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__91_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__91_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__91_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__91_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__91_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__91_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__91_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__91_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__91_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__91_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__91_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__91_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__91_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__91_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__91_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__91_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__91_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__91_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_866 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2079 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_866 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2080 } ) ) ;
cby_1__1_ cby_8__9_ (
    .prog_clk ( { ctsbuf_net_2341152 } ) ,
    .chany_bottom_in ( sb_1__1__84_chany_top_out ) , 
    .chany_top_in ( sb_1__1__85_chany_bottom_out ) , 
    .ccff_head ( grid_clb_92_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__92_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__92_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__92_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__92_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__92_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__92_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__92_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__92_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__92_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__92_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__92_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__92_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__92_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__92_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__92_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__92_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__92_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__92_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__92_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_591 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2081 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_591 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2082 } ) ) ;
cby_1__1_ cby_8__10_ (
    .prog_clk ( { ctsbuf_net_1861104 } ) ,
    .chany_bottom_in ( sb_1__1__85_chany_top_out ) , 
    .chany_top_in ( sb_1__1__86_chany_bottom_out ) , 
    .ccff_head ( grid_clb_93_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__93_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__93_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__93_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__93_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__93_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__93_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__93_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__93_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__93_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__93_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__93_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__93_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__93_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__93_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__93_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__93_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__93_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__93_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__93_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_435 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2083 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_435 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2084 } ) ) ;
cby_1__1_ cby_8__11_ (
    .prog_clk ( { p_abuf12 } ) ,
    .chany_bottom_in ( sb_1__1__86_chany_top_out ) , 
    .chany_top_in ( sb_1__1__87_chany_bottom_out ) , 
    .ccff_head ( grid_clb_94_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__94_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__94_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__94_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__94_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__94_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__94_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__94_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__94_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__94_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__94_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__94_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__94_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__94_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__94_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__94_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__94_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__94_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__94_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__94_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_596 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2085 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_596 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2086 } ) ) ;
cby_1__1_ cby_8__12_ (
    .prog_clk ( { ctsbuf_net_1001018 } ) ,
    .chany_bottom_in ( sb_1__1__87_chany_top_out ) , 
    .chany_top_in ( sb_1__12__7_chany_bottom_out ) , 
    .ccff_head ( grid_clb_95_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__95_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__95_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__95_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__95_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__95_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__95_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__95_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__95_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__95_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__95_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__95_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__95_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__95_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__95_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__95_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__95_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__95_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__95_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__95_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_339 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2087 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_339 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2088 } ) ) ;
cby_1__1_ cby_9__1_ (
    .prog_clk ( { ctsbuf_net_5371455 } ) ,
    .chany_bottom_in ( sb_1__0__8_chany_top_out ) , 
    .chany_top_in ( sb_1__1__88_chany_bottom_out ) , 
    .ccff_head ( grid_clb_96_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__96_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__96_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__96_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__96_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__96_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__96_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__96_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__96_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__96_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__96_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__96_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__96_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__96_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__96_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__96_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__96_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__96_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__96_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__96_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_853 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2089 } ) ,
    
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) , 
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) ) ;
cby_1__1_ cby_9__2_ (
    .prog_clk ( { ctsbuf_net_5071425 } ) ,
    .chany_bottom_in ( sb_1__1__88_chany_top_out ) , 
    .chany_top_in ( sb_1__1__89_chany_bottom_out ) , 
    .ccff_head ( grid_clb_97_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__97_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__97_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__97_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__97_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__97_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__97_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__97_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__97_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__97_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__97_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__97_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__97_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__97_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__97_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__97_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__97_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__97_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__97_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__97_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_555 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2090 } ) ) ;
cby_1__1_ cby_9__3_ (
    .prog_clk ( { ctsbuf_net_4691387 } ) ,
    .chany_bottom_in ( sb_1__1__89_chany_top_out ) , 
    .chany_top_in ( sb_1__1__90_chany_bottom_out ) , 
    .ccff_head ( grid_clb_98_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__98_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__98_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__98_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__98_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__98_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__98_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__98_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__98_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__98_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__98_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__98_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__98_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__98_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__98_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__98_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__98_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__98_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__98_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__98_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_6 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_913 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2091 } ) ) ;
cby_1__1_ cby_9__4_ (
    .prog_clk ( { ctsbuf_net_4241342 } ) ,
    .chany_bottom_in ( sb_1__1__90_chany_top_out ) , 
    .chany_top_in ( sb_1__1__91_chany_bottom_out ) , 
    .ccff_head ( grid_clb_99_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__99_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__99_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__99_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__99_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__99_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__99_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__99_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__99_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__99_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__99_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__99_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__99_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__99_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__99_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__99_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__99_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__99_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__99_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__99_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_7 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_8 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_560 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2092 } ) ) ;
cby_1__1_ cby_9__5_ (
    .prog_clk ( { ctsbuf_net_3761294 } ) ,
    .chany_bottom_in ( sb_1__1__91_chany_top_out ) , 
    .chany_top_in ( sb_1__1__92_chany_bottom_out ) , 
    .ccff_head ( grid_clb_100_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__100_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__100_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__100_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__100_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__100_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__100_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__100_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__100_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__100_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__100_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__100_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__100_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__100_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__100_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__100_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__100_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__100_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__100_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__100_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_9 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_10 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_857 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2093 } ) ) ;
cby_1__1_ cby_9__6_ (
    .prog_clk ( { ctsbuf_net_3281246 } ) ,
    .chany_bottom_in ( sb_1__1__92_chany_top_out ) , 
    .chany_top_in ( sb_1__1__93_chany_bottom_out ) , 
    .ccff_head ( grid_clb_101_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__101_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__101_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__101_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__101_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__101_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__101_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__101_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__101_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__101_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__101_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__101_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__101_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__101_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__101_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__101_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__101_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__101_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__101_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__101_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_11 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_12 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_901 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2094 } ) ) ;
cby_1__1_ cby_9__7_ (
    .prog_clk ( { ctsbuf_net_2801198 } ) ,
    .chany_bottom_in ( sb_1__1__93_chany_top_out ) , 
    .chany_top_in ( sb_1__1__94_chany_bottom_out ) , 
    .ccff_head ( grid_clb_102_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__102_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__102_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__102_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__102_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__102_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__102_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__102_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__102_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__102_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__102_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__102_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__102_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__102_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__102_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__102_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__102_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__102_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__102_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__102_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_13 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_14 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_322 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2095 } ) ) ;
cby_1__1_ cby_9__8_ (
    .prog_clk ( { ctsbuf_net_2321150 } ) ,
    .chany_bottom_in ( sb_1__1__94_chany_top_out ) , 
    .chany_top_in ( sb_1__1__95_chany_bottom_out ) , 
    .ccff_head ( grid_clb_103_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__103_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__103_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__103_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__103_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__103_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__103_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__103_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__103_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__103_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__103_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__103_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__103_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__103_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__103_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__103_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__103_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__103_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__103_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__103_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_15 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_16 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_510 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2096 } ) ) ;
cby_1__1_ cby_9__9_ (
    .prog_clk ( { p_abuf21 } ) ,
    .chany_bottom_in ( sb_1__1__95_chany_top_out ) , 
    .chany_top_in ( sb_1__1__96_chany_bottom_out ) , 
    .ccff_head ( grid_clb_104_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__104_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__104_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__104_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__104_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__104_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__104_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__104_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__104_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__104_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__104_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__104_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__104_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__104_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__104_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__104_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__104_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__104_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__104_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__104_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_17 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_18 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_601 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2097 } ) ) ;
cby_1__1_ cby_9__10_ (
    .prog_clk ( { ctsbuf_net_1381056 } ) ,
    .chany_bottom_in ( sb_1__1__96_chany_top_out ) , 
    .chany_top_in ( sb_1__1__97_chany_bottom_out ) , 
    .ccff_head ( grid_clb_105_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__105_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__105_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__105_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__105_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__105_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__105_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__105_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__105_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__105_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__105_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__105_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__105_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__105_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__105_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__105_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__105_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__105_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__105_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__105_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_19 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_20 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_546 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2098 } ) ) ;
cby_1__1_ cby_9__11_ (
    .prog_clk ( { ctsbuf_net_981016 } ) ,
    .chany_bottom_in ( sb_1__1__97_chany_top_out ) , 
    .chany_top_in ( sb_1__1__98_chany_bottom_out ) , 
    .ccff_head ( grid_clb_106_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__106_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__106_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__106_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__106_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__106_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__106_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__106_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__106_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__106_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__106_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__106_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__106_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__106_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__106_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__106_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__106_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__106_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__106_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__106_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_21 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_22 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_813 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2099 } ) ) ;
cby_1__1_ cby_9__12_ (
    .prog_clk ( { ctsbuf_net_65983 } ) ,
    .chany_bottom_in ( sb_1__1__98_chany_top_out ) , 
    .chany_top_in ( sb_1__12__8_chany_bottom_out ) , 
    .ccff_head ( grid_clb_107_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__107_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__107_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__107_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__107_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__107_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__107_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__107_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__107_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__107_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__107_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__107_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__107_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__107_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__107_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__107_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__107_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__107_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__107_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__107_ccff_tail ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_23 ) , 
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_24 ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_839 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2100 } ) ) ;
cby_1__1_ cby_10__1_ (
    .prog_clk ( { ctsbuf_net_5061424 } ) ,
    .chany_bottom_in ( sb_1__0__9_chany_top_out ) , 
    .chany_top_in ( sb_1__1__99_chany_bottom_out ) , 
    .ccff_head ( grid_clb_108_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__108_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__108_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__108_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__108_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__108_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__108_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__108_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__108_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__108_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__108_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__108_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__108_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__108_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__108_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__108_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__108_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__108_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__108_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__108_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_570 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2101 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_570 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2102 } ) ) ;
cby_1__1_ cby_10__2_ (
    .prog_clk ( { ctsbuf_net_4681386 } ) ,
    .chany_bottom_in ( sb_1__1__99_chany_top_out ) , 
    .chany_top_in ( sb_1__1__100_chany_bottom_out ) , 
    .ccff_head ( grid_clb_109_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__109_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__109_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__109_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__109_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__109_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__109_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__109_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__109_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__109_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__109_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__109_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__109_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__109_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__109_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__109_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__109_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__109_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__109_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__109_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_498 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2103 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_498 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2104 } ) ) ;
cby_1__1_ cby_10__3_ (
    .prog_clk ( { ctsbuf_net_4211339 } ) ,
    .chany_bottom_in ( sb_1__1__100_chany_top_out ) , 
    .chany_top_in ( sb_1__1__101_chany_bottom_out ) , 
    .ccff_head ( grid_clb_110_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__110_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__110_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__110_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__110_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__110_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__110_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__110_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__110_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__110_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__110_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__110_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__110_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__110_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__110_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__110_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__110_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__110_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__110_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__110_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_341 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2105 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_341 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2106 } ) ) ;
cby_1__1_ cby_10__4_ (
    .prog_clk ( { ctsbuf_net_3731291 } ) ,
    .chany_bottom_in ( sb_1__1__101_chany_top_out ) , 
    .chany_top_in ( sb_1__1__102_chany_bottom_out ) , 
    .ccff_head ( grid_clb_111_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__111_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__111_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__111_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__111_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__111_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__111_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__111_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__111_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__111_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__111_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__111_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__111_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__111_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__111_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__111_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__111_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__111_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__111_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__111_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_716 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2107 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_716 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2108 } ) ) ;
cby_1__1_ cby_10__5_ (
    .prog_clk ( { ctsbuf_net_3251243 } ) ,
    .chany_bottom_in ( sb_1__1__102_chany_top_out ) , 
    .chany_top_in ( sb_1__1__103_chany_bottom_out ) , 
    .ccff_head ( grid_clb_112_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__112_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__112_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__112_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__112_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__112_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__112_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__112_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__112_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__112_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__112_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__112_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__112_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__112_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__112_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__112_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__112_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__112_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__112_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__112_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_328 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2109 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_328 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2110 } ) ) ;
cby_1__1_ cby_10__6_ (
    .prog_clk ( { ctsbuf_net_2771195 } ) ,
    .chany_bottom_in ( sb_1__1__103_chany_top_out ) , 
    .chany_top_in ( sb_1__1__104_chany_bottom_out ) , 
    .ccff_head ( grid_clb_113_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__113_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__113_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__113_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__113_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__113_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__113_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__113_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__113_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__113_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__113_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__113_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__113_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__113_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__113_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__113_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__113_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__113_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__113_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__113_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_298 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2111 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_298 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2112 } ) ) ;
cby_1__1_ cby_10__7_ (
    .prog_clk ( { ctsbuf_net_2601178 } ) ,
    .chany_bottom_in ( sb_1__1__104_chany_top_out ) , 
    .chany_top_in ( sb_1__1__105_chany_bottom_out ) , 
    .ccff_head ( grid_clb_114_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__114_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__114_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__114_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__114_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__114_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__114_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__114_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__114_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__114_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__114_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__114_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__114_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__114_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__114_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__114_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__114_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__114_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__114_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__114_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_333 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2113 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_333 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2114 } ) ) ;
cby_1__1_ cby_10__8_ (
    .prog_clk ( { ctsbuf_net_1811099 } ) ,
    .chany_bottom_in ( sb_1__1__105_chany_top_out ) , 
    .chany_top_in ( sb_1__1__106_chany_bottom_out ) , 
    .ccff_head ( grid_clb_115_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__115_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__115_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__115_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__115_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__115_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__115_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__115_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__115_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__115_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__115_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__115_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__115_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__115_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__115_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__115_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__115_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__115_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__115_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__115_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_318 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2115 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_318 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2116 } ) ) ;
cby_1__1_ cby_10__9_ (
    .prog_clk ( { ctsbuf_net_1351053 } ) ,
    .chany_bottom_in ( sb_1__1__106_chany_top_out ) , 
    .chany_top_in ( sb_1__1__107_chany_bottom_out ) , 
    .ccff_head ( grid_clb_116_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__116_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__116_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__116_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__116_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__116_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__116_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__116_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__116_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__116_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__116_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__116_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__116_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__116_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__116_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__116_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__116_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__116_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__116_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__116_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_773 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2117 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_773 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2118 } ) ) ;
cby_1__1_ cby_10__10_ (
    .prog_clk ( { ctsbuf_net_951013 } ) ,
    .chany_bottom_in ( sb_1__1__107_chany_top_out ) , 
    .chany_top_in ( sb_1__1__108_chany_bottom_out ) , 
    .ccff_head ( grid_clb_117_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__117_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__117_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__117_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__117_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__117_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__117_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__117_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__117_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__117_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__117_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__117_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__117_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__117_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__117_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__117_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__117_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__117_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__117_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__117_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_739 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2119 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_739 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2120 } ) ) ;
cby_1__1_ cby_10__11_ (
    .prog_clk ( { ctsbuf_net_62980 } ) ,
    .chany_bottom_in ( sb_1__1__108_chany_top_out ) , 
    .chany_top_in ( sb_1__1__109_chany_bottom_out ) , 
    .ccff_head ( grid_clb_118_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__118_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__118_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__118_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__118_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__118_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__118_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__118_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__118_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__118_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__118_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__118_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__118_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__118_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__118_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__118_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__118_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__118_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__118_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__118_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_676 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2121 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_676 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2122 } ) ) ;
cby_1__1_ cby_10__12_ (
    .prog_clk ( { ctsbuf_net_37955 } ) ,
    .chany_bottom_in ( sb_1__1__109_chany_top_out ) , 
    .chany_top_in ( sb_1__12__9_chany_bottom_out ) , 
    .ccff_head ( grid_clb_119_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__119_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__119_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__119_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__119_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__119_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__119_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__119_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__119_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__119_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__119_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__119_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__119_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__119_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__119_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__119_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__119_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__119_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__119_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__119_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_666 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2123 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_666 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2124 } ) ) ;
cby_1__1_ cby_11__1_ (
    .prog_clk ( { ctsbuf_net_4671385 } ) ,
    .chany_bottom_in ( sb_1__0__10_chany_top_out ) , 
    .chany_top_in ( sb_1__1__110_chany_bottom_out ) , 
    .ccff_head ( grid_clb_120_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__120_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__120_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__120_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__120_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__120_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__120_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__120_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__120_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__120_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__120_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__120_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__120_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__120_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__120_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__120_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__120_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__120_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__120_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__120_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_599 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2125 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_599 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2126 } ) ) ;
cby_1__1_ cby_11__2_ (
    .prog_clk ( { ctsbuf_net_4201338 } ) ,
    .chany_bottom_in ( sb_1__1__110_chany_top_out ) , 
    .chany_top_in ( sb_1__1__111_chany_bottom_out ) , 
    .ccff_head ( grid_clb_121_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__121_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__121_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__121_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__121_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__121_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__121_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__121_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__121_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__121_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__121_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__121_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__121_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__121_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__121_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__121_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__121_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__121_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__121_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__121_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_373 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2127 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_373 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2128 } ) ) ;
cby_1__1_ cby_11__3_ (
    .prog_clk ( { ctsbuf_net_3721290 } ) ,
    .chany_bottom_in ( sb_1__1__111_chany_top_out ) , 
    .chany_top_in ( sb_1__1__112_chany_bottom_out ) , 
    .ccff_head ( grid_clb_122_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__122_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__122_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__122_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__122_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__122_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__122_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__122_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__122_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__122_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__122_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__122_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__122_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__122_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__122_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__122_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__122_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__122_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__122_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__122_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_798 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2129 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_798 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2130 } ) ) ;
cby_1__1_ cby_11__4_ (
    .prog_clk ( { ctsbuf_net_3241242 } ) ,
    .chany_bottom_in ( sb_1__1__112_chany_top_out ) , 
    .chany_top_in ( sb_1__1__113_chany_bottom_out ) , 
    .ccff_head ( grid_clb_123_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__123_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__123_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__123_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__123_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__123_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__123_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__123_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__123_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__123_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__123_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__123_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__123_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__123_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__123_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__123_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__123_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__123_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__123_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__123_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_778 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2131 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_778 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2132 } ) ) ;
cby_1__1_ cby_11__5_ (
    .prog_clk ( { ctsbuf_net_2761194 } ) ,
    .chany_bottom_in ( sb_1__1__113_chany_top_out ) , 
    .chany_top_in ( sb_1__1__114_chany_bottom_out ) , 
    .ccff_head ( grid_clb_124_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__124_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__124_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__124_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__124_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__124_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__124_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__124_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__124_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__124_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__124_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__124_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__124_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__124_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__124_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__124_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__124_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__124_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__124_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__124_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_400 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2133 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_400 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2134 } ) ) ;
cby_1__1_ cby_11__6_ (
    .prog_clk ( { ctsbuf_net_2281146 } ) ,
    .chany_bottom_in ( sb_1__1__114_chany_top_out ) , 
    .chany_top_in ( sb_1__1__115_chany_bottom_out ) , 
    .ccff_head ( grid_clb_125_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__125_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__125_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__125_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__125_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__125_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__125_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__125_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__125_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__125_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__125_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__125_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__125_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__125_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__125_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__125_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__125_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__125_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__125_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__125_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_449 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2135 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_449 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2136 } ) ) ;
cby_1__1_ cby_11__7_ (
    .prog_clk ( { ctsbuf_net_1801098 } ) ,
    .chany_bottom_in ( sb_1__1__115_chany_top_out ) , 
    .chany_top_in ( sb_1__1__116_chany_bottom_out ) , 
    .ccff_head ( grid_clb_126_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__126_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__126_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__126_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__126_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__126_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__126_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__126_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__126_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__126_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__126_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__126_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__126_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__126_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__126_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__126_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__126_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__126_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__126_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__126_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_530 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2137 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_530 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2138 } ) ) ;
cby_1__1_ cby_11__8_ (
    .prog_clk ( { ctsbuf_net_1341052 } ) ,
    .chany_bottom_in ( sb_1__1__116_chany_top_out ) , 
    .chany_top_in ( sb_1__1__117_chany_bottom_out ) , 
    .ccff_head ( grid_clb_127_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__127_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__127_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__127_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__127_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__127_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__127_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__127_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__127_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__127_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__127_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__127_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__127_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__127_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__127_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__127_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__127_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__127_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__127_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__127_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_287 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2139 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_287 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2140 } ) ) ;
cby_1__1_ cby_11__9_ (
    .prog_clk ( { ctsbuf_net_941012 } ) ,
    .chany_bottom_in ( sb_1__1__117_chany_top_out ) , 
    .chany_top_in ( sb_1__1__118_chany_bottom_out ) , 
    .ccff_head ( grid_clb_128_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__128_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__128_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__128_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__128_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__128_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__128_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__128_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__128_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__128_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__128_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__128_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__128_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__128_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__128_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__128_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__128_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__128_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__128_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__128_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_264 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2141 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_264 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2142 } ) ) ;
cby_1__1_ cby_11__10_ (
    .prog_clk ( { ctsbuf_net_61979 } ) ,
    .chany_bottom_in ( sb_1__1__118_chany_top_out ) , 
    .chany_top_in ( sb_1__1__119_chany_bottom_out ) , 
    .ccff_head ( grid_clb_129_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__129_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__129_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__129_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__129_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__129_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__129_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__129_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__129_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__129_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__129_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__129_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__129_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__129_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__129_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__129_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__129_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__129_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__129_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__129_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_497 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2143 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_497 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2144 } ) ) ;
cby_1__1_ cby_11__11_ (
    .prog_clk ( { ctsbuf_net_36954 } ) ,
    .chany_bottom_in ( sb_1__1__119_chany_top_out ) , 
    .chany_top_in ( sb_1__1__120_chany_bottom_out ) , 
    .ccff_head ( grid_clb_130_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__130_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__130_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__130_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__130_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__130_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__130_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__130_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__130_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__130_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__130_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__130_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__130_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__130_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__130_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__130_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__130_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__130_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__130_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__130_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_357 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2145 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_357 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2146 } ) ) ;
cby_1__1_ cby_11__12_ (
    .prog_clk ( { ctsbuf_net_19937 } ) ,
    .chany_bottom_in ( sb_1__1__120_chany_top_out ) , 
    .chany_top_in ( sb_1__12__10_chany_bottom_out ) , 
    .ccff_head ( grid_clb_131_ccff_tail ) , 
    .chany_bottom_out ( cby_1__1__131_chany_bottom_out ) , 
    .chany_top_out ( cby_1__1__131_chany_top_out ) , 
    .left_grid_pin_16_ ( cby_1__1__131_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_1__1__131_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_1__1__131_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_1__1__131_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_1__1__131_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_1__1__131_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_1__1__131_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_1__1__131_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_1__1__131_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_1__1__131_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_1__1__131_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_1__1__131_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_1__1__131_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_1__1__131_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_1__1__131_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_1__1__131_left_grid_pin_31_ ) , 
    .ccff_tail ( cby_1__1__131_ccff_tail ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_796 } ) ,
    .grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2147 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( { 
        optlc_net_796 } ) ,
    .grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( { 
        SYNOPSYS_UNCONNECTED_2148 } ) ) ;
cby_2__1_ cby_12__1_ (
    .prog_clk ( { ctsbuf_net_4191337 } ) ,
    .chany_bottom_in ( sb_12__0__0_chany_top_out ) , 
    .chany_top_in ( sb_12__1__0_chany_bottom_out ) , 
    .ccff_head ( grid_clb_132_ccff_tail ) , 
    .chany_bottom_out ( cby_12__1__0_chany_bottom_out ) , 
    .chany_top_out ( cby_12__1__0_chany_top_out ) , 
    .right_grid_pin_0_ ( cby_12__1__0_right_grid_pin_0_ ) , 
    .left_grid_pin_16_ ( cby_12__1__0_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_12__1__0_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_12__1__0_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_12__1__0_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_12__1__0_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_12__1__0_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_12__1__0_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_12__1__0_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_12__1__0_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_12__1__0_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_12__1__0_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_12__1__0_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_12__1__0_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_12__1__0_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_12__1__0_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_12__1__0_left_grid_pin_31_ ) , 
    .ccff_tail ( grid_io_right_0_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[12] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[12] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[12] ) , 
    .left_width_0_height_0__pin_0_ ( cby_12__1__0_right_grid_pin_0_ ) , 
    .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , 
    .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) ) ;
cby_2__1_ cby_12__2_ (
    .prog_clk ( { ctsbuf_net_3711289 } ) ,
    .chany_bottom_in ( sb_12__1__0_chany_top_out ) , 
    .chany_top_in ( sb_12__1__1_chany_bottom_out ) , 
    .ccff_head ( grid_clb_133_ccff_tail ) , 
    .chany_bottom_out ( cby_12__1__1_chany_bottom_out ) , 
    .chany_top_out ( cby_12__1__1_chany_top_out ) , 
    .right_grid_pin_0_ ( cby_12__1__1_right_grid_pin_0_ ) , 
    .left_grid_pin_16_ ( cby_12__1__1_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_12__1__1_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_12__1__1_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_12__1__1_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_12__1__1_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_12__1__1_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_12__1__1_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_12__1__1_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_12__1__1_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_12__1__1_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_12__1__1_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_12__1__1_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_12__1__1_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_12__1__1_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_12__1__1_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_12__1__1_left_grid_pin_31_ ) , 
    .ccff_tail ( grid_io_right_1_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[13] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[13] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[13] ) , 
    .left_width_0_height_0__pin_0_ ( cby_12__1__1_right_grid_pin_0_ ) , 
    .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , 
    .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) ) ;
cby_2__1_ cby_12__3_ (
    .prog_clk ( { ctsbuf_net_3231241 } ) ,
    .chany_bottom_in ( sb_12__1__1_chany_top_out ) , 
    .chany_top_in ( sb_12__1__2_chany_bottom_out ) , 
    .ccff_head ( grid_clb_134_ccff_tail ) , 
    .chany_bottom_out ( cby_12__1__2_chany_bottom_out ) , 
    .chany_top_out ( cby_12__1__2_chany_top_out ) , 
    .right_grid_pin_0_ ( cby_12__1__2_right_grid_pin_0_ ) , 
    .left_grid_pin_16_ ( cby_12__1__2_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_12__1__2_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_12__1__2_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_12__1__2_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_12__1__2_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_12__1__2_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_12__1__2_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_12__1__2_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_12__1__2_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_12__1__2_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_12__1__2_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_12__1__2_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_12__1__2_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_12__1__2_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_12__1__2_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_12__1__2_left_grid_pin_31_ ) , 
    .ccff_tail ( grid_io_right_2_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[14] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[14] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[14] ) , 
    .left_width_0_height_0__pin_0_ ( cby_12__1__2_right_grid_pin_0_ ) , 
    .left_width_0_height_0__pin_1_upper ( grid_io_right_2_left_width_0_height_0__pin_1_upper ) , 
    .left_width_0_height_0__pin_1_lower ( grid_io_right_2_left_width_0_height_0__pin_1_lower ) ) ;
cby_2__1_ cby_12__4_ (
    .prog_clk ( { ctsbuf_net_2751193 } ) ,
    .chany_bottom_in ( sb_12__1__2_chany_top_out ) , 
    .chany_top_in ( sb_12__1__3_chany_bottom_out ) , 
    .ccff_head ( grid_clb_135_ccff_tail ) , 
    .chany_bottom_out ( cby_12__1__3_chany_bottom_out ) , 
    .chany_top_out ( cby_12__1__3_chany_top_out ) , 
    .right_grid_pin_0_ ( cby_12__1__3_right_grid_pin_0_ ) , 
    .left_grid_pin_16_ ( cby_12__1__3_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_12__1__3_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_12__1__3_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_12__1__3_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_12__1__3_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_12__1__3_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_12__1__3_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_12__1__3_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_12__1__3_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_12__1__3_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_12__1__3_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_12__1__3_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_12__1__3_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_12__1__3_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_12__1__3_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_12__1__3_left_grid_pin_31_ ) , 
    .ccff_tail ( grid_io_right_3_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[15] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[15] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[15] ) , 
    .left_width_0_height_0__pin_0_ ( cby_12__1__3_right_grid_pin_0_ ) , 
    .left_width_0_height_0__pin_1_upper ( grid_io_right_3_left_width_0_height_0__pin_1_upper ) , 
    .left_width_0_height_0__pin_1_lower ( grid_io_right_3_left_width_0_height_0__pin_1_lower ) ) ;
cby_2__1_ cby_12__5_ (
    .prog_clk ( { ctsbuf_net_2271145 } ) ,
    .chany_bottom_in ( sb_12__1__3_chany_top_out ) , 
    .chany_top_in ( sb_12__1__4_chany_bottom_out ) , 
    .ccff_head ( grid_clb_136_ccff_tail ) , 
    .chany_bottom_out ( cby_12__1__4_chany_bottom_out ) , 
    .chany_top_out ( cby_12__1__4_chany_top_out ) , 
    .right_grid_pin_0_ ( cby_12__1__4_right_grid_pin_0_ ) , 
    .left_grid_pin_16_ ( cby_12__1__4_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_12__1__4_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_12__1__4_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_12__1__4_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_12__1__4_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_12__1__4_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_12__1__4_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_12__1__4_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_12__1__4_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_12__1__4_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_12__1__4_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_12__1__4_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_12__1__4_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_12__1__4_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_12__1__4_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_12__1__4_left_grid_pin_31_ ) , 
    .ccff_tail ( grid_io_right_4_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[16] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[16] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[16] ) , 
    .left_width_0_height_0__pin_0_ ( cby_12__1__4_right_grid_pin_0_ ) , 
    .left_width_0_height_0__pin_1_upper ( grid_io_right_4_left_width_0_height_0__pin_1_upper ) , 
    .left_width_0_height_0__pin_1_lower ( grid_io_right_4_left_width_0_height_0__pin_1_lower ) ) ;
cby_2__1_ cby_12__6_ (
    .prog_clk ( { ctsbuf_net_1791097 } ) ,
    .chany_bottom_in ( sb_12__1__4_chany_top_out ) , 
    .chany_top_in ( sb_12__1__5_chany_bottom_out ) , 
    .ccff_head ( grid_clb_137_ccff_tail ) , 
    .chany_bottom_out ( cby_12__1__5_chany_bottom_out ) , 
    .chany_top_out ( cby_12__1__5_chany_top_out ) , 
    .right_grid_pin_0_ ( cby_12__1__5_right_grid_pin_0_ ) , 
    .left_grid_pin_16_ ( cby_12__1__5_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_12__1__5_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_12__1__5_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_12__1__5_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_12__1__5_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_12__1__5_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_12__1__5_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_12__1__5_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_12__1__5_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_12__1__5_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_12__1__5_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_12__1__5_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_12__1__5_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_12__1__5_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_12__1__5_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_12__1__5_left_grid_pin_31_ ) , 
    .ccff_tail ( grid_io_right_5_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[17] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[17] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[17] ) , 
    .left_width_0_height_0__pin_0_ ( cby_12__1__5_right_grid_pin_0_ ) , 
    .left_width_0_height_0__pin_1_upper ( grid_io_right_5_left_width_0_height_0__pin_1_upper ) , 
    .left_width_0_height_0__pin_1_lower ( grid_io_right_5_left_width_0_height_0__pin_1_lower ) ) ;
cby_2__1_ cby_12__7_ (
    .prog_clk ( { ctsbuf_net_1331051 } ) ,
    .chany_bottom_in ( sb_12__1__5_chany_top_out ) , 
    .chany_top_in ( sb_12__1__6_chany_bottom_out ) , 
    .ccff_head ( grid_clb_138_ccff_tail ) , 
    .chany_bottom_out ( cby_12__1__6_chany_bottom_out ) , 
    .chany_top_out ( cby_12__1__6_chany_top_out ) , 
    .right_grid_pin_0_ ( cby_12__1__6_right_grid_pin_0_ ) , 
    .left_grid_pin_16_ ( cby_12__1__6_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_12__1__6_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_12__1__6_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_12__1__6_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_12__1__6_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_12__1__6_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_12__1__6_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_12__1__6_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_12__1__6_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_12__1__6_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_12__1__6_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_12__1__6_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_12__1__6_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_12__1__6_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_12__1__6_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_12__1__6_left_grid_pin_31_ ) , 
    .ccff_tail ( grid_io_right_6_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[18] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[18] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[18] ) , 
    .left_width_0_height_0__pin_0_ ( cby_12__1__6_right_grid_pin_0_ ) , 
    .left_width_0_height_0__pin_1_upper ( grid_io_right_6_left_width_0_height_0__pin_1_upper ) , 
    .left_width_0_height_0__pin_1_lower ( grid_io_right_6_left_width_0_height_0__pin_1_lower ) ) ;
cby_2__1_ cby_12__8_ (
    .prog_clk ( { ctsbuf_net_931011 } ) ,
    .chany_bottom_in ( sb_12__1__6_chany_top_out ) , 
    .chany_top_in ( sb_12__1__7_chany_bottom_out ) , 
    .ccff_head ( grid_clb_139_ccff_tail ) , 
    .chany_bottom_out ( cby_12__1__7_chany_bottom_out ) , 
    .chany_top_out ( cby_12__1__7_chany_top_out ) , 
    .right_grid_pin_0_ ( cby_12__1__7_right_grid_pin_0_ ) , 
    .left_grid_pin_16_ ( cby_12__1__7_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_12__1__7_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_12__1__7_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_12__1__7_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_12__1__7_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_12__1__7_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_12__1__7_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_12__1__7_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_12__1__7_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_12__1__7_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_12__1__7_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_12__1__7_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_12__1__7_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_12__1__7_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_12__1__7_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_12__1__7_left_grid_pin_31_ ) , 
    .ccff_tail ( grid_io_right_7_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[19] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[19] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[19] ) , 
    .left_width_0_height_0__pin_0_ ( cby_12__1__7_right_grid_pin_0_ ) , 
    .left_width_0_height_0__pin_1_upper ( grid_io_right_7_left_width_0_height_0__pin_1_upper ) , 
    .left_width_0_height_0__pin_1_lower ( grid_io_right_7_left_width_0_height_0__pin_1_lower ) ) ;
cby_2__1_ cby_12__9_ (
    .prog_clk ( { ctsbuf_net_60978 } ) ,
    .chany_bottom_in ( sb_12__1__7_chany_top_out ) , 
    .chany_top_in ( sb_12__1__8_chany_bottom_out ) , 
    .ccff_head ( grid_clb_140_ccff_tail ) , 
    .chany_bottom_out ( cby_12__1__8_chany_bottom_out ) , 
    .chany_top_out ( cby_12__1__8_chany_top_out ) , 
    .right_grid_pin_0_ ( cby_12__1__8_right_grid_pin_0_ ) , 
    .left_grid_pin_16_ ( cby_12__1__8_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_12__1__8_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_12__1__8_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_12__1__8_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_12__1__8_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_12__1__8_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_12__1__8_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_12__1__8_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_12__1__8_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_12__1__8_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_12__1__8_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_12__1__8_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_12__1__8_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_12__1__8_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_12__1__8_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_12__1__8_left_grid_pin_31_ ) , 
    .ccff_tail ( grid_io_right_8_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[20] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[20] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[20] ) , 
    .left_width_0_height_0__pin_0_ ( cby_12__1__8_right_grid_pin_0_ ) , 
    .left_width_0_height_0__pin_1_upper ( grid_io_right_8_left_width_0_height_0__pin_1_upper ) , 
    .left_width_0_height_0__pin_1_lower ( grid_io_right_8_left_width_0_height_0__pin_1_lower ) ) ;
cby_2__1_ cby_12__10_ (
    .prog_clk ( { ctsbuf_net_35953 } ) ,
    .chany_bottom_in ( sb_12__1__8_chany_top_out ) , 
    .chany_top_in ( sb_12__1__9_chany_bottom_out ) , 
    .ccff_head ( grid_clb_141_ccff_tail ) , 
    .chany_bottom_out ( cby_12__1__9_chany_bottom_out ) , 
    .chany_top_out ( cby_12__1__9_chany_top_out ) , 
    .right_grid_pin_0_ ( cby_12__1__9_right_grid_pin_0_ ) , 
    .left_grid_pin_16_ ( cby_12__1__9_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_12__1__9_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_12__1__9_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_12__1__9_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_12__1__9_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_12__1__9_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_12__1__9_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_12__1__9_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_12__1__9_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_12__1__9_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_12__1__9_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_12__1__9_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_12__1__9_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_12__1__9_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_12__1__9_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_12__1__9_left_grid_pin_31_ ) , 
    .ccff_tail ( grid_io_right_9_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[21] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[21] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[21] ) , 
    .left_width_0_height_0__pin_0_ ( cby_12__1__9_right_grid_pin_0_ ) , 
    .left_width_0_height_0__pin_1_upper ( grid_io_right_9_left_width_0_height_0__pin_1_upper ) , 
    .left_width_0_height_0__pin_1_lower ( grid_io_right_9_left_width_0_height_0__pin_1_lower ) ) ;
cby_2__1_ cby_12__11_ (
    .prog_clk ( { ctsbuf_net_18936 } ) ,
    .chany_bottom_in ( sb_12__1__9_chany_top_out ) , 
    .chany_top_in ( sb_12__1__10_chany_bottom_out ) , 
    .ccff_head ( grid_clb_142_ccff_tail ) , 
    .chany_bottom_out ( cby_12__1__10_chany_bottom_out ) , 
    .chany_top_out ( cby_12__1__10_chany_top_out ) , 
    .right_grid_pin_0_ ( cby_12__1__10_right_grid_pin_0_ ) , 
    .left_grid_pin_16_ ( cby_12__1__10_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_12__1__10_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_12__1__10_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_12__1__10_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_12__1__10_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_12__1__10_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_12__1__10_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_12__1__10_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_12__1__10_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_12__1__10_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_12__1__10_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_12__1__10_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_12__1__10_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_12__1__10_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_12__1__10_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_12__1__10_left_grid_pin_31_ ) , 
    .ccff_tail ( grid_io_right_10_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[22] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[22] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[22] ) , 
    .left_width_0_height_0__pin_0_ ( cby_12__1__10_right_grid_pin_0_ ) , 
    .left_width_0_height_0__pin_1_upper ( grid_io_right_10_left_width_0_height_0__pin_1_upper ) , 
    .left_width_0_height_0__pin_1_lower ( grid_io_right_10_left_width_0_height_0__pin_1_lower ) ) ;
cby_2__1_ cby_12__12_ (
    .prog_clk ( { ctsbuf_net_9927 } ) ,
    .chany_bottom_in ( sb_12__1__10_chany_top_out ) , 
    .chany_top_in ( sb_12__12__0_chany_bottom_out ) , 
    .ccff_head ( grid_clb_143_ccff_tail ) , 
    .chany_bottom_out ( cby_12__1__11_chany_bottom_out ) , 
    .chany_top_out ( cby_12__1__11_chany_top_out ) , 
    .right_grid_pin_0_ ( cby_12__1__11_right_grid_pin_0_ ) , 
    .left_grid_pin_16_ ( cby_12__1__11_left_grid_pin_16_ ) , 
    .left_grid_pin_17_ ( cby_12__1__11_left_grid_pin_17_ ) , 
    .left_grid_pin_18_ ( cby_12__1__11_left_grid_pin_18_ ) , 
    .left_grid_pin_19_ ( cby_12__1__11_left_grid_pin_19_ ) , 
    .left_grid_pin_20_ ( cby_12__1__11_left_grid_pin_20_ ) , 
    .left_grid_pin_21_ ( cby_12__1__11_left_grid_pin_21_ ) , 
    .left_grid_pin_22_ ( cby_12__1__11_left_grid_pin_22_ ) , 
    .left_grid_pin_23_ ( cby_12__1__11_left_grid_pin_23_ ) , 
    .left_grid_pin_24_ ( cby_12__1__11_left_grid_pin_24_ ) , 
    .left_grid_pin_25_ ( cby_12__1__11_left_grid_pin_25_ ) , 
    .left_grid_pin_26_ ( cby_12__1__11_left_grid_pin_26_ ) , 
    .left_grid_pin_27_ ( cby_12__1__11_left_grid_pin_27_ ) , 
    .left_grid_pin_28_ ( cby_12__1__11_left_grid_pin_28_ ) , 
    .left_grid_pin_29_ ( cby_12__1__11_left_grid_pin_29_ ) , 
    .left_grid_pin_30_ ( cby_12__1__11_left_grid_pin_30_ ) , 
    .left_grid_pin_31_ ( cby_12__1__11_left_grid_pin_31_ ) , 
    .ccff_tail ( grid_io_right_11_ccff_tail ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[23] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[23] ) , 
    .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[23] ) , 
    .left_width_0_height_0__pin_0_ ( cby_12__1__11_right_grid_pin_0_ ) , 
    .left_width_0_height_0__pin_1_upper ( grid_io_right_11_left_width_0_height_0__pin_1_upper ) , 
    .left_width_0_height_0__pin_1_lower ( grid_io_right_11_left_width_0_height_0__pin_1_lower ) ) ;
direct_interc_0 direct_interc_0_ ( 
    .in ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_0_out ) ) ;
direct_interc_1 direct_interc_1_ ( 
    .in ( grid_clb_2_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_1_out ) ) ;
direct_interc_2 direct_interc_2_ ( 
    .in ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_2_out ) ) ;
direct_interc_3 direct_interc_3_ ( 
    .in ( grid_clb_4_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_3_out ) ) ;
direct_interc_4 direct_interc_4_ ( 
    .in ( grid_clb_5_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_4_out ) ) ;
direct_interc_5 direct_interc_5_ ( 
    .in ( grid_clb_6_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_5_out ) ) ;
direct_interc_6 direct_interc_6_ ( 
    .in ( grid_clb_7_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_6_out ) ) ;
direct_interc_7 direct_interc_7_ ( 
    .in ( grid_clb_8_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_7_out ) ) ;
direct_interc_8 direct_interc_8_ ( 
    .in ( grid_clb_9_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_8_out ) ) ;
direct_interc_9 direct_interc_9_ ( 
    .in ( grid_clb_10_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_9_out ) ) ;
direct_interc_10 direct_interc_10_ ( 
    .in ( grid_clb_11_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_10_out ) ) ;
direct_interc_11 direct_interc_11_ ( 
    .in ( grid_clb_13_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_11_out ) ) ;
direct_interc_12 direct_interc_12_ ( 
    .in ( grid_clb_14_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_12_out ) ) ;
direct_interc_13 direct_interc_13_ ( 
    .in ( grid_clb_15_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_13_out ) ) ;
direct_interc_14 direct_interc_14_ ( 
    .in ( grid_clb_16_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_14_out ) ) ;
direct_interc_15 direct_interc_15_ ( 
    .in ( grid_clb_17_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_15_out ) ) ;
direct_interc_16 direct_interc_16_ ( 
    .in ( grid_clb_18_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_16_out ) ) ;
direct_interc_17 direct_interc_17_ ( 
    .in ( grid_clb_19_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_17_out ) ) ;
direct_interc_18 direct_interc_18_ ( 
    .in ( grid_clb_20_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_18_out ) ) ;
direct_interc_19 direct_interc_19_ ( 
    .in ( grid_clb_21_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_19_out ) ) ;
direct_interc_20 direct_interc_20_ ( 
    .in ( grid_clb_22_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_20_out ) ) ;
direct_interc_21 direct_interc_21_ ( 
    .in ( grid_clb_23_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_21_out ) ) ;
direct_interc_22 direct_interc_22_ ( 
    .in ( grid_clb_25_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_22_out ) ) ;
direct_interc_23 direct_interc_23_ ( 
    .in ( grid_clb_26_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_23_out ) ) ;
direct_interc_24 direct_interc_24_ ( 
    .in ( grid_clb_27_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_24_out ) ) ;
direct_interc_25 direct_interc_25_ ( 
    .in ( grid_clb_28_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_25_out ) ) ;
direct_interc_26 direct_interc_26_ ( 
    .in ( grid_clb_29_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_26_out ) ) ;
direct_interc_27 direct_interc_27_ ( 
    .in ( grid_clb_30_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_27_out ) ) ;
direct_interc_28 direct_interc_28_ ( 
    .in ( grid_clb_31_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_28_out ) ) ;
direct_interc_29 direct_interc_29_ ( 
    .in ( grid_clb_32_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_29_out ) ) ;
direct_interc_30 direct_interc_30_ ( 
    .in ( grid_clb_33_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_30_out ) ) ;
direct_interc_31 direct_interc_31_ ( 
    .in ( grid_clb_34_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_31_out ) ) ;
direct_interc_32 direct_interc_32_ ( 
    .in ( grid_clb_35_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_32_out ) ) ;
direct_interc_33 direct_interc_33_ ( 
    .in ( grid_clb_37_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_33_out ) ) ;
direct_interc_34 direct_interc_34_ ( 
    .in ( grid_clb_38_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_34_out ) ) ;
direct_interc_35 direct_interc_35_ ( 
    .in ( grid_clb_39_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_35_out ) ) ;
direct_interc_36 direct_interc_36_ ( 
    .in ( grid_clb_40_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_36_out ) ) ;
direct_interc_37 direct_interc_37_ ( 
    .in ( grid_clb_41_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_37_out ) ) ;
direct_interc_38 direct_interc_38_ ( 
    .in ( grid_clb_42_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_38_out ) ) ;
direct_interc_39 direct_interc_39_ ( 
    .in ( grid_clb_43_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_39_out ) ) ;
direct_interc_40 direct_interc_40_ ( 
    .in ( grid_clb_44_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_40_out ) ) ;
direct_interc_41 direct_interc_41_ ( 
    .in ( grid_clb_45_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_41_out ) ) ;
direct_interc_42 direct_interc_42_ ( 
    .in ( grid_clb_46_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_42_out ) ) ;
direct_interc_43 direct_interc_43_ ( 
    .in ( grid_clb_47_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_43_out ) ) ;
direct_interc_44 direct_interc_44_ ( 
    .in ( grid_clb_49_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_44_out ) ) ;
direct_interc_45 direct_interc_45_ ( 
    .in ( grid_clb_50_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_45_out ) ) ;
direct_interc_46 direct_interc_46_ ( 
    .in ( grid_clb_51_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_46_out ) ) ;
direct_interc_47 direct_interc_47_ ( 
    .in ( grid_clb_52_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_47_out ) ) ;
direct_interc_48 direct_interc_48_ ( 
    .in ( grid_clb_53_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_48_out ) ) ;
direct_interc_49 direct_interc_49_ ( 
    .in ( grid_clb_54_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_49_out ) ) ;
direct_interc_50 direct_interc_50_ ( 
    .in ( grid_clb_55_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_50_out ) ) ;
direct_interc_51 direct_interc_51_ ( 
    .in ( grid_clb_56_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_51_out ) ) ;
direct_interc_52 direct_interc_52_ ( 
    .in ( grid_clb_57_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_52_out ) ) ;
direct_interc_53 direct_interc_53_ ( 
    .in ( grid_clb_58_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_53_out ) ) ;
direct_interc_54 direct_interc_54_ ( 
    .in ( grid_clb_59_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_54_out ) ) ;
direct_interc_55 direct_interc_55_ ( 
    .in ( grid_clb_61_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_55_out ) ) ;
direct_interc_56 direct_interc_56_ ( 
    .in ( grid_clb_62_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_56_out ) ) ;
direct_interc_57 direct_interc_57_ ( 
    .in ( grid_clb_63_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_57_out ) ) ;
direct_interc_58 direct_interc_58_ ( 
    .in ( grid_clb_64_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_58_out ) ) ;
direct_interc_59 direct_interc_59_ ( 
    .in ( grid_clb_65_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_59_out ) ) ;
direct_interc_60 direct_interc_60_ ( 
    .in ( grid_clb_66_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_60_out ) ) ;
direct_interc_61 direct_interc_61_ ( 
    .in ( grid_clb_67_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_61_out ) ) ;
direct_interc_62 direct_interc_62_ ( 
    .in ( grid_clb_68_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_62_out ) ) ;
direct_interc_63 direct_interc_63_ ( 
    .in ( grid_clb_69_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_63_out ) ) ;
direct_interc_64 direct_interc_64_ ( 
    .in ( grid_clb_70_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_64_out ) ) ;
direct_interc_65 direct_interc_65_ ( 
    .in ( grid_clb_71_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_65_out ) ) ;
direct_interc_66 direct_interc_66_ ( 
    .in ( grid_clb_73_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_66_out ) ) ;
direct_interc_67 direct_interc_67_ ( 
    .in ( grid_clb_74_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_67_out ) ) ;
direct_interc_68 direct_interc_68_ ( 
    .in ( grid_clb_75_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_68_out ) ) ;
direct_interc_69 direct_interc_69_ ( 
    .in ( grid_clb_76_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_69_out ) ) ;
direct_interc_70 direct_interc_70_ ( 
    .in ( grid_clb_77_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_70_out ) ) ;
direct_interc_71 direct_interc_71_ ( 
    .in ( grid_clb_78_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_71_out ) ) ;
direct_interc_72 direct_interc_72_ ( 
    .in ( grid_clb_79_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_72_out ) ) ;
direct_interc_73 direct_interc_73_ ( 
    .in ( grid_clb_80_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_73_out ) ) ;
direct_interc_74 direct_interc_74_ ( 
    .in ( grid_clb_81_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_74_out ) ) ;
direct_interc_75 direct_interc_75_ ( 
    .in ( grid_clb_82_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_75_out ) ) ;
direct_interc_76 direct_interc_76_ ( 
    .in ( grid_clb_83_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_76_out ) ) ;
direct_interc_77 direct_interc_77_ ( 
    .in ( grid_clb_85_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_77_out ) ) ;
direct_interc_78 direct_interc_78_ ( 
    .in ( grid_clb_86_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_78_out ) ) ;
direct_interc_79 direct_interc_79_ ( 
    .in ( grid_clb_87_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_79_out ) ) ;
direct_interc_80 direct_interc_80_ ( 
    .in ( grid_clb_88_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_80_out ) ) ;
direct_interc_81 direct_interc_81_ ( 
    .in ( grid_clb_89_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_81_out ) ) ;
direct_interc_82 direct_interc_82_ ( 
    .in ( grid_clb_90_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_82_out ) ) ;
direct_interc_83 direct_interc_83_ ( 
    .in ( grid_clb_91_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_83_out ) ) ;
direct_interc_84 direct_interc_84_ ( 
    .in ( grid_clb_92_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_84_out ) ) ;
direct_interc_85 direct_interc_85_ ( 
    .in ( grid_clb_93_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_85_out ) ) ;
direct_interc_86 direct_interc_86_ ( 
    .in ( grid_clb_94_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_86_out ) ) ;
direct_interc_87 direct_interc_87_ ( 
    .in ( grid_clb_95_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_87_out ) ) ;
direct_interc_88 direct_interc_88_ ( 
    .in ( grid_clb_97_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_88_out ) ) ;
direct_interc_89 direct_interc_89_ ( 
    .in ( grid_clb_98_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_89_out ) ) ;
direct_interc_90 direct_interc_90_ ( 
    .in ( grid_clb_99_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_90_out ) ) ;
direct_interc_91 direct_interc_91_ ( 
    .in ( grid_clb_100_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_91_out ) ) ;
direct_interc_92 direct_interc_92_ ( 
    .in ( grid_clb_101_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_92_out ) ) ;
direct_interc_93 direct_interc_93_ ( 
    .in ( grid_clb_102_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_93_out ) ) ;
direct_interc_94 direct_interc_94_ ( 
    .in ( grid_clb_103_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_94_out ) ) ;
direct_interc_95 direct_interc_95_ ( 
    .in ( grid_clb_104_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_95_out ) ) ;
direct_interc_96 direct_interc_96_ ( 
    .in ( grid_clb_105_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_96_out ) ) ;
direct_interc_97 direct_interc_97_ ( 
    .in ( grid_clb_106_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_97_out ) ) ;
direct_interc_98 direct_interc_98_ ( 
    .in ( grid_clb_107_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_98_out ) ) ;
direct_interc_99 direct_interc_99_ ( 
    .in ( grid_clb_109_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_99_out ) ) ;
direct_interc_100 direct_interc_100_ ( 
    .in ( grid_clb_110_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_100_out ) ) ;
direct_interc_101 direct_interc_101_ ( 
    .in ( grid_clb_111_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_101_out ) ) ;
direct_interc_102 direct_interc_102_ ( 
    .in ( grid_clb_112_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_102_out ) ) ;
direct_interc_103 direct_interc_103_ ( 
    .in ( grid_clb_113_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_103_out ) ) ;
direct_interc_104 direct_interc_104_ ( 
    .in ( grid_clb_114_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_104_out ) ) ;
direct_interc_105 direct_interc_105_ ( 
    .in ( grid_clb_115_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_105_out ) ) ;
direct_interc_106 direct_interc_106_ ( 
    .in ( grid_clb_116_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_106_out ) ) ;
direct_interc_107 direct_interc_107_ ( 
    .in ( grid_clb_117_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_107_out ) ) ;
direct_interc_108 direct_interc_108_ ( 
    .in ( grid_clb_118_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_108_out ) ) ;
direct_interc_109 direct_interc_109_ ( 
    .in ( grid_clb_119_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_109_out ) ) ;
direct_interc_110 direct_interc_110_ ( 
    .in ( grid_clb_121_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_110_out ) ) ;
direct_interc_111 direct_interc_111_ ( 
    .in ( grid_clb_122_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_111_out ) ) ;
direct_interc_112 direct_interc_112_ ( 
    .in ( grid_clb_123_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_112_out ) ) ;
direct_interc_113 direct_interc_113_ ( 
    .in ( grid_clb_124_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_113_out ) ) ;
direct_interc_114 direct_interc_114_ ( 
    .in ( grid_clb_125_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_114_out ) ) ;
direct_interc_115 direct_interc_115_ ( 
    .in ( grid_clb_126_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_115_out ) ) ;
direct_interc_116 direct_interc_116_ ( 
    .in ( grid_clb_127_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_116_out ) ) ;
direct_interc_117 direct_interc_117_ ( 
    .in ( grid_clb_128_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_117_out ) ) ;
direct_interc_118 direct_interc_118_ ( 
    .in ( grid_clb_129_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_118_out ) ) ;
direct_interc_119 direct_interc_119_ ( 
    .in ( grid_clb_130_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_119_out ) ) ;
direct_interc_120 direct_interc_120_ ( 
    .in ( grid_clb_131_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_120_out ) ) ;
direct_interc_121 direct_interc_121_ ( 
    .in ( grid_clb_133_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_121_out ) ) ;
direct_interc_122 direct_interc_122_ ( 
    .in ( grid_clb_134_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_122_out ) ) ;
direct_interc_123 direct_interc_123_ ( 
    .in ( grid_clb_135_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_123_out ) ) ;
direct_interc_124 direct_interc_124_ ( 
    .in ( grid_clb_136_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_124_out ) ) ;
direct_interc_125 direct_interc_125_ ( 
    .in ( grid_clb_137_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_125_out ) ) ;
direct_interc_126 direct_interc_126_ ( 
    .in ( grid_clb_138_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_126_out ) ) ;
direct_interc_127 direct_interc_127_ ( 
    .in ( grid_clb_139_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_127_out ) ) ;
direct_interc_128 direct_interc_128_ ( 
    .in ( grid_clb_140_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_128_out ) ) ;
direct_interc_129 direct_interc_129_ ( 
    .in ( grid_clb_141_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_129_out ) ) ;
direct_interc_130 direct_interc_130_ ( 
    .in ( grid_clb_142_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_130_out ) ) ;
direct_interc_131 direct_interc_131_ ( 
    .in ( grid_clb_143_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_131_out ) ) ;
direct_interc_132 direct_interc_132_ ( 
    .in ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) , 
    .out ( direct_interc_132_out ) ) ;
direct_interc_133 direct_interc_133_ ( 
    .in ( grid_clb_12_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_133_out ) ) ;
direct_interc_134 direct_interc_134_ ( 
    .in ( grid_clb_24_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_134_out ) ) ;
direct_interc_135 direct_interc_135_ ( 
    .in ( grid_clb_36_bottom_width_0_height_0__pin_50___FEEDTHRU_25 ) , 
    .out ( direct_interc_135_out ) ) ;
direct_interc_136 direct_interc_136_ ( 
    .in ( grid_clb_48_bottom_width_0_height_0__pin_50___FEEDTHRU_25 ) , 
    .out ( direct_interc_136_out ) ) ;
direct_interc_137 direct_interc_137_ ( 
    .in ( grid_clb_60_bottom_width_0_height_0__pin_50___FEEDTHRU_11 ) , 
    .out ( direct_interc_137_out ) ) ;
direct_interc_138 direct_interc_138_ ( 
    .in ( grid_clb_72_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_138_out ) ) ;
direct_interc_139 direct_interc_139_ ( 
    .in ( grid_clb_84_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_139_out ) ) ;
direct_interc_140 direct_interc_140_ ( 
    .in ( grid_clb_96_bottom_width_0_height_0__pin_50___FEEDTHRU_25 ) , 
    .out ( direct_interc_140_out ) ) ;
direct_interc_141 direct_interc_141_ ( 
    .in ( grid_clb_108_bottom_width_0_height_0__pin_50_ ) , 
    .out ( direct_interc_141_out ) ) ;
direct_interc_142 direct_interc_142_ ( 
    .in ( grid_clb_120_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) , 
    .out ( direct_interc_142_out ) ) ;
direct_interc_143 direct_interc_143_ (
    .in ( { SYNOPSYS_UNCONNECTED_2149 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2150 } ) ) ;
direct_interc_144 direct_interc_144_ (
    .in ( { SYNOPSYS_UNCONNECTED_2151 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2152 } ) ) ;
direct_interc_145 direct_interc_145_ (
    .in ( { SYNOPSYS_UNCONNECTED_2153 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2154 } ) ) ;
direct_interc_146 direct_interc_146_ (
    .in ( { SYNOPSYS_UNCONNECTED_2155 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2156 } ) ) ;
direct_interc_147 direct_interc_147_ (
    .in ( { SYNOPSYS_UNCONNECTED_2157 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2158 } ) ) ;
direct_interc_148 direct_interc_148_ (
    .in ( { SYNOPSYS_UNCONNECTED_2159 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2160 } ) ) ;
direct_interc_149 direct_interc_149_ (
    .in ( { SYNOPSYS_UNCONNECTED_2161 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2162 } ) ) ;
direct_interc_150 direct_interc_150_ (
    .in ( { SYNOPSYS_UNCONNECTED_2163 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2164 } ) ) ;
direct_interc_151 direct_interc_151_ (
    .in ( { SYNOPSYS_UNCONNECTED_2165 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2166 } ) ) ;
direct_interc_152 direct_interc_152_ (
    .in ( { SYNOPSYS_UNCONNECTED_2167 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2168 } ) ) ;
direct_interc_153 direct_interc_153_ (
    .in ( { SYNOPSYS_UNCONNECTED_2169 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2170 } ) ) ;
direct_interc_154 direct_interc_154_ (
    .in ( { SYNOPSYS_UNCONNECTED_2171 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2172 } ) ) ;
direct_interc_155 direct_interc_155_ (
    .in ( { SYNOPSYS_UNCONNECTED_2173 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2174 } ) ) ;
direct_interc_156 direct_interc_156_ (
    .in ( { SYNOPSYS_UNCONNECTED_2175 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2176 } ) ) ;
direct_interc_157 direct_interc_157_ (
    .in ( { SYNOPSYS_UNCONNECTED_2177 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2178 } ) ) ;
direct_interc_158 direct_interc_158_ (
    .in ( { SYNOPSYS_UNCONNECTED_2179 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2180 } ) ) ;
direct_interc_159 direct_interc_159_ (
    .in ( { SYNOPSYS_UNCONNECTED_2181 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2182 } ) ) ;
direct_interc_160 direct_interc_160_ (
    .in ( { SYNOPSYS_UNCONNECTED_2183 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2184 } ) ) ;
direct_interc_161 direct_interc_161_ (
    .in ( { SYNOPSYS_UNCONNECTED_2185 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2186 } ) ) ;
direct_interc_162 direct_interc_162_ (
    .in ( { SYNOPSYS_UNCONNECTED_2187 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2188 } ) ) ;
direct_interc_163 direct_interc_163_ (
    .in ( { SYNOPSYS_UNCONNECTED_2189 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2190 } ) ) ;
direct_interc_164 direct_interc_164_ (
    .in ( { SYNOPSYS_UNCONNECTED_2191 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2192 } ) ) ;
direct_interc_165 direct_interc_165_ (
    .in ( { SYNOPSYS_UNCONNECTED_2193 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2194 } ) ) ;
direct_interc_166 direct_interc_166_ (
    .in ( { SYNOPSYS_UNCONNECTED_2195 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2196 } ) ) ;
direct_interc_167 direct_interc_167_ (
    .in ( { SYNOPSYS_UNCONNECTED_2197 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2198 } ) ) ;
direct_interc_168 direct_interc_168_ (
    .in ( { SYNOPSYS_UNCONNECTED_2199 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2200 } ) ) ;
direct_interc_169 direct_interc_169_ (
    .in ( { SYNOPSYS_UNCONNECTED_2201 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2202 } ) ) ;
direct_interc_170 direct_interc_170_ (
    .in ( { SYNOPSYS_UNCONNECTED_2203 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2204 } ) ) ;
direct_interc_171 direct_interc_171_ (
    .in ( { SYNOPSYS_UNCONNECTED_2205 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2206 } ) ) ;
direct_interc_172 direct_interc_172_ (
    .in ( { SYNOPSYS_UNCONNECTED_2207 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2208 } ) ) ;
direct_interc_173 direct_interc_173_ (
    .in ( { SYNOPSYS_UNCONNECTED_2209 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2210 } ) ) ;
direct_interc_174 direct_interc_174_ (
    .in ( { SYNOPSYS_UNCONNECTED_2211 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2212 } ) ) ;
direct_interc_175 direct_interc_175_ (
    .in ( { SYNOPSYS_UNCONNECTED_2213 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2214 } ) ) ;
direct_interc_176 direct_interc_176_ (
    .in ( { SYNOPSYS_UNCONNECTED_2215 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2216 } ) ) ;
direct_interc_177 direct_interc_177_ (
    .in ( { SYNOPSYS_UNCONNECTED_2217 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2218 } ) ) ;
direct_interc_178 direct_interc_178_ (
    .in ( { SYNOPSYS_UNCONNECTED_2219 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2220 } ) ) ;
direct_interc_179 direct_interc_179_ (
    .in ( { SYNOPSYS_UNCONNECTED_2221 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2222 } ) ) ;
direct_interc_180 direct_interc_180_ (
    .in ( { SYNOPSYS_UNCONNECTED_2223 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2224 } ) ) ;
direct_interc_181 direct_interc_181_ (
    .in ( { SYNOPSYS_UNCONNECTED_2225 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2226 } ) ) ;
direct_interc_182 direct_interc_182_ (
    .in ( { SYNOPSYS_UNCONNECTED_2227 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2228 } ) ) ;
direct_interc_183 direct_interc_183_ (
    .in ( { SYNOPSYS_UNCONNECTED_2229 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2230 } ) ) ;
direct_interc_184 direct_interc_184_ (
    .in ( { SYNOPSYS_UNCONNECTED_2231 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2232 } ) ) ;
direct_interc_185 direct_interc_185_ (
    .in ( { SYNOPSYS_UNCONNECTED_2233 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2234 } ) ) ;
direct_interc_186 direct_interc_186_ (
    .in ( { SYNOPSYS_UNCONNECTED_2235 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2236 } ) ) ;
direct_interc_187 direct_interc_187_ (
    .in ( { SYNOPSYS_UNCONNECTED_2237 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2238 } ) ) ;
direct_interc_188 direct_interc_188_ (
    .in ( { SYNOPSYS_UNCONNECTED_2239 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2240 } ) ) ;
direct_interc_189 direct_interc_189_ (
    .in ( { SYNOPSYS_UNCONNECTED_2241 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2242 } ) ) ;
direct_interc_190 direct_interc_190_ (
    .in ( { SYNOPSYS_UNCONNECTED_2243 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2244 } ) ) ;
direct_interc_191 direct_interc_191_ (
    .in ( { SYNOPSYS_UNCONNECTED_2245 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2246 } ) ) ;
direct_interc_192 direct_interc_192_ (
    .in ( { SYNOPSYS_UNCONNECTED_2247 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2248 } ) ) ;
direct_interc_193 direct_interc_193_ (
    .in ( { SYNOPSYS_UNCONNECTED_2249 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2250 } ) ) ;
direct_interc_194 direct_interc_194_ (
    .in ( { SYNOPSYS_UNCONNECTED_2251 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2252 } ) ) ;
direct_interc_195 direct_interc_195_ (
    .in ( { SYNOPSYS_UNCONNECTED_2253 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2254 } ) ) ;
direct_interc_196 direct_interc_196_ (
    .in ( { SYNOPSYS_UNCONNECTED_2255 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2256 } ) ) ;
direct_interc_197 direct_interc_197_ (
    .in ( { SYNOPSYS_UNCONNECTED_2257 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2258 } ) ) ;
direct_interc_198 direct_interc_198_ (
    .in ( { SYNOPSYS_UNCONNECTED_2259 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2260 } ) ) ;
direct_interc_199 direct_interc_199_ (
    .in ( { SYNOPSYS_UNCONNECTED_2261 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2262 } ) ) ;
direct_interc_200 direct_interc_200_ (
    .in ( { SYNOPSYS_UNCONNECTED_2263 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2264 } ) ) ;
direct_interc_201 direct_interc_201_ (
    .in ( { SYNOPSYS_UNCONNECTED_2265 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2266 } ) ) ;
direct_interc_202 direct_interc_202_ (
    .in ( { SYNOPSYS_UNCONNECTED_2267 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2268 } ) ) ;
direct_interc_203 direct_interc_203_ (
    .in ( { SYNOPSYS_UNCONNECTED_2269 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2270 } ) ) ;
direct_interc_204 direct_interc_204_ (
    .in ( { SYNOPSYS_UNCONNECTED_2271 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2272 } ) ) ;
direct_interc_205 direct_interc_205_ (
    .in ( { SYNOPSYS_UNCONNECTED_2273 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2274 } ) ) ;
direct_interc_206 direct_interc_206_ (
    .in ( { SYNOPSYS_UNCONNECTED_2275 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2276 } ) ) ;
direct_interc_207 direct_interc_207_ (
    .in ( { SYNOPSYS_UNCONNECTED_2277 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2278 } ) ) ;
direct_interc_208 direct_interc_208_ (
    .in ( { SYNOPSYS_UNCONNECTED_2279 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2280 } ) ) ;
direct_interc_209 direct_interc_209_ (
    .in ( { SYNOPSYS_UNCONNECTED_2281 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2282 } ) ) ;
direct_interc_210 direct_interc_210_ (
    .in ( { SYNOPSYS_UNCONNECTED_2283 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2284 } ) ) ;
direct_interc_211 direct_interc_211_ (
    .in ( { SYNOPSYS_UNCONNECTED_2285 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2286 } ) ) ;
direct_interc_212 direct_interc_212_ (
    .in ( { SYNOPSYS_UNCONNECTED_2287 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2288 } ) ) ;
direct_interc_213 direct_interc_213_ (
    .in ( { SYNOPSYS_UNCONNECTED_2289 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2290 } ) ) ;
direct_interc_214 direct_interc_214_ (
    .in ( { SYNOPSYS_UNCONNECTED_2291 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2292 } ) ) ;
direct_interc_215 direct_interc_215_ (
    .in ( { SYNOPSYS_UNCONNECTED_2293 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2294 } ) ) ;
direct_interc_216 direct_interc_216_ (
    .in ( { SYNOPSYS_UNCONNECTED_2295 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2296 } ) ) ;
direct_interc_217 direct_interc_217_ (
    .in ( { SYNOPSYS_UNCONNECTED_2297 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2298 } ) ) ;
direct_interc_218 direct_interc_218_ (
    .in ( { SYNOPSYS_UNCONNECTED_2299 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2300 } ) ) ;
direct_interc_219 direct_interc_219_ (
    .in ( { SYNOPSYS_UNCONNECTED_2301 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2302 } ) ) ;
direct_interc_220 direct_interc_220_ (
    .in ( { SYNOPSYS_UNCONNECTED_2303 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2304 } ) ) ;
direct_interc_221 direct_interc_221_ (
    .in ( { SYNOPSYS_UNCONNECTED_2305 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2306 } ) ) ;
direct_interc_222 direct_interc_222_ (
    .in ( { SYNOPSYS_UNCONNECTED_2307 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2308 } ) ) ;
direct_interc_223 direct_interc_223_ (
    .in ( { SYNOPSYS_UNCONNECTED_2309 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2310 } ) ) ;
direct_interc_224 direct_interc_224_ (
    .in ( { SYNOPSYS_UNCONNECTED_2311 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2312 } ) ) ;
direct_interc_225 direct_interc_225_ (
    .in ( { SYNOPSYS_UNCONNECTED_2313 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2314 } ) ) ;
direct_interc_226 direct_interc_226_ (
    .in ( { SYNOPSYS_UNCONNECTED_2315 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2316 } ) ) ;
direct_interc_227 direct_interc_227_ (
    .in ( { SYNOPSYS_UNCONNECTED_2317 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2318 } ) ) ;
direct_interc_228 direct_interc_228_ (
    .in ( { SYNOPSYS_UNCONNECTED_2319 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2320 } ) ) ;
direct_interc_229 direct_interc_229_ (
    .in ( { SYNOPSYS_UNCONNECTED_2321 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2322 } ) ) ;
direct_interc_230 direct_interc_230_ (
    .in ( { SYNOPSYS_UNCONNECTED_2323 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2324 } ) ) ;
direct_interc_231 direct_interc_231_ (
    .in ( { SYNOPSYS_UNCONNECTED_2325 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2326 } ) ) ;
direct_interc_232 direct_interc_232_ (
    .in ( { SYNOPSYS_UNCONNECTED_2327 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2328 } ) ) ;
direct_interc_233 direct_interc_233_ (
    .in ( { SYNOPSYS_UNCONNECTED_2329 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2330 } ) ) ;
direct_interc_234 direct_interc_234_ (
    .in ( { SYNOPSYS_UNCONNECTED_2331 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2332 } ) ) ;
direct_interc_235 direct_interc_235_ (
    .in ( { SYNOPSYS_UNCONNECTED_2333 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2334 } ) ) ;
direct_interc_236 direct_interc_236_ (
    .in ( { SYNOPSYS_UNCONNECTED_2335 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2336 } ) ) ;
direct_interc_237 direct_interc_237_ (
    .in ( { SYNOPSYS_UNCONNECTED_2337 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2338 } ) ) ;
direct_interc_238 direct_interc_238_ (
    .in ( { SYNOPSYS_UNCONNECTED_2339 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2340 } ) ) ;
direct_interc_239 direct_interc_239_ (
    .in ( { SYNOPSYS_UNCONNECTED_2341 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2342 } ) ) ;
direct_interc_240 direct_interc_240_ (
    .in ( { SYNOPSYS_UNCONNECTED_2343 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2344 } ) ) ;
direct_interc_241 direct_interc_241_ (
    .in ( { SYNOPSYS_UNCONNECTED_2345 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2346 } ) ) ;
direct_interc_242 direct_interc_242_ (
    .in ( { SYNOPSYS_UNCONNECTED_2347 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2348 } ) ) ;
direct_interc_243 direct_interc_243_ (
    .in ( { SYNOPSYS_UNCONNECTED_2349 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2350 } ) ) ;
direct_interc_244 direct_interc_244_ (
    .in ( { SYNOPSYS_UNCONNECTED_2351 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2352 } ) ) ;
direct_interc_245 direct_interc_245_ (
    .in ( { SYNOPSYS_UNCONNECTED_2353 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2354 } ) ) ;
direct_interc_246 direct_interc_246_ (
    .in ( { SYNOPSYS_UNCONNECTED_2355 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2356 } ) ) ;
direct_interc_247 direct_interc_247_ (
    .in ( { SYNOPSYS_UNCONNECTED_2357 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2358 } ) ) ;
direct_interc_248 direct_interc_248_ (
    .in ( { SYNOPSYS_UNCONNECTED_2359 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2360 } ) ) ;
direct_interc_249 direct_interc_249_ (
    .in ( { SYNOPSYS_UNCONNECTED_2361 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2362 } ) ) ;
direct_interc_250 direct_interc_250_ (
    .in ( { SYNOPSYS_UNCONNECTED_2363 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2364 } ) ) ;
direct_interc_251 direct_interc_251_ (
    .in ( { SYNOPSYS_UNCONNECTED_2365 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2366 } ) ) ;
direct_interc_252 direct_interc_252_ (
    .in ( { SYNOPSYS_UNCONNECTED_2367 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2368 } ) ) ;
direct_interc_253 direct_interc_253_ (
    .in ( { SYNOPSYS_UNCONNECTED_2369 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2370 } ) ) ;
direct_interc_254 direct_interc_254_ (
    .in ( { SYNOPSYS_UNCONNECTED_2371 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2372 } ) ) ;
direct_interc_255 direct_interc_255_ (
    .in ( { SYNOPSYS_UNCONNECTED_2373 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2374 } ) ) ;
direct_interc_256 direct_interc_256_ (
    .in ( { SYNOPSYS_UNCONNECTED_2375 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2376 } ) ) ;
direct_interc_257 direct_interc_257_ (
    .in ( { SYNOPSYS_UNCONNECTED_2377 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2378 } ) ) ;
direct_interc_258 direct_interc_258_ (
    .in ( { SYNOPSYS_UNCONNECTED_2379 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2380 } ) ) ;
direct_interc_259 direct_interc_259_ (
    .in ( { SYNOPSYS_UNCONNECTED_2381 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2382 } ) ) ;
direct_interc_260 direct_interc_260_ (
    .in ( { SYNOPSYS_UNCONNECTED_2383 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2384 } ) ) ;
direct_interc_261 direct_interc_261_ (
    .in ( { SYNOPSYS_UNCONNECTED_2385 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2386 } ) ) ;
direct_interc_262 direct_interc_262_ (
    .in ( { SYNOPSYS_UNCONNECTED_2387 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2388 } ) ) ;
direct_interc_263 direct_interc_263_ (
    .in ( { SYNOPSYS_UNCONNECTED_2389 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2390 } ) ) ;
direct_interc_264 direct_interc_264_ (
    .in ( { SYNOPSYS_UNCONNECTED_2391 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2392 } ) ) ;
direct_interc_265 direct_interc_265_ (
    .in ( { SYNOPSYS_UNCONNECTED_2393 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2394 } ) ) ;
direct_interc_266 direct_interc_266_ (
    .in ( { SYNOPSYS_UNCONNECTED_2395 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2396 } ) ) ;
direct_interc_267 direct_interc_267_ (
    .in ( { SYNOPSYS_UNCONNECTED_2397 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2398 } ) ) ;
direct_interc_268 direct_interc_268_ (
    .in ( { SYNOPSYS_UNCONNECTED_2399 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2400 } ) ) ;
direct_interc_269 direct_interc_269_ (
    .in ( { SYNOPSYS_UNCONNECTED_2401 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2402 } ) ) ;
direct_interc_270 direct_interc_270_ (
    .in ( { SYNOPSYS_UNCONNECTED_2403 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2404 } ) ) ;
direct_interc_271 direct_interc_271_ (
    .in ( { SYNOPSYS_UNCONNECTED_2405 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2406 } ) ) ;
direct_interc_272 direct_interc_272_ (
    .in ( { SYNOPSYS_UNCONNECTED_2407 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2408 } ) ) ;
direct_interc_273 direct_interc_273_ (
    .in ( { SYNOPSYS_UNCONNECTED_2409 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2410 } ) ) ;
direct_interc_274 direct_interc_274_ (
    .in ( { SYNOPSYS_UNCONNECTED_2411 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2412 } ) ) ;
direct_interc_275 direct_interc_275_ (
    .in ( { SYNOPSYS_UNCONNECTED_2413 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2414 } ) ) ;
direct_interc_276 direct_interc_276_ (
    .in ( { SYNOPSYS_UNCONNECTED_2415 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2416 } ) ) ;
direct_interc_277 direct_interc_277_ (
    .in ( { SYNOPSYS_UNCONNECTED_2417 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2418 } ) ) ;
direct_interc_278 direct_interc_278_ (
    .in ( { SYNOPSYS_UNCONNECTED_2419 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2420 } ) ) ;
direct_interc_279 direct_interc_279_ (
    .in ( { SYNOPSYS_UNCONNECTED_2421 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2422 } ) ) ;
direct_interc_280 direct_interc_280_ (
    .in ( { SYNOPSYS_UNCONNECTED_2423 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2424 } ) ) ;
direct_interc_281 direct_interc_281_ (
    .in ( { SYNOPSYS_UNCONNECTED_2425 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2426 } ) ) ;
direct_interc_282 direct_interc_282_ (
    .in ( { SYNOPSYS_UNCONNECTED_2427 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2428 } ) ) ;
direct_interc_283 direct_interc_283_ (
    .in ( { SYNOPSYS_UNCONNECTED_2429 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2430 } ) ) ;
direct_interc_284 direct_interc_284_ (
    .in ( { SYNOPSYS_UNCONNECTED_2431 } ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2432 } ) ) ;
direct_interc direct_interc_285_ ( 
    .in ( grid_clb_120_bottom_width_0_height_0__pin_51_ ) ,
    .out ( { SYNOPSYS_UNCONNECTED_2433 } ) ) ;
sky130_fd_sc_hd__conb_1 optlc_245 ( .LO ( optlc_net_256 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2434 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_247 ( .LO ( optlc_net_257 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2435 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_145 ( .A ( BUF_net_147 ) , 
    .X ( BUF_net_145 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_248 ( .LO ( optlc_net_258 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2436 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_147 ( .A ( BUF_net_150 ) , 
    .X ( BUF_net_147 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_249 ( .LO ( optlc_net_259 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2437 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_251 ( .LO ( optlc_net_260 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2438 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_150 ( 
    .A ( grid_clb_120_bottom_width_0_height_0__pin_50_[0] ) , 
    .X ( BUF_net_150 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_252 ( .LO ( optlc_net_261 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2439 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_253 ( .LO ( optlc_net_262 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2440 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_254 ( .LO ( optlc_net_263 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2441 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_256 ( .LO ( optlc_net_264 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2442 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_257 ( .LO ( optlc_net_265 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2443 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_258 ( .LO ( optlc_net_266 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2444 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_259 ( .LO ( optlc_net_267 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2445 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_260 ( .LO ( optlc_net_268 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2446 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_261 ( .LO ( optlc_net_269 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2447 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_262 ( .LO ( optlc_net_270 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2448 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_263 ( .LO ( optlc_net_271 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2449 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_264 ( .LO ( optlc_net_272 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2450 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_265 ( .LO ( optlc_net_273 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2451 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_266 ( .LO ( optlc_net_274 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2452 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_267 ( .LO ( optlc_net_275 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2453 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_268 ( .LO ( optlc_net_276 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2454 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_270 ( .LO ( optlc_net_277 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2455 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_271 ( .LO ( optlc_net_278 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2456 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_272 ( .LO ( optlc_net_279 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2457 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_273 ( .LO ( optlc_net_280 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2458 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_275 ( .LO ( optlc_net_281 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2459 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_276 ( .LO ( optlc_net_282 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2460 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_277 ( .LO ( optlc_net_283 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2461 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_278 ( .LO ( optlc_net_284 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2462 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_279 ( .LO ( optlc_net_285 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2463 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_281 ( .LO ( optlc_net_286 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2464 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_282 ( .LO ( optlc_net_287 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2465 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_283 ( .LO ( optlc_net_288 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2466 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_285 ( .LO ( optlc_net_289 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2467 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_286 ( .LO ( optlc_net_290 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2468 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_287 ( .LO ( optlc_net_291 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2469 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_288 ( .LO ( optlc_net_292 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2470 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_289 ( .LO ( optlc_net_293 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2471 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_290 ( .LO ( optlc_net_294 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2472 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_291 ( .LO ( optlc_net_295 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2473 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_292 ( .LO ( optlc_net_296 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2474 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_293 ( .LO ( optlc_net_297 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2475 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_294 ( .LO ( optlc_net_298 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2476 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_296 ( .LO ( optlc_net_299 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2477 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_297 ( .LO ( optlc_net_300 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2478 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_299 ( .LO ( optlc_net_301 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2479 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_300 ( .LO ( optlc_net_302 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2480 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_301 ( .LO ( optlc_net_303 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2481 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_302 ( .LO ( optlc_net_304 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2482 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_303 ( .LO ( optlc_net_305 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2483 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_304 ( .LO ( optlc_net_306 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2484 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_305 ( .LO ( optlc_net_307 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2485 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_306 ( .LO ( optlc_net_308 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2486 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_307 ( .LO ( optlc_net_309 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2487 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_308 ( .LO ( optlc_net_310 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2488 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_309 ( .LO ( optlc_net_311 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2489 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_310 ( .LO ( optlc_net_312 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2490 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_312 ( .LO ( optlc_net_313 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2491 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_314 ( .LO ( optlc_net_314 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2492 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_316 ( .LO ( optlc_net_315 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2493 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_317 ( .LO ( optlc_net_316 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2494 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_318 ( .LO ( optlc_net_317 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2495 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_319 ( .LO ( optlc_net_318 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2496 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_320 ( .LO ( optlc_net_319 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2497 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_321 ( .LO ( optlc_net_320 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2498 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_322 ( .LO ( optlc_net_321 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2499 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_323 ( .LO ( optlc_net_322 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2500 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_324 ( .LO ( optlc_net_323 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2501 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_325 ( .LO ( optlc_net_324 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2502 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_326 ( .LO ( optlc_net_325 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2503 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_328 ( .LO ( optlc_net_326 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2504 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_329 ( .LO ( optlc_net_327 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2505 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_331 ( .LO ( optlc_net_328 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2506 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_332 ( .LO ( optlc_net_329 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2507 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_333 ( .LO ( optlc_net_330 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2508 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_335 ( .LO ( optlc_net_331 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2509 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_337 ( .LO ( optlc_net_332 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2510 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_338 ( .LO ( optlc_net_333 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2511 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_339 ( .LO ( optlc_net_334 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2512 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_340 ( .LO ( optlc_net_335 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2513 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_341 ( .LO ( optlc_net_336 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2514 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_343 ( .LO ( optlc_net_337 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2515 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_344 ( .LO ( optlc_net_338 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2516 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_345 ( .LO ( optlc_net_339 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2517 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_346 ( .LO ( optlc_net_340 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2518 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_347 ( .LO ( optlc_net_341 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2519 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_348 ( .LO ( optlc_net_342 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2520 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_349 ( .LO ( optlc_net_343 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2521 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_350 ( .LO ( optlc_net_344 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2522 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_352 ( .LO ( optlc_net_345 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2523 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_354 ( .LO ( optlc_net_346 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2524 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_356 ( .LO ( optlc_net_347 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2525 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_357 ( .LO ( optlc_net_348 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2526 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_358 ( .LO ( optlc_net_349 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2527 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_359 ( .LO ( optlc_net_350 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2528 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_360 ( .LO ( optlc_net_351 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2529 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_361 ( .LO ( optlc_net_352 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2530 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_362 ( .LO ( optlc_net_353 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2531 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_363 ( .LO ( optlc_net_354 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2532 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_364 ( .LO ( optlc_net_355 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2533 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_366 ( .LO ( optlc_net_356 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2534 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_368 ( .LO ( optlc_net_357 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2535 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_369 ( .LO ( optlc_net_358 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2536 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_370 ( .LO ( optlc_net_359 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2537 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_371 ( .LO ( optlc_net_360 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2538 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_372 ( .LO ( optlc_net_361 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2539 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_373 ( .LO ( optlc_net_362 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2540 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_374 ( .LO ( optlc_net_363 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2541 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_375 ( .LO ( optlc_net_364 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2542 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_376 ( .LO ( optlc_net_365 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2543 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_377 ( .LO ( optlc_net_366 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2544 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_378 ( .LO ( optlc_net_367 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2545 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_379 ( .LO ( optlc_net_368 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2546 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_380 ( .LO ( optlc_net_369 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2547 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_381 ( .LO ( optlc_net_370 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2548 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_382 ( .LO ( optlc_net_371 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2549 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_383 ( .LO ( optlc_net_372 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2550 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_384 ( .LO ( optlc_net_373 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2551 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_385 ( .LO ( optlc_net_374 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2552 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_386 ( .LO ( optlc_net_375 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2553 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_387 ( .LO ( optlc_net_376 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2554 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_388 ( .LO ( optlc_net_377 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2555 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_389 ( .LO ( optlc_net_378 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2556 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_390 ( .LO ( optlc_net_379 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2557 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_391 ( .LO ( optlc_net_380 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2558 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_392 ( .LO ( optlc_net_381 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2559 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_393 ( .LO ( optlc_net_382 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2560 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_394 ( .LO ( optlc_net_383 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2561 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_395 ( .LO ( optlc_net_384 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2562 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_396 ( .LO ( optlc_net_385 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2563 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_397 ( .LO ( optlc_net_386 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2564 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_398 ( .LO ( optlc_net_387 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2565 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_399 ( .LO ( optlc_net_388 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2566 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_400 ( .LO ( optlc_net_389 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2567 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_402 ( .LO ( optlc_net_390 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2568 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_404 ( .LO ( optlc_net_391 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2569 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_406 ( .LO ( optlc_net_392 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2570 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_407 ( .LO ( optlc_net_393 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2571 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_408 ( .LO ( optlc_net_394 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2572 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_409 ( .LO ( optlc_net_395 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2573 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_411 ( .LO ( optlc_net_396 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2574 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_412 ( .LO ( optlc_net_397 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2575 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_414 ( .LO ( optlc_net_398 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2576 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_416 ( .LO ( optlc_net_399 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2577 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_417 ( .LO ( optlc_net_400 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2578 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_418 ( .LO ( optlc_net_401 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2579 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_419 ( .LO ( optlc_net_402 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2580 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_420 ( .LO ( optlc_net_403 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2581 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_422 ( .LO ( optlc_net_404 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2582 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_423 ( .LO ( optlc_net_405 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2583 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_424 ( .LO ( optlc_net_406 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2584 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_426 ( .LO ( optlc_net_407 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2585 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_427 ( .LO ( optlc_net_408 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2586 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_428 ( .LO ( optlc_net_409 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2587 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_429 ( .LO ( optlc_net_410 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2588 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_430 ( .LO ( optlc_net_411 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2589 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_431 ( .LO ( optlc_net_412 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2590 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_432 ( .LO ( optlc_net_413 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2591 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_433 ( .LO ( optlc_net_414 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2592 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_434 ( .LO ( optlc_net_415 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2593 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_435 ( .LO ( optlc_net_416 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2594 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_436 ( .LO ( optlc_net_417 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2595 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_437 ( .LO ( optlc_net_418 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2596 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_438 ( .LO ( optlc_net_419 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2597 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_439 ( .LO ( optlc_net_420 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2598 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_440 ( .LO ( optlc_net_421 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2599 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_441 ( .LO ( optlc_net_422 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2600 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_442 ( .LO ( optlc_net_423 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2601 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_443 ( .LO ( optlc_net_424 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2602 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_444 ( .LO ( optlc_net_425 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2603 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_445 ( .LO ( optlc_net_426 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2604 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_446 ( .LO ( optlc_net_427 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2605 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_447 ( .LO ( optlc_net_428 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2606 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_448 ( .LO ( optlc_net_429 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2607 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_450 ( .LO ( optlc_net_430 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2608 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_451 ( .LO ( optlc_net_431 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2609 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_452 ( .LO ( optlc_net_432 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2610 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_453 ( .LO ( optlc_net_433 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2611 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_454 ( .LO ( optlc_net_434 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2612 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_455 ( .LO ( optlc_net_435 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2613 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_456 ( .LO ( optlc_net_436 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2614 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_457 ( .LO ( optlc_net_437 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2615 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_458 ( .LO ( optlc_net_438 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2616 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_459 ( .LO ( optlc_net_439 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2617 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_460 ( .LO ( optlc_net_440 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2618 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_461 ( .LO ( optlc_net_441 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2619 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_462 ( .LO ( optlc_net_442 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2620 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_464 ( .LO ( optlc_net_443 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2621 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_465 ( .LO ( optlc_net_444 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2622 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_466 ( .LO ( optlc_net_445 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2623 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_467 ( .LO ( optlc_net_446 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2624 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_468 ( .LO ( optlc_net_447 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2625 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_469 ( .LO ( optlc_net_448 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2626 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_471 ( .LO ( optlc_net_449 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2627 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_472 ( .LO ( optlc_net_450 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2628 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_473 ( .LO ( optlc_net_451 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2629 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_474 ( .LO ( optlc_net_452 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2630 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_475 ( .LO ( optlc_net_453 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2631 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_476 ( .LO ( optlc_net_454 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2632 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_477 ( .LO ( optlc_net_455 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2633 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_479 ( .LO ( optlc_net_456 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2634 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_480 ( .LO ( optlc_net_457 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2635 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_481 ( .LO ( optlc_net_458 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2636 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_482 ( .LO ( optlc_net_459 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2637 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_483 ( .LO ( optlc_net_460 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2638 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_484 ( .LO ( optlc_net_461 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2639 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_485 ( .LO ( optlc_net_462 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2640 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_487 ( .LO ( optlc_net_463 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2641 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_488 ( .LO ( optlc_net_464 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2642 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_490 ( .LO ( optlc_net_465 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2643 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_492 ( .LO ( optlc_net_466 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2644 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_493 ( .LO ( optlc_net_467 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2645 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_494 ( .LO ( optlc_net_468 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2646 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_496 ( .LO ( optlc_net_469 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2647 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_497 ( .LO ( optlc_net_470 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2648 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_498 ( .LO ( optlc_net_471 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2649 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_499 ( .LO ( optlc_net_472 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2650 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_501 ( .LO ( optlc_net_473 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2651 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_502 ( .LO ( optlc_net_474 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2652 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_504 ( .LO ( optlc_net_475 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2653 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_505 ( .LO ( optlc_net_476 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2654 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_506 ( .LO ( optlc_net_477 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2655 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_507 ( .LO ( optlc_net_478 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2656 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_508 ( .LO ( optlc_net_479 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2657 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_509 ( .LO ( optlc_net_480 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2658 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_510 ( .LO ( optlc_net_481 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2659 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_511 ( .LO ( optlc_net_482 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2660 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_512 ( .LO ( optlc_net_483 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2661 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_514 ( .LO ( optlc_net_484 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2662 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_515 ( .LO ( optlc_net_485 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2663 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_516 ( .LO ( optlc_net_486 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2664 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_518 ( .LO ( optlc_net_487 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2665 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_520 ( .LO ( optlc_net_488 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2666 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_521 ( .LO ( optlc_net_489 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2667 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_522 ( .LO ( optlc_net_490 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2668 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_523 ( .LO ( optlc_net_491 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2669 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_524 ( .LO ( optlc_net_492 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2670 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_526 ( .LO ( optlc_net_493 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2671 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_527 ( .LO ( optlc_net_494 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2672 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_529 ( .LO ( optlc_net_495 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2673 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_530 ( .LO ( optlc_net_496 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2674 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_532 ( .LO ( optlc_net_497 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2675 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_533 ( .LO ( optlc_net_498 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2676 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_534 ( .LO ( optlc_net_499 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2677 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_535 ( .LO ( optlc_net_500 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2678 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_536 ( .LO ( optlc_net_501 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2679 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_538 ( .LO ( optlc_net_502 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2680 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_539 ( .LO ( optlc_net_503 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2681 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_540 ( .LO ( optlc_net_504 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2682 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_541 ( .LO ( optlc_net_505 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2683 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_542 ( .LO ( optlc_net_506 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2684 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_543 ( .LO ( optlc_net_507 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2685 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_545 ( .LO ( optlc_net_508 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2686 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_546 ( .LO ( optlc_net_509 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2687 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_548 ( .LO ( optlc_net_510 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2688 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_549 ( .LO ( optlc_net_511 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2689 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_550 ( .LO ( optlc_net_512 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2690 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_551 ( .LO ( optlc_net_513 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2691 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_552 ( .LO ( optlc_net_514 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2692 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_553 ( .LO ( optlc_net_515 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2693 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_554 ( .LO ( optlc_net_516 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2694 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_555 ( .LO ( optlc_net_517 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2695 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_556 ( .LO ( optlc_net_518 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2696 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_557 ( .LO ( optlc_net_519 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2697 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_558 ( .LO ( optlc_net_520 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2698 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_559 ( .LO ( optlc_net_521 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2699 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_560 ( .LO ( optlc_net_522 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2700 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_561 ( .LO ( optlc_net_523 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2701 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_562 ( .LO ( optlc_net_524 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2702 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_563 ( .LO ( optlc_net_525 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2703 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_564 ( .LO ( optlc_net_526 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2704 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_565 ( .LO ( optlc_net_527 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2705 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_567 ( .LO ( optlc_net_528 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2706 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_568 ( .LO ( optlc_net_529 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2707 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_569 ( .LO ( optlc_net_530 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2708 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_570 ( .LO ( optlc_net_531 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2709 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_571 ( .LO ( optlc_net_532 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2710 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_572 ( .LO ( optlc_net_533 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2711 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_574 ( .LO ( optlc_net_534 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2712 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_575 ( .LO ( optlc_net_535 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2713 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_576 ( .LO ( optlc_net_536 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2714 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_577 ( .LO ( optlc_net_537 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2715 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_578 ( .LO ( optlc_net_538 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2716 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_580 ( .LO ( optlc_net_539 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2717 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_581 ( .LO ( optlc_net_540 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2718 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_582 ( .LO ( optlc_net_541 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2719 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_584 ( .LO ( optlc_net_542 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2720 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_585 ( .LO ( optlc_net_543 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2721 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_586 ( .LO ( optlc_net_544 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2722 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_587 ( .LO ( optlc_net_545 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2723 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_588 ( .LO ( optlc_net_546 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2724 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_589 ( .LO ( optlc_net_547 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2725 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_590 ( .LO ( optlc_net_548 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2726 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_591 ( .LO ( optlc_net_549 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2727 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_592 ( .LO ( optlc_net_550 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2728 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_593 ( .LO ( optlc_net_551 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2729 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_594 ( .LO ( optlc_net_552 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2730 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_595 ( .LO ( optlc_net_553 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2731 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_596 ( .LO ( optlc_net_554 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2732 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_597 ( .LO ( optlc_net_555 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2733 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_598 ( .LO ( optlc_net_556 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2734 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_599 ( .LO ( optlc_net_557 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2735 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_601 ( .LO ( optlc_net_558 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2736 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_602 ( .LO ( optlc_net_559 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2737 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_603 ( .LO ( optlc_net_560 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2738 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_605 ( .LO ( optlc_net_561 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2739 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_607 ( .LO ( optlc_net_562 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2740 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_609 ( .LO ( optlc_net_563 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2741 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_611 ( .LO ( optlc_net_564 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2742 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_613 ( .LO ( optlc_net_565 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2743 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_614 ( .LO ( optlc_net_566 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2744 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_615 ( .LO ( optlc_net_567 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2745 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_617 ( .LO ( optlc_net_568 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2746 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_618 ( .LO ( optlc_net_569 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2747 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_619 ( .LO ( optlc_net_570 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2748 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_620 ( .LO ( optlc_net_571 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2749 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_621 ( .LO ( optlc_net_572 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2750 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_622 ( .LO ( optlc_net_573 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2751 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_623 ( .LO ( optlc_net_574 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2752 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_624 ( .LO ( optlc_net_575 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2753 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_626 ( .LO ( optlc_net_576 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2754 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_627 ( .LO ( optlc_net_577 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2755 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_629 ( .LO ( optlc_net_578 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2756 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_630 ( .LO ( optlc_net_579 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2757 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_631 ( .LO ( optlc_net_580 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2758 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_633 ( .LO ( optlc_net_581 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2759 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_635 ( .LO ( optlc_net_582 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2760 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_636 ( .LO ( optlc_net_583 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2761 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_637 ( .LO ( optlc_net_584 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2762 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_639 ( .LO ( optlc_net_585 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2763 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_640 ( .LO ( optlc_net_586 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2764 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_641 ( .LO ( optlc_net_587 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2765 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_642 ( .LO ( optlc_net_588 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2766 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_643 ( .LO ( optlc_net_589 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2767 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_644 ( .LO ( optlc_net_590 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2768 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_645 ( .LO ( optlc_net_591 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2769 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_647 ( .LO ( optlc_net_592 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2770 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_648 ( .LO ( optlc_net_593 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2771 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_650 ( .LO ( optlc_net_594 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2772 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_651 ( .LO ( optlc_net_595 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2773 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_652 ( .LO ( optlc_net_596 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2774 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_653 ( .LO ( optlc_net_597 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2775 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_655 ( .LO ( optlc_net_598 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2776 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_656 ( .LO ( optlc_net_599 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2777 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_657 ( .LO ( optlc_net_600 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2778 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_658 ( .LO ( optlc_net_601 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2779 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_659 ( .LO ( optlc_net_602 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2780 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_660 ( .LO ( optlc_net_603 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2781 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_661 ( .LO ( optlc_net_604 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2782 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_662 ( .LO ( optlc_net_605 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2783 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_664 ( .LO ( optlc_net_606 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2784 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_665 ( .LO ( optlc_net_607 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2785 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_666 ( .LO ( optlc_net_608 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2786 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_667 ( .LO ( optlc_net_609 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2787 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_668 ( .LO ( optlc_net_610 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2788 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_670 ( .LO ( optlc_net_611 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2789 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_671 ( .LO ( optlc_net_612 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2790 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_672 ( .LO ( optlc_net_613 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2791 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_673 ( .LO ( optlc_net_614 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2792 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_675 ( .LO ( optlc_net_615 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2793 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_677 ( .LO ( optlc_net_616 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2794 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_678 ( .LO ( optlc_net_617 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2795 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_679 ( .LO ( optlc_net_618 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2796 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_680 ( .LO ( optlc_net_619 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2797 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_682 ( .LO ( optlc_net_620 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2798 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_683 ( .LO ( optlc_net_621 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2799 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_684 ( .LO ( optlc_net_622 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2800 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_685 ( .LO ( optlc_net_623 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2801 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_686 ( .LO ( optlc_net_624 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2802 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_687 ( .LO ( optlc_net_625 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2803 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_688 ( .LO ( optlc_net_626 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2804 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_689 ( .LO ( optlc_net_627 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2805 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_690 ( .LO ( optlc_net_628 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2806 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_691 ( .LO ( optlc_net_629 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2807 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_692 ( .LO ( optlc_net_630 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2808 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_693 ( .LO ( optlc_net_631 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2809 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_694 ( .LO ( optlc_net_632 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2810 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_695 ( .LO ( optlc_net_633 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2811 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_697 ( .LO ( optlc_net_634 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2812 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_698 ( .LO ( optlc_net_635 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2813 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_700 ( .LO ( optlc_net_636 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2814 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_701 ( .LO ( optlc_net_637 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2815 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_702 ( .LO ( optlc_net_638 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2816 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_704 ( .LO ( optlc_net_639 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2817 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_705 ( .LO ( optlc_net_640 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2818 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_706 ( .LO ( optlc_net_641 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2819 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_707 ( .LO ( optlc_net_642 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2820 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_709 ( .LO ( optlc_net_643 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2821 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_710 ( .LO ( optlc_net_644 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2822 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_711 ( .LO ( optlc_net_645 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2823 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_712 ( .LO ( optlc_net_646 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2824 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_714 ( .LO ( optlc_net_647 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2825 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_715 ( .LO ( optlc_net_648 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2826 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_716 ( .LO ( optlc_net_649 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2827 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_718 ( .LO ( optlc_net_650 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2828 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_719 ( .LO ( optlc_net_651 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2829 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_720 ( .LO ( optlc_net_652 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2830 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_721 ( .LO ( optlc_net_653 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2831 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_722 ( .LO ( optlc_net_654 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2832 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_723 ( .LO ( optlc_net_655 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2833 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_724 ( .LO ( optlc_net_656 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2834 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_725 ( .LO ( optlc_net_657 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2835 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_726 ( .LO ( optlc_net_658 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2836 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_727 ( .LO ( optlc_net_659 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2837 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_728 ( .LO ( optlc_net_660 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2838 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_729 ( .LO ( optlc_net_661 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2839 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_730 ( .LO ( optlc_net_662 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2840 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_731 ( .LO ( optlc_net_663 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2841 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_732 ( .LO ( optlc_net_664 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2842 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_733 ( .LO ( optlc_net_665 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2843 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_734 ( .LO ( optlc_net_666 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2844 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_736 ( .LO ( optlc_net_667 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2845 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_737 ( .LO ( optlc_net_668 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2846 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_738 ( .LO ( optlc_net_669 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2847 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_740 ( .LO ( optlc_net_670 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2848 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_741 ( .LO ( optlc_net_671 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2849 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_742 ( .LO ( optlc_net_672 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2850 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_743 ( .LO ( optlc_net_673 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2851 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_744 ( .LO ( optlc_net_674 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2852 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_746 ( .LO ( optlc_net_675 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2853 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_747 ( .LO ( optlc_net_676 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2854 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_748 ( .LO ( optlc_net_677 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2855 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_749 ( .LO ( optlc_net_678 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2856 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_750 ( .LO ( optlc_net_679 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2857 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_751 ( .LO ( optlc_net_680 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2858 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_752 ( .LO ( optlc_net_681 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2859 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_753 ( .LO ( optlc_net_682 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2860 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_754 ( .LO ( optlc_net_683 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2861 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_755 ( .LO ( optlc_net_684 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2862 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_756 ( .LO ( optlc_net_685 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2863 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_757 ( .LO ( optlc_net_686 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2864 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_758 ( .LO ( optlc_net_687 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2865 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_760 ( .LO ( optlc_net_688 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2866 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_761 ( .LO ( optlc_net_689 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2867 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_762 ( .LO ( optlc_net_690 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2868 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_763 ( .LO ( optlc_net_691 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2869 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_765 ( .LO ( optlc_net_692 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2870 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_766 ( .LO ( optlc_net_693 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2871 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_767 ( .LO ( optlc_net_694 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2872 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_768 ( .LO ( optlc_net_695 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2873 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_769 ( .LO ( optlc_net_696 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2874 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_771 ( .LO ( optlc_net_697 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2875 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_772 ( .LO ( optlc_net_698 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2876 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_774 ( .LO ( optlc_net_699 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2877 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_775 ( .LO ( optlc_net_700 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2878 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_776 ( .LO ( optlc_net_701 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2879 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_777 ( .LO ( optlc_net_702 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2880 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_778 ( .LO ( optlc_net_703 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2881 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_780 ( .LO ( optlc_net_704 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2882 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_782 ( .LO ( optlc_net_705 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2883 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_783 ( .LO ( optlc_net_706 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2884 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_784 ( .LO ( optlc_net_707 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2885 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_785 ( .LO ( optlc_net_708 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2886 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_786 ( .LO ( optlc_net_709 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2887 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_788 ( .LO ( optlc_net_710 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2888 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_789 ( .LO ( optlc_net_711 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2889 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_790 ( .LO ( optlc_net_712 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2890 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_791 ( .LO ( optlc_net_713 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2891 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_792 ( .LO ( optlc_net_714 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2892 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_793 ( .LO ( optlc_net_715 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2893 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_794 ( .LO ( optlc_net_716 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2894 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_795 ( .LO ( optlc_net_717 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2895 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_796 ( .LO ( optlc_net_718 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2896 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_797 ( .LO ( optlc_net_719 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2897 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_798 ( .LO ( optlc_net_720 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2898 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_799 ( .LO ( optlc_net_721 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2899 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_800 ( .LO ( optlc_net_722 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2900 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_801 ( .LO ( optlc_net_723 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2901 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_802 ( .LO ( optlc_net_724 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2902 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_803 ( .LO ( optlc_net_725 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2903 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_804 ( .LO ( optlc_net_726 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2904 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_805 ( .LO ( optlc_net_727 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2905 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_806 ( .LO ( optlc_net_728 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2906 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_807 ( .LO ( optlc_net_729 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2907 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_808 ( .LO ( optlc_net_730 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2908 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_809 ( .LO ( optlc_net_731 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2909 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_810 ( .LO ( optlc_net_732 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2910 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_811 ( .LO ( optlc_net_733 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2911 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_812 ( .LO ( optlc_net_734 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2912 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_813 ( .LO ( optlc_net_735 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2913 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_814 ( .LO ( optlc_net_736 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2914 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_815 ( .LO ( optlc_net_737 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2915 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_816 ( .LO ( optlc_net_738 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2916 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_817 ( .LO ( optlc_net_739 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2917 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_818 ( .LO ( optlc_net_740 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2918 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_819 ( .LO ( optlc_net_741 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2919 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_820 ( .LO ( optlc_net_742 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2920 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_821 ( .LO ( optlc_net_743 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2921 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_822 ( .LO ( optlc_net_744 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2922 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_824 ( .LO ( optlc_net_745 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2923 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_826 ( .LO ( optlc_net_746 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2924 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_827 ( .LO ( optlc_net_747 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2925 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_829 ( .LO ( optlc_net_748 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2926 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_831 ( .LO ( optlc_net_749 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2927 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_832 ( .LO ( optlc_net_750 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2928 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_834 ( .LO ( optlc_net_751 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2929 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_835 ( .LO ( optlc_net_752 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2930 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_836 ( .LO ( optlc_net_753 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2931 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_837 ( .LO ( optlc_net_754 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2932 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_838 ( .LO ( optlc_net_755 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2933 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_839 ( .LO ( optlc_net_756 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2934 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_840 ( .LO ( optlc_net_757 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2935 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_841 ( .LO ( optlc_net_758 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2936 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_842 ( .LO ( optlc_net_759 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2937 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_843 ( .LO ( optlc_net_760 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2938 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_844 ( .LO ( optlc_net_761 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2939 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_846 ( .LO ( optlc_net_762 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2940 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_847 ( .LO ( optlc_net_763 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2941 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_848 ( .LO ( optlc_net_764 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2942 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_849 ( .LO ( optlc_net_765 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2943 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_850 ( .LO ( optlc_net_766 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2944 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_852 ( .LO ( optlc_net_767 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2945 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_853 ( .LO ( optlc_net_768 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2946 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_854 ( .LO ( optlc_net_769 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2947 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_855 ( .LO ( optlc_net_770 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2948 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_856 ( .LO ( optlc_net_771 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2949 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_857 ( .LO ( optlc_net_772 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2950 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_858 ( .LO ( optlc_net_773 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2951 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_859 ( .LO ( optlc_net_774 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2952 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_860 ( .LO ( optlc_net_775 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2953 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_861 ( .LO ( optlc_net_776 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2954 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_862 ( .LO ( optlc_net_777 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2955 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_863 ( .LO ( optlc_net_778 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2956 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_864 ( .LO ( optlc_net_779 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2957 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_865 ( .LO ( optlc_net_780 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2958 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_866 ( .LO ( optlc_net_781 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2959 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_867 ( .LO ( optlc_net_782 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2960 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_869 ( .LO ( optlc_net_783 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2961 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_870 ( .LO ( optlc_net_784 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2962 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_871 ( .LO ( optlc_net_785 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2963 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_872 ( .LO ( optlc_net_786 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2964 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_873 ( .LO ( optlc_net_787 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2965 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_874 ( .LO ( optlc_net_788 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2966 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_875 ( .LO ( optlc_net_789 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2967 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_876 ( .LO ( optlc_net_790 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2968 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_877 ( .LO ( optlc_net_791 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2969 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_878 ( .LO ( optlc_net_792 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2970 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_879 ( .LO ( optlc_net_793 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2971 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_880 ( .LO ( optlc_net_794 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2972 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_881 ( .LO ( optlc_net_795 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2973 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_882 ( .LO ( optlc_net_796 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2974 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_883 ( .LO ( optlc_net_797 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2975 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_884 ( .LO ( optlc_net_798 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2976 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_886 ( .LO ( optlc_net_799 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2977 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_887 ( .LO ( optlc_net_800 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2978 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_888 ( .LO ( optlc_net_801 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2979 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_889 ( .LO ( optlc_net_802 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2980 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_890 ( .LO ( optlc_net_803 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2981 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_891 ( .LO ( optlc_net_804 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2982 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_892 ( .LO ( optlc_net_805 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2983 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_893 ( .LO ( optlc_net_806 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2984 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_895 ( .LO ( optlc_net_807 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2985 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_896 ( .LO ( optlc_net_808 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2986 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_897 ( .LO ( optlc_net_809 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2987 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_898 ( .LO ( optlc_net_810 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2988 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_899 ( .LO ( optlc_net_811 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2989 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_900 ( .LO ( optlc_net_812 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2990 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_901 ( .LO ( optlc_net_813 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2991 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_902 ( .LO ( optlc_net_814 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2992 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_903 ( .LO ( optlc_net_815 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2993 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_904 ( .LO ( optlc_net_816 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2994 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_905 ( .LO ( optlc_net_817 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2995 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_906 ( .LO ( optlc_net_818 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2996 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_908 ( .LO ( optlc_net_819 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2997 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_909 ( .LO ( optlc_net_820 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2998 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_910 ( .LO ( optlc_net_821 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_2999 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_912 ( .LO ( optlc_net_822 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3000 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_913 ( .LO ( optlc_net_823 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3001 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_914 ( .LO ( optlc_net_824 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3002 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_915 ( .LO ( optlc_net_825 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3003 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_917 ( .LO ( optlc_net_826 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3004 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_918 ( .LO ( optlc_net_827 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3005 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_919 ( .LO ( optlc_net_828 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3006 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_920 ( .LO ( optlc_net_829 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3007 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_921 ( .LO ( optlc_net_830 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3008 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_922 ( .LO ( optlc_net_831 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3009 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_923 ( .LO ( optlc_net_832 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3010 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_924 ( .LO ( optlc_net_833 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3011 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_925 ( .LO ( optlc_net_834 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3012 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_926 ( .LO ( optlc_net_835 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3013 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_928 ( .LO ( optlc_net_836 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3014 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_929 ( .LO ( optlc_net_837 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3015 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_930 ( .LO ( optlc_net_838 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3016 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_931 ( .LO ( optlc_net_839 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3017 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_932 ( .LO ( optlc_net_840 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3018 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_933 ( .LO ( optlc_net_841 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3019 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_934 ( .LO ( optlc_net_842 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3020 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_936 ( .LO ( optlc_net_843 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3021 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_937 ( .LO ( optlc_net_844 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3022 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_938 ( .LO ( optlc_net_845 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3023 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_939 ( .LO ( optlc_net_846 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3024 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_940 ( .LO ( optlc_net_847 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3025 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_941 ( .LO ( optlc_net_848 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3026 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_942 ( .LO ( optlc_net_849 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3027 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_944 ( .LO ( optlc_net_850 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3028 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_945 ( .LO ( optlc_net_851 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3029 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_946 ( .LO ( optlc_net_852 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3030 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_947 ( .LO ( optlc_net_853 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3031 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_948 ( .LO ( optlc_net_854 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3032 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_949 ( .LO ( optlc_net_855 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3033 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_950 ( .LO ( optlc_net_856 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3034 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_951 ( .LO ( optlc_net_857 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3035 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_952 ( .LO ( optlc_net_858 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3036 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_953 ( .LO ( optlc_net_859 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3037 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_954 ( .LO ( optlc_net_860 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3038 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_955 ( .LO ( optlc_net_861 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3039 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_956 ( .LO ( optlc_net_862 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3040 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_957 ( .LO ( optlc_net_863 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3041 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_958 ( .LO ( optlc_net_864 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3042 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_959 ( .LO ( optlc_net_865 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3043 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_960 ( .LO ( optlc_net_866 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3044 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_961 ( .LO ( optlc_net_867 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3045 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_962 ( .LO ( optlc_net_868 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3046 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_963 ( .LO ( optlc_net_869 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3047 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_964 ( .LO ( optlc_net_870 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3048 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_965 ( .LO ( optlc_net_871 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3049 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_966 ( .LO ( optlc_net_872 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3050 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_967 ( .LO ( optlc_net_873 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3051 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_968 ( .LO ( optlc_net_874 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3052 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_969 ( .LO ( optlc_net_875 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3053 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_970 ( .LO ( optlc_net_876 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3054 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_971 ( .LO ( optlc_net_877 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3055 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_972 ( .LO ( optlc_net_878 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3056 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_973 ( .LO ( optlc_net_879 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3057 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_974 ( .LO ( optlc_net_880 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3058 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_975 ( .LO ( optlc_net_881 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3059 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_976 ( .LO ( optlc_net_882 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3060 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_977 ( .LO ( optlc_net_883 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3061 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_978 ( .LO ( optlc_net_884 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3062 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_979 ( .LO ( optlc_net_885 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3063 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_980 ( .LO ( optlc_net_886 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3064 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_981 ( .LO ( optlc_net_887 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3065 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_983 ( .LO ( optlc_net_888 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3066 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_984 ( .LO ( optlc_net_889 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3067 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_985 ( .LO ( optlc_net_890 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3068 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_986 ( .LO ( optlc_net_891 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3069 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_987 ( .LO ( optlc_net_892 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3070 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_988 ( .LO ( optlc_net_893 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3071 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_989 ( .LO ( optlc_net_894 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3072 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_990 ( .LO ( optlc_net_895 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3073 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_991 ( .LO ( optlc_net_896 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3074 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_992 ( .LO ( optlc_net_897 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3075 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_993 ( .LO ( optlc_net_898 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3076 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_994 ( .LO ( optlc_net_899 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3077 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_995 ( .LO ( optlc_net_900 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3078 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_997 ( .LO ( optlc_net_901 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3079 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_998 ( .LO ( optlc_net_902 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3080 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_999 ( .LO ( optlc_net_903 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3081 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_1000 ( .LO ( optlc_net_904 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3082 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_1001 ( .LO ( optlc_net_905 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3083 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_1002 ( .LO ( optlc_net_906 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3084 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_1003 ( .LO ( optlc_net_907 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3085 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_1004 ( .LO ( optlc_net_908 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3086 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_1005 ( .LO ( optlc_net_909 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3087 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_1006 ( .LO ( optlc_net_910 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3088 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_1007 ( .LO ( optlc_net_911 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3089 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_1008 ( .LO ( optlc_net_912 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3090 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_1010 ( .LO ( optlc_net_913 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3091 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_1013 ( .LO ( optlc_net_914 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3092 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_1014 ( .LO ( optlc_net_915 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3093 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_1017 ( .LO ( optlc_net_916 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3094 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_1018 ( .LO ( optlc_net_917 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3095 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_1020 ( .LO ( optlc_net_918 ) , 
    .HI ( SYNOPSYS_UNCONNECTED_3096 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_55291 ( .A ( ropt_net_1586 ) , 
    .X ( ropt_net_1583 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_1824719538 ( .A ( ctsbuf_net_4922 ) , 
    .Y ( ctsbuf_net_1919 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_1824819539 ( .A ( ctsbuf_net_4922 ) , 
    .Y ( ctsbuf_net_2920 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_1824919540 ( .A ( ctsbuf_net_4922 ) , 
    .Y ( ctsbuf_net_3921 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_1825319544 ( .A ( clk[0] ) , 
    .Y ( ctsbuf_net_4922 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_1825719548 ( .A ( ctsbuf_net_6924 ) , 
    .Y ( ctsbuf_net_5923 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_1826119552 ( .A ( clk[0] ) , 
    .Y ( ctsbuf_net_6924 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5181153102 ( .A ( ctsbuf_net_6001518 ) , 
    .Y ( ctsbuf_net_7925 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5181253103 ( .A ( ctsbuf_net_6081526 ) , 
    .Y ( ctsbuf_net_8926 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_55292 ( .A ( ropt_net_1587 ) , 
    .X ( ropt_net_1584 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_55293 ( .A ( ropt_net_1584 ) , 
    .X ( ropt_net_1585 ) ) ;
sky130_fd_sc_hd__inv_12 cts_inv_5181553106 ( .A ( ctsbuf_net_6081526 ) , 
    .Y ( ctsbuf_net_11929 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5181653107 ( .A ( ctsbuf_net_6241542 ) , 
    .Y ( ctsbuf_net_12930 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5181753108 ( .A ( ctsbuf_net_5981516 ) , 
    .Y ( ctsbuf_net_13931 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5181853109 ( .A ( ctsbuf_net_6031521 ) , 
    .Y ( ctsbuf_net_14932 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5181953110 ( .A ( ctsbuf_net_6241542 ) , 
    .Y ( ctsbuf_net_15933 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5182053111 ( .A ( ctsbuf_net_6031521 ) , 
    .Y ( ctsbuf_net_16934 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5182153112 ( .A ( ctsbuf_net_6081526 ) , 
    .Y ( ctsbuf_net_17935 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_55294 ( 
    .A ( direct_interc_138_out[0] ) , .X ( ropt_net_1586 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_55295 ( .A ( ropt_net_1583 ) , 
    .X ( ropt_net_1587 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_55296 ( .A ( ropt_net_1585 ) , 
    .X ( ropt_net_1588 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_55297 ( .A ( ropt_net_1590 ) , 
    .X ( ropt_net_1589 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5182653117 ( .A ( ctsbuf_net_6351553 ) , 
    .Y ( ctsbuf_net_22940 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5182753118 ( .A ( ctsbuf_net_6241542 ) , 
    .Y ( ctsbuf_net_23941 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5182853119 ( .A ( ctsbuf_net_6351553 ) , 
    .Y ( ctsbuf_net_24942 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5182953120 ( .A ( ctsbuf_net_5981516 ) , 
    .Y ( ctsbuf_net_25943 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5183053121 ( .A ( ctsbuf_net_5981516 ) , 
    .Y ( ctsbuf_net_26944 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5183153122 ( .A ( ctsbuf_net_5991517 ) , 
    .Y ( ctsbuf_net_27945 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5183253123 ( .A ( ctsbuf_net_6101528 ) , 
    .Y ( ctsbuf_net_28946 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5183353124 ( .A ( ctsbuf_net_5981516 ) , 
    .Y ( ctsbuf_net_29947 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5183453125 ( .A ( ctsbuf_net_6031521 ) , 
    .Y ( ctsbuf_net_30948 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_55298 ( 
    .A ( direct_interc_133_out[0] ) , .X ( ropt_net_1590 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_55299 ( .A ( ropt_net_1589 ) , 
    .X ( ropt_net_1591 ) ) ;
sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_55300 ( .A ( ropt_net_1591 ) , 
    .X ( ropt_net_1592 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5183853129 ( .A ( ctsbuf_net_6081526 ) , 
    .Y ( ctsbuf_net_34952 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5184553136 ( .A ( ctsbuf_net_6321550 ) , 
    .Y ( ctsbuf_net_41959 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5184653137 ( .A ( ctsbuf_net_6351553 ) , 
    .Y ( ctsbuf_net_42960 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5184753138 ( .A ( ctsbuf_net_6101528 ) , 
    .Y ( ctsbuf_net_43961 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5184853139 ( .A ( ctsbuf_net_6321550 ) , 
    .Y ( ctsbuf_net_44962 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5184953140 ( .A ( ctsbuf_net_6081526 ) , 
    .Y ( ctsbuf_net_45963 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5185053141 ( .A ( ctsbuf_net_6001518 ) , 
    .Y ( ctsbuf_net_46964 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5185153142 ( .A ( ctsbuf_net_5981516 ) , 
    .Y ( ctsbuf_net_47965 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5185253143 ( .A ( ctsbuf_net_6031521 ) , 
    .Y ( ctsbuf_net_48966 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5185353144 ( .A ( ctsbuf_net_6101528 ) , 
    .Y ( ctsbuf_net_49967 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5185453145 ( .A ( ctsbuf_net_5851503 ) , 
    .Y ( ctsbuf_net_50968 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5185553146 ( .A ( ctsbuf_net_5951513 ) , 
    .Y ( ctsbuf_net_51969 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5185653147 ( .A ( ctsbuf_net_5981516 ) , 
    .Y ( ctsbuf_net_52970 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5185853149 ( .A ( ctsbuf_net_5991517 ) , 
    .Y ( ctsbuf_net_54972 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5186353154 ( .A ( ctsbuf_net_5861504 ) , 
    .Y ( ctsbuf_net_59977 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5187353164 ( .A ( ctsbuf_net_6241542 ) , 
    .Y ( ctsbuf_net_69987 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5187453165 ( .A ( ctsbuf_net_6101528 ) , 
    .Y ( ctsbuf_net_70988 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5187553166 ( .A ( ctsbuf_net_5861504 ) , 
    .Y ( ctsbuf_net_71989 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5187653167 ( .A ( ctsbuf_net_6321550 ) , 
    .Y ( ctsbuf_net_72990 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5187753168 ( .A ( ctsbuf_net_6321550 ) , 
    .Y ( ctsbuf_net_73991 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5187853169 ( .A ( ctsbuf_net_5861504 ) , 
    .Y ( ctsbuf_net_74992 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5187953170 ( .A ( ctsbuf_net_5851503 ) , 
    .Y ( ctsbuf_net_75993 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5188053171 ( .A ( ctsbuf_net_5851503 ) , 
    .Y ( ctsbuf_net_76994 ) ) ;
sky130_fd_sc_hd__inv_12 cts_inv_5188153172 ( .A ( ctsbuf_net_6031521 ) , 
    .Y ( ctsbuf_net_77995 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5188253173 ( .A ( ctsbuf_net_6101528 ) , 
    .Y ( ctsbuf_net_78996 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5188353174 ( .A ( ctsbuf_net_5851503 ) , 
    .Y ( ctsbuf_net_79997 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5188453175 ( .A ( ctsbuf_net_6031521 ) , 
    .Y ( ctsbuf_net_80998 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5188553176 ( .A ( ctsbuf_net_5851503 ) , 
    .Y ( ctsbuf_net_81999 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5188753178 ( .A ( ctsbuf_net_5951513 ) , 
    .Y ( ctsbuf_net_831001 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5188853179 ( .A ( ctsbuf_net_5881506 ) , 
    .Y ( ctsbuf_net_841002 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5189053181 ( .A ( ctsbuf_net_5951513 ) , 
    .Y ( ctsbuf_net_861004 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5189353184 ( .A ( ctsbuf_net_5861504 ) , 
    .Y ( ctsbuf_net_891007 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5189453185 ( .A ( ctsbuf_net_6301548 ) , 
    .Y ( ctsbuf_net_901008 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5189553186 ( .A ( ctsbuf_net_5821500 ) , 
    .Y ( ctsbuf_net_911009 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5189653187 ( .A ( ctsbuf_net_5861504 ) , 
    .Y ( ctsbuf_net_921010 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5189753188 ( .A ( ctsbuf_net_5871505 ) , 
    .Y ( ctsbuf_net_931011 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5189953190 ( .A ( ctsbuf_net_5851503 ) , 
    .Y ( ctsbuf_net_951013 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5190353194 ( .A ( ctsbuf_net_5851503 ) , 
    .Y ( ctsbuf_net_991017 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5190953200 ( .A ( ctsbuf_net_6101528 ) , 
    .Y ( ctsbuf_net_1051023 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5191153202 ( .A ( ctsbuf_net_6211539 ) , 
    .Y ( ctsbuf_net_1071025 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5191353204 ( .A ( ctsbuf_net_6301548 ) , 
    .Y ( ctsbuf_net_1091027 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5191453205 ( .A ( ctsbuf_net_5821500 ) , 
    .Y ( ctsbuf_net_1101028 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5191553206 ( .A ( ctsbuf_net_5861504 ) , 
    .Y ( ctsbuf_net_1111029 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5191853209 ( .A ( ctsbuf_net_6101528 ) , 
    .Y ( ctsbuf_net_1141032 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5191953210 ( .A ( ctsbuf_net_5871505 ) , 
    .Y ( ctsbuf_net_1151033 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5192153212 ( .A ( ctsbuf_net_5851503 ) , 
    .Y ( ctsbuf_net_1171035 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5192453215 ( .A ( ctsbuf_net_5991517 ) , 
    .Y ( ctsbuf_net_1201038 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5192653217 ( .A ( ctsbuf_net_5971515 ) , 
    .Y ( ctsbuf_net_1221040 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5192753218 ( .A ( ctsbuf_net_5881506 ) , 
    .Y ( ctsbuf_net_1231041 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5193053221 ( .A ( ctsbuf_net_5951513 ) , 
    .Y ( ctsbuf_net_1261044 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5193553226 ( .A ( ctsbuf_net_5861504 ) , 
    .Y ( ctsbuf_net_1311049 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5193653227 ( .A ( ctsbuf_net_5971515 ) , 
    .Y ( ctsbuf_net_1321050 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5193753228 ( .A ( ctsbuf_net_5841502 ) , 
    .Y ( ctsbuf_net_1331051 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5193953230 ( .A ( ctsbuf_net_5851503 ) , 
    .Y ( ctsbuf_net_1351053 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5194253233 ( .A ( ctsbuf_net_5991517 ) , 
    .Y ( ctsbuf_net_1381056 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5194853239 ( .A ( ctsbuf_net_5951513 ) , 
    .Y ( ctsbuf_net_1441062 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5195153242 ( .A ( ctsbuf_net_6111529 ) , 
    .Y ( ctsbuf_net_1471065 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5195353244 ( .A ( ctsbuf_net_6311549 ) , 
    .Y ( ctsbuf_net_1491067 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5195453245 ( .A ( ctsbuf_net_6191537 ) , 
    .Y ( ctsbuf_net_1501068 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5195553246 ( .A ( ctsbuf_net_6211539 ) , 
    .Y ( ctsbuf_net_1511069 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5195753248 ( .A ( ctsbuf_net_6301548 ) , 
    .Y ( ctsbuf_net_1531071 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5195853249 ( .A ( ctsbuf_net_5821500 ) , 
    .Y ( ctsbuf_net_1541072 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5195953250 ( .A ( ctsbuf_net_6041522 ) , 
    .Y ( ctsbuf_net_1551073 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5196253253 ( .A ( ctsbuf_net_6121530 ) , 
    .Y ( ctsbuf_net_1581076 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5196353254 ( .A ( ctsbuf_net_5871505 ) , 
    .Y ( ctsbuf_net_1591077 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5196553256 ( .A ( ctsbuf_net_5871505 ) , 
    .Y ( ctsbuf_net_1611079 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5196853259 ( .A ( ctsbuf_net_6021520 ) , 
    .Y ( ctsbuf_net_1641082 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5197153262 ( .A ( ctsbuf_net_5991517 ) , 
    .Y ( ctsbuf_net_1671085 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5197453265 ( .A ( ctsbuf_net_6011519 ) , 
    .Y ( ctsbuf_net_1701088 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5197753268 ( .A ( ctsbuf_net_5971515 ) , 
    .Y ( ctsbuf_net_1731091 ) ) ;
sky130_fd_sc_hd__bufinv_8 cts_inv_5198253273 ( .A ( ctsbuf_net_6041522 ) , 
    .Y ( ctsbuf_net_1781096 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5198353274 ( .A ( ctsbuf_net_5841502 ) , 
    .Y ( ctsbuf_net_1791097 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5198453275 ( .A ( ctsbuf_net_5871505 ) , 
    .Y ( ctsbuf_net_1801098 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5198953280 ( .A ( ctsbuf_net_5871505 ) , 
    .Y ( ctsbuf_net_1851103 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5199853289 ( .A ( ctsbuf_net_6121530 ) , 
    .Y ( ctsbuf_net_1941112 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5200053291 ( .A ( ctsbuf_net_6091527 ) , 
    .Y ( ctsbuf_net_1961114 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5200253293 ( .A ( ctsbuf_net_6311549 ) , 
    .Y ( ctsbuf_net_1981116 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5200453295 ( .A ( ctsbuf_net_6231541 ) , 
    .Y ( ctsbuf_net_2001118 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5200653297 ( .A ( ctsbuf_net_6191537 ) , 
    .Y ( ctsbuf_net_2021120 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5200753298 ( .A ( ctsbuf_net_6041522 ) , 
    .Y ( ctsbuf_net_2031121 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5201153302 ( .A ( ctsbuf_net_5841502 ) , 
    .Y ( ctsbuf_net_2071125 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5201353304 ( .A ( ctsbuf_net_5871505 ) , 
    .Y ( ctsbuf_net_2091127 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5201653307 ( .A ( ctsbuf_net_6371555 ) , 
    .Y ( ctsbuf_net_2121130 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5201953310 ( .A ( ctsbuf_net_6021520 ) , 
    .Y ( ctsbuf_net_2151133 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5202253313 ( .A ( ctsbuf_net_6011519 ) , 
    .Y ( ctsbuf_net_2181136 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5202553316 ( .A ( ctsbuf_net_5971515 ) , 
    .Y ( ctsbuf_net_2211139 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5203053321 ( .A ( ctsbuf_net_6041522 ) , 
    .Y ( ctsbuf_net_2261144 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5203153322 ( .A ( ctsbuf_net_5831501 ) , 
    .Y ( ctsbuf_net_2271145 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5204653337 ( .A ( ctsbuf_net_6151533 ) , 
    .Y ( ctsbuf_net_2421160 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5204853339 ( .A ( ctsbuf_net_6091527 ) , 
    .Y ( ctsbuf_net_2441162 ) ) ;
sky130_fd_sc_hd__bufinv_8 cts_inv_5204953340 ( .A ( ctsbuf_net_6231541 ) , 
    .Y ( ctsbuf_net_2451163 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5205053341 ( .A ( ctsbuf_net_6111529 ) , 
    .Y ( ctsbuf_net_2461164 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5205253343 ( .A ( ctsbuf_net_6221540 ) , 
    .Y ( ctsbuf_net_2481166 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5205453345 ( .A ( ctsbuf_net_6231541 ) , 
    .Y ( ctsbuf_net_2501168 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5205553346 ( .A ( ctsbuf_net_6191537 ) , 
    .Y ( ctsbuf_net_2511169 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5205853349 ( .A ( ctsbuf_net_6121530 ) , 
    .Y ( ctsbuf_net_2541172 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5205953350 ( .A ( ctsbuf_net_5831501 ) , 
    .Y ( ctsbuf_net_2551173 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5206153352 ( .A ( ctsbuf_net_6061524 ) , 
    .Y ( ctsbuf_net_2571175 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5206353354 ( .A ( ctsbuf_net_6051523 ) , 
    .Y ( ctsbuf_net_2591177 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5206453355 ( .A ( ctsbuf_net_5841502 ) , 
    .Y ( ctsbuf_net_2601178 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5206753358 ( .A ( ctsbuf_net_6051523 ) , 
    .Y ( ctsbuf_net_2631181 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5206953360 ( .A ( ctsbuf_net_6091527 ) , 
    .Y ( ctsbuf_net_2651183 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5207053361 ( .A ( ctsbuf_net_6011519 ) , 
    .Y ( ctsbuf_net_2661184 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5207353364 ( .A ( ctsbuf_net_6041522 ) , 
    .Y ( ctsbuf_net_2691187 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5207753368 ( .A ( ctsbuf_net_6231541 ) , 
    .Y ( ctsbuf_net_2731191 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5207953370 ( .A ( ctsbuf_net_5831501 ) , 
    .Y ( ctsbuf_net_2751193 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5209453385 ( .A ( ctsbuf_net_6131531 ) , 
    .Y ( ctsbuf_net_2901208 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5209653387 ( .A ( ctsbuf_net_6141532 ) , 
    .Y ( ctsbuf_net_2921210 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5209853389 ( .A ( ctsbuf_net_6091527 ) , 
    .Y ( ctsbuf_net_2941212 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5210053391 ( .A ( ctsbuf_net_6111529 ) , 
    .Y ( ctsbuf_net_2961214 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5210253393 ( .A ( ctsbuf_net_6221540 ) , 
    .Y ( ctsbuf_net_2981216 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5210353394 ( .A ( ctsbuf_net_6231541 ) , 
    .Y ( ctsbuf_net_2991217 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5210553396 ( .A ( ctsbuf_net_5871505 ) , 
    .Y ( ctsbuf_net_3011219 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5210653397 ( .A ( ctsbuf_net_6131531 ) , 
    .Y ( ctsbuf_net_3021220 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5210753398 ( .A ( ctsbuf_net_5831501 ) , 
    .Y ( ctsbuf_net_3031221 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5210953400 ( .A ( ctsbuf_net_6401558 ) , 
    .Y ( ctsbuf_net_3051223 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5211253403 ( .A ( ctsbuf_net_6421560 ) , 
    .Y ( ctsbuf_net_3081226 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5211553406 ( .A ( ctsbuf_net_6061524 ) , 
    .Y ( ctsbuf_net_3111229 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5211853409 ( .A ( ctsbuf_net_6051523 ) , 
    .Y ( ctsbuf_net_3141232 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5212153412 ( .A ( ctsbuf_net_6201538 ) , 
    .Y ( ctsbuf_net_3171235 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5212753418 ( .A ( ctsbuf_net_5891507 ) , 
    .Y ( ctsbuf_net_3231241 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5212853419 ( .A ( ctsbuf_net_5831501 ) , 
    .Y ( ctsbuf_net_3241242 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5213653427 ( .A ( ctsbuf_net_6051523 ) , 
    .Y ( ctsbuf_net_3321250 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5213853429 ( .A ( ctsbuf_net_6051523 ) , 
    .Y ( ctsbuf_net_3341252 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5213953430 ( .A ( ctsbuf_net_6201538 ) , 
    .Y ( ctsbuf_net_3351253 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5214253433 ( .A ( ctsbuf_net_6131531 ) , 
    .Y ( ctsbuf_net_3381256 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5214453435 ( .A ( ctsbuf_net_6261544 ) , 
    .Y ( ctsbuf_net_3401258 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5214653437 ( .A ( ctsbuf_net_6141532 ) , 
    .Y ( ctsbuf_net_3421260 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5214853439 ( .A ( ctsbuf_net_6291547 ) , 
    .Y ( ctsbuf_net_3441262 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5215053441 ( .A ( ctsbuf_net_6221540 ) , 
    .Y ( ctsbuf_net_3461264 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5215153442 ( .A ( ctsbuf_net_6221540 ) , 
    .Y ( ctsbuf_net_3471265 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5215353444 ( .A ( ctsbuf_net_6401558 ) , 
    .Y ( ctsbuf_net_3491267 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5215453445 ( .A ( ctsbuf_net_5931511 ) , 
    .Y ( ctsbuf_net_3501268 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5215553446 ( .A ( ctsbuf_net_5831501 ) , 
    .Y ( ctsbuf_net_3511269 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5215753448 ( .A ( ctsbuf_net_5831501 ) , 
    .Y ( ctsbuf_net_3531271 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5216053451 ( .A ( ctsbuf_net_6401558 ) , 
    .Y ( ctsbuf_net_3561274 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5216353454 ( .A ( ctsbuf_net_6061524 ) , 
    .Y ( ctsbuf_net_3591277 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5216553456 ( .A ( ctsbuf_net_6261544 ) , 
    .Y ( ctsbuf_net_3611279 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5216653457 ( .A ( ctsbuf_net_6061524 ) , 
    .Y ( ctsbuf_net_3621280 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5216953460 ( .A ( ctsbuf_net_6201538 ) , 
    .Y ( ctsbuf_net_3651283 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5217553466 ( .A ( ctsbuf_net_5891507 ) , 
    .Y ( ctsbuf_net_3711289 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5218353474 ( .A ( ctsbuf_net_6401558 ) , 
    .Y ( ctsbuf_net_3791297 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5218753478 ( .A ( ctsbuf_net_6071525 ) , 
    .Y ( ctsbuf_net_3831301 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5219053481 ( .A ( ctsbuf_net_5931511 ) , 
    .Y ( ctsbuf_net_3861304 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5219253483 ( .A ( ctsbuf_net_6261544 ) , 
    .Y ( ctsbuf_net_3881306 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5219453485 ( .A ( ctsbuf_net_6151533 ) , 
    .Y ( ctsbuf_net_3901308 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5219653487 ( .A ( ctsbuf_net_6271545 ) , 
    .Y ( ctsbuf_net_3921310 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5219853489 ( .A ( ctsbuf_net_6291547 ) , 
    .Y ( ctsbuf_net_3941312 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5219953490 ( .A ( ctsbuf_net_6071525 ) , 
    .Y ( ctsbuf_net_3951313 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5220253493 ( .A ( ctsbuf_net_5931511 ) , 
    .Y ( ctsbuf_net_3981316 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5220353494 ( .A ( ctsbuf_net_5891507 ) , 
    .Y ( ctsbuf_net_3991317 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5220553496 ( .A ( ctsbuf_net_5891507 ) , 
    .Y ( ctsbuf_net_4011319 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5220753498 ( .A ( ctsbuf_net_6361554 ) , 
    .Y ( ctsbuf_net_4031321 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5220853499 ( .A ( ctsbuf_net_6401558 ) , 
    .Y ( ctsbuf_net_4041322 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5221153502 ( .A ( ctsbuf_net_6361554 ) , 
    .Y ( ctsbuf_net_4071325 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5221453505 ( .A ( ctsbuf_net_6341552 ) , 
    .Y ( ctsbuf_net_4101328 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5221753508 ( .A ( ctsbuf_net_6071525 ) , 
    .Y ( ctsbuf_net_4131331 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5221953510 ( .A ( ctsbuf_net_6271545 ) , 
    .Y ( ctsbuf_net_4151333 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5222353514 ( .A ( ctsbuf_net_5911509 ) , 
    .Y ( ctsbuf_net_4191337 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5222453515 ( .A ( ctsbuf_net_5891507 ) , 
    .Y ( ctsbuf_net_4201338 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5222753518 ( .A ( ctsbuf_net_5891507 ) , 
    .Y ( ctsbuf_net_4231341 ) ) ;
sky130_fd_sc_hd__bufinv_8 cts_inv_5223053521 ( .A ( ctsbuf_net_6361554 ) , 
    .Y ( ctsbuf_net_4261344 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5223853529 ( .A ( ctsbuf_net_6171535 ) , 
    .Y ( ctsbuf_net_4341352 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5224053531 ( .A ( ctsbuf_net_5931511 ) , 
    .Y ( ctsbuf_net_4361354 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5224153532 ( .A ( ctsbuf_net_6271545 ) , 
    .Y ( ctsbuf_net_4371355 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5224253533 ( .A ( ctsbuf_net_6261544 ) , 
    .Y ( ctsbuf_net_4381356 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5224453535 ( .A ( ctsbuf_net_6281546 ) , 
    .Y ( ctsbuf_net_4401358 ) ) ;
sky130_fd_sc_hd__bufinv_8 cts_inv_5224553536 ( .A ( ctsbuf_net_6071525 ) , 
    .Y ( ctsbuf_net_4411359 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5224653537 ( .A ( ctsbuf_net_6271545 ) , 
    .Y ( ctsbuf_net_4421360 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5224753538 ( .A ( ctsbuf_net_6341552 ) , 
    .Y ( ctsbuf_net_4431361 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5224853539 ( .A ( ctsbuf_net_6171535 ) , 
    .Y ( ctsbuf_net_4441362 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5225153542 ( .A ( ctsbuf_net_5911509 ) , 
    .Y ( ctsbuf_net_4471365 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5225353544 ( .A ( ctsbuf_net_5891507 ) , 
    .Y ( ctsbuf_net_4491367 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5225553546 ( .A ( ctsbuf_net_6361554 ) , 
    .Y ( ctsbuf_net_4511369 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5225753548 ( .A ( ctsbuf_net_6261544 ) , 
    .Y ( ctsbuf_net_4531371 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5225953550 ( .A ( ctsbuf_net_6361554 ) , 
    .Y ( ctsbuf_net_4551373 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5226253553 ( .A ( ctsbuf_net_6361554 ) , 
    .Y ( ctsbuf_net_4581376 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5226553556 ( .A ( ctsbuf_net_6071525 ) , 
    .Y ( ctsbuf_net_4611379 ) ) ;
sky130_fd_sc_hd__bufinv_8 cts_inv_5227053561 ( .A ( ctsbuf_net_6341552 ) , 
    .Y ( ctsbuf_net_4661384 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5227153562 ( .A ( ctsbuf_net_5911509 ) , 
    .Y ( ctsbuf_net_4671385 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5227253563 ( .A ( ctsbuf_net_5891507 ) , 
    .Y ( ctsbuf_net_4681386 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5227453565 ( .A ( ctsbuf_net_5911509 ) , 
    .Y ( ctsbuf_net_4701388 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5228353574 ( .A ( ctsbuf_net_6171535 ) , 
    .Y ( ctsbuf_net_4791397 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5228553576 ( .A ( ctsbuf_net_6261544 ) , 
    .Y ( ctsbuf_net_4811399 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5228753578 ( .A ( ctsbuf_net_6271545 ) , 
    .Y ( ctsbuf_net_4831401 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5228953580 ( .A ( ctsbuf_net_6251543 ) , 
    .Y ( ctsbuf_net_4851403 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5229153582 ( .A ( ctsbuf_net_6171535 ) , 
    .Y ( ctsbuf_net_4871405 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5229453585 ( .A ( ctsbuf_net_5911509 ) , 
    .Y ( ctsbuf_net_4901408 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5229653587 ( .A ( ctsbuf_net_6391557 ) , 
    .Y ( ctsbuf_net_4921410 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5229953590 ( .A ( ctsbuf_net_6391557 ) , 
    .Y ( ctsbuf_net_4951413 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5230053591 ( .A ( ctsbuf_net_5921510 ) , 
    .Y ( ctsbuf_net_4961414 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5230153592 ( .A ( ctsbuf_net_6181536 ) , 
    .Y ( ctsbuf_net_4971415 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5230653597 ( .A ( ctsbuf_net_5921510 ) , 
    .Y ( ctsbuf_net_5021420 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5231053601 ( .A ( ctsbuf_net_5911509 ) , 
    .Y ( ctsbuf_net_5061424 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5231153602 ( .A ( ctsbuf_net_6391557 ) , 
    .Y ( ctsbuf_net_5071425 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5231353604 ( .A ( ctsbuf_net_5911509 ) , 
    .Y ( ctsbuf_net_5091427 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5231953610 ( .A ( ctsbuf_net_5921510 ) , 
    .Y ( ctsbuf_net_5151433 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5232053611 ( .A ( ctsbuf_net_6171535 ) , 
    .Y ( ctsbuf_net_5161434 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5232253613 ( .A ( ctsbuf_net_5921510 ) , 
    .Y ( ctsbuf_net_5181436 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5232453615 ( .A ( ctsbuf_net_6251543 ) , 
    .Y ( ctsbuf_net_5201438 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5232553616 ( .A ( ctsbuf_net_6181536 ) , 
    .Y ( ctsbuf_net_5211439 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5232653617 ( .A ( ctsbuf_net_6171535 ) , 
    .Y ( ctsbuf_net_5221440 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5232953620 ( .A ( ctsbuf_net_6381556 ) , 
    .Y ( ctsbuf_net_5251443 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5233153622 ( .A ( ctsbuf_net_6391557 ) , 
    .Y ( ctsbuf_net_5271445 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5233353624 ( .A ( ctsbuf_net_6161534 ) , 
    .Y ( ctsbuf_net_5291447 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5233453625 ( .A ( ctsbuf_net_5921510 ) , 
    .Y ( ctsbuf_net_5301448 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5233553626 ( .A ( ctsbuf_net_6181536 ) , 
    .Y ( ctsbuf_net_5311449 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5233753628 ( .A ( ctsbuf_net_5921510 ) , 
    .Y ( ctsbuf_net_5331451 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5233953630 ( .A ( ctsbuf_net_5921510 ) , 
    .Y ( ctsbuf_net_5351453 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5234153632 ( .A ( ctsbuf_net_6381556 ) , 
    .Y ( ctsbuf_net_5371455 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5234253633 ( .A ( ctsbuf_net_6391557 ) , 
    .Y ( ctsbuf_net_5381456 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5234453635 ( .A ( ctsbuf_net_6381556 ) , 
    .Y ( ctsbuf_net_5401458 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5234553636 ( .A ( ctsbuf_net_6161534 ) , 
    .Y ( ctsbuf_net_5411459 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5234853639 ( .A ( ctsbuf_net_5961514 ) , 
    .Y ( ctsbuf_net_5441462 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5234953640 ( .A ( ctsbuf_net_5901508 ) , 
    .Y ( ctsbuf_net_5451463 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5235153642 ( .A ( ctsbuf_net_5921510 ) , 
    .Y ( ctsbuf_net_5471465 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5235253643 ( .A ( ctsbuf_net_6251543 ) , 
    .Y ( ctsbuf_net_5481466 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5235353644 ( .A ( ctsbuf_net_5901508 ) , 
    .Y ( ctsbuf_net_5491467 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5235453645 ( .A ( ctsbuf_net_6391557 ) , 
    .Y ( ctsbuf_net_5501468 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5235553646 ( .A ( ctsbuf_net_5941512 ) , 
    .Y ( ctsbuf_net_5511469 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5235653647 ( .A ( ctsbuf_net_6381556 ) , 
    .Y ( ctsbuf_net_5521470 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5235753648 ( .A ( ctsbuf_net_6161534 ) , 
    .Y ( ctsbuf_net_5531471 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5235853649 ( .A ( ctsbuf_net_5901508 ) , 
    .Y ( ctsbuf_net_5541472 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5235953650 ( .A ( ctsbuf_net_6181536 ) , 
    .Y ( ctsbuf_net_5551473 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5236153652 ( .A ( ctsbuf_net_6181536 ) , 
    .Y ( ctsbuf_net_5571475 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5236253653 ( .A ( ctsbuf_net_5921510 ) , 
    .Y ( ctsbuf_net_5581476 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5236453655 ( .A ( ctsbuf_net_5941512 ) , 
    .Y ( ctsbuf_net_5601478 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5236653657 ( .A ( ctsbuf_net_5941512 ) , 
    .Y ( ctsbuf_net_5621480 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5236753658 ( .A ( ctsbuf_net_5941512 ) , 
    .Y ( ctsbuf_net_5631481 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5236953660 ( .A ( ctsbuf_net_5961514 ) , 
    .Y ( ctsbuf_net_5651483 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5237053661 ( .A ( ctsbuf_net_5901508 ) , 
    .Y ( ctsbuf_net_5661484 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5237153662 ( .A ( ctsbuf_net_5961514 ) , 
    .Y ( ctsbuf_net_5671485 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5237253663 ( .A ( ctsbuf_net_5901508 ) , 
    .Y ( ctsbuf_net_5681486 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5237353664 ( .A ( ctsbuf_net_5941512 ) , 
    .Y ( ctsbuf_net_5691487 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5237453665 ( .A ( ctsbuf_net_5941512 ) , 
    .Y ( ctsbuf_net_5701488 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5237553666 ( .A ( ctsbuf_net_5961514 ) , 
    .Y ( ctsbuf_net_5711489 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5237653667 ( .A ( ctsbuf_net_5961514 ) , 
    .Y ( ctsbuf_net_5721490 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5237953670 ( .A ( ctsbuf_net_5941512 ) , 
    .Y ( ctsbuf_net_5751493 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5238053671 ( .A ( ctsbuf_net_5941512 ) , 
    .Y ( ctsbuf_net_5761494 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5238253673 ( .A ( ctsbuf_net_5961514 ) , 
    .Y ( ctsbuf_net_5781496 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5238353674 ( .A ( ctsbuf_net_5941512 ) , 
    .Y ( ctsbuf_net_5791497 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5238453675 ( .A ( ctsbuf_net_5941512 ) , 
    .Y ( ctsbuf_net_5801498 ) ) ;
sky130_fd_sc_hd__inv_12 cts_inv_5182253113_5238653677 ( 
    .A ( SYNOPSYS_UNCONNECTED_3097 ) , .Y ( SYNOPSYS_UNCONNECTED_3098 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5184353134_5238753678 ( 
    .A ( SYNOPSYS_UNCONNECTED_3099 ) , .Y ( SYNOPSYS_UNCONNECTED_3100 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5182553116_5238853679 ( 
    .A ( SYNOPSYS_UNCONNECTED_3101 ) , .Y ( SYNOPSYS_UNCONNECTED_3102 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5182353114_5238953680 ( 
    .A ( SYNOPSYS_UNCONNECTED_3103 ) , .Y ( SYNOPSYS_UNCONNECTED_3104 ) ) ;
sky130_fd_sc_hd__inv_12 cts_inv_5186553156_5239053681 ( 
    .A ( SYNOPSYS_UNCONNECTED_3105 ) , .Y ( SYNOPSYS_UNCONNECTED_3106 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5186653157_5239153682 ( 
    .A ( SYNOPSYS_UNCONNECTED_3107 ) , .Y ( SYNOPSYS_UNCONNECTED_3108 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5186153152_5239253683 ( 
    .A ( SYNOPSYS_UNCONNECTED_3109 ) , .Y ( SYNOPSYS_UNCONNECTED_3110 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5183653127_5239353684 ( 
    .A ( SYNOPSYS_UNCONNECTED_3111 ) , .Y ( SYNOPSYS_UNCONNECTED_3112 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5185953150_5239453685 ( 
    .A ( SYNOPSYS_UNCONNECTED_3113 ) , .Y ( SYNOPSYS_UNCONNECTED_3114 ) ) ;
sky130_fd_sc_hd__inv_12 cts_inv_5187053161_5239753688 ( 
    .A ( SYNOPSYS_UNCONNECTED_3115 ) , .Y ( SYNOPSYS_UNCONNECTED_3116 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5183753128_5239953690 ( 
    .A ( SYNOPSYS_UNCONNECTED_3117 ) , .Y ( SYNOPSYS_UNCONNECTED_3118 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5185753148_5240053691 ( 
    .A ( SYNOPSYS_UNCONNECTED_3119 ) , .Y ( SYNOPSYS_UNCONNECTED_3120 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5184253133_5240153692 ( 
    .A ( SYNOPSYS_UNCONNECTED_3121 ) , .Y ( SYNOPSYS_UNCONNECTED_3122 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5183953130_5240253693 ( 
    .A ( SYNOPSYS_UNCONNECTED_3123 ) , .Y ( SYNOPSYS_UNCONNECTED_3124 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5186853159_5240353694 ( 
    .A ( SYNOPSYS_UNCONNECTED_3125 ) , .Y ( SYNOPSYS_UNCONNECTED_3126 ) ) ;
sky130_fd_sc_hd__inv_12 cts_inv_5181353104_5240453695 ( 
    .A ( SYNOPSYS_UNCONNECTED_3127 ) , .Y ( SYNOPSYS_UNCONNECTED_3128 ) ) ;
sky130_fd_sc_hd__inv_12 cts_inv_5186953160_5240653697 ( 
    .A ( SYNOPSYS_UNCONNECTED_3129 ) , .Y ( SYNOPSYS_UNCONNECTED_3130 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5184053131_5240753698 ( 
    .A ( SYNOPSYS_UNCONNECTED_3131 ) , .Y ( p_abuf1 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5186453155_5241053701 ( 
    .A ( SYNOPSYS_UNCONNECTED_3132 ) , .Y ( p_abuf6 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5186253153_5241153702 ( 
    .A ( SYNOPSYS_UNCONNECTED_3133 ) , .Y ( p_abuf0 ) ) ;
sky130_fd_sc_hd__inv_12 cts_inv_5186053151_5241253703 ( 
    .A ( SYNOPSYS_UNCONNECTED_3134 ) , .Y ( SYNOPSYS_UNCONNECTED_3135 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5222653517_5242053711 ( 
    .A ( SYNOPSYS_UNCONNECTED_3136 ) , .Y ( SYNOPSYS_UNCONNECTED_3137 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5206253353_5242153712 ( 
    .A ( SYNOPSYS_UNCONNECTED_3138 ) , .Y ( SYNOPSYS_UNCONNECTED_3139 ) ) ;
sky130_fd_sc_hd__clkinv_8 cts_inv_5198553276_5242253713 ( 
    .A ( SYNOPSYS_UNCONNECTED_3140 ) , .Y ( SYNOPSYS_UNCONNECTED_3141 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5218253473_5242453715 ( 
    .A ( SYNOPSYS_UNCONNECTED_3142 ) , .Y ( SYNOPSYS_UNCONNECTED_3143 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5217953470_5242553716 ( 
    .A ( SYNOPSYS_UNCONNECTED_3144 ) , .Y ( SYNOPSYS_UNCONNECTED_3145 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5217653467_5242653717 ( 
    .A ( SYNOPSYS_UNCONNECTED_3146 ) , .Y ( SYNOPSYS_UNCONNECTED_3147 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5194153232_5242753718 ( 
    .A ( SYNOPSYS_UNCONNECTED_3148 ) , .Y ( SYNOPSYS_UNCONNECTED_3149 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5193853229_5242853719 ( 
    .A ( SYNOPSYS_UNCONNECTED_3150 ) , .Y ( SYNOPSYS_UNCONNECTED_3151 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5234353634_5242953720 ( 
    .A ( SYNOPSYS_UNCONNECTED_3152 ) , .Y ( SYNOPSYS_UNCONNECTED_3153 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5236553656_5243053721 ( 
    .A ( SYNOPSYS_UNCONNECTED_3154 ) , .Y ( SYNOPSYS_UNCONNECTED_3155 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5208953380_5243153722 ( 
    .A ( SYNOPSYS_UNCONNECTED_3156 ) , .Y ( SYNOPSYS_UNCONNECTED_3157 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5208653377_5243253723 ( 
    .A ( SYNOPSYS_UNCONNECTED_3158 ) , .Y ( SYNOPSYS_UNCONNECTED_3159 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5190253193_5243353724 ( 
    .A ( SYNOPSYS_UNCONNECTED_3160 ) , .Y ( p_abuf5 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5194553236_5243453725 ( 
    .A ( SYNOPSYS_UNCONNECTED_3161 ) , .Y ( SYNOPSYS_UNCONNECTED_3162 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5208353374_5243553726 ( 
    .A ( SYNOPSYS_UNCONNECTED_3163 ) , .Y ( SYNOPSYS_UNCONNECTED_3164 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5220653497_5243653727 ( 
    .A ( SYNOPSYS_UNCONNECTED_3165 ) , .Y ( SYNOPSYS_UNCONNECTED_3166 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5190653197_5243753728 ( 
    .A ( SYNOPSYS_UNCONNECTED_3167 ) , .Y ( SYNOPSYS_UNCONNECTED_3168 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5190453195_5243853729 ( 
    .A ( SYNOPSYS_UNCONNECTED_3169 ) , .Y ( p_abuf3 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5189253183_5243953730 ( 
    .A ( SYNOPSYS_UNCONNECTED_3170 ) , .Y ( p_abuf8 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5192553216_5244053731 ( 
    .A ( SYNOPSYS_UNCONNECTED_3171 ) , .Y ( SYNOPSYS_UNCONNECTED_3172 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5222953520_5244153732 ( 
    .A ( SYNOPSYS_UNCONNECTED_3173 ) , .Y ( SYNOPSYS_UNCONNECTED_3174 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5231653607_5244253733 ( 
    .A ( SYNOPSYS_UNCONNECTED_3175 ) , .Y ( SYNOPSYS_UNCONNECTED_3176 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5227953570_5244353734 ( 
    .A ( SYNOPSYS_UNCONNECTED_3177 ) , .Y ( SYNOPSYS_UNCONNECTED_3178 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5227553566_5244453735 ( 
    .A ( SYNOPSYS_UNCONNECTED_3179 ) , .Y ( SYNOPSYS_UNCONNECTED_3180 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5236053651_5244553736 ( 
    .A ( SYNOPSYS_UNCONNECTED_3181 ) , .Y ( SYNOPSYS_UNCONNECTED_3182 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5237753668_5244653737 ( 
    .A ( SYNOPSYS_UNCONNECTED_3183 ) , .Y ( SYNOPSYS_UNCONNECTED_3184 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5238553676_5244753738 ( 
    .A ( SYNOPSYS_UNCONNECTED_3185 ) , .Y ( SYNOPSYS_UNCONNECTED_3186 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5212353414_5244853739 ( 
    .A ( SYNOPSYS_UNCONNECTED_3187 ) , .Y ( SYNOPSYS_UNCONNECTED_3188 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5222153512_5244953740 ( 
    .A ( SYNOPSYS_UNCONNECTED_3189 ) , .Y ( SYNOPSYS_UNCONNECTED_3190 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5217353464_5245053741 ( 
    .A ( SYNOPSYS_UNCONNECTED_3191 ) , .Y ( SYNOPSYS_UNCONNECTED_3192 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5211653407_5245153742 ( 
    .A ( SYNOPSYS_UNCONNECTED_3193 ) , .Y ( SYNOPSYS_UNCONNECTED_3194 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5221553506_5245253743 ( 
    .A ( SYNOPSYS_UNCONNECTED_3195 ) , .Y ( SYNOPSYS_UNCONNECTED_3196 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5202953320_5245453745 ( 
    .A ( SYNOPSYS_UNCONNECTED_3197 ) , .Y ( SYNOPSYS_UNCONNECTED_3198 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5207853369_5245553746 ( 
    .A ( SYNOPSYS_UNCONNECTED_3199 ) , .Y ( SYNOPSYS_UNCONNECTED_3200 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5212653417_5245653747 ( 
    .A ( SYNOPSYS_UNCONNECTED_3201 ) , .Y ( SYNOPSYS_UNCONNECTED_3202 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5202353314_5245753748 ( 
    .A ( SYNOPSYS_UNCONNECTED_3203 ) , .Y ( SYNOPSYS_UNCONNECTED_3204 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5212453415_5245853749 ( 
    .A ( SYNOPSYS_UNCONNECTED_3205 ) , .Y ( SYNOPSYS_UNCONNECTED_3206 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5192953220_5245953750 ( 
    .A ( SYNOPSYS_UNCONNECTED_3207 ) , .Y ( SYNOPSYS_UNCONNECTED_3208 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5202453315_5246053751 ( 
    .A ( SYNOPSYS_UNCONNECTED_3209 ) , .Y ( SYNOPSYS_UNCONNECTED_3210 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5197653267_5246153752 ( 
    .A ( SYNOPSYS_UNCONNECTED_3211 ) , .Y ( p_abuf18 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5192253213_5246253753 ( 
    .A ( SYNOPSYS_UNCONNECTED_3212 ) , .Y ( SYNOPSYS_UNCONNECTED_3213 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5222253513_5246453755 ( 
    .A ( SYNOPSYS_UNCONNECTED_3214 ) , .Y ( p_abuf41 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5228053571_5246553756 ( 
    .A ( SYNOPSYS_UNCONNECTED_3215 ) , .Y ( SYNOPSYS_UNCONNECTED_3216 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5223553526_5246653757 ( 
    .A ( SYNOPSYS_UNCONNECTED_3217 ) , .Y ( SYNOPSYS_UNCONNECTED_3218 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5230753598_5246753758 ( 
    .A ( SYNOPSYS_UNCONNECTED_3219 ) , .Y ( SYNOPSYS_UNCONNECTED_3220 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5193453225_5246853759 ( 
    .A ( SYNOPSYS_UNCONNECTED_3221 ) , .Y ( SYNOPSYS_UNCONNECTED_3222 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5197953270_5246953760 ( 
    .A ( SYNOPSYS_UNCONNECTED_3223 ) , .Y ( SYNOPSYS_UNCONNECTED_3224 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5188953180_5247053761 ( 
    .A ( SYNOPSYS_UNCONNECTED_3225 ) , .Y ( SYNOPSYS_UNCONNECTED_3226 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5197553266_5247153762 ( 
    .A ( SYNOPSYS_UNCONNECTED_3227 ) , .Y ( SYNOPSYS_UNCONNECTED_3228 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5188653177_5247253763 ( 
    .A ( SYNOPSYS_UNCONNECTED_3229 ) , .Y ( SYNOPSYS_UNCONNECTED_3230 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5213553426_5247453765 ( 
    .A ( SYNOPSYS_UNCONNECTED_3231 ) , .Y ( SYNOPSYS_UNCONNECTED_3232 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5213353424_5247553766 ( 
    .A ( SYNOPSYS_UNCONNECTED_3233 ) , .Y ( SYNOPSYS_UNCONNECTED_3234 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5218053471_5247653767 ( 
    .A ( SYNOPSYS_UNCONNECTED_3235 ) , .Y ( SYNOPSYS_UNCONNECTED_3236 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5222853519_5247753768 ( 
    .A ( SYNOPSYS_UNCONNECTED_3237 ) , .Y ( SYNOPSYS_UNCONNECTED_3238 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5202153312_5247853769 ( 
    .A ( SYNOPSYS_UNCONNECTED_3239 ) , .Y ( SYNOPSYS_UNCONNECTED_3240 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5212053411_5247953770 ( 
    .A ( SYNOPSYS_UNCONNECTED_3241 ) , .Y ( SYNOPSYS_UNCONNECTED_3242 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5207253363_5248053771 ( 
    .A ( SYNOPSYS_UNCONNECTED_3243 ) , .Y ( SYNOPSYS_UNCONNECTED_3244 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5201453305_5248153772 ( 
    .A ( SYNOPSYS_UNCONNECTED_3245 ) , .Y ( SYNOPSYS_UNCONNECTED_3246 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5211353404_5248253773 ( 
    .A ( SYNOPSYS_UNCONNECTED_3247 ) , .Y ( SYNOPSYS_UNCONNECTED_3248 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5198153272_5248353774 ( 
    .A ( SYNOPSYS_UNCONNECTED_3249 ) , .Y ( SYNOPSYS_UNCONNECTED_3250 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5189153182_5248453775 ( 
    .A ( SYNOPSYS_UNCONNECTED_3251 ) , .Y ( SYNOPSYS_UNCONNECTED_3252 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5197853269_5248553776 ( 
    .A ( SYNOPSYS_UNCONNECTED_3253 ) , .Y ( p_abuf16 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5217453465_5248653777 ( 
    .A ( SYNOPSYS_UNCONNECTED_3254 ) , .Y ( SYNOPSYS_UNCONNECTED_3255 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5207153362_5248753778 ( 
    .A ( SYNOPSYS_UNCONNECTED_3256 ) , .Y ( SYNOPSYS_UNCONNECTED_3257 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5217253463_5248853779 ( 
    .A ( SYNOPSYS_UNCONNECTED_3258 ) , .Y ( SYNOPSYS_UNCONNECTED_3259 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5211953410_5248953780 ( 
    .A ( SYNOPSYS_UNCONNECTED_3260 ) , .Y ( SYNOPSYS_UNCONNECTED_3261 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5226953560_5249153782 ( 
    .A ( SYNOPSYS_UNCONNECTED_3262 ) , .Y ( SYNOPSYS_UNCONNECTED_3263 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5226653557_5249353784 ( 
    .A ( SYNOPSYS_UNCONNECTED_3264 ) , .Y ( SYNOPSYS_UNCONNECTED_3265 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5226353554_5249453785 ( 
    .A ( SYNOPSYS_UNCONNECTED_3266 ) , .Y ( SYNOPSYS_UNCONNECTED_3267 ) ) ;
sky130_fd_sc_hd__inv_12 cts_inv_5208553376_5249553786 ( 
    .A ( SYNOPSYS_UNCONNECTED_3268 ) , .Y ( SYNOPSYS_UNCONNECTED_3269 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5203753328_5249653787 ( 
    .A ( SYNOPSYS_UNCONNECTED_3270 ) , .Y ( SYNOPSYS_UNCONNECTED_3271 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5203553326_5249753788 ( 
    .A ( SYNOPSYS_UNCONNECTED_3272 ) , .Y ( SYNOPSYS_UNCONNECTED_3273 ) ) ;
sky130_fd_sc_hd__inv_12 cts_inv_5198753278_5249853789 ( 
    .A ( SYNOPSYS_UNCONNECTED_3274 ) , .Y ( SYNOPSYS_UNCONNECTED_3275 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5208053371_5249953790 ( 
    .A ( SYNOPSYS_UNCONNECTED_3276 ) , .Y ( SYNOPSYS_UNCONNECTED_3277 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5208153372_5250053791 ( 
    .A ( SYNOPSYS_UNCONNECTED_3278 ) , .Y ( SYNOPSYS_UNCONNECTED_3279 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5232153612_5250153792 ( 
    .A ( SYNOPSYS_UNCONNECTED_3280 ) , .Y ( SYNOPSYS_UNCONNECTED_3281 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5234053631_5250253793 ( 
    .A ( SYNOPSYS_UNCONNECTED_3282 ) , .Y ( SYNOPSYS_UNCONNECTED_3283 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5230253593_5250353794 ( 
    .A ( SYNOPSYS_UNCONNECTED_3284 ) , .Y ( SYNOPSYS_UNCONNECTED_3285 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5210153392_5250453795 ( 
    .A ( SYNOPSYS_UNCONNECTED_3286 ) , .Y ( SYNOPSYS_UNCONNECTED_3287 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5209153382_5250553796 ( 
    .A ( SYNOPSYS_UNCONNECTED_3288 ) , .Y ( SYNOPSYS_UNCONNECTED_3289 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5207453365_5250653797 ( 
    .A ( SYNOPSYS_UNCONNECTED_3290 ) , .Y ( SYNOPSYS_UNCONNECTED_3291 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5202653317_5250753798 ( 
    .A ( SYNOPSYS_UNCONNECTED_3292 ) , .Y ( SYNOPSYS_UNCONNECTED_3293 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5207653367_5250853799 ( 
    .A ( SYNOPSYS_UNCONNECTED_3294 ) , .Y ( SYNOPSYS_UNCONNECTED_3295 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5200553296_5250953800 ( 
    .A ( SYNOPSYS_UNCONNECTED_3296 ) , .Y ( p_abuf11 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5199553286_5251053801 ( 
    .A ( SYNOPSYS_UNCONNECTED_3297 ) , .Y ( SYNOPSYS_UNCONNECTED_3298 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5198053271_5251253803 ( 
    .A ( SYNOPSYS_UNCONNECTED_3299 ) , .Y ( SYNOPSYS_UNCONNECTED_3300 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5202853319_5251353804 ( 
    .A ( SYNOPSYS_UNCONNECTED_3301 ) , .Y ( SYNOPSYS_UNCONNECTED_3302 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5223353524_5251453805 ( 
    .A ( SYNOPSYS_UNCONNECTED_3303 ) , .Y ( SYNOPSYS_UNCONNECTED_3304 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5231453605_5251553806 ( 
    .A ( SYNOPSYS_UNCONNECTED_3305 ) , .Y ( SYNOPSYS_UNCONNECTED_3306 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5208853379_5251753808 ( 
    .A ( SYNOPSYS_UNCONNECTED_3307 ) , .Y ( SYNOPSYS_UNCONNECTED_3308 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5223153522_5251853809 ( 
    .A ( SYNOPSYS_UNCONNECTED_3309 ) , .Y ( p_abuf42 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5227653567_5251953810 ( 
    .A ( SYNOPSYS_UNCONNECTED_3310 ) , .Y ( SYNOPSYS_UNCONNECTED_3311 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5222553516_5252053811 ( 
    .A ( SYNOPSYS_UNCONNECTED_3312 ) , .Y ( SYNOPSYS_UNCONNECTED_3313 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5223953530_5252153812 ( 
    .A ( SYNOPSYS_UNCONNECTED_3314 ) , .Y ( SYNOPSYS_UNCONNECTED_3315 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5226753558_5252253813 ( 
    .A ( SYNOPSYS_UNCONNECTED_3316 ) , .Y ( SYNOPSYS_UNCONNECTED_3317 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5220953500_5252353814 ( 
    .A ( SYNOPSYS_UNCONNECTED_3318 ) , .Y ( SYNOPSYS_UNCONNECTED_3319 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5230953600_5252453815 ( 
    .A ( SYNOPSYS_UNCONNECTED_3320 ) , .Y ( SYNOPSYS_UNCONNECTED_3321 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5231753608_5252553816 ( 
    .A ( SYNOPSYS_UNCONNECTED_3322 ) , .Y ( SYNOPSYS_UNCONNECTED_3323 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5233853629_5252653817 ( 
    .A ( SYNOPSYS_UNCONNECTED_3324 ) , .Y ( SYNOPSYS_UNCONNECTED_3325 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5212253413_5252753818 ( 
    .A ( SYNOPSYS_UNCONNECTED_3326 ) , .Y ( SYNOPSYS_UNCONNECTED_3327 ) ) ;
sky130_fd_sc_hd__inv_12 cts_inv_5218653477_5252853819 ( 
    .A ( SYNOPSYS_UNCONNECTED_3328 ) , .Y ( SYNOPSYS_UNCONNECTED_3329 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5227753568_5252953820 ( 
    .A ( SYNOPSYS_UNCONNECTED_3330 ) , .Y ( SYNOPSYS_UNCONNECTED_3331 ) ) ;
sky130_fd_sc_hd__inv_12 cts_inv_5223253523_5253053821 ( 
    .A ( SYNOPSYS_UNCONNECTED_3332 ) , .Y ( SYNOPSYS_UNCONNECTED_3333 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5203953330_5253153822 ( 
    .A ( SYNOPSYS_UNCONNECTED_3334 ) , .Y ( SYNOPSYS_UNCONNECTED_3335 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5208753378_5253253823 ( 
    .A ( SYNOPSYS_UNCONNECTED_3336 ) , .Y ( SYNOPSYS_UNCONNECTED_3337 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5203653327_5253353824 ( 
    .A ( SYNOPSYS_UNCONNECTED_3338 ) , .Y ( p_abuf27 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5213253423_5253453825 ( 
    .A ( SYNOPSYS_UNCONNECTED_3339 ) , .Y ( SYNOPSYS_UNCONNECTED_3340 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5204353334_5253553826 ( 
    .A ( SYNOPSYS_UNCONNECTED_3341 ) , .Y ( SYNOPSYS_UNCONNECTED_3342 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5227853569_5253653827 ( 
    .A ( SYNOPSYS_UNCONNECTED_3343 ) , .Y ( SYNOPSYS_UNCONNECTED_3344 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5227353564_5253753828 ( 
    .A ( SYNOPSYS_UNCONNECTED_3345 ) , .Y ( SYNOPSYS_UNCONNECTED_3346 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5189853189_5253853829 ( 
    .A ( SYNOPSYS_UNCONNECTED_3347 ) , .Y ( SYNOPSYS_UNCONNECTED_3348 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5209353384_5253953830 ( 
    .A ( SYNOPSYS_UNCONNECTED_3349 ) , .Y ( SYNOPSYS_UNCONNECTED_3350 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5211753408_5254053831 ( 
    .A ( SYNOPSYS_UNCONNECTED_3351 ) , .Y ( SYNOPSYS_UNCONNECTED_3352 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5216853459_5254153832 ( 
    .A ( SYNOPSYS_UNCONNECTED_3353 ) , .Y ( SYNOPSYS_UNCONNECTED_3354 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5216153452_5254253833 ( 
    .A ( SYNOPSYS_UNCONNECTED_3355 ) , .Y ( p_abuf33 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5206553356_5254353834 ( 
    .A ( SYNOPSYS_UNCONNECTED_3356 ) , .Y ( SYNOPSYS_UNCONNECTED_3357 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5199753288_5254453835 ( 
    .A ( SYNOPSYS_UNCONNECTED_3358 ) , .Y ( SYNOPSYS_UNCONNECTED_3359 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5196653257_5254553836 ( 
    .A ( SYNOPSYS_UNCONNECTED_3360 ) , .Y ( SYNOPSYS_UNCONNECTED_3361 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5196953260_5254653837 ( 
    .A ( SYNOPSYS_UNCONNECTED_3362 ) , .Y ( p_abuf17 ) ) ;
sky130_fd_sc_hd__inv_12 cts_inv_5229753588_5254853839 ( 
    .A ( SYNOPSYS_UNCONNECTED_3363 ) , .Y ( p_abuf44 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5214753438_5254953840 ( 
    .A ( SYNOPSYS_UNCONNECTED_3364 ) , .Y ( p_abuf31 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5207553366_5255053841 ( 
    .A ( SYNOPSYS_UNCONNECTED_3365 ) , .Y ( SYNOPSYS_UNCONNECTED_3366 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5196753258_5255253843 ( 
    .A ( SYNOPSYS_UNCONNECTED_3367 ) , .Y ( p_abuf12 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5194753238_5255353844 ( 
    .A ( SYNOPSYS_UNCONNECTED_3368 ) , .Y ( p_abuf13 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5199053281_5255453845 ( 
    .A ( SYNOPSYS_UNCONNECTED_3369 ) , .Y ( SYNOPSYS_UNCONNECTED_3370 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5211153402_5255653847 ( 
    .A ( SYNOPSYS_UNCONNECTED_3371 ) , .Y ( SYNOPSYS_UNCONNECTED_3372 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5213753428_5255753848 ( 
    .A ( SYNOPSYS_UNCONNECTED_3373 ) , .Y ( p_abuf32 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5208453375_5255853849 ( 
    .A ( SYNOPSYS_UNCONNECTED_3374 ) , .Y ( SYNOPSYS_UNCONNECTED_3375 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5218453475_5255953850 ( 
    .A ( SYNOPSYS_UNCONNECTED_3376 ) , .Y ( SYNOPSYS_UNCONNECTED_3377 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5201253303_5256053851 ( 
    .A ( SYNOPSYS_UNCONNECTED_3378 ) , .Y ( p_abuf21 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5209053381_5256253853 ( 
    .A ( SYNOPSYS_UNCONNECTED_3379 ) , .Y ( SYNOPSYS_UNCONNECTED_3380 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5199153282_5256353854 ( 
    .A ( SYNOPSYS_UNCONNECTED_3381 ) , .Y ( SYNOPSYS_UNCONNECTED_3382 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5205653347_5256453855 ( 
    .A ( SYNOPSYS_UNCONNECTED_3383 ) , .Y ( SYNOPSYS_UNCONNECTED_3384 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5217753468_5256553856 ( 
    .A ( SYNOPSYS_UNCONNECTED_3385 ) , .Y ( SYNOPSYS_UNCONNECTED_3386 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5203253323_5256653857 ( 
    .A ( SYNOPSYS_UNCONNECTED_3387 ) , .Y ( SYNOPSYS_UNCONNECTED_3388 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5221653507_5256753858 ( 
    .A ( SYNOPSYS_UNCONNECTED_3389 ) , .Y ( SYNOPSYS_UNCONNECTED_3390 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5215853449_5256853859 ( 
    .A ( SYNOPSYS_UNCONNECTED_3391 ) , .Y ( SYNOPSYS_UNCONNECTED_3392 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5226053551_5256953860 ( 
    .A ( SYNOPSYS_UNCONNECTED_3393 ) , .Y ( SYNOPSYS_UNCONNECTED_3394 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5233253623_5257053861 ( 
    .A ( SYNOPSYS_UNCONNECTED_3395 ) , .Y ( SYNOPSYS_UNCONNECTED_3396 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5233053621_5257153862 ( 
    .A ( SYNOPSYS_UNCONNECTED_3397 ) , .Y ( SYNOPSYS_UNCONNECTED_3398 ) ) ;
sky130_fd_sc_hd__inv_12 cts_inv_5199453285_5257253863 ( 
    .A ( SYNOPSYS_UNCONNECTED_3399 ) , .Y ( SYNOPSYS_UNCONNECTED_3400 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5194653237_5257353864 ( 
    .A ( SYNOPSYS_UNCONNECTED_3401 ) , .Y ( SYNOPSYS_UNCONNECTED_3402 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5199253283_5257453865 ( 
    .A ( SYNOPSYS_UNCONNECTED_3403 ) , .Y ( SYNOPSYS_UNCONNECTED_3404 ) ) ;
sky130_fd_sc_hd__clkinv_8 cts_inv_5196453255_5257553866 ( 
    .A ( SYNOPSYS_UNCONNECTED_3405 ) , .Y ( SYNOPSYS_UNCONNECTED_3406 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5192053211_5257653867 ( 
    .A ( SYNOPSYS_UNCONNECTED_3407 ) , .Y ( SYNOPSYS_UNCONNECTED_3408 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5204253333_5257753868 ( 
    .A ( SYNOPSYS_UNCONNECTED_3409 ) , .Y ( SYNOPSYS_UNCONNECTED_3410 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5190553196_5257853869 ( 
    .A ( SYNOPSYS_UNCONNECTED_3411 ) , .Y ( SYNOPSYS_UNCONNECTED_3412 ) ) ;
sky130_fd_sc_hd__inv_12 cts_inv_5225253543_5258053871 ( 
    .A ( SYNOPSYS_UNCONNECTED_3413 ) , .Y ( SYNOPSYS_UNCONNECTED_3414 ) ) ;
sky130_fd_sc_hd__clkinv_8 cts_inv_5220153492_5258153872 ( 
    .A ( SYNOPSYS_UNCONNECTED_3415 ) , .Y ( SYNOPSYS_UNCONNECTED_3416 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5231553606_5258253873 ( 
    .A ( SYNOPSYS_UNCONNECTED_3417 ) , .Y ( SYNOPSYS_UNCONNECTED_3418 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5218153472_5258353874 ( 
    .A ( SYNOPSYS_UNCONNECTED_3419 ) , .Y ( SYNOPSYS_UNCONNECTED_3420 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5231253603_5258453875 ( 
    .A ( SYNOPSYS_UNCONNECTED_3421 ) , .Y ( SYNOPSYS_UNCONNECTED_3422 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5219353484_5258553876 ( 
    .A ( SYNOPSYS_UNCONNECTED_3423 ) , .Y ( SYNOPSYS_UNCONNECTED_3424 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5214353434_5258653877 ( 
    .A ( SYNOPSYS_UNCONNECTED_3425 ) , .Y ( SYNOPSYS_UNCONNECTED_3426 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5221253503_5258753878 ( 
    .A ( SYNOPSYS_UNCONNECTED_3427 ) , .Y ( SYNOPSYS_UNCONNECTED_3428 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5216753458_5258853879 ( 
    .A ( SYNOPSYS_UNCONNECTED_3429 ) , .Y ( p_abuf36 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5200353294_5258953880 ( 
    .A ( SYNOPSYS_UNCONNECTED_3430 ) , .Y ( SYNOPSYS_UNCONNECTED_3431 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5192853219_5259053881 ( 
    .A ( SYNOPSYS_UNCONNECTED_3432 ) , .Y ( SYNOPSYS_UNCONNECTED_3433 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5193153222_5259153882 ( 
    .A ( SYNOPSYS_UNCONNECTED_3434 ) , .Y ( SYNOPSYS_UNCONNECTED_3435 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5228853579_5259253883 ( 
    .A ( SYNOPSYS_UNCONNECTED_3436 ) , .Y ( SYNOPSYS_UNCONNECTED_3437 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5224353534_5259353884 ( 
    .A ( SYNOPSYS_UNCONNECTED_3438 ) , .Y ( p_abuf43 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5230553596_5259453885 ( 
    .A ( SYNOPSYS_UNCONNECTED_3439 ) , .Y ( SYNOPSYS_UNCONNECTED_3440 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5226853559_5259553886 ( 
    .A ( SYNOPSYS_UNCONNECTED_3441 ) , .Y ( SYNOPSYS_UNCONNECTED_3442 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5220453495_5259653887 ( 
    .A ( SYNOPSYS_UNCONNECTED_3443 ) , .Y ( SYNOPSYS_UNCONNECTED_3444 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5215653447_5259753888 ( 
    .A ( SYNOPSYS_UNCONNECTED_3445 ) , .Y ( SYNOPSYS_UNCONNECTED_3446 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5223453525_5259853889 ( 
    .A ( SYNOPSYS_UNCONNECTED_3447 ) , .Y ( p_abuf40 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5212953420_5259953890 ( 
    .A ( SYNOPSYS_UNCONNECTED_3448 ) , .Y ( SYNOPSYS_UNCONNECTED_3449 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5204753338_5260053891 ( 
    .A ( SYNOPSYS_UNCONNECTED_3450 ) , .Y ( SYNOPSYS_UNCONNECTED_3451 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5202753318_5260153892 ( 
    .A ( SYNOPSYS_UNCONNECTED_3452 ) , .Y ( SYNOPSYS_UNCONNECTED_3453 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5195253243_5260353894 ( 
    .A ( SYNOPSYS_UNCONNECTED_3454 ) , .Y ( p_abuf15 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5199953290_5260453895 ( 
    .A ( SYNOPSYS_UNCONNECTED_3455 ) , .Y ( p_abuf9 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5190853199_5260553896 ( 
    .A ( SYNOPSYS_UNCONNECTED_3456 ) , .Y ( SYNOPSYS_UNCONNECTED_3457 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5205153342_5260653897 ( 
    .A ( SYNOPSYS_UNCONNECTED_3458 ) , .Y ( p_abuf29 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5200153292_5260753898 ( 
    .A ( SYNOPSYS_UNCONNECTED_3459 ) , .Y ( SYNOPSYS_UNCONNECTED_3460 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5209953390_5260853899 ( 
    .A ( SYNOPSYS_UNCONNECTED_3461 ) , .Y ( p_abuf30 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5229353584_5260953900 ( 
    .A ( SYNOPSYS_UNCONNECTED_3462 ) , .Y ( SYNOPSYS_UNCONNECTED_3463 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5232853619_5261053901 ( 
    .A ( SYNOPSYS_UNCONNECTED_3464 ) , .Y ( SYNOPSYS_UNCONNECTED_3465 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5232753618_5261153902 ( 
    .A ( SYNOPSYS_UNCONNECTED_3466 ) , .Y ( SYNOPSYS_UNCONNECTED_3467 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5219153482_5261253903 ( 
    .A ( SYNOPSYS_UNCONNECTED_3468 ) , .Y ( SYNOPSYS_UNCONNECTED_3469 ) ) ;
sky130_fd_sc_hd__clkinv_8 cts_inv_5211053401_5261353904 ( 
    .A ( SYNOPSYS_UNCONNECTED_3470 ) , .Y ( SYNOPSYS_UNCONNECTED_3471 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5215253443_5261453905 ( 
    .A ( SYNOPSYS_UNCONNECTED_3472 ) , .Y ( SYNOPSYS_UNCONNECTED_3473 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5225053541_5261553906 ( 
    .A ( SYNOPSYS_UNCONNECTED_3474 ) , .Y ( SYNOPSYS_UNCONNECTED_3475 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5213153422_5261653907 ( 
    .A ( SYNOPSYS_UNCONNECTED_3476 ) , .Y ( SYNOPSYS_UNCONNECTED_3477 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5196053251_5261753908 ( 
    .A ( SYNOPSYS_UNCONNECTED_3478 ) , .Y ( SYNOPSYS_UNCONNECTED_3479 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5196153252_5261853909 ( 
    .A ( SYNOPSYS_UNCONNECTED_3480 ) , .Y ( SYNOPSYS_UNCONNECTED_3481 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5205753348_5261953910 ( 
    .A ( SYNOPSYS_UNCONNECTED_3482 ) , .Y ( SYNOPSYS_UNCONNECTED_3483 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5194353234_5262053911 ( 
    .A ( SYNOPSYS_UNCONNECTED_3484 ) , .Y ( SYNOPSYS_UNCONNECTED_3485 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5191753208_5262153912 ( 
    .A ( SYNOPSYS_UNCONNECTED_3486 ) , .Y ( SYNOPSYS_UNCONNECTED_3487 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5191653207_5262253913 ( 
    .A ( SYNOPSYS_UNCONNECTED_3488 ) , .Y ( SYNOPSYS_UNCONNECTED_3489 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5200953300_5262353914 ( 
    .A ( SYNOPSYS_UNCONNECTED_3490 ) , .Y ( SYNOPSYS_UNCONNECTED_3491 ) ) ;
sky130_fd_sc_hd__clkinv_8 cts_inv_5190153192_5262453915 ( 
    .A ( SYNOPSYS_UNCONNECTED_3492 ) , .Y ( SYNOPSYS_UNCONNECTED_3493 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5209253383_5262553916 ( 
    .A ( SYNOPSYS_UNCONNECTED_3494 ) , .Y ( SYNOPSYS_UNCONNECTED_3495 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5204453335_5262653917 ( 
    .A ( SYNOPSYS_UNCONNECTED_3496 ) , .Y ( SYNOPSYS_UNCONNECTED_3497 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5219553486_5262753918 ( 
    .A ( SYNOPSYS_UNCONNECTED_3498 ) , .Y ( SYNOPSYS_UNCONNECTED_3499 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5209753388_5262853919 ( 
    .A ( SYNOPSYS_UNCONNECTED_3500 ) , .Y ( SYNOPSYS_UNCONNECTED_3501 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5209553386_5262953920 ( 
    .A ( SYNOPSYS_UNCONNECTED_3502 ) , .Y ( SYNOPSYS_UNCONNECTED_3503 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5229853589_5263053921 ( 
    .A ( SYNOPSYS_UNCONNECTED_3504 ) , .Y ( p_abuf45 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5232353614_5263153922 ( 
    .A ( SYNOPSYS_UNCONNECTED_3505 ) , .Y ( SYNOPSYS_UNCONNECTED_3506 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5225853549_5263253923 ( 
    .A ( SYNOPSYS_UNCONNECTED_3507 ) , .Y ( SYNOPSYS_UNCONNECTED_3508 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5216253453_5263353924 ( 
    .A ( SYNOPSYS_UNCONNECTED_3509 ) , .Y ( p_abuf35 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5221053501_5263453925 ( 
    .A ( SYNOPSYS_UNCONNECTED_3510 ) , .Y ( SYNOPSYS_UNCONNECTED_3511 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5206653357_5263553926 ( 
    .A ( SYNOPSYS_UNCONNECTED_3512 ) , .Y ( SYNOPSYS_UNCONNECTED_3513 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5211453405_5263653927 ( 
    .A ( SYNOPSYS_UNCONNECTED_3514 ) , .Y ( SYNOPSYS_UNCONNECTED_3515 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5214953440_5263753928 ( 
    .A ( SYNOPSYS_UNCONNECTED_3516 ) , .Y ( SYNOPSYS_UNCONNECTED_3517 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5191053201_5263853929 ( 
    .A ( SYNOPSYS_UNCONNECTED_3518 ) , .Y ( SYNOPSYS_UNCONNECTED_3519 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5230853599_5263953930 ( 
    .A ( SYNOPSYS_UNCONNECTED_3520 ) , .Y ( SYNOPSYS_UNCONNECTED_3521 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5235053641_5264153932 ( 
    .A ( SYNOPSYS_UNCONNECTED_3522 ) , .Y ( SYNOPSYS_UNCONNECTED_3523 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5228453575_5264253933 ( 
    .A ( SYNOPSYS_UNCONNECTED_3524 ) , .Y ( SYNOPSYS_UNCONNECTED_3525 ) ) ;
sky130_fd_sc_hd__clkinv_8 cts_inv_5234653637_5264353934 ( 
    .A ( SYNOPSYS_UNCONNECTED_3526 ) , .Y ( SYNOPSYS_UNCONNECTED_3527 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5201553306_5264453935 ( 
    .A ( SYNOPSYS_UNCONNECTED_3528 ) , .Y ( SYNOPSYS_UNCONNECTED_3529 ) ) ;
sky130_fd_sc_hd__inv_6 cts_inv_5206053351_5264553936 ( 
    .A ( SYNOPSYS_UNCONNECTED_3530 ) , .Y ( SYNOPSYS_UNCONNECTED_3531 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5215953450_5264653937 ( 
    .A ( SYNOPSYS_UNCONNECTED_3532 ) , .Y ( SYNOPSYS_UNCONNECTED_3533 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5229253583_5264753938 ( 
    .A ( SYNOPSYS_UNCONNECTED_3534 ) , .Y ( SYNOPSYS_UNCONNECTED_3535 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5225453545_5264853939 ( 
    .A ( SYNOPSYS_UNCONNECTED_3536 ) , .Y ( SYNOPSYS_UNCONNECTED_3537 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5224953540_5264953940 ( 
    .A ( SYNOPSYS_UNCONNECTED_3538 ) , .Y ( SYNOPSYS_UNCONNECTED_3539 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5214053431_5265053941 ( 
    .A ( SYNOPSYS_UNCONNECTED_3540 ) , .Y ( SYNOPSYS_UNCONNECTED_3541 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5229553586_5265353944 ( 
    .A ( SYNOPSYS_UNCONNECTED_3542 ) , .Y ( SYNOPSYS_UNCONNECTED_3543 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5201853309_5265753948 ( 
    .A ( SYNOPSYS_UNCONNECTED_3544 ) , .Y ( SYNOPSYS_UNCONNECTED_3545 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5238153672_5266053951 ( 
    .A ( SYNOPSYS_UNCONNECTED_3546 ) , .Y ( SYNOPSYS_UNCONNECTED_3547 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5210853399_5266253953 ( 
    .A ( SYNOPSYS_UNCONNECTED_3548 ) , .Y ( SYNOPSYS_UNCONNECTED_3549 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5219753488_5266353954 ( 
    .A ( SYNOPSYS_UNCONNECTED_3550 ) , .Y ( SYNOPSYS_UNCONNECTED_3551 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5236853659_5266453955 ( 
    .A ( SYNOPSYS_UNCONNECTED_3552 ) , .Y ( SYNOPSYS_UNCONNECTED_3553 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5195653247_5266553956 ( 
    .A ( SYNOPSYS_UNCONNECTED_3554 ) , .Y ( SYNOPSYS_UNCONNECTED_3555 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5234753638_5266653957 ( 
    .A ( SYNOPSYS_UNCONNECTED_3556 ) , .Y ( SYNOPSYS_UNCONNECTED_3557 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5228253573_5266853959 ( 
    .A ( SYNOPSYS_UNCONNECTED_3558 ) , .Y ( SYNOPSYS_UNCONNECTED_3559 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5231853609_5266953960 ( 
    .A ( SYNOPSYS_UNCONNECTED_3560 ) , .Y ( SYNOPSYS_UNCONNECTED_3561 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5214553436_5267053961 ( 
    .A ( SYNOPSYS_UNCONNECTED_3562 ) , .Y ( SYNOPSYS_UNCONNECTED_3563 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5228153572_5267353964 ( 
    .A ( SYNOPSYS_UNCONNECTED_3564 ) , .Y ( SYNOPSYS_UNCONNECTED_3565 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5223753528_5267453965 ( 
    .A ( SYNOPSYS_UNCONNECTED_3566 ) , .Y ( SYNOPSYS_UNCONNECTED_3567 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5204553336_5267753968 ( 
    .A ( SYNOPSYS_UNCONNECTED_3568 ) , .Y ( p_abuf24 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5226153552_5267853969 ( 
    .A ( SYNOPSYS_UNCONNECTED_3569 ) , .Y ( SYNOPSYS_UNCONNECTED_3570 ) ) ;
sky130_fd_sc_hd__clkinv_16 cts_inv_5230353594_5268053971 ( 
    .A ( SYNOPSYS_UNCONNECTED_3571 ) , .Y ( p_abuf46 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5237853669_5268253973 ( 
    .A ( SYNOPSYS_UNCONNECTED_3572 ) , .Y ( SYNOPSYS_UNCONNECTED_3573 ) ) ;
sky130_fd_sc_hd__inv_8 cts_inv_5236353654_5268353974 ( 
    .A ( SYNOPSYS_UNCONNECTED_3574 ) , .Y ( SYNOPSYS_UNCONNECTED_3575 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5375155042 ( .A ( ctsbuf_net_6441562 ) , 
    .Y ( ctsbuf_net_5821500 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5375255043 ( .A ( ctsbuf_net_6501568 ) , 
    .Y ( ctsbuf_net_5831501 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5375355044 ( .A ( ctsbuf_net_6501568 ) , 
    .Y ( ctsbuf_net_5841502 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5375455045 ( .A ( ctsbuf_net_6451563 ) , 
    .Y ( ctsbuf_net_5851503 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5375555046 ( .A ( ctsbuf_net_6441562 ) , 
    .Y ( ctsbuf_net_5861504 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5375655047 ( .A ( ctsbuf_net_6491567 ) , 
    .Y ( ctsbuf_net_5871505 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5375755048 ( .A ( ctsbuf_net_6451563 ) , 
    .Y ( ctsbuf_net_5881506 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5375855049 ( .A ( ctsbuf_net_6541572 ) , 
    .Y ( ctsbuf_net_5891507 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5375955050 ( .A ( ctsbuf_net_6561574 ) , 
    .Y ( ctsbuf_net_5901508 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5376055051 ( .A ( ctsbuf_net_6541572 ) , 
    .Y ( ctsbuf_net_5911509 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5376155052 ( .A ( ctsbuf_net_6531571 ) , 
    .Y ( ctsbuf_net_5921510 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5376255053 ( .A ( ctsbuf_net_6531571 ) , 
    .Y ( ctsbuf_net_5931511 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5376355054 ( .A ( ctsbuf_net_6561574 ) , 
    .Y ( ctsbuf_net_5941512 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5376455055 ( .A ( ctsbuf_net_6461564 ) , 
    .Y ( ctsbuf_net_5951513 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5376555056 ( .A ( ctsbuf_net_6531571 ) , 
    .Y ( ctsbuf_net_5961514 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5376655057 ( .A ( ctsbuf_net_6441562 ) , 
    .Y ( ctsbuf_net_5971515 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5376755058 ( .A ( ctsbuf_net_6451563 ) , 
    .Y ( ctsbuf_net_5981516 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5376855059 ( .A ( ctsbuf_net_6451563 ) , 
    .Y ( ctsbuf_net_5991517 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5376955060 ( .A ( ctsbuf_net_6451563 ) , 
    .Y ( ctsbuf_net_6001518 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5377055061 ( .A ( ctsbuf_net_6461564 ) , 
    .Y ( ctsbuf_net_6011519 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5377155062 ( .A ( ctsbuf_net_6491567 ) , 
    .Y ( ctsbuf_net_6021520 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5377255063 ( .A ( ctsbuf_net_6451563 ) , 
    .Y ( ctsbuf_net_6031521 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5377355064 ( .A ( ctsbuf_net_6461564 ) , 
    .Y ( ctsbuf_net_6041522 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5377455065 ( .A ( ctsbuf_net_6491567 ) , 
    .Y ( ctsbuf_net_6051523 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5377555066 ( .A ( ctsbuf_net_6521570 ) , 
    .Y ( ctsbuf_net_6061524 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5377655067 ( .A ( ctsbuf_net_6521570 ) , 
    .Y ( ctsbuf_net_6071525 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5377755068 ( .A ( ctsbuf_net_6441562 ) , 
    .Y ( ctsbuf_net_6081526 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5377855069 ( .A ( ctsbuf_net_6511569 ) , 
    .Y ( ctsbuf_net_6091527 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5377955070 ( .A ( ctsbuf_net_6471565 ) , 
    .Y ( ctsbuf_net_6101528 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5378055071 ( .A ( ctsbuf_net_6471565 ) , 
    .Y ( ctsbuf_net_6111529 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5378155072 ( .A ( ctsbuf_net_6511569 ) , 
    .Y ( ctsbuf_net_6121530 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5378255073 ( .A ( ctsbuf_net_6531571 ) , 
    .Y ( ctsbuf_net_6131531 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5378355074 ( .A ( ctsbuf_net_6511569 ) , 
    .Y ( ctsbuf_net_6141532 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5378455075 ( .A ( ctsbuf_net_6511569 ) , 
    .Y ( ctsbuf_net_6151533 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5378555076 ( .A ( ctsbuf_net_6551573 ) , 
    .Y ( ctsbuf_net_6161534 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5378655077 ( .A ( ctsbuf_net_6531571 ) , 
    .Y ( ctsbuf_net_6171535 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5378755078 ( .A ( ctsbuf_net_6551573 ) , 
    .Y ( ctsbuf_net_6181536 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5378855079 ( .A ( ctsbuf_net_6481566 ) , 
    .Y ( ctsbuf_net_6191537 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5378955080 ( .A ( ctsbuf_net_6481566 ) , 
    .Y ( ctsbuf_net_6201538 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5379055081 ( .A ( ctsbuf_net_6471565 ) , 
    .Y ( ctsbuf_net_6211539 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5379155082 ( .A ( ctsbuf_net_6481566 ) , 
    .Y ( ctsbuf_net_6221540 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5379255083 ( .A ( ctsbuf_net_6481566 ) , 
    .Y ( ctsbuf_net_6231541 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5379355084 ( .A ( ctsbuf_net_6441562 ) , 
    .Y ( ctsbuf_net_6241542 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5379455085 ( .A ( ctsbuf_net_6551573 ) , 
    .Y ( ctsbuf_net_6251543 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5379555086 ( .A ( ctsbuf_net_6531571 ) , 
    .Y ( ctsbuf_net_6261544 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5379655087 ( .A ( ctsbuf_net_6511569 ) , 
    .Y ( ctsbuf_net_6271545 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5379755088 ( .A ( ctsbuf_net_6511569 ) , 
    .Y ( ctsbuf_net_6281546 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5379855089 ( .A ( ctsbuf_net_6521570 ) , 
    .Y ( ctsbuf_net_6291547 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5379955090 ( .A ( ctsbuf_net_6471565 ) , 
    .Y ( ctsbuf_net_6301548 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5380055091 ( .A ( ctsbuf_net_6471565 ) , 
    .Y ( ctsbuf_net_6311549 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5380155092 ( .A ( ctsbuf_net_6441562 ) , 
    .Y ( ctsbuf_net_6321550 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5380355094 ( .A ( ctsbuf_net_6521570 ) , 
    .Y ( ctsbuf_net_6341552 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5380455095 ( .A ( ctsbuf_net_6441562 ) , 
    .Y ( ctsbuf_net_6351553 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5380555096 ( .A ( ctsbuf_net_6521570 ) , 
    .Y ( ctsbuf_net_6361554 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5380655097 ( .A ( ctsbuf_net_6491567 ) , 
    .Y ( ctsbuf_net_6371555 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5380755098 ( .A ( ctsbuf_net_6541572 ) , 
    .Y ( ctsbuf_net_6381556 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5380855099 ( .A ( ctsbuf_net_6541572 ) , 
    .Y ( ctsbuf_net_6391557 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5380955100 ( .A ( ctsbuf_net_6501568 ) , 
    .Y ( ctsbuf_net_6401558 ) ) ;
sky130_fd_sc_hd__inv_16 cts_inv_5381055101 ( .A ( ctsbuf_net_6541572 ) , 
    .Y ( ctsbuf_net_6411559 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5381155102 ( .A ( ctsbuf_net_6491567 ) , 
    .Y ( ctsbuf_net_6421560 ) ) ;
sky130_fd_sc_hd__inv_12 cts_inv_5381255103 ( .A ( ctsbuf_net_6451563 ) , 
    .Y ( ctsbuf_net_6431561 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5386955160 ( .A ( ctsbuf_net_6581576 ) , 
    .Y ( ctsbuf_net_6441562 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5387055161 ( .A ( ctsbuf_net_6571575 ) , 
    .Y ( ctsbuf_net_6451563 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5387155162 ( .A ( ctsbuf_net_6581576 ) , 
    .Y ( ctsbuf_net_6461564 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5387255163 ( .A ( ctsbuf_net_6591577 ) , 
    .Y ( ctsbuf_net_6471565 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5387355164 ( .A ( ctsbuf_net_6581576 ) , 
    .Y ( ctsbuf_net_6481566 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5387455165 ( .A ( ctsbuf_net_6571575 ) , 
    .Y ( ctsbuf_net_6491567 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5387555166 ( .A ( ctsbuf_net_6571575 ) , 
    .Y ( ctsbuf_net_6501568 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5387655167 ( .A ( ctsbuf_net_6591577 ) , 
    .Y ( ctsbuf_net_6511569 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5387755168 ( .A ( ctsbuf_net_6591577 ) , 
    .Y ( ctsbuf_net_6521570 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5387855169 ( .A ( ctsbuf_net_6601578 ) , 
    .Y ( ctsbuf_net_6531571 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5387955170 ( .A ( ctsbuf_net_6611579 ) , 
    .Y ( ctsbuf_net_6541572 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5388055171 ( .A ( ctsbuf_net_6601578 ) , 
    .Y ( ctsbuf_net_6551573 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5388155172 ( .A ( ctsbuf_net_6611579 ) , 
    .Y ( ctsbuf_net_6561574 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5390155192 ( .A ( ctsbuf_net_6631581 ) , 
    .Y ( ctsbuf_net_6571575 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5390255193 ( .A ( ctsbuf_net_6621580 ) , 
    .Y ( ctsbuf_net_6581576 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5390355194 ( .A ( ctsbuf_net_6621580 ) , 
    .Y ( ctsbuf_net_6591577 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5390455195 ( .A ( ctsbuf_net_6621580 ) , 
    .Y ( ctsbuf_net_6601578 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5390555196 ( .A ( ctsbuf_net_6631581 ) , 
    .Y ( ctsbuf_net_6611579 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5391355204 ( .A ( ctsbuf_net_6641582 ) , 
    .Y ( ctsbuf_net_6621580 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5391455205 ( .A ( ctsbuf_net_6641582 ) , 
    .Y ( ctsbuf_net_6631581 ) ) ;
sky130_fd_sc_hd__clkinvlp_2 cts_inv_5391855209 ( .A ( prog_clk[0] ) , 
    .Y ( ctsbuf_net_6641582 ) ) ;
endmodule


