AurelienUoU ffdcd4bb9c Path correction 2		2019-05-28 11:59:09 -06:00
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ARCH	Path correction 2	2019-05-28 11:59:09 -06:00
Circuits	Add missing Verilog source, Archictecture folder and Testbenches correction	2019-05-13 16:41:35 -06:00
SRC	fixed the bug in mirror node direction	2019-05-27 21:58:21 -06:00
SpiceNetlists	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
VerilogNetlists	Add travis full path to avoid missing sources	2019-05-16 15:51:10 -06:00
.regression_verilog.sh	Add travis full path to avoid missing sources	2019-05-16 15:51:10 -06:00
CMakeLists.txt	Force graphics to false	2019-05-15 15:01:54 -06:00
Makefile	fixed bugs in CMakeLists.txt and Makefile	2019-05-03 23:03:04 -06:00
go_fpga_spice.sh	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
go_fpga_verilog.sh	skip rotating mirror detection which is too time-consuming	2019-05-25 23:41:46 -06:00