OpenFPGA/openfpga_flow
ganeshgore fefba0db59 Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev 2020-11-25 17:29:53 -07:00
..
arch_bitstreams [Architecture] Update external bitstream 2020-09-25 21:30:59 -06:00
benchmarks [Benchmark] Bug fix in the and2_or2 benchmark 2020-09-17 10:35:13 -06:00
docs
fabric_keys [Architecture] Add example fabric key using multiple regions 2020-09-29 14:14:50 -06:00
misc Edits to enable basic run_fpga_flow.py 2020-10-02 10:18:10 -04:00
openfpga_arch Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev 2020-11-25 17:29:53 -07:00
openfpga_cell_library [HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals 2020-11-22 20:53:32 -07:00
openfpga_shell_scripts [Flow] Add example script for behaviorial verilog generation 2020-11-22 21:14:10 -07:00
openfpga_simulation_settings add example simulation setting for openfpga flow 2020-06-11 19:31:15 -06:00
scripts Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev 2020-11-25 17:29:53 -07:00
tasks Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev 2020-11-25 17:29:53 -07:00
tech
vpr_arch [Arch] Add k4 arch using global clock from tile port (with zero fc) 2020-11-10 19:17:34 -07:00
.gitignore