OpenFPGA/libopenfpga/libfpgabitstream/bitstream_example/arch_bitstream_example.xml

<!--
	- Architecture independent bitstream
	- Author: Xifan TANG
	- Organization: University of Utah
	- Date: Sat Jun 20 18:28:19 2020
-->

<bitstream_block name="fpga_top" hierarchy_level="0">
	<bitstream_block name="grid_clb_1_1" hierarchy_level="1">
		<bitstream_block name="logical_tile_clb_mode_clb__0" hierarchy_level="2">
			<bitstream_block name="logical_tile_clb_mode_default__fle_0" hierarchy_level="3">
				<bitstream_block name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0" hierarchy_level="4">
					<bitstream_block name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0" hierarchy_level="5">
						<bitstream_block name="lut4_config_latch_mem" hierarchy_level="6">
							<hierarchy>
								<instance level="0" name="fpga_top"/>
								<instance level="1" name="grid_clb_1_1"/>
								<instance level="2" name="logical_tile_clb_mode_clb__0"/>
								<instance level="3" name="logical_tile_clb_mode_default__fle_0"/>
								<instance level="4" name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0"/>
								<instance level="5" name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0"/>
								<instance level="6" name="lut4_config_latch_mem"/>
							</hierarchy>
							<bitstream>
								<bit memory_port="mem_out[0]" value="0"/>
								<bit memory_port="mem_out[1]" value="0"/>
								<bit memory_port="mem_out[2]" value="0"/>
								<bit memory_port="mem_out[3]" value="0"/>
								<bit memory_port="mem_out[4]" value="0"/>
								<bit memory_port="mem_out[5]" value="0"/>
								<bit memory_port="mem_out[6]" value="0"/>
								<bit memory_port="mem_out[7]" value="0"/>
								<bit memory_port="mem_out[8]" value="0"/>
								<bit memory_port="mem_out[9]" value="0"/>
								<bit memory_port="mem_out[10]" value="0"/>
								<bit memory_port="mem_out[11]" value="0"/>
								<bit memory_port="mem_out[12]" value="0"/>
								<bit memory_port="mem_out[13]" value="0"/>
								<bit memory_port="mem_out[14]" value="0"/>
								<bit memory_port="mem_out[15]" value="0"/>
							</bitstream>
						</bitstream_block>
					</bitstream_block>
					<bitstream_block name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0" hierarchy_level="5">
					</bitstream_block>
					<bitstream_block name="mem_ble4_out_0" hierarchy_level="5">
						<hierarchy>
							<instance level="0" name="fpga_top"/>
							<instance level="1" name="grid_clb_1_1"/>
							<instance level="2" name="logical_tile_clb_mode_clb__0"/>
							<instance level="3" name="logical_tile_clb_mode_default__fle_0"/>
							<instance level="4" name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0"/>
							<instance level="5" name="mem_ble4_out_0"/>
						</hierarchy>
						<output_nets>
							<path id="0" net_name="unmapped"/>
						</output_nets>
						<bitstream path_id="-1">
							<bit memory_port="mem_out[0]" value="0"/>
							<bit memory_port="mem_out[1]" value="0"/>
							<bit memory_port="mem_out[2]" value="1"/>
						</bitstream>
					</bitstream_block>
				</bitstream_block>
			</bitstream_block>
			<bitstream_block name="logical_tile_clb_mode_default__fle_1" hierarchy_level="3">
				<bitstream_block name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0" hierarchy_level="4">
					<bitstream_block name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0" hierarchy_level="5">
						<bitstream_block name="lut4_config_latch_mem" hierarchy_level="6">
							<hierarchy>
								<instance level="0" name="fpga_top"/>
								<instance level="1" name="grid_clb_1_1"/>
								<instance level="2" name="logical_tile_clb_mode_clb__0"/>
								<instance level="3" name="logical_tile_clb_mode_default__fle_1"/>
								<instance level="4" name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0"/>
								<instance level="5" name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0"/>
								<instance level="6" name="lut4_config_latch_mem"/>
							</hierarchy>
							<bitstream>
								<bit memory_port="mem_out[0]" value="0"/>
								<bit memory_port="mem_out[1]" value="0"/>
								<bit memory_port="mem_out[2]" value="0"/>
								<bit memory_port="mem_out[3]" value="0"/>
								<bit memory_port="mem_out[4]" value="0"/>
								<bit memory_port="mem_out[5]" value="0"/>
								<bit memory_port="mem_out[6]" value="0"/>
								<bit memory_port="mem_out[7]" value="0"/>
								<bit memory_port="mem_out[8]" value="0"/>
								<bit memory_port="mem_out[9]" value="0"/>
								<bit memory_port="mem_out[10]" value="0"/>
								<bit memory_port="mem_out[11]" value="0"/>
								<bit memory_port="mem_out[12]" value="0"/>
								<bit memory_port="mem_out[13]" value="0"/>
								<bit memory_port="mem_out[14]" value="0"/>
								<bit memory_port="mem_out[15]" value="0"/>
							</bitstream>
						</bitstream_block>
					</bitstream_block>
					<bitstream_block name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0" hierarchy_level="5">
					</bitstream_block>
					<bitstream_block name="mem_ble4_out_0" hierarchy_level="5">
						<hierarchy>
							<instance level="0" name="fpga_top"/>
							<instance level="1" name="grid_clb_1_1"/>
							<instance level="2" name="logical_tile_clb_mode_clb__0"/>
							<instance level="3" name="logical_tile_clb_mode_default__fle_1"/>
							<instance level="4" name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0"/>
							<instance level="5" name="mem_ble4_out_0"/>
						</hierarchy>
						<output_nets>
							<path id="0" net_name="unmapped"/>
						</output_nets>
						<bitstream path_id="-1">
							<bit memory_port="mem_out[0]" value="0"/>
							<bit memory_port="mem_out[1]" value="0"/>
							<bit memory_port="mem_out[2]" value="1"/>
						</bitstream>
					</bitstream_block>
				</bitstream_block>
			</bitstream_block>
			<bitstream_block name="logical_tile_clb_mode_default__fle_2" hierarchy_level="3">
				<bitstream_block name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0" hierarchy_level="4">
					<bitstream_block name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0" hierarchy_level="5">
						<bitstream_block name="lut4_config_latch_mem" hierarchy_level="6">
							<hierarchy>
								<instance level="0" name="fpga_top"/>
								<instance level="1" name="grid_clb_1_1"/>
								<instance level="2" name="logical_tile_clb_mode_clb__0"/>
								<instance level="3" name="logical_tile_clb_mode_default__fle_2"/>
								<instance level="4" name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0"/>
								<instance level="5" name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0"/>
								<instance level="6" name="lut4_config_latch_mem"/>
							</hierarchy>
							<bitstream>
								<bit memory_port="mem_out[0]" value="0"/>
								<bit memory_port="mem_out[1]" value="0"/>
								<bit memory_port="mem_out[2]" value="0"/>
								<bit memory_port="mem_out[3]" value="0"/>
								<bit memory_port="mem_out[4]" value="0"/>
								<bit memory_port="mem_out[5]" value="0"/>
								<bit memory_port="mem_out[6]" value="0"/>
								<bit memory_port="mem_out[7]" value="0"/>
								<bit memory_port="mem_out[8]" value="0"/>
								<bit memory_port="mem_out[9]" value="0"/>
								<bit memory_port="mem_out[10]" value="0"/>
								<bit memory_port="mem_out[11]" value="0"/>
								<bit memory_port="mem_out[12]" value="0"/>
								<bit memory_port="mem_out[13]" value="0"/>
								<bit memory_port="mem_out[14]" value="0"/>
								<bit memory_port="mem_out[15]" value="0"/>
							</bitstream>
						</bitstream_block>
					</bitstream_block>
					<bitstream_block name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0" hierarchy_level="5">
					</bitstream_block>
					<bitstream_block name="mem_ble4_out_0" hierarchy_level="5">
						<hierarchy>
							<instance level="0" name="fpga_top"/>
							<instance level="1" name="grid_clb_1_1"/>
							<instance level="2" name="logical_tile_clb_mode_clb__0"/>
							<instance level="3" name="logical_tile_clb_mode_default__fle_2"/>
							<instance level="4" name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0"/>
							<instance level="5" name="mem_ble4_out_0"/>
						</hierarchy>
						<output_nets>
							<path id="0" net_name="unmapped"/>
						</output_nets>
						<bitstream path_id="-1">
							<bit memory_port="mem_out[0]" value="0"/>
							<bit memory_port="mem_out[1]" value="0"/>
							<bit memory_port="mem_out[2]" value="1"/>
						</bitstream>
					</bitstream_block>
				</bitstream_block>
			</bitstream_block>
			<bitstream_block name="logical_tile_clb_mode_default__fle_3" hierarchy_level="3">
				<bitstream_block name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0" hierarchy_level="4">
					<bitstream_block name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0" hierarchy_level="5">
						<bitstream_block name="lut4_config_latch_mem" hierarchy_level="6">
							<hierarchy>
								<instance level="0" name="fpga_top"/>
								<instance level="1" name="grid_clb_1_1"/>
								<instance level="2" name="logical_tile_clb_mode_clb__0"/>
								<instance level="3" name="logical_tile_clb_mode_default__fle_3"/>
								<instance level="4" name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0"/>
								<instance level="5" name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0"/>
								<instance level="6" name="lut4_config_latch_mem"/>
							</hierarchy>
							<bitstream>
								<bit memory_port="mem_out[0]" value="0"/>
								<bit memory_port="mem_out[1]" value="0"/>
								<bit memory_port="mem_out[2]" value="0"/>
								<bit memory_port="mem_out[3]" value="0"/>
								<bit memory_port="mem_out[4]" value="0"/>
								<bit memory_port="mem_out[5]" value="0"/>
								<bit memory_port="mem_out[6]" value="0"/>
								<bit memory_port="mem_out[7]" value="0"/>
								<bit memory_port="mem_out[8]" value="0"/>
								<bit memory_port="mem_out[9]" value="0"/>
								<bit memory_port="mem_out[10]" value="0"/>
								<bit memory_port="mem_out[11]" value="0"/>
								<bit memory_port="mem_out[12]" value="0"/>
								<bit memory_port="mem_out[13]" value="0"/>
								<bit memory_port="mem_out[14]" value="0"/>
								<bit memory_port="mem_out[15]" value="0"/>
							</bitstream>
						</bitstream_block>
					</bitstream_block>
					<bitstream_block name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0" hierarchy_level="5">
					</bitstream_block>
					<bitstream_block name="mem_ble4_out_0" hierarchy_level="5">
						<hierarchy>
							<instance level="0" name="fpga_top"/>
							<instance level="1" name="grid_clb_1_1"/>
							<instance level="2" name="logical_tile_clb_mode_clb__0"/>
							<instance level="3" name="logical_tile_clb_mode_default__fle_3"/>
							<instance level="4" name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0"/>
							<instance level="5" name="mem_ble4_out_0"/>
						</hierarchy>
						<output_nets>
							<path id="0" net_name="unmapped"/>
						</output_nets>
						<bitstream path_id="-1">
							<bit memory_port="mem_out[0]" value="0"/>
							<bit memory_port="mem_out[1]" value="0"/>
							<bit memory_port="mem_out[2]" value="1"/>
						</bitstream>
					</bitstream_block>
				</bitstream_block>
			</bitstream_block>
			<bitstream_block name="mem_fle_0_in_0" hierarchy_level="3">
				<hierarchy>
					<instance level="0" name="fpga_top"/>
					<instance level="1" name="grid_clb_1_1"/>
					<instance level="2" name="logical_tile_clb_mode_clb__0"/>
					<instance level="3" name="mem_fle_0_in_0"/>
				</hierarchy>
				<output_nets>
					<path id="0" net_name="unmapped"/>
				</output_nets>
				<bitstream path_id="-1">
					<bit memory_port="mem_out[0]" value="0"/>
					<bit memory_port="mem_out[1]" value="0"/>
					<bit memory_port="mem_out[2]" value="1"/>
					<bit memory_port="mem_out[3]" value="0"/>
					<bit memory_port="mem_out[4]" value="0"/>
					<bit memory_port="mem_out[5]" value="0"/>
					<bit memory_port="mem_out[6]" value="0"/>
					<bit memory_port="mem_out[7]" value="1"/>
				</bitstream>
			</bitstream_block>
			<bitstream_block name="mem_fle_0_in_1" hierarchy_level="3">
				<hierarchy>
					<instance level="0" name="fpga_top"/>
					<instance level="1" name="grid_clb_1_1"/>
					<instance level="2" name="logical_tile_clb_mode_clb__0"/>
					<instance level="3" name="mem_fle_0_in_1"/>
				</hierarchy>
				<output_nets>
					<path id="0" net_name="unmapped"/>
				</output_nets>
				<bitstream path_id="-1">
					<bit memory_port="mem_out[0]" value="0"/>
					<bit memory_port="mem_out[1]" value="0"/>
					<bit memory_port="mem_out[2]" value="1"/>
					<bit memory_port="mem_out[3]" value="0"/>
					<bit memory_port="mem_out[4]" value="0"/>
					<bit memory_port="mem_out[5]" value="0"/>
					<bit memory_port="mem_out[6]" value="0"/>
					<bit memory_port="mem_out[7]" value="1"/>
				</bitstream>
			</bitstream_block>
			<bitstream_block name="mem_fle_0_in_2" hierarchy_level="3">
				<hierarchy>
					<instance level="0" name="fpga_top"/>
					<instance level="1" name="grid_clb_1_1"/>
					<instance level="2" name="logical_tile_clb_mode_clb__0"/>
					<instance level="3" name="mem_fle_0_in_2"/>
				</hierarchy>
				<output_nets>
					<path id="0" net_name="unmapped"/>
				</output_nets>
				<bitstream path_id="-1">
					<bit memory_port="mem_out[0]" value="0"/>
					<bit memory_port="mem_out[1]" value="0"/>
					<bit memory_port="mem_out[2]" value="1"/>
					<bit memory_port="mem_out[3]" value="0"/>
					<bit memory_port="mem_out[4]" value="0"/>
					<bit memory_port="mem_out[5]" value="0"/>
					<bit memory_port="mem_out[6]" value="0"/>
					<bit memory_port="mem_out[7]" value="1"/>
				</bitstream>
			</bitstream_block>
			<bitstream_block name="mem_fle_0_in_3" hierarchy_level="3">
				<hierarchy>
					<instance level="0" name="fpga_top"/>
					<instance level="1" name="grid_clb_1_1"/>
					<instance level="2" name="logical_tile_clb_mode_clb__0"/>
					<instance level="3" name="mem_fle_0_in_3"/>
				</hierarchy>
				<output_nets>
					<path id="0" net_name="unmapped"/>
				</output_nets>
				<bitstream path_id="-1">
					<bit memory_port="mem_out[0]" value="0"/>
					<bit memory_port="mem_out[1]" value="0"/>
					<bit memory_port="mem_out[2]" value="1"/>
					<bit memory_port="mem_out[3]" value="0"/>
					<bit memory_port="mem_out[4]" value="0"/>
					<bit memory_port="mem_out[5]" value="0"/>
					<bit memory_port="mem_out[6]" value="0"/>
					<bit memory_port="mem_out[7]" value="1"/>
				</bitstream>
			</bitstream_block>
			<bitstream_block name="mem_fle_1_in_0" hierarchy_level="3">
				<hierarchy>
					<instance level="0" name="fpga_top"/>
					<instance level="1" name="grid_clb_1_1"/>
					<instance level="2" name="logical_tile_clb_mode_clb__0"/>
					<instance level="3" name="mem_fle_1_in_0"/>
				</hierarchy>
				<output_nets>
					<path id="0" net_name="unmapped"/>
				</output_nets>
				<bitstream path_id="-1">
					<bit memory_port="mem_out[0]" value="0"/>
					<bit memory_port="mem_out[1]" value="0"/>
					<bit memory_port="mem_out[2]" value="1"/>
					<bit memory_port="mem_out[3]" value="0"/>
					<bit memory_port="mem_out[4]" value="0"/>
					<bit memory_port="mem_out[5]" value="0"/>
					<bit memory_port="mem_out[6]" value="0"/>
					<bit memory_port="mem_out[7]" value="1"/>
				</bitstream>
			</bitstream_block>
			<bitstream_block name="mem_fle_1_in_1" hierarchy_level="3">
				<hierarchy>
					<instance level="0" name="fpga_top"/>
					<instance level="1" name="grid_clb_1_1"/>
					<instance level="2" name="logical_tile_clb_mode_clb__0"/>
					<instance level="3" name="mem_fle_1_in_1"/>
				</hierarchy>
				<output_nets>
					<path id="0" net_name="unmapped"/>
				</output_nets>
				<bitstream path_id="-1">
					<bit memory_port="mem_out[0]" value="0"/>
					<bit memory_port="mem_out[1]" value="0"/>
					<bit memory_port="mem_out[2]" value="1"/>
					<bit memory_port="mem_out[3]" value="0"/>
					<bit memory_port="mem_out[4]" value="0"/>
					<bit memory_port="mem_out[5]" value="0"/>
					<bit memory_port="mem_out[6]" value="0"/>
					<bit memory_port="mem_out[7]" value="1"/>
				</bitstream>
			</bitstream_block>
			<bitstream_block name="mem_fle_1_in_2" hierarchy_level="3">
				<hierarchy>
					<instance level="0" name="fpga_top"/>
					<instance level="1" name="grid_clb_1_1"/>
					<instance level="2" name="logical_tile_clb_mode_clb__0"/>
					<instance level="3" name="mem_fle_1_in_2"/>
				</hierarchy>
				<output_nets>
					<path id="0" net_name="unmapped"/>
				</output_nets>
				<bitstream path_id="-1">
					<bit memory_port="mem_out[0]" value="0"/>
					<bit memory_port="mem_out[1]" value="0"/>
					<bit memory_port="mem_out[2]" value="1"/>
					<bit memory_port="mem_out[3]" value="0"/>
					<bit memory_port="mem_out[4]" value="0"/>
					<bit memory_port="mem_out[5]" value="0"/>
					<bit memory_port="mem_out[6]" value="0"/>
					<bit memory_port="mem_out[7]" value="1"/>
				</bitstream>
			</bitstream_block>
			<bitstream_block name="mem_fle_1_in_3" hierarchy_level="3">
				<hierarchy>
					<instance level="0" name="fpga_top"/>
					<instance level="1" name="grid_clb_1_1"/>
					<instance level="2" name="logical_tile_clb_mode_clb__0"/>
					<instance level="3" name="mem_fle_1_in_3"/>
				</hierarchy>
				<output_nets>
					<path id="0" net_name="unmapped"/>
				</output_nets>
				<bitstream path_id="-1">
					<bit memory_port="mem_out[0]" value="0"/>
					<bit memory_port="mem_out[1]" value="0"/>
					<bit memory_port="mem_out[2]" value="1"/>
					<bit memory_port="mem_out[3]" value="0"/>
					<bit memory_port="mem_out[4]" value="0"/>
					<bit memory_port="mem_out[5]" value="0"/>
					<bit memory_port="mem_out[6]" value="0"/>
					<bit memory_port="mem_out[7]" value="1"/>
				</bitstream>
			</bitstream_block>
			<bitstream_block name="mem_fle_2_in_0" hierarchy_level="3">
				<hierarchy>
					<instance level="0" name="fpga_top"/>
					<instance level="1" name="grid_clb_1_1"/>
					<instance level="2" name="logical_tile_clb_mode_clb__0"/>
					<instance level="3" name="mem_fle_2_in_0"/>
				</hierarchy>
				<output_nets>
					<path id="0" net_name="unmapped"/>
				</output_nets>
				<bitstream path_id="-1">
					<bit memory_port="mem_out[0]" value="0"/>
					<bit memory_port="mem_out[1]" value="0"/>
					<bit memory_port="mem_out[2]" value="1"/>
					<bit memory_port="mem_out[3]" value="0"/>
					<bit memory_port="mem_out[4]" value="0"/>
					<bit memory_port="mem_out[5]" value="0"/>
					<bit memory_port="mem_out[6]" value="0"/>
					<bit memory_port="mem_out[7]" value="1"/>
				</bitstream>
			</bitstream_block>
			<bitstream_block name="mem_fle_2_in_1" hierarchy_level="3">
				<hierarchy>
					<instance level="0" name="fpga_top"/>
					<instance level="1" name="grid_clb_1_1"/>
					<instance level="2" name="logical_tile_clb_mode_clb__0"/>
					<instance level="3" name="mem_fle_2_in_1"/>
				</hierarchy>
				<output_nets>
					<path id="0" net_name="unmapped"/>
				</output_nets>
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