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OpenFPGA/vpr7_x2p/vpr
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AurelienUoU 4f921b03da Add travis full path to avoid missing sources 2019-05-16 15:51:10 -06:00
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ARCH Add travis full path to avoid missing sources 2019-05-16 15:51:10 -06:00
Circuits Add missing Verilog source, Archictecture folder and Testbenches correction 2019-05-13 16:41:35 -06:00
SRC Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-13 16:42:27 -06:00
SpiceNetlists Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
VerilogNetlists Add travis full path to avoid missing sources 2019-05-16 15:51:10 -06:00
.regression_verilog.sh Add travis full path to avoid missing sources 2019-05-16 15:51:10 -06:00
CMakeLists.txt Force graphics to false 2019-05-15 15:01:54 -06:00
Makefile fixed bugs in CMakeLists.txt and Makefile 2019-05-03 23:03:04 -06:00
go_fpga_spice.sh Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
go_fpga_verilog.sh Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-10 14:09:23 -06:00