236 lines
10 KiB
XML
236 lines
10 KiB
XML
<architecture>
|
|
<models/>
|
|
<tiles>
|
|
<tile name="io" capacity="8">
|
|
<equivalent_sites>
|
|
<site pb_type="io"/>
|
|
</equivalent_sites>
|
|
<input name="outpad" num_pins="1"/>
|
|
<output name="inpad" num_pins="1"/>
|
|
<clock name="clock" num_pins="1"/>
|
|
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
|
<pinlocations pattern="custom">
|
|
<loc side="left">io.outpad io.inpad io.clock</loc>
|
|
<loc side="top">io.outpad io.inpad io.clock</loc>
|
|
<loc side="right">io.outpad io.inpad io.clock</loc>
|
|
<loc side="bottom">io.outpad io.inpad io.clock</loc>
|
|
</pinlocations>
|
|
</tile>
|
|
<tile name="clb">
|
|
<equivalent_sites>
|
|
<site pb_type="clb"/>
|
|
</equivalent_sites>
|
|
<input name="I" num_pins="33" equivalent="full"/>
|
|
<output name="O" num_pins="20" equivalent="none"/>
|
|
<clock name="clk" num_pins="1"/>
|
|
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
|
<pinlocations pattern="spread"/>
|
|
</tile>
|
|
</tiles>
|
|
<layout>
|
|
<auto_layout aspect_ratio="1.0">
|
|
<perimeter type="io" priority="100">
|
|
<metadata>
|
|
<meta name="type">io</meta>
|
|
</metadata>
|
|
</perimeter>
|
|
<single type="clb" priority="1" x="5" y="5">
|
|
<metadata>
|
|
<meta name="single">clb</meta>
|
|
</metadata>
|
|
</single>
|
|
<corners type="EMPTY" priority="101"/>
|
|
<fill type="clb" priority="10"/>
|
|
<col type="EMPTY" startx="6" repeatx="8" starty="1" priority="19"/>
|
|
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
|
|
</auto_layout>
|
|
</layout>
|
|
<device>
|
|
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
|
|
<area grid_logic_tile_area="53894"/>
|
|
<chan_width_distr>
|
|
<x distr="uniform" peak="1.000000"/>
|
|
<y distr="uniform" peak="1.000000"/>
|
|
</chan_width_distr>
|
|
<switch_block type="wilton" fs="3"/>
|
|
<connection_block input_switch_name="ipin_cblock"/>
|
|
</device>
|
|
<switchlist>
|
|
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
|
|
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
|
|
</switchlist>
|
|
<segmentlist>
|
|
<segment freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
|
|
<mux name="0"/>
|
|
<sb type="pattern">1 1 1 1 1</sb>
|
|
<cb type="pattern">1 1 1 1</cb>
|
|
</segment>
|
|
</segmentlist>
|
|
<complexblocklist>
|
|
<pb_type name="io">
|
|
<metadata>
|
|
<meta name="pb_type_type">pb_type = io</meta>
|
|
</metadata>
|
|
<input name="outpad" num_pins="1"/>
|
|
<output name="inpad" num_pins="1"/>
|
|
<clock name="clock" num_pins="1"/>
|
|
<mode name="inpad">
|
|
<metadata>
|
|
<meta name="mode">inpad</meta>
|
|
</metadata>
|
|
<pb_type name="inpad" blif_model=".input" num_pb="1">
|
|
<output name="inpad" num_pins="1"/>
|
|
</pb_type>
|
|
<interconnect>
|
|
<direct name="inpad" input="inpad.inpad" output="io.inpad">
|
|
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
|
|
<metadata>
|
|
<meta name="interconnect">inpad_iconnect</meta>
|
|
</metadata>
|
|
</direct>
|
|
</interconnect>
|
|
</mode>
|
|
<mode name="outpad">
|
|
<pb_type name="outpad" blif_model=".output" num_pb="1">
|
|
<input name="outpad" num_pins="1"/>
|
|
</pb_type>
|
|
<interconnect>
|
|
<direct name="outpad" input="io.outpad" output="outpad.outpad">
|
|
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
|
|
</direct>
|
|
</interconnect>
|
|
</mode>
|
|
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
|
|
<!-- IOs go on the periphery of the FPGA, for consistency,
|
|
make it physically equivalent on all sides so that only one definition of I/Os is needed.
|
|
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
|
|
-->
|
|
<!-- Place I/Os on the sides of the FPGA -->
|
|
<power method="ignore"/>
|
|
</pb_type>
|
|
<pb_type name="clb">
|
|
<input name="I" num_pins="33" equivalent="full"/>
|
|
<output name="O" num_pins="20" equivalent="none"/>
|
|
<clock name="clk" num_pins="1"/>
|
|
<pb_type name="fle" num_pb="10">
|
|
<input name="in" num_pins="6"/>
|
|
<output name="out" num_pins="2"/>
|
|
<clock name="clk" num_pins="1"/>
|
|
<mode name="n2_lut5">
|
|
<pb_type name="lut5inter" num_pb="1">
|
|
<input name="in" num_pins="5"/>
|
|
<output name="out" num_pins="2"/>
|
|
<clock name="clk" num_pins="1"/>
|
|
<pb_type name="ble5" num_pb="2">
|
|
<input name="in" num_pins="5"/>
|
|
<output name="out" num_pins="1"/>
|
|
<clock name="clk" num_pins="1"/>
|
|
<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
|
|
<input name="in" num_pins="5" port_class="lut_in"/>
|
|
<output name="out" num_pins="1" port_class="lut_out"/>
|
|
<delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
|
|
235e-12
|
|
235e-12
|
|
235e-12
|
|
235e-12
|
|
235e-12
|
|
</delay_matrix>
|
|
</pb_type>
|
|
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
|
<input name="D" num_pins="1" port_class="D"/>
|
|
<output name="Q" num_pins="1" port_class="Q"/>
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
|
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
|
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
|
</pb_type>
|
|
<interconnect>
|
|
<direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/>
|
|
<direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D">
|
|
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
|
<pack_pattern name="ble5" in_port="lut5[0:0].out" out_port="ff[0:0].D"/>
|
|
</direct>
|
|
<direct name="direct3" input="ble5.clk" output="ff[0:0].clk"/>
|
|
<mux name="mux1" input="ff[0:0].Q lut5.out[0:0]" output="ble5.out[0:0]">
|
|
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
|
<delay_constant max="25e-12" in_port="lut5.out[0:0]" out_port="ble5.out[0:0]"/>
|
|
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble5.out[0:0]"/>
|
|
</mux>
|
|
</interconnect>
|
|
</pb_type>
|
|
<interconnect>
|
|
<direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
|
|
<direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
|
|
<direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
|
|
<complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
|
|
</interconnect>
|
|
</pb_type>
|
|
<interconnect>
|
|
<direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
|
|
<direct name="direct2" input="lut5inter.out" output="fle.out"/>
|
|
<direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
|
|
</interconnect>
|
|
</mode>
|
|
<mode name="n1_lut6">
|
|
<pb_type name="ble6" num_pb="1">
|
|
<input name="in" num_pins="6"/>
|
|
<output name="out" num_pins="1"/>
|
|
<clock name="clk" num_pins="1"/>
|
|
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
|
|
<input name="in" num_pins="6" port_class="lut_in"/>
|
|
<output name="out" num_pins="1" port_class="lut_out"/>
|
|
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
|
|
261e-12
|
|
261e-12
|
|
261e-12
|
|
261e-12
|
|
261e-12
|
|
261e-12
|
|
</delay_matrix>
|
|
</pb_type>
|
|
<!-- Define flip-flop -->
|
|
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
|
<input name="D" num_pins="1" port_class="D"/>
|
|
<output name="Q" num_pins="1" port_class="Q"/>
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
|
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
|
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
|
</pb_type>
|
|
<interconnect>
|
|
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
|
|
<direct name="direct2" input="lut6.out" output="ff.D">
|
|
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
|
|
</direct>
|
|
<direct name="direct3" input="ble6.clk" output="ff.clk"/>
|
|
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
|
|
<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
|
|
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
|
|
</mux>
|
|
</interconnect>
|
|
</pb_type>
|
|
<interconnect>
|
|
<direct name="direct1" input="fle.in" output="ble6.in"/>
|
|
<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
|
|
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
|
|
</interconnect>
|
|
</mode>
|
|
</pb_type>
|
|
<interconnect>
|
|
<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
|
|
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
|
|
<delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
|
|
</complete>
|
|
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
|
|
</complete>
|
|
<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
|
|
<direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
|
|
</interconnect>
|
|
</pb_type>
|
|
</complexblocklist>
|
|
<power>
|
|
<local_interconnect C_wire="2.5e-10"/>
|
|
</power>
|
|
<clocks>
|
|
<clock buffer_size="auto" C_wire="2.5e-10"/>
|
|
</clocks>
|
|
</architecture>
|