ganeshgore d502410b40 Merge pull request #179 from lnis-uofu/unused_gpout_patch ... Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches		2021-01-23 18:27:54 -07:00
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src	Merge pull request #179 from lnis-uofu/unused_gpout_patch	2021-01-23 18:27:54 -07:00
CMakeLists.txt	[Tool] Deploy pin constraints to preconfig Verilog module generation	2021-01-19 16:56:30 -07:00