riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenFPGA/yosys/tests/errors/syntax_err02.v

8 lines
65 B
Verilog
Raw Blame History

module a;
task to (
input integer [3:0]x
);
endtask
endmodule
Reference in New Issue View Git Blame Copy Permalink