OpenFPGA/yosys/manual/PRESENTATION_ExAdv/macc_simple_test.ys

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read_verilog macc_simple_test.v
hierarchy -check -top test;;
show -prefix macc_simple_test_00a -format pdf -notitle -lib macc_simple_xmap.v
extract -constports -map macc_simple_xmap.v;;
show -prefix macc_simple_test_00b -format pdf -notitle -lib macc_simple_xmap.v
#################################################
design -reset
read_verilog macc_simple_test_01.v
hierarchy -check -top test;;
show -prefix macc_simple_test_01a -format pdf -notitle -lib macc_simple_xmap.v
extract -map macc_simple_xmap.v;;
show -prefix macc_simple_test_01b -format pdf -notitle -lib macc_simple_xmap.v
#################################################
design -reset
read_verilog macc_simple_test_02.v
hierarchy -check -top test;;
show -prefix macc_simple_test_02a -format pdf -notitle -lib macc_simple_xmap.v
extract -map macc_simple_xmap.v;;
show -prefix macc_simple_test_02b -format pdf -notitle -lib macc_simple_xmap.v
#################################################
design -reset
read_verilog macc_simple_xmap.v
hierarchy -check -top macc_16_16_32;;
show -prefix macc_simple_xmap -format pdf -notitle