37 lines
1.3 KiB
Plaintext
37 lines
1.3 KiB
Plaintext
# Run VPR for the 'and' design
|
|
#--write_rr_graph example_rr_graph.xml
|
|
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --skip_sync_clustering_and_routing_results on
|
|
|
|
# Read OpenFPGA architecture definition
|
|
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
|
|
|
|
# Read OpenFPGA simulation settings
|
|
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
|
|
|
|
# Annotate the OpenFPGA architecture to VPR data base
|
|
# to debug use --verbose options
|
|
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
|
|
|
|
# Check and correct any naming conflicts in the BLIF netlist
|
|
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
|
|
|
|
# Apply fix-up to clustering nets based on routing results
|
|
pb_pin_fixup --verbose
|
|
|
|
# Apply fix-up to Look-Up Table truth tables based on packing results
|
|
lut_truth_table_fixup
|
|
|
|
# Build the module graph
|
|
# - Enabled compression on routing architecture modules
|
|
# - Enable pin duplication on grid modules
|
|
build_fabric ${OPENFPGA_BUILD_FABRIC_OPTION} #--verbose
|
|
|
|
# Write gsb to XML
|
|
write_gsb_to_xml --file gsb_xml --verbose ${OPENFPGA_WRITE_GSB_OPTION}
|
|
|
|
# Finish and exit OpenFPGA
|
|
exit
|
|
|
|
# Note :
|
|
# To run verification at the end of the flow maintain source in ./SRC directory
|