39 lines
1.7 KiB
Plaintext
39 lines
1.7 KiB
Plaintext
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
|
# Configuration file for running experiments
|
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
|
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
|
# Each job execute fpga_flow script on combination of architecture & benchmark
|
|
# timeout_each_job is timeout for each job
|
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
|
|
|
[GENERAL]
|
|
run_engine=openfpga_shell
|
|
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
|
power_analysis = true
|
|
spice_output=false
|
|
verilog_output=true
|
|
timeout_each_job = 20*60
|
|
fpga_flow=yosys_vpr
|
|
|
|
[OpenFPGA_SHELL]
|
|
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga
|
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
|
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
|
|
|
[ARCHITECTURES]
|
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
|
|
|
[BENCHMARKS]
|
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v
|
|
# bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v
|
|
# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v
|
|
|
|
[SYNTHESIS_PARAM]
|
|
bench0_top = pulse_generator
|
|
# bench1_top = reset_generator
|
|
# bench2_top = clock_divider
|
|
|
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
|
end_flow_with_test=
|
|
#vpr_fpga_verilog_formal_verification_top_netlist=
|