OpenFPGA/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp

30 lines
686 B
Cap'n Proto

# This file is generated by uxsdcap 0.1.0.
# https://github.com/duck2/uxsdcxx
# Modify only if your build process doesn't involve regenerating this file.
#
# Cmdline: /home/talaeikh/uxsdcxx/uxsdcap.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
# Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
# md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6
@0xa136dddfdd48783b;
using Cxx = import "/capnp/c++.capnp";
$Cxx.namespace("uniqueblockcap");
enum BlockType {
cbx @0;
cby @1;
sb @2;
}
struct BlockInfo {
type @0: BlockType;
x @1: Int32;
y @2: Int32;
}
struct InstanceInfo {
x @0 :Int32;
y @1 :Int32;
}