484 lines
14 KiB
Verilog
484 lines
14 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// Protocol Layer ////
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//// This block is typically referred to as the SEI in USB ////
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//// Specification. It encapsulates the Packet Assembler, ////
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//// disassembler, protocol engine and internal DMA ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/usb/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2003 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: usbf_pl.v,v 1.5 2003/10/17 02:36:57 rudi Exp $
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//
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// $Date: 2003/10/17 02:36:57 $
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// $Revision: 1.5 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: usbf_pl.v,v $
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// Revision 1.5 2003/10/17 02:36:57 rudi
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// - Disabling bit stuffing and NRZI encoding during speed negotiation
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// - Now the core can send zero size packets
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// - Fixed register addresses for some of the higher endpoints
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// (conversion between decimal/hex was wrong)
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// - The core now does properly evaluate the function address to
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// determine if the packet was intended for it.
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// - Various other minor bugs and typos
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//
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// Revision 1.4 2001/11/04 12:22:45 rudi
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//
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// - Fixed previous fix (brocke something else ...)
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// - Majore Synthesis cleanup
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//
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// Revision 1.3 2001/09/24 01:15:28 rudi
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//
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// Changed reset to be active high async.
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//
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// Revision 1.2 2001/08/10 08:48:33 rudi
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//
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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//
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// Revision 1.1 2001/08/03 05:30:09 rudi
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//
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//
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// 1) Reorganized directory structure
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//
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// Revision 1.2 2001/03/31 13:00:52 rudi
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//
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// - Added Core configuration
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// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode
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// - Modified WISHBONE interface and sync logic
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// - Moved SSRAM outside the core (added interface)
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// - Many small bug fixes ...
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//
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// Revision 1.0 2001/03/07 09:17:12 rudi
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//
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//
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// Changed all revisions to revision 1.0. This is because OpenCores CVS
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// interface could not handle the original '0.1' revision ....
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//
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// Revision 0.1.0.1 2001/02/28 08:11:11 rudi
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// Initial Release
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//
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//
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`include "usbf_defines.v"
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module usbf_pl( clk, rst,
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// UTMI Interface
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rx_data, rx_valid, rx_active, rx_err,
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tx_data, tx_valid, tx_valid_last, tx_ready,
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tx_first, tx_valid_out,
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mode_hs, usb_reset, usb_suspend, usb_attached,
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// memory interface
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madr, mdout, mdin, mwe, mreq, mack,
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// Register File Interface
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fa, idin,
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ep_sel, match,
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dma_in_buf_sz1, dma_out_buf_avail,
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buf0_rl, buf0_set, buf1_set,
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uc_bsel_set, uc_dpd_set,
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int_buf1_set, int_buf0_set, int_upid_set,
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int_crc16_set, int_to_set, int_seqerr_set,
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out_to_small, csr, buf0, buf1,
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// Misc
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frm_nat,
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pid_cs_err, nse_err,
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crc5_err
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);
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parameter SSRAM_HADR = 14;
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// UTMI Interface
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input clk, rst;
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input [7:0] rx_data;
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input rx_valid, rx_active, rx_err;
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output [7:0] tx_data;
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output tx_valid;
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output tx_valid_last;
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input tx_ready;
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output tx_first;
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input tx_valid_out;
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input mode_hs; // High Speed Mode
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input usb_reset; // USB Reset
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input usb_suspend; // USB Suspend
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input usb_attached; // Attached to USB
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// Memory Arbiter Interface
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output [SSRAM_HADR:0] madr; // word address
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output [31:0] mdout;
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input [31:0] mdin;
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output mwe;
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output mreq;
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input mack;
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// Register File interface
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input [6:0] fa; // Function Address (as set by the controller)
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output [31:0] idin; // Data Input
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output [3:0] ep_sel; // Endpoint Number Input
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input match; // Endpoint Matched
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input dma_in_buf_sz1;
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input dma_out_buf_avail;
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output nse_err; // no such endpoint error
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output buf0_rl; // Reload Buf 0 with original values
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output buf0_set; // Write to buf 0
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output buf1_set; // Write to buf 1
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output uc_bsel_set; // Write to the uc_bsel field
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output uc_dpd_set; // Write to the uc_dpd field
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output int_buf1_set; // Set buf1 full/empty interrupt
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output int_buf0_set; // Set buf0 full/empty interrupt
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output int_upid_set; // Set unsupported PID interrupt
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output int_crc16_set; // Set CRC16 error interrupt
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output int_to_set; // Set time out interrupt
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output int_seqerr_set; // Set PID sequence error interrupt
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output out_to_small; // OUT packet was to small for DMA operation
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input [31:0] csr; // Internal CSR Output
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input [31:0] buf0; // Internal Buf 0 Output
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input [31:0] buf1; // Internal Buf 1 Output
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// Misc
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output pid_cs_err; // pid checksum error
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output crc5_err; // crc5 error
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output [31:0] frm_nat;
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///////////////////////////////////////////////////////////////////
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//
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// Local Wires and Registers
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//
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// Packet Disassembler Interface
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wire clk, rst;
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wire [7:0] rx_data;
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wire pid_OUT, pid_IN, pid_SOF, pid_SETUP;
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wire pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA;
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wire pid_ACK, pid_NACK, pid_STALL, pid_NYET;
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wire pid_PRE, pid_ERR, pid_SPLIT, pid_PING;
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wire [6:0] token_fadr;
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wire token_valid;
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wire crc5_err;
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wire [10:0] frame_no;
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wire [7:0] rx_data_st;
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wire rx_data_valid;
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wire rx_data_done;
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wire crc16_err;
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wire rx_seq_err;
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// Packet Assembler Interface
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wire send_token;
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wire [1:0] token_pid_sel;
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wire send_data;
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wire [1:0] data_pid_sel;
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wire [7:0] tx_data_st;
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wire rd_next;
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// IDMA Interface
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wire rx_dma_en; // Allows the data to be stored
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wire tx_dma_en; // Allows for data to be retrieved
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wire abort; // Abort Transfer (time_out, crc_err or rx_error)
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wire idma_done; // DMA is done
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wire [SSRAM_HADR + 2:0] adr; // Byte Address
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wire [13:0] size; // Size in bytes
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wire [10:0] sizu_c; // Up and Down counting size registers, used
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// to update
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wire [13:0] buf_size; // Actual buffer size
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wire dma_en; // external dma enabled
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// Memory Arbiter Interface
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wire [SSRAM_HADR:0] madr; // word address
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wire [31:0] mdout;
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wire [31:0] mdin;
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wire mwe;
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wire mreq;
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wire mack;
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// Local signals
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wire pid_bad, pid_bad1, pid_bad2;
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reg hms_clk; // 0.5 Micro Second Clock
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reg [4:0] hms_cnt;
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reg [10:0] frame_no_r; // Current Frame Number register
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wire frame_no_we;
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reg frame_no_same; // Indicates current and prev. frame numbers
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// are equal
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reg [3:0] mfm_cnt; // Micro Frame Counter
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reg [11:0] sof_time; // Time since last sof
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reg clr_sof_time;
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wire fsel; // This Function is selected
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wire match_o;
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reg frame_no_we_r;
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///////////////////////////////////////////////////////////////////
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//
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// Misc Logic
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//
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// PIDs we should never receive
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assign pid_bad1 = pid_ACK | pid_NACK | pid_STALL | pid_NYET | pid_PRE |
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pid_ERR | pid_SPLIT;
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// PIDs we should never get in full speed mode (high speed mode only)
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assign pid_bad2 = !mode_hs & pid_PING;
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// All bad pids
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assign pid_bad = pid_bad1 | pid_bad2;
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assign match_o = !pid_bad & fsel & match & token_valid & !crc5_err;
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// Frame Number (from SOF token)
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assign frame_no_we = token_valid & !crc5_err & pid_SOF;
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always @(posedge clk)
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frame_no_we_r <= frame_no_we;
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`ifdef USBF_ASYNC_RESET
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always @(posedge clk or negedge rst)
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`else
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always @(posedge clk)
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`endif
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if(!rst) frame_no_r <= 11'h0;
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else
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if(frame_no_we_r) frame_no_r <= frame_no;
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// Micro Frame Counter
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always @(posedge clk)
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frame_no_same <= frame_no_we & (frame_no_r == frame_no);
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`ifdef USBF_ASYNC_RESET
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always @(posedge clk or negedge rst)
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`else
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always @(posedge clk)
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`endif
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if(!rst) mfm_cnt <= 4'h0;
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else
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if(frame_no_we_r && !frame_no_same)
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mfm_cnt <= 4'h0;
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else
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if(frame_no_same) mfm_cnt <= mfm_cnt + 4'h1;
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//SOF delay counter
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always @(posedge clk)
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clr_sof_time <= frame_no_we;
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always @(posedge clk)
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if(clr_sof_time) sof_time <= 12'h0;
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else
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if(hms_clk) sof_time <= sof_time + 12'h1;
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assign frm_nat = {mfm_cnt, 1'b0, frame_no_r, 4'h0, sof_time};
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// 0.5 Micro Seconds Clock Generator
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`ifdef USBF_ASYNC_RESET
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always @(posedge clk or negedge rst)
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`else
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always @(posedge clk)
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`endif
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if(!rst) hms_cnt <= 5'h0;
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else
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if(hms_clk || frame_no_we_r) hms_cnt <= 5'h0;
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else hms_cnt <= hms_cnt + 5'h1;
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always @(posedge clk)
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hms_clk <= (hms_cnt == `USBF_HMS_DEL);
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///////////////////////////////////////////////////////////////////
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// This function is addressed
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assign fsel = (token_fadr == fa);
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///////////////////////////////////////////////////////////////////
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//
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// Module Instantiations
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//
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//Packet Decoder
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usbf_pd u0( .clk( clk ),
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.rst( rst ),
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.rx_data( rx_data ),
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.rx_valid( rx_valid ),
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.rx_active( rx_active ),
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.rx_err( rx_err ),
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.pid_OUT( pid_OUT ),
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.pid_IN( pid_IN ),
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.pid_SOF( pid_SOF ),
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.pid_SETUP( pid_SETUP ),
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.pid_DATA0( pid_DATA0 ),
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.pid_DATA1( pid_DATA1 ),
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.pid_DATA2( pid_DATA2 ),
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.pid_MDATA( pid_MDATA ),
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.pid_ACK( pid_ACK ),
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.pid_NACK( pid_NACK ),
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.pid_STALL( pid_STALL ),
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.pid_NYET( pid_NYET ),
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.pid_PRE( pid_PRE ),
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.pid_ERR( pid_ERR ),
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.pid_SPLIT( pid_SPLIT ),
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.pid_PING( pid_PING ),
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.pid_cks_err( pid_cs_err ),
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.token_fadr( token_fadr ),
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.token_endp( ep_sel ),
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.token_valid( token_valid ),
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.crc5_err( crc5_err ),
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.frame_no( frame_no ),
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.rx_data_st( rx_data_st ),
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.rx_data_valid( rx_data_valid ),
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.rx_data_done( rx_data_done ),
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.crc16_err( crc16_err ),
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.seq_err( rx_seq_err )
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);
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// Packet Assembler
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usbf_pa u1( .clk( clk ),
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.rst( rst ),
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.tx_data( tx_data ),
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.tx_valid( tx_valid ),
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.tx_valid_last( tx_valid_last ),
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.tx_ready( tx_ready ),
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.tx_first( tx_first ),
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.send_token( send_token ),
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.token_pid_sel( token_pid_sel ),
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.send_data( send_data ),
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.data_pid_sel( data_pid_sel ),
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.send_zero_length( send_zero_length ),
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.tx_data_st( tx_data_st ),
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.rd_next( rd_next )
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);
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// Internal DMA / Memory Arbiter Interface
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usbf_idma #(SSRAM_HADR)
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u2( .clk( clk ),
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.rst( rst ),
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.rx_data_st( rx_data_st ),
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.rx_data_valid( rx_data_valid ),
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.rx_data_done( rx_data_done ),
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.send_data( send_data ),
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.tx_data_st( tx_data_st ),
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.rd_next( rd_next ),
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.rx_dma_en( rx_dma_en ),
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.tx_dma_en( tx_dma_en ),
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.abort( abort ),
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.idma_done( idma_done ),
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.adr( adr ),
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.size( size ),
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.buf_size( buf_size ),
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.dma_en( dma_en ),
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.send_zero_length( send_zero_length ),
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.madr( madr ),
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.sizu_c( sizu_c ),
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.mdout( mdout ),
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.mdin( mdin ),
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.mwe( mwe ),
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.mreq( mreq ),
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.mack( mack )
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);
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// Protocol Engine
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usbf_pe #(SSRAM_HADR)
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u3( .clk( clk ),
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.rst( rst ),
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.tx_valid( tx_valid_out ),
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.rx_active( rx_active ),
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.pid_OUT( pid_OUT ),
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.pid_IN( pid_IN ),
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.pid_SOF( pid_SOF ),
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.pid_SETUP( pid_SETUP ),
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.pid_DATA0( pid_DATA0 ),
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.pid_DATA1( pid_DATA1 ),
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.pid_DATA2( pid_DATA2 ),
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.pid_MDATA( pid_MDATA ),
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.pid_ACK( pid_ACK ),
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.pid_NACK( pid_NACK ),
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.pid_STALL( pid_STALL ),
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.pid_NYET( pid_NYET ),
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.pid_PRE( pid_PRE ),
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.pid_ERR( pid_ERR ),
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.pid_SPLIT( pid_SPLIT ),
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.pid_PING( pid_PING ),
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.mode_hs( mode_hs ),
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.token_valid( token_valid ),
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.crc5_err( crc5_err ),
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.rx_data_valid( rx_data_valid ),
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.rx_data_done( rx_data_done ),
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.crc16_err( crc16_err ),
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.send_token( send_token ),
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.token_pid_sel( token_pid_sel ),
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.data_pid_sel( data_pid_sel ),
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.send_zero_length( send_zero_length ),
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.rx_dma_en( rx_dma_en ),
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.tx_dma_en( tx_dma_en ),
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.abort( abort ),
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.idma_done( idma_done ),
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.adr( adr ),
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.size( size ),
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.buf_size( buf_size ),
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.sizu_c( sizu_c ),
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.dma_en( dma_en ),
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.fsel( fsel ),
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.idin( idin ),
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.ep_sel( ep_sel ),
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.match( match_o ),
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.dma_in_buf_sz1( dma_in_buf_sz1 ),
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.dma_out_buf_avail( dma_out_buf_avail ),
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.nse_err( nse_err ),
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.buf0_rl( buf0_rl ),
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.buf0_set( buf0_set ),
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.buf1_set( buf1_set ),
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.uc_bsel_set( uc_bsel_set ),
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.uc_dpd_set( uc_dpd_set ),
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.int_buf1_set( int_buf1_set ),
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.int_buf0_set( int_buf0_set ),
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.int_upid_set( int_upid_set ),
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.int_crc16_set( int_crc16_set ),
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.int_to_set( int_to_set ),
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.int_seqerr_set( int_seqerr_set ),
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.out_to_small( out_to_small ),
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.csr( csr ),
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.buf0( buf0 ),
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.buf1( buf1 )
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);
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endmodule
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