19 lines
776 B
Verilog
19 lines
776 B
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "timescale.v" ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: timescale.v,v $
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// Revision 1.2 2002/02/01 15:25:13 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.1 2001/10/05 08:11:22 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// timescale directive is included in all core's modules for simulation purposes
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`timescale 1ns/1ps |