tangxifan f9dc7c1b54 [HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells		2021-03-17 15:15:22 -06:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	add shift register test case	2021-03-05 09:06:05 -08:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	[Script] Bug fix in yosys script to synthesis BRAM	2021-03-17 15:12:04 -06:00
openfpga_arch	[Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys)	2021-03-17 15:10:05 -06:00
openfpga_cell_library	[HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells	2021-03-17 15:15:22 -06:00
openfpga_shell_scripts	[Script] Add example script to run vtr benchmarks	2021-03-17 15:10:56 -06:00
openfpga_simulation_settings	[Arch] Add simulation setting for 8-clock architectures	2021-02-22 11:10:03 -07:00
openfpga_yosys_techlib	[HDL] Add an adhoc yosys technology library for a heterogeneous FPGA architecture	2021-03-17 15:09:12 -06:00
regression_test_scripts	[Test] Add vtr benchmark regression test	2021-03-17 15:13:58 -06:00
scripts	Merge branch 'master' into yosys_heterogeneous_block_support	2021-03-16 20:05:21 -06:00
tasks	[Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added)	2021-03-17 15:11:17 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys)	2021-03-17 15:10:05 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00