367 lines
14 KiB
Verilog
367 lines
14 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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/* No clearbox model */
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`ifdef NO_CLEARBOX
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(* blackbox *)
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module altpll
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( inclk,
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fbin,
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pllena,
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clkswitch,
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areset,
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pfdena,
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clkena,
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extclkena,
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scanclk,
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scanaclr,
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scanclkena,
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scanread,
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scanwrite,
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scandata,
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phasecounterselect,
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phaseupdown,
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phasestep,
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configupdate,
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fbmimicbidir,
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clk,
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extclk,
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clkbad,
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enable0,
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enable1,
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activeclock,
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clkloss,
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locked,
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scandataout,
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scandone,
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sclkout0,
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sclkout1,
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phasedone,
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vcooverrange,
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vcounderrange,
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fbout,
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fref,
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icdrclk,
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c0,
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c1,
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c2,
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c3,
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c4);
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parameter intended_device_family = "MAX 10";
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parameter operation_mode = "NORMAL";
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parameter pll_type = "AUTO";
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parameter qualify_conf_done = "OFF";
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parameter compensate_clock = "CLK0";
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parameter scan_chain = "LONG";
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parameter primary_clock = "inclk0";
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parameter inclk0_input_frequency = 1000;
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parameter inclk1_input_frequency = 0;
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parameter gate_lock_signal = "NO";
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parameter gate_lock_counter = 0;
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parameter lock_high = 1;
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parameter lock_low = 0;
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parameter valid_lock_multiplier = 1;
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parameter invalid_lock_multiplier = 5;
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parameter switch_over_type = "AUTO";
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parameter switch_over_on_lossclk = "OFF" ;
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parameter switch_over_on_gated_lock = "OFF" ;
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parameter enable_switch_over_counter = "OFF";
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parameter switch_over_counter = 0;
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parameter feedback_source = "EXTCLK0" ;
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parameter bandwidth = 0;
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parameter bandwidth_type = "UNUSED";
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parameter lpm_hint = "UNUSED";
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parameter spread_frequency = 0;
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parameter down_spread = "0.0";
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parameter self_reset_on_gated_loss_lock = "OFF";
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parameter self_reset_on_loss_lock = "OFF";
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parameter lock_window_ui = "0.05";
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parameter width_clock = 6;
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parameter width_phasecounterselect = 4;
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parameter charge_pump_current_bits = 9999;
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parameter loop_filter_c_bits = 9999;
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parameter loop_filter_r_bits = 9999;
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parameter scan_chain_mif_file = "UNUSED";
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parameter clk9_multiply_by = 1;
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parameter clk8_multiply_by = 1;
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parameter clk7_multiply_by = 1;
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parameter clk6_multiply_by = 1;
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parameter clk5_multiply_by = 1;
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parameter clk4_multiply_by = 1;
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parameter clk3_multiply_by = 1;
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parameter clk2_multiply_by = 1;
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parameter clk1_multiply_by = 1;
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parameter clk0_multiply_by = 1;
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parameter clk9_divide_by = 1;
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parameter clk8_divide_by = 1;
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parameter clk7_divide_by = 1;
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parameter clk6_divide_by = 1;
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parameter clk5_divide_by = 1;
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parameter clk4_divide_by = 1;
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parameter clk3_divide_by = 1;
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parameter clk2_divide_by = 1;
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parameter clk1_divide_by = 1;
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parameter clk0_divide_by = 1;
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parameter clk9_phase_shift = "0";
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parameter clk8_phase_shift = "0";
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parameter clk7_phase_shift = "0";
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parameter clk6_phase_shift = "0";
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parameter clk5_phase_shift = "0";
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parameter clk4_phase_shift = "0";
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parameter clk3_phase_shift = "0";
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parameter clk2_phase_shift = "0";
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parameter clk1_phase_shift = "0";
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parameter clk0_phase_shift = "0";
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parameter clk9_duty_cycle = 50;
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parameter clk8_duty_cycle = 50;
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parameter clk7_duty_cycle = 50;
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parameter clk6_duty_cycle = 50;
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parameter clk5_duty_cycle = 50;
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parameter clk4_duty_cycle = 50;
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parameter clk3_duty_cycle = 50;
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parameter clk2_duty_cycle = 50;
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parameter clk1_duty_cycle = 50;
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parameter clk0_duty_cycle = 50;
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parameter clk9_use_even_counter_mode = "OFF";
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parameter clk8_use_even_counter_mode = "OFF";
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parameter clk7_use_even_counter_mode = "OFF";
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parameter clk6_use_even_counter_mode = "OFF";
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parameter clk5_use_even_counter_mode = "OFF";
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parameter clk4_use_even_counter_mode = "OFF";
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parameter clk3_use_even_counter_mode = "OFF";
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parameter clk2_use_even_counter_mode = "OFF";
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parameter clk1_use_even_counter_mode = "OFF";
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parameter clk0_use_even_counter_mode = "OFF";
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parameter clk9_use_even_counter_value = "OFF";
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parameter clk8_use_even_counter_value = "OFF";
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parameter clk7_use_even_counter_value = "OFF";
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parameter clk6_use_even_counter_value = "OFF";
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parameter clk5_use_even_counter_value = "OFF";
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parameter clk4_use_even_counter_value = "OFF";
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parameter clk3_use_even_counter_value = "OFF";
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parameter clk2_use_even_counter_value = "OFF";
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parameter clk1_use_even_counter_value = "OFF";
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parameter clk0_use_even_counter_value = "OFF";
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parameter clk2_output_frequency = 0;
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parameter clk1_output_frequency = 0;
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parameter clk0_output_frequency = 0;
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parameter vco_min = 0;
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parameter vco_max = 0;
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parameter vco_center = 0;
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parameter pfd_min = 0;
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parameter pfd_max = 0;
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parameter m_initial = 1;
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parameter m = 0;
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parameter n = 1;
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parameter m2 = 1;
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parameter n2 = 1;
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parameter ss = 0;
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parameter l0_high = 1;
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parameter l1_high = 1;
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parameter g0_high = 1;
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parameter g1_high = 1;
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parameter g2_high = 1;
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parameter g3_high = 1;
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parameter e0_high = 1;
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parameter e1_high = 1;
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parameter e2_high = 1;
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parameter e3_high = 1;
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parameter l0_low = 1;
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parameter l1_low = 1;
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parameter g0_low = 1;
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parameter g1_low = 1;
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parameter g2_low = 1;
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parameter g3_low = 1;
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parameter e0_low = 1;
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parameter e1_low = 1;
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parameter e2_low = 1;
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parameter e3_low = 1;
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parameter l0_initial = 1;
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parameter l1_initial = 1;
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parameter g0_initial = 1;
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parameter g1_initial = 1;
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parameter g2_initial = 1;
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parameter g3_initial = 1;
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parameter e0_initial = 1;
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parameter e1_initial = 1;
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parameter e2_initial = 1;
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parameter e3_initial = 1;
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parameter l0_mode = "bypass";
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parameter l1_mode = "bypass";
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parameter g0_mode = "bypass";
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parameter g1_mode = "bypass";
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parameter g2_mode = "bypass";
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parameter g3_mode = "bypass";
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parameter e0_mode = "bypass";
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parameter e1_mode = "bypass";
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parameter e2_mode = "bypass";
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parameter e3_mode = "bypass";
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parameter l0_ph = 0;
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parameter l1_ph = 0;
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parameter g0_ph = 0;
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parameter g1_ph = 0;
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parameter g2_ph = 0;
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parameter g3_ph = 0;
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parameter e0_ph = 0;
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parameter e1_ph = 0;
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parameter e2_ph = 0;
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parameter e3_ph = 0;
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parameter m_ph = 0;
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parameter l0_time_delay = 0;
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parameter l1_time_delay = 0;
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parameter g0_time_delay = 0;
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parameter g1_time_delay = 0;
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parameter g2_time_delay = 0;
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parameter g3_time_delay = 0;
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parameter e0_time_delay = 0;
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parameter e1_time_delay = 0;
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parameter e2_time_delay = 0;
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parameter e3_time_delay = 0;
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parameter m_time_delay = 0;
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parameter n_time_delay = 0;
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parameter extclk3_counter = "e3" ;
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parameter extclk2_counter = "e2" ;
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parameter extclk1_counter = "e1" ;
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parameter extclk0_counter = "e0" ;
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parameter clk9_counter = "c9" ;
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parameter clk8_counter = "c8" ;
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parameter clk7_counter = "c7" ;
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parameter clk6_counter = "c6" ;
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parameter clk5_counter = "l1" ;
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parameter clk4_counter = "l0" ;
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parameter clk3_counter = "g3" ;
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parameter clk2_counter = "g2" ;
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parameter clk1_counter = "g1" ;
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parameter clk0_counter = "g0" ;
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parameter enable0_counter = "l0";
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parameter enable1_counter = "l0";
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parameter charge_pump_current = 2;
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parameter loop_filter_r = "1.0";
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parameter loop_filter_c = 5;
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parameter vco_post_scale = 0;
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parameter vco_frequency_control = "AUTO";
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parameter vco_phase_shift_step = 0;
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parameter lpm_type = "altpll";
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parameter port_clkena0 = "PORT_CONNECTIVITY";
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parameter port_clkena1 = "PORT_CONNECTIVITY";
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parameter port_clkena2 = "PORT_CONNECTIVITY";
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parameter port_clkena3 = "PORT_CONNECTIVITY";
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parameter port_clkena4 = "PORT_CONNECTIVITY";
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parameter port_clkena5 = "PORT_CONNECTIVITY";
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parameter port_extclkena0 = "PORT_CONNECTIVITY";
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parameter port_extclkena1 = "PORT_CONNECTIVITY";
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parameter port_extclkena2 = "PORT_CONNECTIVITY";
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parameter port_extclkena3 = "PORT_CONNECTIVITY";
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parameter port_extclk0 = "PORT_CONNECTIVITY";
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parameter port_extclk1 = "PORT_CONNECTIVITY";
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parameter port_extclk2 = "PORT_CONNECTIVITY";
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parameter port_extclk3 = "PORT_CONNECTIVITY";
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parameter port_clk0 = "PORT_CONNECTIVITY";
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parameter port_clk1 = "PORT_CONNECTIVITY";
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parameter port_clk2 = "PORT_CONNECTIVITY";
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parameter port_clk3 = "PORT_CONNECTIVITY";
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parameter port_clk4 = "PORT_CONNECTIVITY";
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parameter port_clk5 = "PORT_CONNECTIVITY";
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parameter port_clk6 = "PORT_CONNECTIVITY";
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parameter port_clk7 = "PORT_CONNECTIVITY";
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parameter port_clk8 = "PORT_CONNECTIVITY";
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parameter port_clk9 = "PORT_CONNECTIVITY";
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parameter port_scandata = "PORT_CONNECTIVITY";
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parameter port_scandataout = "PORT_CONNECTIVITY";
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parameter port_scandone = "PORT_CONNECTIVITY";
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parameter port_sclkout1 = "PORT_CONNECTIVITY";
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parameter port_sclkout0 = "PORT_CONNECTIVITY";
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parameter port_clkbad0 = "PORT_CONNECTIVITY";
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parameter port_clkbad1 = "PORT_CONNECTIVITY";
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parameter port_activeclock = "PORT_CONNECTIVITY";
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parameter port_clkloss = "PORT_CONNECTIVITY";
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parameter port_inclk1 = "PORT_CONNECTIVITY";
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parameter port_inclk0 = "PORT_CONNECTIVITY";
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parameter port_fbin = "PORT_CONNECTIVITY";
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parameter port_fbout = "PORT_CONNECTIVITY";
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parameter port_pllena = "PORT_CONNECTIVITY";
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parameter port_clkswitch = "PORT_CONNECTIVITY";
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parameter port_areset = "PORT_CONNECTIVITY";
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parameter port_pfdena = "PORT_CONNECTIVITY";
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parameter port_scanclk = "PORT_CONNECTIVITY";
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parameter port_scanaclr = "PORT_CONNECTIVITY";
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parameter port_scanread = "PORT_CONNECTIVITY";
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parameter port_scanwrite = "PORT_CONNECTIVITY";
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parameter port_enable0 = "PORT_CONNECTIVITY";
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parameter port_enable1 = "PORT_CONNECTIVITY";
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parameter port_locked = "PORT_CONNECTIVITY";
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parameter port_configupdate = "PORT_CONNECTIVITY";
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parameter port_phasecounterselect = "PORT_CONNECTIVITY";
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parameter port_phasedone = "PORT_CONNECTIVITY";
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parameter port_phasestep = "PORT_CONNECTIVITY";
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parameter port_phaseupdown = "PORT_CONNECTIVITY";
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parameter port_vcooverrange = "PORT_CONNECTIVITY";
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parameter port_vcounderrange = "PORT_CONNECTIVITY";
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parameter port_scanclkena = "PORT_CONNECTIVITY";
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parameter using_fbmimicbidir_port = "ON";
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input [1:0] inclk;
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input fbin;
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input pllena;
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input clkswitch;
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input areset;
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input pfdena;
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input clkena;
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input extclkena;
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input scanclk;
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input scanaclr;
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input scanclkena;
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input scanread;
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input scanwrite;
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input scandata;
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input phasecounterselect;
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input phaseupdown;
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input phasestep;
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input configupdate;
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inout fbmimicbidir;
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output [width_clock-1:0] clk;
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output [3:0] extclk;
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output [1:0] clkbad;
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output enable0;
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output enable1;
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output activeclock;
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output clkloss;
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output locked;
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output scandataout;
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output scandone;
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output sclkout0;
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output sclkout1;
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output phasedone;
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output vcooverrange;
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output vcounderrange;
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output fbout;
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output fref;
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output icdrclk;
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output c0, c1, c2, c3, c4;
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endmodule // altpll
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`endif
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