riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenFPGA/openfpga
History
tangxifan f79da76656 [core] supporting renaming on all the verilog modules 2023-09-17 17:29:11 -07:00
..
src [core] supporting renaming on all the verilog modules 2023-09-17 17:29:11 -07:00
CMakeLists.txt [lib] rename lib to namemanager as a unified library to provide naming support on FPGA modules 2023-09-15 13:51:14 -07:00