OpenFPGA/openfpga/test_openfpga_arch
tangxifan e6c896d583 now inout must be global port and I/O port so that it will appear in the top-level module 2020-04-08 16:54:08 -06:00
..
k6_N10_40nm_openfpga.xml now inout must be global port and I/O port so that it will appear in the top-level module 2020-04-08 16:54:08 -06:00
k6_frac_N10_40nm_openfpga.xml now inout must be global port and I/O port so that it will appear in the top-level module 2020-04-08 16:54:08 -06:00
k6_frac_N10_adder_chain_40nm_openfpga.xml now inout must be global port and I/O port so that it will appear in the top-level module 2020-04-08 16:54:08 -06:00
k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml now inout must be global port and I/O port so that it will appear in the top-level module 2020-04-08 16:54:08 -06:00
k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml now inout must be global port and I/O port so that it will appear in the top-level module 2020-04-08 16:54:08 -06:00
k6_frac_N10_adder_column_chain_40nm_openfpga.xml now inout must be global port and I/O port so that it will appear in the top-level module 2020-04-08 16:54:08 -06:00
k6_frac_N10_adder_register_chain_40nm_openfpga.xml now inout must be global port and I/O port so that it will appear in the top-level module 2020-04-08 16:54:08 -06:00
k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml now inout must be global port and I/O port so that it will appear in the top-level module 2020-04-08 16:54:08 -06:00
k6_frac_N10_spyio_40nm_openfpga.xml now inout must be global port and I/O port so that it will appear in the top-level module 2020-04-08 16:54:08 -06:00
k6_frac_N10_stdcell_mux_40nm_openfpga.xml now inout must be global port and I/O port so that it will appear in the top-level module 2020-04-08 16:54:08 -06:00
k6_frac_N10_tree_mux_40nm_openfpga.xml now inout must be global port and I/O port so that it will appear in the top-level module 2020-04-08 16:54:08 -06:00