103 lines
4.7 KiB
Bash
Executable File
103 lines
4.7 KiB
Bash
Executable File
#!/bin/bash
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source .travis/common.sh
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set -e
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start_section "OpenFPGA.build" "${GREEN}Building..${NC}"
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mkdir build
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cd build
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if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
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cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off
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else
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cmake .. -DCMAKE_BUILD_TYPE=debug
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fi
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make -j16
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end_section "OpenFPGA.build"
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start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
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cd -
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###############################################
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# OpenFPGA with VPR7
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# TO BE DEPRECATED
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##############################################
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echo -e "Testing single-mode architectures";
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python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs
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#python3 openfpga_flow/scripts/run_fpga_task.py s298
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echo -e "Testing multi-mode architectures";
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python3 openfpga_flow/scripts/run_fpga_task.py multi_mode --maxthreads 4 --debug --show_thread_logs
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echo -e "Testing compact routing techniques";
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python3 openfpga_flow/scripts/run_fpga_task.py compact_routing --debug --show_thread_logs
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echo -e "Testing tileable architectures";
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python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing --debug --show_thread_logs
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echo -e "Testing Verilog generation with explicit port mapping ";
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python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog --debug --show_thread_logs
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echo -e "Testing Verilog generation with grid pin duplication ";
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python3 openfpga_flow/scripts/run_fpga_task.py duplicate_grid_pin --debug --show_thread_logs
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###############################################
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# OpenFPGA Shell with VPR8
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# (Will replace all the old tests)
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##############################################
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echo -e "Testing OpenFPGA Shell";
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echo -e "Testing configuration chain of a K4N4 FPGA";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/configuration_chain --debug --show_thread_logs
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echo -e "Testing Verilog generation with simple fracturable LUT6 ";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/frac_lut --debug --show_thread_logs
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echo -e "Testing Verilog generation with VPR's untileable routing architecture ";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/untileable --debug --show_thread_logs
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echo -e "Testing Verilog generation with hard adder chain in CLBs ";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/hard_adder --debug --show_thread_logs
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echo -e "Testing Verilog generation with 16k block RAMs ";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/bram/dpram16k --debug --show_thread_logs
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echo -e "Testing Verilog generation with 16k block RAMs spanning two columns ";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/bram/wide_dpram16k --debug --show_thread_logs
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echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA ";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/io/multi_io_capacity --debug --show_thread_logs
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echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA ";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/io/reduced_io --debug --show_thread_logs
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echo -e "Testing Verilog generation with adder chain across an FPGA";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_chain/adder_chain --debug --show_thread_logs
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echo -e "Testing Verilog generation with shift register chain across an FPGA";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_chain/register_chain --debug --show_thread_logs
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echo -e "Testing Verilog generation with scan chain across an FPGA";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_chain/scan_chain --debug --show_thread_logs
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echo -e "Testing Verilog generation with routing mutliplexers implemented by tree structure";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/mux_design/tree_structure --debug --show_thread_logs
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echo -e "Testing Verilog generation with routing mutliplexers implemented by standard cell MUX2";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/mux_design/stdcell_mux2 --debug --show_thread_logs
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echo -e "Testing Verilog generation with behavioral description";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/behavioral_verilog --debug --show_thread_logs
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echo -e "Testing implicit Verilog generation";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/implicit_verilog --debug --show_thread_logs
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echo -e "Testing Verilog generation with flatten routing modules";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/flatten_routing --debug --show_thread_logs
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echo -e "Testing Verilog generation with duplicated grid output pins";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/duplicated_grid_pin --debug --show_thread_logs
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end_section "OpenFPGA.TaskTun"
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