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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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f4e017f06c
OpenFPGA
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openfpga_flow
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tasks
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fpga_verilog
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adder
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tangxifan
12d114bbae
[test] hit the bug of tileable rr_graph skip it
2022-11-05 10:52:04 -07:00
..
hard_adder
/config
[test] hit the bug of tileable rr_graph skip it
2022-11-05 10:52:04 -07:00
soft_adder
/config
[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases
2022-09-29 10:45:27 -07:00