244 lines
6.4 KiB
C++
244 lines
6.4 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/sigtools.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SetundefWorker
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{
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int next_bit_mode;
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uint32_t next_bit_state;
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RTLIL::State next_bit()
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{
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if (next_bit_mode == 0)
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return RTLIL::State::S0;
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if (next_bit_mode == 1)
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return RTLIL::State::S1;
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// xorshift32
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next_bit_state ^= next_bit_state << 13;
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next_bit_state ^= next_bit_state >> 17;
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next_bit_state ^= next_bit_state << 5;
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log_assert(next_bit_state != 0);
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return ((next_bit_state >> (next_bit_state & 15)) & 16) ? RTLIL::State::S0 : RTLIL::State::S1;
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}
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void operator()(RTLIL::SigSpec &sig)
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{
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for (auto &bit : sig)
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if (bit.wire == NULL && bit.data > RTLIL::State::S1)
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bit = next_bit();
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}
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};
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struct SetundefPass : public Pass {
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SetundefPass() : Pass("setundef", "replace undef values with defined constants") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" setundef [options] [selection]\n");
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log("\n");
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log("This command replaced undef (x) constants with defined (0/1) constants.\n");
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log("\n");
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log(" -undriven\n");
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log(" also set undriven nets to constant values\n");
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log("\n");
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log(" -zero\n");
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log(" replace with bits cleared (0)\n");
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log("\n");
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log(" -one\n");
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log(" replace with bits set (1)\n");
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log("\n");
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log(" -random <seed>\n");
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log(" replace with random bits using the specified integer als seed\n");
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log(" value for the random number generator.\n");
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log("\n");
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log(" -init\n");
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log(" also create/update init values for flip-flops\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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bool got_value = false;
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bool undriven_mode = false;
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bool init_mode = false;
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SetundefWorker worker;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-undriven") {
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undriven_mode = true;
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continue;
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}
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if (args[argidx] == "-zero") {
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got_value = true;
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worker.next_bit_mode = 0;
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continue;
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}
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if (args[argidx] == "-one") {
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got_value = true;
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worker.next_bit_mode = 1;
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continue;
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}
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if (args[argidx] == "-init") {
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init_mode = true;
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continue;
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}
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if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) {
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got_value = true;
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worker.next_bit_mode = 2;
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worker.next_bit_state = atoi(args[++argidx].c_str()) + 1;
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for (int i = 0; i < 10; i++)
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worker.next_bit();
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!got_value)
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log_cmd_error("One of the options -zero, -one, or -random <seed> must be specified.\n");
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for (auto module : design->selected_modules())
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{
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if (undriven_mode)
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{
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if (!module->processes.empty())
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log_error("The 'setundef' command can't operate in -undriven mode on modules with processes. Run 'proc' first.\n");
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SigMap sigmap(module);
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SigPool undriven_signals;
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for (auto &it : module->wires_)
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if (!it.second->port_input)
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undriven_signals.add(sigmap(it.second));
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CellTypes ct(design);
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for (auto &it : module->cells_)
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for (auto &conn : it.second->connections())
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if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
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undriven_signals.del(sigmap(conn.second));
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RTLIL::SigSpec sig = undriven_signals.export_all();
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for (auto &c : sig.chunks()) {
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RTLIL::SigSpec bits;
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for (int i = 0; i < c.width; i++)
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bits.append(worker.next_bit());
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module->connect(RTLIL::SigSig(c, bits));
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}
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}
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if (init_mode)
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{
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SigMap sigmap(module);
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pool<SigBit> ffbits;
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pool<Wire*> initwires;
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pool<IdString> fftypes;
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fftypes.insert("$dff");
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fftypes.insert("$dffe");
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fftypes.insert("$dffsr");
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fftypes.insert("$adff");
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std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};
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for (auto c1 : list_np)
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fftypes.insert(stringf("$_DFF_%c_", c1));
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for (auto c1 : list_np)
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for (auto c2 : list_np)
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fftypes.insert(stringf("$_DFFE_%c%c_", c1, c2));
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for (auto c1 : list_np)
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for (auto c2 : list_np)
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for (auto c3 : list_01)
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fftypes.insert(stringf("$_DFF_%c%c%c_", c1, c2, c3));
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for (auto c1 : list_np)
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for (auto c2 : list_np)
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for (auto c3 : list_np)
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fftypes.insert(stringf("$_DFFSR_%c%c%c_", c1, c2, c3));
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for (auto cell : module->cells())
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{
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if (!fftypes.count(cell->type))
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continue;
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for (auto bit : sigmap(cell->getPort("\\Q")))
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ffbits.insert(bit);
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}
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for (auto wire : module->wires())
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{
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if (!wire->attributes.count("\\init"))
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continue;
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for (auto bit : sigmap(wire))
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ffbits.erase(bit);
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initwires.insert(wire);
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}
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for (int wire_types = 0; wire_types < 2; wire_types++)
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for (auto wire : module->wires())
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{
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if (wire->name[0] == (wire_types ? '\\' : '$'))
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next_wire:
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continue;
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for (auto bit : sigmap(wire))
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if (!ffbits.count(bit))
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goto next_wire;
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for (auto bit : sigmap(wire))
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ffbits.erase(bit);
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initwires.insert(wire);
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}
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for (auto wire : initwires)
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{
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Const &initval = wire->attributes["\\init"];
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for (int i = 0; i < GetSize(wire); i++)
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if (GetSize(initval) <= i)
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initval.bits.push_back(worker.next_bit());
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else if (initval.bits[i] == State::Sx)
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initval.bits[i] = worker.next_bit();
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}
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}
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module->rewrite_sigspecs(worker);
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}
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}
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} SetundefPass;
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PRIVATE_NAMESPACE_END
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