OpenFPGA/openfpga_flow/tasks/fpga_verilog/mux_design
tangxifan efdb8bf441 [test] use fixed route chan width to avoid the bug on vpr which failed routing on min chan width condition 2024-10-07 17:14:11 -07:00
..
const_input_gnd/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
debuf_mux/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
inbuf_only_mux/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
local_encoder/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
no_const_input/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
outbuf_only_mux/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
stdcell_mux2/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
stdcell_mux2_last_stage/config [test] use fixed route chan width to avoid the bug on vpr which failed routing on min chan width condition 2024-10-07 17:14:11 -07:00
tree_structure/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00