48 lines
1.5 KiB
C++
48 lines
1.5 KiB
C++
/********************************************************************
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* Unit test functions to validate the correctness of
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* 1. parser of data structures
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* 2. writer of data structures
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*******************************************************************/
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/* Headers from vtrutils */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from readarchopenfpga */
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#include "read_xml_clock_network.h"
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#include "write_xml_clock_network.h"
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int main(int argc, const char** argv) {
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/* Ensure we have only one or two argument */
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VTR_ASSERT((2 == argc) || (3 == argc));
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/* Parse the circuit library from an XML file */
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openfpga::ClockNetwork clk_ntwk = openfpga::read_xml_clock_network(argv[1]);
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VTR_LOG("Parsed %lu clock tree(s) from XML into clock network.\n",
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clk_ntwk.trees().size());
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/* Validate before write out */
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if (!clk_ntwk.link()) {
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VTR_LOG_ERROR("Invalid clock network when linking.\n");
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exit(1);
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}
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if (!clk_ntwk.validate()) {
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VTR_LOG_ERROR("Invalid clock network.\n");
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exit(1);
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}
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VTR_ASSERT(clk_ntwk.is_valid());
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for (auto tree_id : clk_ntwk.trees()) {
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VTR_LOG("Max. depth of the clock tree '%lu' is %d\n", size_t(tree_id),
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clk_ntwk.tree_depth(tree_id));
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}
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/* Output the bus group to an XML file
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* This is optional only used when there is a second argument
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*/
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if (3 <= argc) {
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openfpga::write_xml_clock_network(argv[2], clk_ntwk);
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VTR_LOG("Write the clock network to an XML file: %s.\n", argv[2]);
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}
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return 0;
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}
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