394 lines
16 KiB
ReStructuredText
394 lines
16 KiB
ReStructuredText
.. _file_formats_clock_network:
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Clock Network (.xml)
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--------------------
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The XML-based clock network description language is used to describe
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- One or more programmable clock networks constaining programmable switches for routing clock signals
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- The routing for clock signals on the programmable clock network
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Using the clock network description language, users can define multiple clock networks, each of which consists:
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- A number of clock spines which can propagate clock signals from one point to another. See details in :ref:`file_formats_clock_network_clock_spine`.
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- A number of switch points which interconnects clock spines using programmable routing switches. See details in :ref:`file_formats_clock_network_switch_point`.
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- A number of tap points which connect the clock spines to programmable blocks, e.g., CLBs. See details in :ref:`file_formats_clock_network_tap_point`.
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The entry point of a clock tree must be at a valid connection block.
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.. note:: Please note that the levels of a clock network will be automatically inferred from the clock spines and switch points. Clock network will be **only** built based on the width and the number of levels, as well as the tap points.
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.. note:: The switch points and clock spines will be used to route a clock network. The switch points will not impact the physical clock network but only impact the configuration of the programmable routing switches in the physical clock network.
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.. warning:: Clock network is a feature for power-users. It requires additional EDA support to leverage the best performance of the clock network, as timing analysis and convergence is more challenging.
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.. code-block:: xml
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<clock_networks default_segment="<string>" default_tap_switch="<string>" default_driver_switch="<string>">
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<clock_network name="<string>" global_port="<int>">
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<spine name="<string>" start_x="<int>" start_y="<int>" end_x="<int>" end_y="<int>">
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<intermediate_driver x="<int>" y="<int>">
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<tap from_pin="<string>" to_pin="<string>"/>
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</intermediate_driver>
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<switch_point tap="<string>" x="<int>" y="<int>">
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<internal_driver from_pin="<string>" to_pin="<string>"/>
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</switch_point>
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</spine>
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<taps>
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<all from_pin="<string>" to_pin="<string>"/>
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<region from_pin="<string>" to_pin="<string>" start_x="<int>" start_y="<int>" end_x="<int>" end_y="<int>" repeat_x="<int>" repeat_y="<int>"/>
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<single from_pin="<string>" to_pin="<string>" x="<int>" y="<int>"/>
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</taps>
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</clock_network>
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</clock_networks>
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.. _fig_prog_clock_network_example_2x2:
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.. figure:: figures/prog_clk_network_example_2x2.png
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:width: 100%
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:alt: An example of programmable clock network considering a 2x2 FPGA fabric
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An example of programmable clock network considering a 2x2 FPGA fabric
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Note that when the ``perimeter_cb`` is enabled for routing architecture (See details in :ref:`addon_vpr_syntax`), clock entry point can be indeed at the fringe of FPGA fabrics. See example in :numref:`prog_clock_network_example_2x2_perimeter_cb`.
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.. _fig_prog_clock_network_example_2x2_perimeter_cb:
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.. figure:: figures/prog_clk_network_example_2x2_perimeter_cb.png
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:width: 100%
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:alt: An example of programmable clock network considering a 2x2 FPGA fabric with perimeter cb
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An example of programmable clock network considering a 2x2 FPGA fabric with perimeter cb
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General Settings
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^^^^^^^^^^^^^^^^
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The following syntax are applicable to the XML definition under the root node ``clock_networks``
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.. option:: default_segment="<string>"
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Define the default routing segment to be used when building the routing tracks for the clock network. The routing segments are used to build the spines of clock networks as shown in :numref:`fig_prog_clock_network_example_2x2`. Must be a valid routing segment defined in the VPR architecture file. For example,
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.. code-block:: xml
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default_segment="L1"
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where the segment is defined in the VPR architecture file:
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.. code-block:: xml
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<segmentlist>
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<segment name="L1" freq="1" length="1" type="undir"/>
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</segmentlist>
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.. note:: Currently, clock network requires only length-1 wire segment to be used!
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.. option:: default_tap_switch="<string>"
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Define the default routing switch to be used when interconnects the routing tracks to the input pins of programmable blocks in the clock network. The tap switches are used to build the taps of clock networks as shown in :numref:`fig_prog_clock_network_example_2x2`. Must be a valid routing switch defined in the VPR architecture file. See the example in the ``default_driver_switch``.
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.. option:: default_driver_switch="<string>"
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.. note:: For internal drivers, suggest to use the same driver switch for the output pins of a programmable block as defined in VPR architecture.
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Define the default routing switch to be used when interconnects the routing tracks in the clock network. The driver switches are used to build the switch points of clock networks as shown in :numref:`fig_prog_clock_network_example_2x2`. Must be a valid routing switch defined in the VPR architecture file. For example,
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.. code-block:: xml
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default_tap_switch="cb_mux" default_driver_switch="sb_clk_mux"
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where the switch is defined in the VPR architecture file:
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.. code-block:: xml
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<switchlist>
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<switch type="mux" name="cb_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
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<switch type="mux" name="sb_clk_mux" R="55" Cin=".7e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
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</switchlist>
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.. note:: Currently, clock network only supports the default types of routing switch, which means all the programmable routing switch in the clock network will be in the same type and circuit design topology.
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Clock Network Settings
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^^^^^^^^^^^^^^^^^^^^^^
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The following syntax are applicable to the XML definition tagged by ``clock_network``.
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Note that a number of clock networks can be defined under the root node ``clock_networks``.
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.. option:: name="<string>"
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The unique name of the clock network. It will be used to link the clock network to a specific global port in :ref:`annotate_vpr_arch_physical_tile_annotation`. For example,
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.. code-block:: xml
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name="clk_tree_0"
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where the clock network is used to drive the global clock pin ``clk0`` in OpenFPGA's architecture description file:
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.. code-block:: xml
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<tile_annotations>
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<global_port name="clk0" is_clock="true" clock_arch_tree_name="clk_tree_0" default_val="0">
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<tile name="clb" port="clk[0:0]"/>
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</global_port>
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</tile_annotations>
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.. option:: global_port="<string>"
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.. note:: When programmable clock network is specified for a global port in OpenFPGA architecure description file, the width of clock tree will be the final size of the global port.
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Define the source port of the clock network. For example, ``clk[0:7]``. Note that the global port name should match
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- the ``from_pin`` when defining the tap points (See details in :ref:`file_formats_clock_network_clock_tap_point`).
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- the ``name`` of global port definition in OpenFPGA architecture description file
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.. _file_formats_clock_network_clock_spine:
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Clock Spine Settings
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^^^^^^^^^^^^^^^^^^^^
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The following syntax are applicable to the XML definition tagged by ``spine``.
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Note that a number of clock spines can be defined under the node ``clock_network``.
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.. note:: Use coordinates of connection blocks to define the starting and ending points of clock spines.
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.. option:: name="<string>"
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The unique name of the clock spine. It will be used to build switch points between other clock spines.
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.. option:: start_x="<int>"
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The coordinate X of the starting point of the clock spine.
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.. option:: start_y="<int>"
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The coordinate Y of the starting point of the clock spine.
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.. option:: end_x="<int>"
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The coordinate X of the ending point of the clock spine.
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.. option:: end_y="<int>"
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The coordinate Y of the ending point of the clock spine.
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For example,
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.. code-block:: xml
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<spine name="spine0" start_x="1" start_y="1" end_x="2" end_y="1"/>
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where a horizental clock spine ``spine0`` is defined which spans from (1, 1) to (2, 1), as highlighted in orange in the :numref:`fig_prog_clock_network_example_2x2`
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.. note:: We only support clock spines in horizental and vertical directions. Diagonal clock spine is not supported!
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.. _file_formats_clock_network_intermediate_driver:
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Intermediate Driver
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^^^^^^^^^^^^^^^^^^^
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The following syntax are applicable to the XML definition tagged by ``intermediate_driver``
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Note that a number of intermediate drivers can be defined under each clock spine ``spine``.
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.. option:: x="<int>"
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The coordinate X where the intermediate driver should occur on the spine. Must be a valid coordinate within the range of the current clock spine and the clock spine to be tapped.
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.. option:: y="<int>"
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The coordinate Y where the intermediate driver should occur on the spine. Must be a valid coordinate within the range of the current clock spine and the clock spine to be tapped.
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.. note:: The intermeidate driver is different than the internal driver (see details in :ref:`file_formats_clock_network_switch_point`). Intermediate driver may occur in any mid points of a spine, while internal driver occurs **ONLY** on the switch points between spines.
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Under each intermediate driver, a number of tap points can be specified.
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For each tap point, outputs of neighbouring programmable blocks are allowed to drive the spine through syntax ``tap``.
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.. option:: from_pin="<string>"
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Define the pin of a programmable block as an internal driver to a clock network. The pin must be a valid pin defined in the VPR architecture description file.
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.. option:: to_pin="<string>"
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Define the source pin of a clock network. The pin must be a valid pin of the global ports defined in the tile_annotation part of OpenFPGA architecture description file.
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For example,
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.. code-block:: xml
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<clock_network name="clk_tree_0" global_port="clk[0:1]">
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<!-- Some clock spines -->
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<spine name="spine0" start_x="1" start_y="1" end_x="2" end_y="1">
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<intermediate_driver x="1" y="1">
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<tap from_pin="clb.O[0:1]" to_pin="clk[0:0]"/>
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</intermediate_driver>
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<spine>
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</clock_network>
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where clock spine ``spine0`` will be driven by other programmable blocks at (1, 1), as highlighted in purple in the :numref:`fig_prog_clock_network_example_2x2_perimeter_cb`
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To be specific, the clock routing can be driven at (x=1,y=1) by the output pins ``O[0:3]`` of tile ``clb`` in a VPR architecture description file:
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.. code-block:: xml
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<tile name="clb">
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<sub_tile name="clb">
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<output name="O" num_pins="8"/>
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</sub_tile>
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</tile>
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.. _file_formats_clock_network_switch_point:
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Switch Point Settings
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^^^^^^^^^^^^^^^^^^^^^
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The following syntax are applicable to the XML definition tagged by ``switch_point``.
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Note that a number of switch points can be defined under each clock spine ``spine``.
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.. note:: Use the coordinate of switch block to define switching points!
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.. option:: tap="<string>"
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Define which clock spine will be tapped from the current clock spine.
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.. option:: x="<int>"
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The coordinate X of the switch point. Must be a valid coordinate within the range of the current clock spine and the clock spine to be tapped.
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.. option:: y="<int>"
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The coordinate Y of the switch point. Must be a valid coordinate within the range of the current clock spine and the clock spine to be tapped.
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For example,
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.. code-block:: xml
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<spine name="spine0" start_x="1" start_y="1" end_x="2" end_y="1">
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<switch_point tap="spine1" x="1" y="1"/>
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<spine>
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where clock spine ``spine0`` will drive another clock spine ``spine1`` at (1, 1), as highlighted in blue in the :numref:`fig_prog_clock_network_example_2x2`
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For each switch point, outputs of neighbouring programmable blocks are allowed to drive the spine at next level, through syntax ``internal_driver``.
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.. option:: from_pin="<string>"
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Define the pin of a programmable block as an internal driver to a clock network. The pin must be a valid pin defined in the VPR architecture description file.
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.. option:: to_pin="<string>"
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Define the source pin of a clock network. The pin must be a valid pin of the global ports defined in the tile_annotation part of OpenFPGA architecture description file.
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For example,
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.. code-block:: xml
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<clock_network name="clk_tree_0" global_port="clk[0:1]">
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<!-- Some clock spines -->
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<spine name="spine0" start_x="1" start_y="1" end_x="2" end_y="1">
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<switch_point tap="spine1" x="1" y="1">
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<internal_driver from_pin="clb.O[0:1]" to_pin="clk[0:0]"/>
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</switch_point>
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<spine>
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</clock_network>
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where the clock routing can be driven at (x=1,y=1) by the output pins ``O[0:3]`` of tile ``clb`` in a VPR architecture description file:
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.. code-block:: xml
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<tile name="clb">
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<sub_tile name="clb">
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<output name="O" num_pins="8"/>
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</sub_tile>
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</tile>
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.. _file_formats_clock_network_tap_point:
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Tap Point Settings
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^^^^^^^^^^^^^^^^^^
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The following syntax are applicable to the XML definition tagged by ``all``, ``region`` and ``single``.
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Note that a number of tap points can be defined under the node ``taps``.
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.. option:: from_pin="<string>"
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Define the source pin of a programmable block to be tapped by a clock network. The pin must be a valid pin of the global ports defined in the tile_annotation part of OpenFPGA architecture description file.
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.. option:: to_pin="<string>"
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Define the destination pin of a programmable block to be tapped by a clock network. The pin must be a valid pin defined in the VPR architecture description file.
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.. note:: Only the leaf clock spine (not switch points to drive other clock spine) can tap pins of programmable blocks.
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.. note:: Each coordinate must be a valid integer within the device height and width that are defined in VPR architecture!!!
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.. warning:: The following syntax are only applicable to ``single`` tap mode.
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.. option:: x="<int>"
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Define the x coordinate of the tap point, which is applied to the destination pin ``to_pin``
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.. option:: y="<int>"
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Define the y coordinate of the tap point, which is applied to the destination pin ``to_pin``
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.. warning:: The following syntax are only applicable to ``region`` tap mode.
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.. option:: start_x="<int>"
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Define the starting x coordinate of the tap region, which is applied to the destination pin ``to_pin``
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.. option:: start_y="<int>"
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Define the starting y coordinate of the tap region, which is applied to the destination pin ``to_pin``
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.. option:: end_x="<int>"
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Define the ending x coordinate of the tap region, which is applied to the destination pin ``to_pin``
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.. option:: end_y="<int>"
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Define the ending y coordinate of the tap region, which is applied to the destination pin ``to_pin``
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.. option:: repeat_x="<int>"
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Define the repeating factor on x coordinate of the tap region, which is applied to the destination pin ``to_pin``
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.. option:: repeat_y="<int>"
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Define the repeating factor on y coordinate of the tap region, which is applied to the destination pin ``to_pin``
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For example,
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.. code-block:: xml
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<clock_network name="clk_tree_0" global_port="clk[0:1]">
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<!-- Some clock spines -->
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<taps>
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<all from_pin="clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
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<region from_pin="clk[1:1]" to_pin="clb[1:1].clk[1:1]" start_x="1" start_y="1" end_x="4" end_y="4" repeat_x="2" repeat_y="2"/>
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<single from_pin="clk[1:1]" to_pin="clb[2:2].clk[1:1]" x="2" y="2"/>
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</taps>
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</clock_network>
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where all the clock spines of the clock network ``clk_tree_0`` tap the clock pins ``clk`` of tile ``clb`` in a VPR architecture description file:
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.. note:: Use the name of ``tile`` in the ``to_pin`` when there are a number of subtiles in your tile! Use the absolute index for the subtile in the tile.
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.. code-block:: xml
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<tile name="clb">
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<!-- subtile index ranges [0:0] -->
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<sub_tile name="clbM" capacity="1">
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<clock name="clk" num_pins="2"/>
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</sub_tile>
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<!-- subtile index ranges [1:2] -->
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<sub_tile name="clbA" capacity="2">
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<clock name="clk" num_pins="2"/>
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</sub_tile>
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</tile>
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