205 lines
8.0 KiB
ReStructuredText
205 lines
8.0 KiB
ReStructuredText
.. _file_formats_bitstream_setting:
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Bitstream Setting (.xml)
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------------------------
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An example of bitstream settings is shown as follows.
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This can define a hard-coded bitstream for a reconfigurable resource in FPGA fabrics.
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.. warning:: Bitstream setting is a feature for power-users. It may cause wrong bitstream to be generated. For example, the hard-coded bitstream is not compatible with LUTs whose nets may be swapped during routing stage (cause a change on the truth table as well as bitstream). It is users's responsibility to ensure correct bitstream.
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.. code-block:: xml
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<openfpga_bitstream_setting>
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<pb_type name="<string>" source="eblif" content=".param LUT" is_mode_select_bistream="true" bitstream_offset="1"/>
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<default_mode_bits name="<string>" mode_bits="<string>"/>
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<interconnect name="<string>" default_path="<string>"/>
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<clock_routing network="<string>" pin="<string>"/>
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<non_fabric name="<string>" file="<string>">
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<pb name="<string>" type="<string>" content="<string>"/>
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</non_fabric>
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<overwrite_bitstream>
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<bit value="<0 or 1>" path="<string>"/>
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</overwrite_bitstream>
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</openfpga_bitstream_setting>
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pb_type-related Settings
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^^^^^^^^^^^^^^^^^^^^^^^^
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The following syntax are applicable to the XML definition tagged by ``pb_type`` in bitstream setting files.
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.. option:: name="<string>"
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The ``pb_type`` name to be constrained, which should be the full path of a ``pb_type`` consistent with VPR's architecture description. For example,
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.. code-block:: xml
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pb_type="clb.fle[arithmetic].soft_adder.adder_lut4"
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.. option:: source="<string>"
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The source of the ``pb_type`` bitstream, which could be from a ``.eblif`` file. For example,
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.. code-block:: xml
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source="eblif"
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.. option:: content="<string>"
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The content of the ``pb_type`` bitstream, which could be a keyword in a ``.eblif`` file. For example, ``content=".attr LUT"`` means that the bitstream will be extracted from the ``.attr LUT`` line which is defined under the ``.blif model`` (that is defined under the ``pb_type`` in VPR architecture file).
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.. option:: is_mode_select_bitstream="<bool>"
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Can be either ``true`` or ``false``. When set ``true``, the bitstream is considered as mode-selection bitstream, which may overwrite ``mode_bits`` definition in ``pb_type_annotation`` of OpenFPGA architecture description. (See details in :ref:`annotate_vpr_arch_pb_type_annotation`)
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.. option:: bitstream_offset="<int>"
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Specify the offset to be applied when overloading the bitstream to a target. For example, a LUT may have a 16-bit bitstream. When ``offset=1``, bitstream overloading will skip the first bit and start from the second bit of the 16-bit bitstream.
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Default Mode Bits-related Settings
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following syntax are applicable to the XML definition tagged by ``default_mode_bits`` in bitstream setting files.
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.. option:: name="<string>"
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The ``pb_type`` name to be constrained, which should be the full path of a ``pb_type`` consistent with VPR's architecture description. For example,
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.. note:: This must be a valid primitive pb_type (one has zero leaf nodes)!
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.. code-block:: xml
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pb_type="clb.fle[arithmetic].soft_adder.adder_lut4"
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.. option:: mode_bits="<string>"
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The default mode bits when the ``pb_type`` is not mapped. Note that the size of mode bits must comply with the definition in the OpenFPGA architecture description (See details in :ref:`annotate_vpr_arch_pb_type_annotation`). For example,
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.. note:: Bitstream setting has a higher priority than the ``mode_bits`` definition in the OpenFPGA architecture description!
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.. code-block:: xml
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mode_bits="0100"
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Interconnection-related Settings
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following syntax are applicable to the XML definition tagged by ``interconnect`` in bitstream setting files.
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.. option:: name="<string>"
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The ``interconnect`` name to be constrained, which should be the full path of a ``pb_type`` consistent with VPR's architecture description. For example,
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.. code-block:: xml
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pb_type="clb.fle[arithmetic].mux1"
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.. option:: default_path="<string>"
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The default path denotes an input name that is consistent with VPR's architecture description. For example, in VPR architecture, there is a mux defined as
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.. code-block:: xml
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<mux name="mux1" input="iopad.inpad ff.Q" output="io.inpad"/>
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The default path can be either ``iopad.inpad`` or ``ff.Q`` which corresponds to the first input and the second input respectively.
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Clock Routing-related Settings
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following syntax are applicable to the XML definition tagged by ``clock_routing`` in bitstream setting files.
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This is to force the routing for clock tap multiplexers (green line in :numref:`fig_prog_clock_network_example_2x2`) even when they are not used/mapped. If no specified, only the used clock tap multiplexers will be configured to propagate clock signals.
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.. note:: This requires the benchmark has at least 1 global signal. Otherwise, the clock routing will be skipped, and there is no impact from this setting.
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.. option:: network="<string>"
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The ``network`` name to be constrained, which should be a valid name defined in the clock network file (See details in :ref:`file_formats_clock_network`). For example,
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.. code-block:: xml
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<clock_routing network="clk_tree_2lvl" pin="clk[0:0]"/>
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<clock_routing network="rst_tree_2lvl" pin="rst[1:1]"/>
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The network and pin correspond to the clock network name and a valid pin of ``global_port`` in the clock network description.
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.. code-block:: xml
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<clock_network name="clk_tree_2lvl" global_port="clk[0:7]"/>
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<clock_network name="rst_tree_2lvl" global_port="rst[0:7]"/>
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.. option:: pin="<string>"
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The pin should be a valid pin of the ``global_port`` that is defined in the clock network description under the selected clock network.
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non_fabric-related Settings
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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This is special syntax to extract PB defined parameter or attribute and save the data into dedicated JSON file outside of fabric bitstream
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The following syntax are applicable to the XML definition tagged by ``non_fabric`` in bitstream setting files.
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.. option:: name="<string: pb_type top level name>"
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The ``pb_type`` top level name that the data to be extracted. For example,
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.. code-block:: xml
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name="bram"
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.. option:: file="<string: JSON filepath>"
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The filepath the data is saved to. For example,
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.. code-block:: xml
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file="bram.json"
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.. option:: pb child element name="<string: pb_type child name>"
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Together with ``pb_type`` top level name, that is the source of the ``pb_type`` bitstream
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The final ``pb_type`` name is "<pb_type top level name>" + "<pb_type child name>"
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For example,
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.. code-block:: xml
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<non_fabric name="bram" file="bram_bitstream.json">
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<pb name=".bram_lr[mem_36K_tdp].mem_36K" content=".param INIT_i"/>
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</non_fabric>
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The final ``pb_type`` name is "bram.bram_lr[mem_36K_tdp].mem_36K"
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.. option:: pb child element content="<string>"
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The content of the ``pb_type`` data to be extracted. For example, ``content=".param INIT_i"`` means that the data will be extracted from the ``.param INIT_i`` line defined under the ``.blif model``.
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overwrite_bitstream-related Settings
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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This is to allow user to set value of a list of bits which is represented using full path in the hierarchy of FPGA fabric
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This ``overwrite_bitstream`` settings has the highest priority than loading any external bitstream file
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Each bit to overwrite is represented by one ``bit`` child node/tag
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The following syntax are applicable to the XML definition tagged by ``bit`` node under ``overwrite_bitstream`` setting.
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.. option:: value="<0 or 1>"
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The boolean ``0`` or ``1`` that will be set. For example,
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.. code-block:: xml
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value="0"
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.. option:: path="<string>"
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``path`` represents the location of this block in FPGA fabric, i.e., the full path in the hierarchy of FPGA fabric.
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.. code-block:: xml
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path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5[0]"
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