OpenFPGA/vpr7_x2p/vpr/ARCH
Ganesh Gore 443a73954f Removed all local files
+ Removed local configurations and scripts from previous commit
2019-07-03 14:26:06 -06:00
..
.regression_k6_N10_sram_chain_HC.xml Verilog verification with Travis 2019-05-15 15:57:05 -06:00
.travis_k6_N10_sram_chain_HC.xml Update spice path in architecture 2019-05-29 10:08:58 -06:00
k6_N10_scan_chain_ptm45nm_TT.xml Added additional architecure files 2019-06-11 11:26:44 -06:00
k6_N10_scan_chain_template.xml Added additional architecure files 2019-06-11 11:26:44 -06:00
k6_N10_sram_chain_HC_6Input.xml Added additional architecure files 2019-06-11 11:26:44 -06:00
k6_N10_sram_chain_HC_template.xml skip rotating mirror detection which is too time-consuming 2019-05-25 23:41:46 -06:00
k6_N10_sram_chain_SC_gf130_2x2.xml Added additional architecure files 2019-06-11 11:26:44 -06:00
k6_N10_sram_ptm45nm_TT.xml Added additional architecure files 2019-06-11 11:26:44 -06:00