114 lines
3.8 KiB
Verilog
114 lines
3.8 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 05/05/2021 09:43:10 AM
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// Design Name:
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// Module Name: bitstream_loader
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module bitstream_loader(
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input prog_clk,
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input start,
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output config_chain_head,
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output reg done
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);
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parameter BITSTREAM_FILE="";
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parameter BITSTREAM_SIZE=6140;
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reg [BITSTREAM_SIZE<=2 ? 2 : $clog2(BITSTREAM_SIZE):0] bitstream_index;
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reg [13:0] bram_addr;
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reg [3:0] bram_line_index;
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wire bram_output;
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assign config_chain_head = bram_output;
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EFX_RAM_5K #(
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.READ_WIDTH(1),
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.WRITE_WIDTH(0),
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.INIT_0(256'h00000000000000000000000000000000000000000000007f00000000000000ff),
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.INIT_1(256'h0000fff8ffffffff000000000000000000000000000000000000000000000000),
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.INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4(256'h00000003f8000000000000000000000000000000000000000000000000000000),
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.INIT_5(256'h0000000000000000078000000000000000000000000000000000000000000000),
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.INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_17(256'h0021000000000000000000000000000000000000000000000000000000000000),
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)
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EFX_RAM_5K_inst (
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// Port A Data: 16-bit (each) output: Port A data
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.WDATA(0), // Write data
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.WADDR(0), // Write address
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.WE(0), // Write enable
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.WCLK(0),
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.WCLKE(0),
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.RDATA(bram_output),
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.RADDR(bram_addr),
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.RE(1'b1),
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.RCLK(prog_clk)
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);
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initial begin
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bram_addr <= 0;
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bram_line_index <= 0;
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bitstream_index <= 0;
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done <= 1'b0;
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end
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always @(posedge prog_clk) begin
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if (start && !done) begin
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bram_addr <= bram_addr + 1;
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bitstream_index <= bitstream_index + 1;
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end
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if (bitstream_index == BITSTREAM_SIZE) begin
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done <= 1'b1;
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end
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end
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endmodule
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