riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenFPGA/openfpga_flow/benchmarks/micro_benchmark/asyn_spram_4x1
History
AurelienAlacchi 3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200) 
* Add required files for LUTRAM integration and testing

* Add task for lutram

* Repair format (tab and space mismatched)

* Add disclaimer in architecture file

Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
 		2021-01-29 10:19:05 -07:00
..
asyn_spram_4x1.act Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200) 2021-01-29 10:19:05 -07:00
asyn_spram_4x1.blif Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200) 2021-01-29 10:19:05 -07:00
asyn_spram_4x1.v Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200) 2021-01-29 10:19:05 -07:00