103 lines
4.2 KiB
Verilog
103 lines
4.2 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE rev.B2 compliant enhanced VGA/LCD Core ////
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//// Defines file ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// Downloaded from: http://www.opencores.org/projects/vga_lcd ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001, 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: vga_defines.v,v 1.6 2003/08/01 11:46:38 rherveille Exp $
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//
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// $Date: 2003/08/01 11:46:38 $
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// $Revision: 1.6 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: vga_defines.v,v $
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// Revision 1.6 2003/08/01 11:46:38 rherveille
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// 1) Rewrote vga_fifo_dc. It now uses gray codes and a more elaborate anti-metastability scheme.
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// 2) Changed top level and pixel generator to reflect changes in the fifo.
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// 3) Changed a bug in vga_fifo.
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// 4) Changed pixel generator and wishbone master to reflect changes.
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//
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// Revision 1.5 2003/05/07 09:48:54 rherveille
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// Fixed some Wishbone RevB.3 related bugs.
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// Changed layout of the core. Blocks are located more logically now.
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// Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.
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//
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// Revision 1.4 2002/02/07 05:42:10 rherveille
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// Fixed some bugs discovered by modified testbench
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// Removed / Changed some strange logic constructions
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// Started work on hardware cursor support (not finished yet)
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// Changed top-level name to vga_enh_top.v
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//
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////////////////////////
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//
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// Global settings
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//
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//
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// define memory vendor
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// for FPGA implementations use `define VENDOR_FPGA
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`define VENDOR_FPGA
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//
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// enable / disable 12bit DVI output
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// (for use with external DVI transmitters)
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//`define VGA_12BIT_DVI
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////////////////////////
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//
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// Hardware Cursors
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//
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//
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// enable / disable hardware cursors
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//
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//`define VGA_HWC0
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//`define VGA_HWC1
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//
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// enable / disabled 3D support for hardware cursors
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//
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//`define VGA_HWC_3D
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