riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenFPGA/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/timescale.v

3 lines
25 B
Verilog
Raw Blame History

`timescale 1ns / 10ps
Reference in New Issue View Git Blame Copy Permalink