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OpenFPGA/openfpga
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tangxifan be8f18310d [FPGA-Verilog] Fix a bug on the polarity of reset signals that drive FPGA instances 2022-02-14 17:16:26 -08:00
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src [FPGA-Verilog] Fix a bug on the polarity of reset signals that drive FPGA instances 2022-02-14 17:16:26 -08:00
CMakeLists.txt [Tool] Deploy pin constraints to preconfig Verilog module generation 2021-01-19 16:56:30 -07:00