34 lines
1.3 KiB
Bash
Executable File
34 lines
1.3 KiB
Bash
Executable File
#!/bin/bash
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echo "#################################################"
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echo "The current shell environment is the following:"
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echo $0
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echo "#################################################"
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# Example of how to run vprset circuit_name = pip_add
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#set circuit_name = pip_add
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circuit_name=sync_4bits_add
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circuit_blif=${PWD}/Circuits/${circuit_name}.blif
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arch_file=${PWD}/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml
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arch_file_template=${PWD}/ARCH/k6_N10_sram_chain_HC_template.xml
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circuit_act=${PWD}/Circuits/${circuit_name}.act
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circuit_verilog=${PWD}/Circuits/${circuit_name}.v
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spice_output=${PWD}/spice_demo
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verilog_output=${PWD}/verilog_demo
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modelsim_ini=/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini
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openfpga_path=${PWD}/../..
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# Make sure a clean start
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rm -rf ${spice_output}
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rm -rf ${verilog_output}
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echo "*******************************"
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echo "THIS SCRIPT NEEDS TO BE SOURCED"
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echo "source ./go.sh"
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echo "*******************************"
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sed "s:OPENFPGAPATH:${openfpga_path}:g" ${arch_file_template} > ${arch_file}
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# Pack, place, and route a heterogeneous FPGA
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# Packing uses the AAPack algorithm
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./vpr ${arch_file} ${circuit_blif} --full_stats --nodisp --activity_file ${circuit_act} --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ${spice_output} --fpga_spice_print_top_testbench
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