tangxifan 392f579836 add linking functions for circuit models and architecture, memory sanitizing is ongoing		2019-08-13 13:25:23 -06:00
..
base	add linking functions for circuit models and architecture, memory sanitizing is ongoing	2019-08-13 13:25:23 -06:00
bitstream	added Switch Block SubType and SubFs for tileable rr_graph generation	2019-07-02 10:00:02 -06:00
clb_pin_remap	cleaned unused variables	2019-05-13 14:45:02 -06:00
router	added Switch Block SubType and SubFs for tileable rr_graph generation	2019-07-02 10:00:02 -06:00
shell	Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb	2019-05-13 14:45:57 -06:00
spice	added Switch Block SubType and SubFs for tileable rr_graph generation	2019-07-02 10:00:02 -06:00
verilog	Now we can also auto-generate the Verilog for a mux2 std cell	2019-08-06 15:19:01 -06:00