Ganesh Gore edd5be2cae [CI] Added testcase for benchmark variable		2021-07-02 12:51:34 -06:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	fixed tab spacing	2021-07-01 16:42:04 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	[Script] Update yosys script using BRAMs	2021-04-27 21:44:27 -06:00
openfpga_arch	[Arch] recover the mem16k arch as it is used in other test cases	2021-04-28 15:05:30 -06:00
openfpga_cell_library	[HDL] Remove the instrusive signal initialization in the configuration flip-flop HDL codes	2021-06-29 11:40:22 -06:00
openfpga_shell_scripts	[Test] Bug fix	2021-06-29 18:51:28 -06:00
openfpga_simulation_settings	[Arch] Add simulation setting for 8-clock architectures	2021-02-22 11:10:03 -07:00
openfpga_yosys_techlib	[Script] Update yosys script due to arch changes in DPRAM sizes	2021-04-28 10:55:59 -06:00
regression_test_scripts	Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench	2021-07-01 15:29:39 -06:00
scripts	[CI] Added testcase for benchmark variable	2021-07-02 12:51:34 -06:00
tasks	[CI] Added testcase for benchmark variable	2021-07-02 12:51:34 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Bug fix in the architecture using BRAM spanning two columns	2021-04-28 14:32:17 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00