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OpenFPGA/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config
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Aram Kostanyan 758453f725 Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections. 2022-01-21 02:21:00 +05:00
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pin_constraints.xml [Test] Bug fix in the 5clock test case 2021-02-22 11:46:23 -07:00
repack_pin_constraints.xml [Test] Bug fix in the 5clock test case 2021-02-22 11:46:23 -07:00
task.conf Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections. 2022-01-21 02:21:00 +05:00